JP2021047938A - Nonvolatile semiconductor storage device - Google Patents

Abstract

To provide a nonvolatile semiconductor storage device which recognizes a state of a memory device and can simultaneously perform refreshing operation at every reading or within one clock in a writing state.SOLUTION: A reading SA (sense amplifier) 10 compares current Io of a memory cell 20 with reading reference current Ith of a reading reference setting part 30, determines an erased state or a writing state, and outputs an output signal FB. A voltage setting circuit 40 applies reading reference voltage V0 to the memory cell 20 in reading operation by reading SA 10, and applies deterioration improvement voltage V1 higher than the reading reference voltage V0 to the memory cell 20 when the output signal FB in the writing state is given. When deterioration progresses, the memory cell 20 is brought into the writing state when the current Io is smaller than the reading reference current Ith, and brought into a state larger than writing reference. Thus, the deterioration improvement voltage V1 is given and the voltage can be improved by read disturbance.SELECTED DRAWING: Figure 1

Description

The present invention relates to a non-volatile semiconductor storage device.

In an electrically rewritable non-volatile semiconductor storage device, a device that automatically refreshes data so as to prevent deterioration of data stored in a memory element and extend the life of the data has been proposed.

In such a non-volatile semiconductor storage device, a refresh voltage is automatically generated and a refresh voltage is applied after a predetermined time elapses after a write voltage or an erasure voltage is applied to the memory element or after a refresh voltage is applied. It is configured to. Further, in the non-volatile semiconductor storage device, the change in the threshold value of the memory element is read, and the refresh voltage is controlled to be generated and applied according to the measurement result of the threshold value.

The above-mentioned refresh voltage is, for example, a weak voltage of about half of the write voltage or the erase voltage. As a result, the memory element can be refreshed without affecting the memory element in the erased state, and the threshold voltage of only the memory element in the written state regardless of whether the memory element is in the write state or the erased state. Can be varied to extend the data life of the memory element.

However, in the non-volatile semiconductor storage device as described above, since a predetermined time elapses or the data of the memory element is read and the mode shifts to the mode for determining the deterioration state and the deterioration state is confirmed, the mode shifts to the refresh mode. , It took a long time to complete the refresh.

Japanese Unexamined Patent Publication No. 2011-141929

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to confirm the state of a memory element without going through a plurality of modes, and if it is a write memory element, simultaneously or at each read operation. An object of the present invention is to provide a non-volatile semiconductor storage device capable of performing refresh in a clock.

The non-volatile semiconductor storage device according to claim 1 is a non-volatile semiconductor storage device that can electrically write and erase data to a memory element (20, 20a, 20b), and the memory element writes. A read sense amplifier (10, 70) that detects whether it is in a state or an erase state based on a comparison with a read reference and outputs an output signal, and a normal read voltage when reading the data of the memory element. Is provided as a read voltage, and a voltage setting circuit (40, 510, 710) is provided for setting a read voltage applied to the memory element based on the output signal to a deterioration improvement voltage higher than the normal read voltage. When the read voltage is applied to the memory element by the voltage setting circuit, the read sense amplifier reads the current of the memory element when the memory element is an N-channel type MOS transistor. When it is determined to be in the write state below the reference, it is determined to be in the erase state when the current of the memory element is larger than the read reference, and when the memory element is a P-channel type MOS transistor, the current of the memory element is determined. Is determined to be in the write state when the value is equal to or higher than the read reference, and is determined to be in the erase state when the current of the memory element is smaller than the read reference. In the read operation after the determination, when the memory element is in the erase state. Continues the application state of the normal read voltage, and when the memory element is in the writing state, gives an output signal to the voltage setting circuit to switch to the application state of the deterioration improvement voltage.

By adopting the above configuration, when the memory element is in the write state in the read operation by the read sense amplifier, in the read operation after the determination, an output signal is given to the voltage setting circuit to apply the deterioration improvement voltage. Switch to. As a result, the state of the memory element can be confirmed without going through a plurality of modes, and refreshing can be performed simultaneously or within one clock for each read operation, and deterioration of write data of the memory element can be suppressed. The read operation speed of the memory element can be improved.

Basic block configuration diagram showing the first embodiment Electrical configuration diagram of the sense amplifier The figure which shows the flow of the read mode of 1 cycle Electrical configuration diagram showing a specific example Timing chart Operation explanatory diagram Modification example of the sense amplifier for reading Electrical configuration diagram showing the second embodiment Timing chart Operation explanatory diagram Electrical configuration diagram showing a third embodiment Electrical configuration diagram showing a fourth embodiment Operation explanatory diagram Electrical configuration diagram showing a fifth embodiment Timing chart Electrical configuration diagram showing the sixth embodiment Timing chart

(First Embodiment)
Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 to 6.
In FIG. 1, which shows a basic block configuration diagram, the non-volatile semiconductor storage device 100 includes a read SA (sense amplifier) 10, a memory cell 20 as a memory element, a read reference setting unit 30, and a voltage setting circuit 40.

The read SA10 is for determining the stored contents of the memory cell 20, and here, the determination is made based on the current Io of the memory cell 20. The read reference setting unit 30 outputs the read reference current Is for comparison to the read SA10.

The voltage setting circuit 40 determines the voltage to be applied to the memory cell 20 by the output signal FB of the read SA10 and outputs the voltage. Here, the memory cell 20 is connected to the inverting input terminal of the reading SA10, the reading reference setting unit 30 is connected to the non-inverting input terminal, and the output terminal of the reading SA10 is the output signal FB to the voltage setting circuit 40. Is connected to give.

As shown in FIG. 2, in the above-mentioned reading SA10, a current comparison type amplifier for comparing the magnitudes of currents is connected between the power supply VD and ground. The current Io of the memory cell 20 as the inverting input is input to the P-channel type MOS transistors 11 and 12 constituting the current mirror circuit. The read reference current Is of the read reference setting unit 30, which is a non-inverting input, is input to the P-channel type MOS transistors 13 and 14 constituting the current mirror circuit.

The N-channel type MOS transistors 15 and 16 compare the current Io with the read reference current Is and output the output signal FB. This output signal FB is input to the voltage setting circuit 40.

In the above configuration, in the read operation of the stored contents of the memory cell 20, the magnitude of the current Io flowing through the memory cell 20 is compared with the read reference current Is by the read reference setting unit 30 using the read SA10. It is determined whether 20 is in the writing state or the erasing state. Here, the reading SA10 outputs "0" when a current Io larger than the reading reference current Is flows, and outputs "1" when a current Io smaller than the reading reference current Is flows.

FIG. 3 shows the flow of processing in the read mode of one cycle of the non-volatile semiconductor storage device 100 having the above configuration. In the execution of the read mode, first, in step S100, the state of the memory cell 20 is confirmed by the normal read reference voltage. After that, in step S110, when the storage state of the memory cell 20 is in the erased state, deterioration improvement is not necessary. Therefore, the read mode for one cycle ends, and then the process returns to step S100 to read the next. Move to the mode cycle.

On the other hand, in step S110, when the storage state of the memory cell 20 is the writing state, deterioration improvement is required, and the process proceeds to step S120, the voltage setting circuit 40 changes the reading voltage to a higher reading voltage, and the reading voltage is read after the change. To execute. As a result, if it is determined that deterioration improvement is necessary during the execution of the read mode of one cycle, refreshing using the read disturb can be quickly executed.

Next, the operation of the read disturb in the memory cell 20 in the above configuration will be described. When the memory cell transistor constituting the memory cell 20 is of, for example, a hot electron injection method, a large current is passed to generate hot electrons when writing, and FG (FG) which is a charge holding region in the memory cell transistor is generated. Inject electrons into the floating gate).

Therefore, when the memory cell transistor used in the memory cell 20 is an N-channel type MOS transistor, the threshold voltage of the transmission characteristic shifts positively in the write state, so that no current flows even when the read voltage is applied. Is a feature.

On the other hand, the erasing method employs the Folder-Nodeheim (FN) tunnel method, and emits electrons in the FG by giving a large potential difference between the source and gate of the MOS transistor. Therefore, in the erased state, the threshold voltage of the transmission characteristic shifts negatively, so that when a read voltage is applied, a current flows unlike the write state.

In the writing state, many electrons are present in the FG, but due to time, reading operation, etc., the electrons in the FG escape to the outside, and the threshold value of the shifted transmission characteristic tries to return to the original state. Similarly, in the erased state, since there are few electrons in the FG, electrons enter the FG due to time or the like, and the threshold value of the transmission characteristic tries to return to the original state. This is called memory deterioration, and a method for improving this deterioration is an important issue.

Next, at the time of reading, since the reading reference voltage is applied and the reading current Io is passed through the memory cell 20, the memory cell transistor of the memory cell 20 is written a little. This is commonly referred to as a reed disturb. In general, since a large amount of read current flows in an erase memory cell, the life of data is shortened by this read disturb, but in a write memory cell, the life is slightly longer because the read memory is weakly written. Therefore, when the memory cell 20 is in the writing state, deterioration can be improved by using the read disturb.

Next, with reference to FIG. 4, the non-volatile semiconductor storage device 200 as a specific configuration of the non-volatile semiconductor storage device 100 shown in FIG. 1 will be described. The non-volatile semiconductor storage device 200 has a configuration in which a precharge circuit 50 and a read FF (flip-flop) 60 are added in addition to the configuration shown in FIG.

The memory cell 20 is schematically shown as a configuration in which the memory cell transistor 21 and the selection transistor 22 are connected in series. Here, the memory cell transistor 21 uses, for example, an N-channel type MOS transistor having an FG (floating gate). The memory cell 20 is connected to the inverting input terminal of the reading SA10 via the voltage setting circuit 40. The memory cell 20 is actually configured as a memory cell array in which a large number of cells are connected in parallel, and the memory cell 20 to be read is selected by the selection transistor 22.

The voltage setting circuit 40 includes a MOS transistor 41 that couples the memory cell 20 and the reading SA10, and also includes a switch 42, a normal voltage setting unit 43, and a deterioration improving voltage setting unit 44. The normal voltage setting unit 43 sets the voltage divided by the series circuit of the voltage dividing resistors 43a and 43b connected between the DC power supply VD and the ground as the read reference voltage V0. The deterioration improvement voltage setting unit 44 sets the voltage divided by the series circuit of the voltage dividing resistors 44a and 44b connected between the DC power supply VD and the ground as the deterioration improving voltage V1. The deterioration improvement voltage V1 is set to a voltage higher than the read reference voltage V0.

The switch 42 switches the gate voltage of the MOS transistor 41 when the output voltage FB of the read SA10 outputs “1”. When the output voltage FB of the read SA10 is "0", the switch 42 gives the read reference voltage V0 to the gate of the MOS transistor 41 as Vbias, and when the output voltage FB becomes "1", the deterioration improvement voltage V1 is applied to the gate of the MOS transistor 41. The switching operation is performed so as to give the voltage as Vbias.

A precharge circuit 50 is connected to the inverting input terminal of the read SA10. In the precharge circuit 50, the output signal FB is indefinite from the time when the first clock rises after the read SA10 receives the read command until the read is executed and the comparison result with the read reference voltage V0 is output. Fix the potential so that it does not become.

Here, the precharge circuit 50 fixes the output signal FB to a specific logic level (logical value) by lowering the potential of the inverting input terminal of the read SA10 once below the read reference voltage V0 at the rising edge of the clock. ing. In this embodiment, for example, the output signal FB of the reading SA10 is fixed so as to be “0”. When the output signal FB is “0”, the switch 42 of the voltage setting circuit 40 is set to output the read reference voltage V0.
The read FF60 is provided so that the output signal FB of the read SA10 is input, and stores the output signal FB at the rising edge of the clock.

Next, the operation of the read mode of the non-volatile semiconductor storage device 200 will be described with reference to FIG. FIG. 5 shows the operation when the memory cell 20 is in the writing state. Moreover, the erase memory cell 20 is also shown as a comparison. In the read mode of the non-volatile semiconductor storage device 200, the clock cycle is set to one cycle between the rising times t0, t1 and t2 of the clock CLK, that is, the read operation itself is precharged once in the read mode. Will be executed later. That is, it is assumed that the read mode here is composed of a precharge and a read operation.

When a read command is given from the outside, the precharge circuit 50 precharges immediately after the clock CLK rises. As a result, the initial signal of the output signal FB of the read SA10 becomes "0", and since the switch 42 is connected to the normal voltage setting unit 43, the read reference voltage V0 is initially set as Vbias at the gate of the MOS transistor 41. It will be in the applied state.

When the read operation is subsequently executed, the read SA10 compares the read reference current Is with the current Io flowing through the memory cell 20. When the memory cell 20 is an erased memory cell, a current Io larger than the read reference current Is flows, so that the output signal FB at that time remains “0”.

On the other hand, when the memory cell 20 is a memory cell in the writing state, the output signal FB changes to "1" because a current Io smaller than the read reference current Is flows. In the voltage setting circuit 40, since the output signal FB of "1" is input from the read SA10, the Vbias given to the gate of the MOS transistor 41 by the switch 42 is a deterioration improvement voltage of a voltage higher than the read reference voltage V0. Switch to V1. As a result, the memory cell 20 is subjected to the read operation at a voltage higher than the read reference voltage V0, so that the read disturb is applied, and the deterioration of the data can be improved.

Next, with reference to FIG. 6, the degree of progress of deterioration of the memory cell 20 in the present embodiment will be compared with that of the conventional method. In FIG. 6, the progress of deterioration of the memory cell using the present embodiment with the passage of time is shown by a solid line, and the progress of deterioration in the conventional method is shown by a dotted line for comparison. Further, in FIG. 6, the level of the read reference current Is is indicated by a broken line. The level of the read reference current Is is a level at which it cannot be determined that the memory cell 20 is in the write state when the current Io of the memory cell 20 in the write state exceeds this, and it is erroneously determined that the memory cell 20 is in the erase state. This is the level at which the so-called "garbled data" state occurs.

The above phenomenon will be described. Immediately after writing, the memory cell transistor 21 constituting the memory cell 20 is in a state in which a large amount of electrons are injected into the FG, so that almost no current flows through the memory cell 20, so that there is almost no writing effect due to the read disturb. Conceivable. However, as time elapses, electrons in the FG of the memory cell transistor 21 escape, so that the current easily flows through the memory cell 20 due to the escape of electrons.

Therefore, since the memory cell 20 in the present embodiment applies a high voltage deterioration improving voltage in the writing state, the deterioration improving effect by the read disturb becomes large. It can be seen that in the method using the read disturb of the present embodiment, the time until data garbled occurs is longer than the progress of normal deterioration, and the deterioration is suppressed.

In such an embodiment, when the voltage setting circuit 40 is provided and the output signal FB of the read SA10 becomes "1" when the memory cell 20 is in the write state, Vbias is read from the read reference voltage V0. It was configured to switch to the deterioration improvement voltage V1 of a high voltage and output it. As a result, when the memory cell 20 is in the write state, it can be refreshed by the read disturb during one cycle of the read operation, data deterioration of the memory cell 20 can be suppressed, and the memory read speed can be improved. Can be done.

Although the memory cell 20 used in the present embodiment has a configuration using an N-channel type MOS transistor, a memory cell using a P-channel type MOS transistor may be used. In this case, when the current Io flowing through the memory cell at the time of reading is larger than the reading reference current Is, the writing state is set, and when the current Io is equal to or less than the reading reference current Is, the erasing state is set.

Therefore, the output signal FB of the read SA10 outputs "1" when the current Io larger than the read reference current Is flows, and the read SA10 is set to the read reference current, contrary to the above case. When a current Io of Is or less flows, it may be changed to output "0".

Further, in the above embodiment, the reading SA10 has been described in the case where a current comparison type reading SA10 is used, but as shown in FIG. 7, a voltage comparison type reading SA70 may be used. The read SA70 includes P-channel type MOS transistors 71 and 72, N-channel type MOS transistors 73, 74 and 75, and a pull-up resistor 76.

The sources of the MOS transistors 71 and 72 are commonly connected to the DC power supply VD to form a current mirror circuit. The drains of the MOS transistors 71 and 72 are commonly connected to the source via the MOS transistors 73 and 74 in series, respectively, and are further connected to the ground via the MOS transistors 75 in series.

The gate of the MOS transistor 73 is connected to the DC power supply VD as an inverting input terminal via a pull-up resistor 76, and is provided so that the current Io of the memory cell 20 is input as the voltage Vo. On the other hand, the gate of the MOS transistor 74 is provided as a non-inverting input terminal so that the read reference voltage Vth is input to 6.

When the read SA70 is used, the voltage setting circuit 40 determines the read voltage to be given to the memory cell 20 by the output signal FB of the read SA70. Therefore, such a read SA70 can also perform the same operation as the above-mentioned read SA10 except that it is configured as a voltage comparison type instead of the current.

(Second Embodiment)
8 to 10 show the second embodiment, and the parts different from the first embodiment will be described below. In the first embodiment, when the memory cell 20 is in the writing state, the deterioration improving voltage V1 is always applied, whereas in this embodiment, the memory cell is in the writing state. It is not implemented when the current Io of 20 is equal to or less than the deterioration detection standard.

FIG. 8 shows the electrical configuration of the non-volatile semiconductor storage device 300. In addition to the configuration of FIG. 4 of the first embodiment, a deterioration detection SA (sense amplifier) 310, a deterioration detection reference setting unit 320, and an AND circuit 330 as a logic circuit are added. Further, the memory cells 20 show two memory cells 20a and 20b for convenience of explanation.

Similar to the read SA10, the deterioration detection SA310 is connected to the memory cell 20 via the voltage setting circuit 40 to the inverting input terminal, and the current Io of the memory cell 20 is input. Further, in the deterioration detection SA310, the deterioration detection reference setting unit 320 is connected to the non-inverting input terminal, and the deterioration detection reference current Ix is input. The deterioration detection reference current Ix is set to a current value larger than the write reference current Iw and smaller than the read reference current Is.

The AND circuit 330 is input with the output signal of the reading SA10 and the output signal of the deterioration detection SA310. Here, the output signal of the deterioration detection SA310 is inverting input to the AND circuit 330. The AND circuit 330 outputs a high level output signal FB of "1" when the output signal from the read SA10 is high level and the output signal from the deterioration detection SA310 is low level. The output signal FB of the AND circuit 330 is input to the voltage setting circuit 40.

Next, the operation of the above configuration will be described. In this embodiment, the condition for newly introducing the deterioration detection reference and refreshing is determined by determining whether or not the current Io exceeds the deterioration detection reference current Ix when the memory cell 20 is in the writing state. ing.

FIG. 9 shows an operation timing chart of the read mode of the non-volatile semiconductor storage device 300, similar to that shown in FIG. FIG. 9 shows an operation when the memory cell 20a is selected in the writing state. Further, here, the case where the memory cell 20a as the target for the read operation is in the deteriorated write state and the case where the memory cell 20a is in the non-deteriorated write state are also shown.

Similarly to the above, in the read mode of the non-volatile semiconductor storage device 300, the rise time of the clock CLK is between t0, t1, and t2, that is, the clock cycle is set to one cycle, and the read operation itself is precharged once in the read mode. Will be executed after.

At the rising edge of the clock CLK immediately after the read command signal is issued, the precharge circuit 50 precharges, and then the read operation by the read SA10 and the deterioration detection operation by the deterioration detection SA310 start in parallel at the same time. Will be done. Due to precharging, the output signal of the read SA10 is initially set to "0". As a result, the initial value of the output signal FB of the AND circuit 330 also becomes “0”, and the voltage setting circuit 40 is in a state of outputting the read reference voltage V0 to the gate of the MOS transistor 41.

When the read operation is subsequently executed, the read reference current Is and the current Io flowing through the memory cell 20a are compared by the read SA10 and the deterioration detection SA310. When the memory cell 20a is in the erased state, a current Io larger than the read reference current Is flows, so that the output signals of the read SA10 and the deterioration detection SA310 at that time remain "0". As a result, the output signal FB of the AND circuit 330 remains “0”, and the voltage setting circuit 40 continues to output the read reference voltage V0 to the gate of the MOS transistor 41.

On the other hand, when the memory cell 20a is in the writing state, the current Io smaller than the reading reference current Is flows, so that the output signal of the reading SA10 changes to "1". At this time, when the current Io of the memory cell 20a is larger than the deterioration detection reference current Ix, the output signal of the deterioration detection SA310 remains “0”, so that the AND circuit 330 sets the output signal FB to “1”. Output as.

As a result, in the voltage setting circuit 40, since the output signal FB of "1" is input from the AND circuit 330, the Vbias given to the gate of the MOS transistor 41 by the switch 42 is set to a voltage higher than the read reference voltage V0. Switch to the deterioration improvement voltage V1. As a result, the memory cell transistor 21 of the memory cell 20 is disturbed, and the deterioration of data can be improved.

Even when the memory cell 20a is in the writing state and a current Io smaller than the read reference current Is flows and the output signal of the read SA10 changes to "1", the current Io of the memory cell 20a is the deterioration detection reference current. When it is Ix or less, it operates as follows. That is, in this case, the output signal of the deterioration detection SA310 becomes “1”, and the AND circuit 330 outputs the output signal FB as “0”. As a result, the output signal FB of the AND circuit 330 remains “0”, and the voltage setting circuit 40 continues to output the read reference voltage V0 to the gate of the MOS transistor 41.

FIG. 10 illustrates the above operation, and the deterioration detection reference current Ix is provided between the write reference current Iw and the read reference current Is, which are current values immediately after the write voltage is applied. The section between the read reference current Is and the deterioration detection reference current Ix is defined as a deterioration improvement implementation section, and when the current Io of the memory cell 20a flows, the deterioration improvement voltage V1 is applied to perform deterioration using the read disturb. I try to suppress it.

As described above, in the present embodiment, the deterioration detection SA310 is newly provided, and even when the memory cell 20a is in the storage state, if the current Io is smaller than the deterioration detection reference Ix, the deterioration improvement voltage V1 is regarded as a non-deterioration state. Was not applied. As a result, the deterioration improvement voltage V1 can be applied by selecting the memory cell 20a in the written state that has deteriorated to some extent, and the number of times the memory cell 20b in the non-selected state is exposed to the high voltage can be reduced.

The above effect is due to the following reasons. That is, in a memory cell array provided with a plurality of memory cells 20a, 20b, etc., when the deterioration improvement voltage V1 is unconditionally applied when the memory cell 20a selected for reading is in the writing state. A high voltage deterioration improving voltage V1 is also applied to the non-selected memory cells 20b of the memory cell array. This may lead to deterioration of the memory structure itself depending on the type and characteristics of the non-volatile semiconductor storage device or the usage pattern.

Therefore, when applied to such a non-volatile semiconductor storage device, it is preferable to minimize the application of the deterioration improvement voltage V1 to the non-selected memory cells. Further, even if the current is not passed through the selection transistor 22b of the memory cell 20b, if the selection transistor 22b of the non-selection erase memory cell 20b is also turned on due to some malfunction, the deterioration improvement voltage V1 is applied. This is because a strong lead disturb may occur and the life may be shortened.

(Third Embodiment)
FIG. 11 shows a third embodiment, and the parts different from the second embodiment will be described below. In this embodiment, instead of providing the deterioration detection SA310 as the non-volatile semiconductor storage device 400, a simple circuit for determining the current Io of the memory cell 20 based on the deterioration detection standard is provided.

That is, as shown in FIG. 11, P-channel type MOS transistors 410 and 420 are provided with current mirror circuits for copying the current of the memory cell 20. In the N-channel type MOS transistor 430 for determining the current level of the memory cell 20, the source is connected to the ground and the drain is connected to the DC power supply VD via the pull-up resistor 440.

The resistor 450 for detecting the current level is provided so that a current flows from the MOS transistor 420 constituting the current mirror circuit, and is connected so as to apply a terminal voltage to the gate of the MOS transistor 430.

In this case, the resistance value of the resistor 450 is set so as not to reach the terminal voltage that reaches the threshold voltage of the MOS transistor 430 in a state where a current smaller than the deterioration detection reference Ix flows. In this state, the MOS transistor 430 is in the off state, the drain is in the output state of the DC power supply VD level, that is, the high level by the pull-up resistor 440, and the low level is input to the AND circuit 330. As a result, the output signal FB can be set to a low level of "0".

On the other hand, when the current Io of the memory cell 20 becomes equal to or higher than the deterioration detection reference Ix, the terminal voltage of the resistor 450 becomes equal to or higher than the threshold voltage of the MOS transistor 430, and the MOS transistor 430 is turned on. As a result, the drain of the MOS transistor 430 is in the ground level, that is, the low level output state, and the high level is input to the AND circuit 330. As a result, the output signal FB can be set to a high level of "1".

Therefore, even with such a third embodiment, the same effect as that of the second embodiment can be obtained.
In the above embodiment, the deterioration detection reference Ix can be adjusted and set to an appropriate level by changing the resistance value of the resistor 450.

(Fourth Embodiment)
12 and 13 show the fourth embodiment, and the parts different from the second embodiment will be described below. In this embodiment, the non-volatile semiconductor storage device 500 is configured to provide deterioration improvement implementation sections in a plurality of stages, a plurality of deterioration improvement voltages are provided, and the voltage applied finely is changed according to the state of the memory cell 20. I have to.

In FIG. 12, the non-volatile semiconductor storage device 500 includes a voltage setting circuit 510 instead of the voltage setting circuit 40. The voltage setting circuit 510 includes two switches 42a and 42b instead of the switch 42. Further, it includes a normal voltage setting unit 43, a first deterioration improvement voltage setting unit 44, and a second deterioration improvement voltage setting unit 45. The normal voltage setting unit 43 and the first deterioration improvement voltage setting unit 44 are the same as the normal voltage setting unit 43 and the deterioration improvement voltage setting unit 44 in FIG. 4 of the first embodiment.

The first deterioration improvement voltage setting unit 44 sets the voltage divided by the series circuit of the voltage dividing resistors 44a and 44b connected between the DC power supply VD and the ground as the first deterioration improving voltage V1. Further, the second deterioration improvement voltage setting unit 45 sets the voltage divided by the series circuit of the voltage dividing resistors 45a and 45b connected between the DC power supply VD and the ground as the second deterioration improving voltage V2.

The switch 42a gives a read reference voltage V0 to the gate of the MOS transistor 41 as Vbias when the output voltage FB1 of the read SA10 is at a low level “0”. That is, when the memory cell 20 is read and when the read result is in the erased state, the read reference voltage V0 becomes Vbias. Further, the switch 42a is connected to the switch 42b when the output voltage FB1 of the reading SA10 reaches the high level “1”, and performs a switching operation so as to give the deterioration improvement voltage V1 or V2 to the gate of the MOS transistor 41 as Vbias. .. That is, when the memory cell 20 is in the writing state, either the first deterioration improving voltage V1 or the second deterioration improving voltage V2 becomes Vbias.

The switch 42b has either a first deterioration improvement voltage V1 or a second deterioration improvement voltage V2 at the gate of the MOS transistor 41 via the switch 42a in an output state where the output voltage FB1 of the read SA10 is at a high level “1”. It is a selection switch that gives Vbias. In this case, the switch 42b gives the first deterioration improving voltage V1 to the gate of the MOS transistor 41 as Vbias when the output signal FB2 from the AND circuit 330 is at the low level “0”. Further, the switch 42b gives the second deterioration improving voltage V2 to the gate of the MOS transistor 41 as Vbias when the output signal FB2 from the AND circuit 330 is in the output state of the high level “1”.

In the above configuration, when the current Io of the memory cell 20 is equal to or less than the read reference current Is and is in the writing state, the switch 42a is connected to the switch 42b side. In this state, the deterioration improvement voltage V1 or V2 is selected by the switch 42b.

Here, when the current Io of the memory cell 20 is smaller than the deterioration detection reference current Ix, the deterioration detection SA310 outputs a high level “1” signal, so that the AND circuit 330 switches the low level output signal FB. Output to 42b. As a result, the switch 42b is set to apply the first deterioration improving voltage V1 to the gate of the MOS transistor 41. At this time, the memory cell 20 is refreshed at the first deterioration improving voltage V1 to weakly improve the deterioration.

On the other hand, when the current Io of the memory cell 20 is equal to or higher than the deterioration detection reference current Ix, the deterioration detection SA310 outputs a low level “0” signal, so that the AND circuit 330 switches the high level output signal FB to the switch 42b. Output to. As a result, the switch 42b is switched so as to apply the second deterioration improving voltage V2 to the gate of the MOS transistor 41. At this time, the memory cell 20 is refreshed at the second deterioration improving voltage V2, which is higher than the first deterioration improving voltage V1, and the deterioration is strongly improved.

In such a fourth embodiment, when the memory cell 20 is in the writing state, the first deterioration improving voltage V1 and the first deterioration improving voltage V1 and depending on whether the current Io of the memory cell 20 is equal to or less than or equal to the deterioration detection reference current Ix. The second deterioration improvement voltage V2 is switched to perform refreshing. As a result, the deterioration improvement voltages V1 and V2 are used properly according to the deterioration state of the memory cell 20 in the writing state, so that the influence on the adjacent memory cells is greater than in the case of constantly refreshing with a high deterioration improvement voltage. It can be reduced.

In the above embodiment, the two switches 42a and 42b are configured to selectively apply three types of voltages V0, V1 and V2, but the switch is configured to provide one 3-input switch for reading. It can also be configured to switch by logically calculating the output signals of the SA10 for SA10 and the SA310 for deterioration detection.

Further, in the above embodiment, the deterioration detection reference current is provided and the deterioration state is divided into two stages to apply the deterioration improvement voltages V1 and V2. However, the deterioration detection reference current is set in a plurality of stages and the deterioration state is applied. May be configured to apply the deterioration improvement voltage in three or more stages. Further, it is also possible to allocate and apply a continuous value of deterioration improvement voltage according to the magnitude of the current Io of the memory cell 20.

(Fifth Embodiment)
14 and 15 show the fifth embodiment, and the parts different from the first embodiment will be described below. Instead of the method of executing the read operation and the deterioration detection in parallel at the rising edge of the clock CLK described above, the non-volatile semiconductor storage device 600 of this embodiment employs a method of serially executing the read operation and the deterioration detection. ..

As shown in FIG. 14, the non-volatile semiconductor storage device 600 is provided with a switch 610 instead of the deterioration detection SA310, and inputs the input to the non-inverting input terminal of the reading SA10 to the reading reference setting unit 30 or the deterioration detection reference setting. It is configured to selectively connect any one of the units 320. Further, a deterioration FF620 for temporarily storing the output signal of the read SA10 and an AND circuit 630 as a logic circuit are provided.

As the switching operation of the switch 610, after the switch 610 is turned on on the deterioration detection reference setting unit 320 side, a certain delay is generated, and then the switch 610 is switched to the read reference setting unit 30 side. The deterioration FF620 as a latch circuit that temporarily stores the deterioration detection result data is the level of the output signal from the read SA10 at the timing when the switch 620 switches from the deterioration detection reference setting unit 320 side to the read reference setting unit 30 side. Remember.

In the AND circuit 630, the output signal of the reading SA10 is input, and the output signal of the deterioration FF620 is input in reverse. The AND circuit 630 gives an output signal FB to the switch 42 of the voltage setting circuit 40 based on the input signal.
Next, the operation of the above configuration will be described with reference to FIG.

In this embodiment, since the read operation and the deterioration detection are performed serially, the deterioration detection is first performed during one cycle of the clock CLK, and then the read operation is performed. Further, the precharge circuit 50 is operated to perform precharging prior to the deterioration detection and reading operations, respectively.

First, a case where the memory cell 20 is in the erased state will be briefly described. The current Io of the memory cell 20 is larger than the read reference current Is. At the timing when the clock CLK rises, the switch 610 is switched so as to be connected to the deterioration detection reference setting unit 320. Further, the output signal FB via the AND circuit 630 is set so that the initial value becomes the low level "0" by the precharge operation.

After that, in the read SA10, the comparison result of the current Io of the memory cell 20 with the deterioration detection reference current Ix becomes a low level “0”, so that “0” is temporarily stored in the deterioration FF620 at the switching timing of the switch 610. Will be done.

Next, in order to prevent the output state from becoming unknown during the switching of the switch 610, the precharge operation by the precharge circuit 50 is performed again. As a result, the output signal of the read SA10 is in the low level “0” state until the comparison with the read reference current Is is performed. After that, in the read SA10, the current Io of the memory cell 20 and the read reference current Is are compared, and the output signal becomes the low level “0”. As a result, the AND circuit 630 sets the output signal FB to the low level "0", whereby the switch 610 is held in a state where the read reference voltage V0 is output.

Next, as shown in FIG. 15, a case where the current Io of the memory cell 20 in the writing state exceeds the deterioration detection reference Ix will be described. At the timing when the clock CLK rises, the output signal FB of the AND circuit 630 is set so that the initial value becomes the low level "0" as described above.

After that, in the read SA10, the comparison result of the current Io of the memory cell 20 with the deterioration detection reference current Ix becomes a high level “1”, so that “1” is temporarily stored in the deterioration FF620 at the switching timing of the switch 610. Will be done.

Next, while the output signal FB is held at the low level “0” by precharging while the switch 610 is switched, the read SA10 compares the current Io of the memory cell 20 with the read reference current Is. .. Since the memory cell 20 is in the writing state, the output signal at this time becomes the low level “0”. As a result, the AND circuit 630 sets the output signal FB to the high level "1", whereby the switch 610 switches to a state in which the deterioration improvement voltage V1 is output.

In this state, the memory cell 20 is in the writing state, but the current Io exceeds the deterioration detection reference Ix. Therefore, the deterioration state is improved by refreshing with the deterioration improvement voltage V1.

On the other hand, as shown in FIG. 15, when the current Io of the memory cell 20 in the writing state is equal to or less than the deterioration detection reference current Ix, the current Io of the memory cell 20 is the deterioration detection reference current Ix in the read SA10. Since the comparison result becomes the low level "0", "0" is temporarily stored in the deterioration FF620 at the switching timing of the switch 610.

Next, when the read SA10 compares the current Io of the memory cell 20 with the read reference current Is, the output signal becomes a low level “0”. As a result, the AND circuit 630 sets the output signal FB to the low level "0", whereby the switch 610 maintains a state in which the read reference voltage V0 is output.

In this state, the memory cell 20 is in the writing state, but since the current Io is in the state of the deterioration detection reference Ix or less, it is not necessary to refresh with the deterioration improvement voltage V1, so that the read reference voltage V0 is applied. Is retained.

The same effect as that of the second embodiment can be obtained by such a fifth embodiment, and the read reference setting unit 30 and the deterioration detection reference setting unit 320 are switched by the switch 610 with respect to the read SA10. Since the configuration is such that switching connection is possible and the deterioration detection and the reading operation are performed serially, the deterioration detection SA310 can be omitted, and the circuit area can be saved.

(Sixth Embodiment)
16 and 17 show the sixth embodiment, and the parts different from the first embodiment will be described below. In this embodiment, instead of the non-volatile semiconductor storage device 200 shown in FIG. 4, the non-volatile semiconductor storage device 700 has a configuration in which a deterioration improving voltage is applied by utilizing the falling timing within one cycle of the clock CLK. There is.

As shown in FIG. 16, the non-volatile semiconductor storage device 700 has a configuration in which a switch 42 and a normal voltage setting unit 43 are provided as a voltage setting circuit 710 instead of the voltage setting circuit 40. In this embodiment, instead of the deterioration improvement voltage setting unit 44, the voltage of the DC power supply VD can be directly applied to the memory cell 20 as the deterioration improvement voltage via the switch 42. The voltage of the DC power supply VD is higher than the read reference voltage V0 and higher than the deterioration improvement voltage V1.

The output signal FB given to the switch 42 is output from the AND circuit 720. In the AND circuit 720, an output signal is given from the reading SA10 via the FF (flip-flop) circuit 730, and a signal in which the clock CLK is inverted is given from the clock circuit 740.

In the above configuration, when the switch 42 is connected to the DC power supply VD side, the memory cell 20 is not connected to the inverting input terminal of the reading SA10. Therefore, since the output of the read SA10 becomes undefined, the output state of the read SA10 is stored in the read FF60 and FF730 at the rising timing of the clock CLK.

Further, by storing the output signal of the read SA10 in the read FF60 and FF730, the output signal FB of the AND circuit 720 becomes "0" when both the FF730 and the clock CLK are "1". , A clock circuit 740 is provided. Thereby, in this embodiment, the precharge circuit 50 can be omitted.
Next, the operation of the above configuration will be described with reference to FIG.

First, the output signal FB of the AND circuit 720 is undefined until the rising point t0 of the clock CLK, but at the rising timing t0 of the clock signal CLK, the output signal of “1” of the FF730 and the “0” of the clock circuit 740 The low level "0" output signal FB is output by the clock signal of.

As a result, the switch 42 is connected to the memory cell 20 side, the read reference voltage V0 is applied to the gate of the MOS transistor 41, and the read operation is performed until the falling timing of the clock CLK. The read SA10 compares the current Io of the memory cell 20 with the read reference current Is from the read reference setting unit 30, and then stores the result in the read FF60 and FF730 at the falling timing of the clock CLK. ..

Here, the read SA10 stores the read result as “0” in the erased state of the memory cell 20 and “1” in the read state, and holds the read result until the rising timing t1 of the next clock CLK. As a result, when a high level "1" clock signal is output from the clock circuit 720 at the falling timing of the clock CLK, the AND circuit 720 inputs the contents stored in the FF 730 and switches this as an output signal FB. Give to 42.

When the memory cell 20 is in the erased state, the output signal FB of the AND circuit 720 remains at the low level “0”, so that the state in which the read reference voltage V0 is applied to the gate of the MOS transistor 41 is maintained.

On the other hand, when the memory cell 20 is in the writing state, the output signal FB of the AND circuit 720 changes to the high level "1", so that the switch 42 is switched and the DC power supply VD is applied to the memory cell 20. It continues until the rising timing of the next clock CLK. As a result, the memory cell 20 in the written state is refreshed by the DC voltage VD, and deterioration is suppressed.

In such a sixth embodiment, when the memory cell 20 is in the writing state, a DC voltage VD is applied to the memory cell 20 instead of the deterioration improvement voltage V1 to improve the deterioration, so that the deterioration improvement voltage is MOS. A high voltage can be applied while avoiding a value reduced by the gate-source voltage Vgs of the transistor 41.

In this embodiment, it is effective when the read operation is sufficiently fast, and if the read operation is completed at the falling timing of the clock CLK, that is, the rising timing of the output signal of the clock circuit 740, the drain terminal of the memory cell 20 is reached. By making it possible to directly apply the high voltage of the DC power supply VD as the deterioration improvement voltage, it is possible to improve the deterioration by the power supply voltage VD which is as high as possible.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and can be applied to various embodiments without departing from the gist thereof. For example, the present invention can be modified or extended as follows.

In each of the above embodiments, an example in which an N-channel type MOS transistor is used as the memory cell 20 is shown, but the same concept may be applied to a memory cell 20 using a P-channel type MOS transistor. Can be done.

Although the present disclosure has been described in accordance with the examples, it is understood that the present disclosure is not limited to the examples and structures. The present disclosure also includes various modifications and modifications within an equal range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are also within the scope of the present disclosure.

In the drawings, 10 and 70 are read SAs (read sense amplifiers), 20, 20a and 20b are memory cells (memory elements), 21 are memory cell transistors, 22 are selection transistors, and 30 are read reference setting units, 40, 510 and 710 are voltage setting circuits, 41 are MOS transistors, 42, 42a, 42b, 610 and 715 are switches, 43 is a normal voltage setting unit, 44 is a deterioration improvement voltage setting unit (first deterioration improvement voltage setting unit), 45. Is a second deterioration improvement voltage setting unit, 50 is a precharge circuit, 60 is a read FF, 100, 200, 300, 400, 500, 600, 700 are non-volatile semiconductor storage devices, and 310 is a deterioration detection SA (deterioration detection). Sense amplifier), 320 is the deterioration detection reference setting unit, 330, 630, 720 is the AND circuit (logic circuit), 430 is the MOS transistor, 450 is the resistor, 620 is the deterioration FF (memory circuit), 730 is the FF (memory). Circuit), 740 is a clock circuit.

Claims (6)

A non-volatile semiconductor storage device that is electrically capable of writing and erasing data to memory elements (20, 20a, 20b).
A reading sense amplifier (10, 70) that detects whether the memory element is in a writing state or an erasing state based on a comparison with a reading standard and outputs an output signal.
When reading the data of the memory element, the normal read voltage is set as the read voltage, and the deterioration improvement voltage higher than the normal read voltage is set as the read voltage applied to the memory element based on the output signal. Equipped with a voltage setting circuit (40, 510, 710)
The reading sense amplifier is
When the normal read voltage is applied to the memory element by the voltage setting circuit,
When the memory element is an N-channel type MOS transistor, it is determined that the current of the memory element is below the read reference and is in the write state, and when the current of the memory element is larger than the read reference, it is in the erase state. Judge,
When the memory element is a P-channel type MOS transistor, it is determined that the current of the memory element is equal to or higher than the read reference and is in the write state, and when the current of the memory element is smaller than the read reference, it is in the erase state. Judge,
In the read operation after the determination, when the memory element is in the erase state, the normal read voltage application state is continued, and when the memory element is in the write state, an output signal is sent to the voltage setting circuit. A non-volatile semiconductor storage device that is given and switched to an applied state of the deterioration improvement voltage. The memory element is connected to the terminal of the reading sense amplifier to which the memory element is connected, and the output state of the memory element before reading is fixed to a logical level indicating an erasing state in response to a reading command given from the outside. The non-volatile semiconductor storage device according to claim 1, further comprising a precharge circuit (50) for setting a potential to a read sense amplifier. Deterioration detection sense amplifier (310) that determines whether the memory element is in a deteriorated state or a non-deteriorated state based on a comparison between the current of the memory element and the deterioration detection standard by the deterioration detection standard setting unit (320). )When,
A logic circuit (330) to which each detection signal of the read sense amplifier and the deterioration detection sense amplifier is input and an output signal is given to the voltage setting circuit is provided.
The logic circuit
When the memory element is an N-channel type MOS transistor, the read sense amplifier determines that the memory element is in a writing state, and the deterioration detection sense amplifier determines a current value larger than the deterioration detection reference. When it is determined, the output signal is given to the voltage setting circuit so that the read operation after the determination performs reading by the deterioration improving voltage.
When the memory element is a P-channel type MOS transistor, the read sense amplifier determines that the memory element is in a writing state, and the deterioration detection sense amplifier determines a current value smaller than the deterioration detection reference. The non-volatile semiconductor storage device according to claim 1, wherein when the determination is made, the output signal is given to the voltage setting circuit to perform reading by the deterioration improving voltage in the reading operation after the determination. Deterioration detection sense that detects and outputs whether the memory element is in a deteriorated state or a non-deteriorated state based on a comparison between the current of the memory element and the deterioration detection standard of the deterioration detection standard setting unit (320). With the amplifier (310)
A logic circuit (330) to which each output of the deterioration detection sense amplifier and the reading sense amplifier is input is provided.
The voltage setting circuit (510)
It is configured to set the first deterioration improvement voltage and the second deterioration improvement voltage higher than this as the deterioration improvement voltage.
When the memory element is an N-channel type MOS transistor, the read voltage is set to the normal read voltage when the memory element is in the erased state, and the current of the memory element is equal to or less than the deterioration detection reference. The read voltage is set to the first deterioration improvement voltage, and when the current of the memory element is larger than the deterioration detection reference and is in the writing state, the read voltage is set to the second deterioration improvement voltage.
When the memory element is a P-channel type MOS transistor, the read voltage is set to the normal read voltage when the memory element is in the erased state, and the current of the memory element is equal to or higher than the deterioration detection reference. Claim 1 in which the read voltage is set to the first deterioration improvement voltage, and the read voltage is set to the second deterioration improvement voltage when the current of the memory element is smaller than the deterioration detection reference and is in the writing state. The non-volatile semiconductor storage device according to. A switch (610) that outputs either the read standard or the deterioration detection standard to the read sense amplifier, and
A storage circuit (620) that temporarily stores the comparison result when the current of the memory element is compared with the deterioration detection reference in the read sense amplifier.
In the read sense amplifier, a comparison result signal comparing the current of the memory element with the read reference and a comparison result signal stored in the storage circuit are input, and an output signal is given to the voltage setting circuit based on these. Equipped with a logic circuit (630)
The logic circuit
When the memory element is an N-channel type MOS transistor, the output signal is given to the voltage setting circuit when the memory element is in a writing state and the current of the memory element is equal to or higher than the deterioration detection reference. The read operation by the deterioration improvement voltage is continued, and when the memory element is in the erased state or the current of the memory element is smaller than the deterioration detection reference, the read operation is continued at the normal read voltage.
When the memory element is a P-channel type MOS transistor, the output to the voltage setting circuit is obtained when the memory element is in a writing state and the current of the memory element is equal to or less than the deterioration detection reference. A request for giving a signal to continue the read operation by the deterioration improvement voltage and continuing the read operation at the normal read voltage when the memory element is in the erased state or the current of the memory element is larger than the deterioration detection reference. Item 2. The non-volatile semiconductor storage device according to Item 1. A deterioration improving power supply that connects the memory element so as to perform reading by the reading sense amplifier and applies the deterioration improving voltage to the memory element in the writing state after the state determination by the reading sense amplifier. Switch (715) to connect to
A storage circuit (730) that stores the comparison result between the current of the memory element and the read reference in the read sense amplifier before the next read operation.
A logic circuit (720) for inputting a comparison result between the storage signal of the storage circuit and the reading sense amplifier and giving an output signal to the switch based on these is provided.
The logic circuit claims that when the memory element is in the writing state, after the reading operation by the reading sense amplifier is completed, an output signal for switching is given to the switch to connect the memory element to the deterioration improving power supply. Item 2. The non-volatile semiconductor storage device according to Item 1.

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