JP2021044709A - A/d conversion circuit, a/d conversion method, and semiconductor device - Google Patents

Abstract

To provide an A/D conversion circuit for correcting the offset of a comparison circuit.SOLUTION: According to one embodiment, an A/D conversion circuit includes an offset variable comparison circuit and a first control circuit. The offset variable comparison circuit includes a first input node, a second input node, an offset control node, and an output node. A comparison result of the comparing operation about the potential of the two input nodes is output from the output node. The first control circuit is connected to the output node and the offset control node. The first control circuit controls the offset voltage of the offset variable comparison circuit by supplying, to the offset control node, a control signal according to the comparison result of the comparing operation performed in an offset adjustment period overlapping with a sampling period of an analog signal to be a subject of the A/D conversion.SELECTED DRAWING: Figure 1

Description

The present embodiment relates to an A / D conversion circuit, a semiconductor device, and an A / D conversion method.

Conventionally, A / D (Analog-to-Digital) conversion in which the supplied analog signal is sampled by a sample hold circuit, and the sampling voltage output from the sample hold circuit is quantized by a comparator (comparison circuit) and converted into a digital signal. There is a circuit.

However, an offset may occur in the quantization by the comparator (comparison circuit). The offset of the comparison circuit deteriorates the conversion accuracy of the A / D conversion.

Japanese Unexamined Patent Publication No. 5-259909

One embodiment aims to provide an A / D conversion circuit, a semiconductor device, and an A / D conversion method for correcting the offset of the comparison circuit.

According to one embodiment, the A / D conversion circuit includes an offset variable comparison circuit and a first control circuit. The offset variable comparison circuit has a first input node, a second input node, an offset control node, and an output node. The comparison result of the comparison operation regarding the potentials of the two input nodes is output from the output node. The first control circuit is connected to the output node and the offset control node. The first control circuit supplies a control signal according to the comparison result of the comparison operation executed in the offset adjustment period overlapping the sampling period of the analog signal to be A / D converted to the offset control node. The offset voltage of the offset variable comparison circuit is controlled.

FIG. 1 is a diagram showing an example of the configuration of the A / D conversion circuit according to the embodiment. FIG. 2 is a diagram showing an example of the configuration of the offset variable comparison circuit of FIG. FIG. 3 is a diagram showing an example of the configuration of the offset correction control circuit of FIG. FIG. 4 is a diagram showing an example of the operation timing of the A / D conversion circuit of FIG. FIG. 5 is a diagram showing another example of the configuration of the offset variable comparison circuit of FIG. FIG. 6 is a diagram showing an example of the configuration of the semiconductor device having the A / D conversion circuit of FIG.

Hereinafter, the A / D conversion circuit, the semiconductor device, and the A / D conversion method according to the embodiment will be described in detail with reference to the accompanying drawings. The present invention is not limited to this embodiment.

(Embodiment)
Conventionally, in the comparison circuit of the A / D (Analog-to-Digital) conversion circuit, a preamplifier is provided in front of the dynamic comparator, and the comparator input voltage is such that the offset of the comparator in the latter stage does not appear in the A / D conversion characteristics during the comparison operation. There is a technique for correcting the offset of the comparator by amplifying the power with a preamplifier. There is also a configuration in which a preamplifier is not provided in the comparison circuit. For example, there is a technique for correcting the offset of a comparator by providing a circuit for adjusting the offset voltage with a digital value in a comparator (comparison circuit) and setting a digital value for correcting the offset voltage of the comparator in advance.

However, in the prior art, the power consumption increases by providing the preamplifier, and the A / D conversion speed decreases depending on the voltage amplification period of the preamplifier during the comparative operation. On the other hand, if the preamplifier is not provided in the comparison circuit with priority given to power consumption and A / D conversion speed, it is not possible to correct the offset fluctuation of the comparator (comparison circuit) caused by changes in the usage environment such as temperature and voltage.

Therefore, in the present embodiment, the offset is corrected by controlling the offset voltage of the comparator (comparison circuit) with a digital value during actual operation, and high-precision high-speed A / D conversion is realized.

Hereinafter, the A / D conversion circuit, the semiconductor device, and the A / D conversion method according to the embodiment will be described by taking the case of performing the Successive Approximation Register (SAR) type A / D conversion as an example.

FIG. 1 is a diagram showing an example of the configuration of the A / D conversion circuit 10 according to the embodiment. As shown in FIG. 1, the A / D conversion circuit 10 includes an offset variable comparison circuit 11, a voltage generation circuit 12, an offset correction control circuit 15, and a D / A (Digital-to-Analog) conversion circuit for A / D conversion. 17. It has an A / D conversion control circuit 18, a plurality of switches SSW, DSW, CSWIN, CSWP, and a plurality of capacitive elements CS1 and CS2. Here, the voltage generation circuit 12 is an example of an equipotential circuit. The offset correction control circuit 15 is an example of the first control circuit. The A / D conversion control circuit 18 is an example of the second control circuit. The switch CSWAN is an example of the first switch. The switch CSWP is an example of a second switch. The capacitive element CS1 is an example of the first capacitive element. The capacitive element CS2 is an example of a second capacitive element.

The A / D conversion circuit 10 charges the input analog signal AIN to the capacitive element CS1 and compares the charged sampling voltage with the reference voltage by the offset variable comparison circuit 11 to quantify the input analog signal AIN. This is a circuit that outputs a digital signal DOUT corresponding to the input analog signal AIN.

As shown in FIG. 1, the A / D conversion circuit 10 is provided with an offset correction control circuit 15 that digitally controls the offset voltage of the offset variable comparison circuit 11 during the actual operation of the A / D conversion. The offset correction control circuit 15 searches for a digital code in which the offset voltage of the offset variable comparison circuit 11 becomes zero during the sampling operation during the actual operation of the A / D conversion. The digital code search is, for example, an operation similar to the sequential comparison operation of A / D conversion. The offset correction control circuit 15 adjusts the offset voltage of the offset variable comparison circuit 11 during the sampling operation according to the obtained digital code.

As described above, in the actual operation of the A / D conversion circuit 10 according to the present embodiment, the offset voltage of the offset variable comparison circuit 11 is controlled by a digital value during the sampling period, so that the offset variable comparison circuit 11 is used during the conversion period. Since the offset is corrected, high-precision high-speed A / D conversion can be realized.

Hereinafter, the A / D conversion circuit 10 according to the present embodiment will be described in more detail.

The offset variable comparison circuit 11 is a circuit that compares the sampling voltage charged in the capacitance element CS1 with the reference voltage (ground potential) charged in the capacitance element CS2 and outputs the comparison result. Details of the offset variable comparison circuit 11 will be described later (see FIG. 2).

The voltage generation circuit 12 is a circuit that generates a predetermined voltage for offset correction. The output node of the voltage generation circuit 12 is electrically connected to the first input node INN of the offset variable comparison circuit 11 via the switch CSWAN. Further, the output node of the voltage generation circuit 12 is electrically connected to the second input node INP of the offset variable comparison circuit 11 via the switch CSWP. Further, a control signal is input to the voltage generation circuit 12 from the A / D conversion control circuit 18.

The offset correction control circuit 15 is a circuit that determines the control value (digital code) of the offset correction analog circuit 14 of the offset variable comparison circuit 11 during the sampling operation of the A / D conversion. Further, the offset correction control circuit 15 is a circuit that supplies the determined control value (digital code) to the offset control node CTL of the offset variable comparison circuit 11. Details of the offset correction control circuit 15 will be described later (see FIG. 3).

The D / A conversion circuit 17 for A / D conversion is a circuit that converts an input digital signal (digital code) into an analog signal and supplies the converted analog signal to the capacitive element CS1. The digital code is supplied from the A / D conversion control circuit 18. The D / A conversion circuit 17 is electrically connected to the A / D conversion control circuit 18. Further, the D / A conversion circuit 17 is electrically connected to the capacitance element CS1 via the switch DSW.

The A / D conversion control circuit 18 is a circuit that outputs a plurality of bit values from the MSB to the LSB output by the offset variable comparison circuit 11 as a digital signal DOUT. Further, the A / D conversion control circuit 18 is a control signal (φ0, φ1, φ2, which controls an offset variable comparison circuit 11, a voltage generation circuit 12, an offset correction control circuit 15, and a plurality of switches SSW, DSW, CSWIN, CSWP. This is a circuit that outputs (including φSSW, φDSW, φCSWIN, and φCSWP). The A / D conversion control circuit 18 outputs the output node COMPOUT of the offset variable comparison circuit 11, the input node of the D / A conversion circuit 17 for A / D conversion, and the A / D converted input signal (digital signal DOUT). It is electrically connected to the node. Further, the A / D conversion control circuit 18 is electrically connected to the offset variable comparison circuit 11, the voltage generation circuit 12, the offset correction control circuit 15, and a plurality of switches SSW, DSW, CSWIN, CSWP.

The switch SSW is a switch that switches between an on state and an off state according to the switching signal φSSW supplied from the A / D conversion control circuit 18. One end of the switch SSW is electrically connected to the input node of the analog signal (input signal AIN) to be A / D converted, the other end is electrically connected to the capacitive element CS1, and the control node is A / D converted. It is electrically connected to the control circuit 18.

The switch DSW is a switch that switches between an on state and an off state according to the switching signal φDSW supplied from the A / D conversion control circuit 18. One end of the switch DSW is electrically connected to the output node of the D / A conversion circuit 17, the other end is electrically connected to the capacitive element CS2, and the control node is electrically connected to the A / D conversion control circuit 18. Be connected.

The switch CSWAN is a switch that switches between an on state and an off state according to the switching signal φCSWAN supplied from the A / D conversion control circuit 18. Specifically, one end of the switch CSWAN is electrically connected to the output node of the voltage generation circuit 12, the other end is electrically connected to the capacitance element CS1, and the control node is electrically connected to the A / D conversion control circuit 18. It is electrically connected. Further, the switch CSWP is a switch that switches between an on state and an off state according to the switching signal φCSWP supplied from the A / D conversion control circuit 18. Specifically, one end of the switch CSWP is electrically connected to the output node of the voltage generation circuit 12, the other end is electrically connected to the capacitive element CS2, and the control node is electrically connected to the A / D conversion control circuit 18. It is electrically connected. The control nodes of the plurality of switches CSWAN and CSWP may be electrically connected to the offset correction control circuit 15. In other words, even if the switching signals φCSWIN and φCSWP are generated by the offset correction control circuit 15 in response to the control signal from the A / D conversion control circuit 18 and supplied to the switches CSWAN and CSWP from the offset correction control circuit 15, for example. Good.

The plurality of capacitance elements CS1 and CS2 are sampling capacitances for storing the charges of the supplied analog signals. One end of the capacitive element CS1 is electrically connected to the switch SSW and the switch DSW, and the other end is electrically connected to the switch CSWAN and the first input node INN. One end of the capacitive element CS2 is electrically connected to a node having a ground potential (a ground wire to which a reference potential is supplied), and the other end is electrically connected to a switch CSWP and a second input node INP.

Here, the offset variable comparison circuit 11 according to the embodiment will be described in more detail. FIG. 2 is a diagram showing an example of the configuration of the offset variable comparison circuit 11 of FIG.

As shown in FIGS. 1 and 2, the offset variable comparison circuit 11 further includes a comparison circuit (comparator) 111 and an offset correction analog circuit 14. Further, the offset variable comparison circuit 11 is provided with a first input node INN, a second input node INP, an offset control node CTL, and an output node COMPOUT. Here, the offset correction analog circuit 14 is an example of an offset adjustment circuit.

A predetermined voltage supplied from the voltage generation circuit 12 is applied to the first input node INN via the switch CSWAN during the sampling period during actual operation. Further, the sampling voltage charged in the capacitive element CS1 is applied to the first input node INN during the conversion period during actual operation. Specifically, the first input node INN is an inverting input terminal (−). The first input node INN is electrically connected to the capacitive element CS1.

A predetermined voltage supplied from the voltage generation circuit 12 is applied to the second input node INP via the switch CSWP during the sampling period during actual operation. Further, the reference voltage charged in the capacitive element CS2 is applied to the second input node INP during the conversion period during actual operation. Specifically, the second input node INP is a non-inverting input terminal (+). The second input node INP is electrically connected to the capacitive element CS2.

A digital control signal (digital code) is input from the offset correction control circuit 15 to the offset control node CTL. The input control signal is supplied to the offset correction analog circuit 14. Specifically, the offset control node CTL is electrically connected to the output node of the offset correction control circuit 15 and the offset correction analog circuit 14.

The output node COMPOUT outputs the amplification result (high level or low level signal) by the comparison circuit 111, that is, the comparison result by the offset variable comparison circuit 11. The output comparison result is supplied to the input node of the offset correction control circuit 15 during the sampling period during actual operation, and is supplied to the input node of the A / D conversion control circuit 18 during the conversion period during actual operation. Specifically, the output node COMPOUT is electrically connected to the input node of the offset correction control circuit 15 and the input node of the A / D conversion control circuit 18.

The comparison circuit 111 is a differential amplifier circuit that compares the voltage applied to the first input node INN with the voltage applied to the second input node INP. The amplification operation of the comparison circuit 111 is adjusted by the offset correction analog circuit 14. The comparison circuit 111 amplifies according to the clocks φ1 (φ11, φ12, φ13, φ14) and φ2 (φ21, φ22, φ23, φ24) input from the A / D conversion control circuit 18 via the clock input node CLK. To start. Specifically, the comparison circuit 111 is electrically connected to the first input node INN, the second input node INP, the output node COMPOUT, the clock input node CLK, and the offset correction analog circuit 14. More specifically, as shown in FIG. 2, the comparison circuit 111 includes a first analog control node ACTL_N, a second analog control node ACTL_P, a plurality of NMOS transistors NM1, NM2, NM3, NM4, NM5, and a plurality of NMOS transistors. It has a MOSFET transistors PM1, PM2, PM3, PM4, PM5, PM6.

The first analog control node ACTL_N is an analog node for offset adjustment provided on the negative electrode side of the comparison circuit 111, and the second analog control node ACTL_P is an offset provided on the positive electrode side of the comparison circuit 111. It is an analog node for adjustment. The two analog control nodes ACTL_N and ACTL_P are electrically connected to the offset correction analog circuit 14.

In the NMOS transistor NM1, the gate is electrically connected to the clock input node CLK, the source is electrically connected to the node having the ground potential, and the drain is electrically connected to each source of the NMOS transistors NM2 and NM3.

In the NMOS transistor NM2, the gate is electrically connected to the first input node INN, the source is electrically connected to the drain of the NMOS transistor NM1 and the source of the NMOS transistor NM3, and the drain is the drain of the NMOS transistor PM5, the second. It is electrically connected to the gate of the analog control node ACTL_P and the MOSFET transistor PM1.

In the NMOS transistor NM3, the gate is electrically connected to the second input node INP, the source is electrically connected to the drain of the NMOS transistor NM1 and the source of the NMOS transistor NM2, and the drain is the drain of the NMOS transistor NM6, the first. It is electrically connected to the gate of the analog control node ACTL_N and the MOSFET transistor PM2.

In the NMOS transistor NM4, the gate is electrically connected to the gate of the NMOS transistor PM4, the source is electrically connected to the node where the ground potential is reached, and the drain is electrically connected to the drain of the NMOS transistor PM3.

In the NMOS transistor NM5, the gate is electrically connected to the gate of the NMOS transistor PM3, the source is electrically connected to the node where the ground potential is reached, and the drain is electrically connected to the drain of the NMOS transistor PM4.

In the MOSFET transistor PM1, the gate is electrically connected to the drain of the NMOS transistor NM2, the drain of the NMOS transistor PM5, and the second analog control node ACTL_P, the source is electrically connected to the node where the power supply potential is obtained, and the drain is epitaxial. It is electrically connected to the source of the transistor PM3.

In the MOSFET transistor PM2, the gate is electrically connected to the drain of the NMOS transistor NM3, the drain of the NMOS transistor PM6, and the first analog control node ACTL_N, and the source is electrically connected to the node where the power supply potential is obtained, and the drain is electrically connected to the MOSFET. It is electrically connected to the source and output nodes COMPOUT of the transistor PM4.

In the NMOS transistor PM3, the gate is electrically connected to the gate of the NMOS transistor NM5, the source is electrically connected to the drain of the NMOS transistor PM1, and the drain is electrically connected to the drain of the NMOS transistor NM4.

In the NMOS transistor PM4, the gate is electrically connected to the gate of the NMOS transistor NM4, the source is electrically connected to the drain of the NMOS transistor PM2 and the output node COMPOUT, and the drain is electrically connected to the drain of the NMOS transistor NM5. To.

In the MOSFET transistor PM5, the gate is electrically connected to the clock node CLK, the source is electrically connected to the node where the power potential becomes, and the drain is the drain of the NMOS transistor NM2, the gate of the NMOS transistor PM1, and the second analog control. It is electrically connected to the node MOSFET_P.

In the MOSFET transistor PM6, the gate is electrically connected to the clock node CLK, the source is electrically connected to the node where the power potential becomes, and the drain is the drain of the NMOS transistor NM3, the gate of the NMOS transistor PM2, and the first analog control. It is electrically connected to the node MOSFET_N.

The offset correction analog circuit 14 is a circuit that adjusts the offset voltage of the comparison circuit 111. More specifically, in the offset correction analog circuit 14, a control value (digital code) is input from the offset correction control circuit 15 via the offset control node CTL. The offset correction analog circuit 14 is a circuit that changes the offset voltage of the comparison circuit 111 according to the supplied digital code. From this, the offset correction analog circuit 14 can also be expressed as a D / A conversion circuit for offset correction. Specifically, the offset correction analog circuit 14 includes an offset adjusting circuit having a variable capacitance and an offset adjusting circuit having a fixed capacitance.

The capacity-variable offset adjustment circuit is a circuit that changes the offset voltage of the comparison circuit 111 according to the digital code input from the offset correction control circuit 15 via the offset control node CTL. Specifically, the variable capacitance offset adjustment circuit is provided on the second input node INP (non-inverting input (+)) side of the comparison circuit 111. More specifically, the variable capacitance offset adjustment circuit is connected to the second analog control node ACTL_P of the comparison circuit 111. The variable capacitance offset adjustment circuit has a plurality of capacitance elements C1, C2, C3, C4 and a plurality of switches SW1, SW2, SW3, SW4.

The plurality of capacitance elements C1, C2, C3, and C4 are capacitances for storing electric charges supplied from the comparison circuit 111. For example, binary weighting is applied to the four capacitive elements C1, C2, C3, and C4. As an example, the capacitance ratio of the four capacitive elements C1, C2, C3, and C4 is C1: C2: C3: C4 = 8: 4: 2: 1. Specifically, one end of each of the plurality of capacitive elements C1, C2, C3, and C4 is electrically connected to the drain of the NMOS transistor NM3 of the comparison circuit 111 and the gate of the NMOS transistor PM2. The other end of the capacitive element C1 is electrically connected to the switch SW1. The other end of the capacitive element C2 is electrically connected to the switch SW2. The other end of the capacitive element C3 is electrically connected to the switch SW3. The other end of the capacitive element C4 is electrically connected to the switch SW4.

The plurality of switches SW1, SW2, SW3, and SW4 electrically connect / disconnect the plurality of capacitive elements C1, C2, C3, and C4 to the node (ground wire to which the reference potential is supplied) that becomes the ground potential. It is a switch to switch. Each of the plurality of switches SW1, SW2, SW3, and SW4 operates according to the value (switching signal) of each bit of the digital code supplied from the offset correction control circuit 15 via the offset control node CTL. Specifically, the switch SW1 is provided between the capacitance element C1 and the ground wire, and operates in response to the switching signal φSW1. The switch SW2 is provided between the capacitance element C2 and the ground wire, and operates in response to the switching signal φSW2. The switch SW3 is provided between the capacitance element C3 and the ground wire, and operates in response to the switching signal φSW3. The switch SW4 is provided between the capacitance element C4 and the ground wire, and operates in response to the switching signal φSW4. As the plurality of switches SW1, SW2, SW3, and SW4, for example, a MOS transistor in which each control node (gate) is connected to the offset control node CTL can be used.

The capacity-fixed offset adjustment circuit is provided on the first input node INN (inverted input (−)) side of the comparison circuit 111. Specifically, the offset adjustment circuit having a fixed capacitance is connected to the first analog control node ACTL_N of the comparison circuit 111. The capacity-fixed offset adjustment circuit has a capacitance element C5. The capacitance element C5 is a capacitance for storing the electric charge supplied from the comparison circuit 111. Specifically, one end of the capacitive element C5 is electrically connected to the drain of the NMOS transistor NM2 of the comparison circuit 111 and the gate of the NMOS transistor PM1, and the other end is electrically connected to the node having the ground potential. ..

Here, the offset correction control circuit 15 according to the embodiment will be described in more detail. FIG. 3 is a diagram showing an example of the configuration of the offset correction control circuit 15 of FIG.

As shown in FIG. 1, the offset correction control circuit 15 is electrically connected to the output node COMPOUT and the offset control node CTL of the offset variable comparison circuit 11. Further, a control signal is input to the offset correction control circuit 15 from the A / D conversion control circuit 18.

The offset correction control circuit 15 is a circuit that determines the adjustment amount of the amplification operation by the offset correction analog circuit 14. More specifically, the offset correction control circuit 15 is a circuit that determines a control value (digital code) for the offset correction operation and supplies the determined digital code to the offset correction analog circuit 14. Specifically, as shown in FIG. 3, the offset correction control circuit 15 includes a clock generation circuit 151, a sequential comparison register 152, and an output register 153.

Clocks (control signals) φ0 and φ1 (φ11, φ12, φ13, φ14) are input to the clock generation circuit 151 from the A / D conversion control circuit 18. The clock generation circuit 151 is a circuit that generates a clock according to the input clocks φ0 and φ1 and supplies the generated clock to the sequential comparison register 152 or the output register 153. Specifically, the clock generation circuit 151 has a plurality of output nodes, and the plurality of output nodes are electrically connected to the plurality of input nodes and the output register 153 of the sequential comparison register 152.

The sequential comparison register 152 determines the value in order from the high-order bit according to the comparison result output from the output node COMPOUT of the offset variable comparison circuit 11 in synchronization with the clock supplied from the clock generation circuit 151. It is a circuit that controls. Specifically, the sequential comparison register 152 is electrically connected to the output node COMPOUT of the offset variable comparison circuit 11, the plurality of output nodes of the clock generation circuit 151, and the plurality of input nodes of the output register 153.

The output register 153 is a circuit that holds a plurality of bit values output from the registers of each stage of the sequential comparison register 152 and initial values of digital codes (control values) supplied to the offset correction analog circuit 14. Further, the output register 153 is a circuit that supplies a plurality of held bit values (digital codes) to the offset correction analog circuit 14 in synchronization with the clock supplied from the clock generation circuit 151. Specifically, the output register 153 is electrically connected to a plurality of output nodes of the sequential comparison register 152, a clock generation circuit 151, and a plurality of offset control nodes CTL of the offset correction analog circuit 14.

Here, an example of the operation of the A / D conversion circuit 10 according to the embodiment will be described. FIG. 4 is a diagram showing an example of the operation timing of the A / D conversion circuit 10 of FIG. FIG. 4 illustrates cycle 1 of one of a plurality of cycles of A / D conversion in actual operation. Each cycle includes a sampling period and a conversion period.

Hereinafter, a case where the A / D conversion control circuit 18 of the A / D conversion circuit 10 has a 4-bit sequential comparison register will be described as an example. In this case, the digital code (control value) supplied from the output register 153 to the offset correction analog circuit 14 is a 4-bit code, and the four switches SW1 and SW1 connected to the four capacitive elements C1, C2, C3, and C4. It shall indicate the ON / OFF state of SW2, SW3 and SW4. Here, in the example shown in FIG. 2, it is assumed that the four capacitive elements C1, C2, C3, and C4 store electric charges when the four switches SW1, SW2, SW3, and SW4 are in the ON state.

The number of bits of the digital code, that is, the adjustment gradation of the offset voltage by the offset correction analog circuit 14, can be appropriately set according to the required resolution (accuracy) of the offset correction and the voltage width that can be corrected. Here, the digital code (control value) can also be expressed as having a number of bits corresponding to the adjustment gradation of the offset voltage by the offset correction analog circuit 14.

First, the operation during the sampling period (t1 to t2, t3 to FIG. 4) will be described.

At timing t1, A / D conversion is started and sampling of the input signal AIN is started. Specifically, the A / D conversion control circuit 18 generates a high-level switching signal φSSW and supplies it to the control node of the switch SSW. The switch SSW transitions from the off state to the on state according to the supplied switching signal φSSW. The input signal AIN is input to the capacitive element CS1 while the switch SSW is in the ON state, and the sampling voltage is charged.

Further, at the timing t1, the offset correction operation is started. Specifically, the A / D conversion control circuit 18 generates a high-level switching signal φCSWIN and supplies it to the control node of the switch CSWAN. The switch CSWIN transitions from an off state to an on state according to the supplied switching signal φCSWAN. Further, the A / D conversion control circuit 18 generates a high-level switching signal φCSWP and supplies it to the control node of the switch CSWP. The switch CSWP transitions from an off state to an on state according to the supplied switching signal φCSWP. The voltage generation circuit 12 applies a predetermined voltage for offset correction to the opposite polarity sides of the capacitance elements CS1 and CS2, that is, the input nodes INN and INP of the offset variable comparison circuit 11 via the switches CSWAN and CSWP. The two capacitive elements CS1 and CS2 are charged with a predetermined voltage for offset correction supplied from the voltage generation circuit 12. In this way, the two input nodes INN and INP of the offset variable comparison circuit 11 become equipotential during the sampling period.

As a predetermined voltage for offset correction, for example, an intermediate voltage (common voltage) can be used, but it is a voltage at which the offset variable comparison circuit 11 operates, and the two input nodes INN and INP are equipotential. Any voltage will do.

Prior to the timing t11, the offset correction control circuit 15 sets the initial value of the offset voltage of the offset variable comparison circuit 11 by using the initial value of the digital code. The initial value of the digital code is held in, for example, the output register 153. As the initial value of the digital code, for example, the center value "1000 [bin]" can be used. Here, it is assumed that the center value is a digital code that does not generate an offset in the offset correction analog circuit 14 when the offset variable comparison circuit 11 is in an ideal state without an offset. Specifically, the A / D conversion control circuit 18 generates a clock φ0 in synchronization with, for example, a high-level switching signal φSSW, and supplies the clock φ0 to the clock generation circuit 151 of the offset correction control circuit 15. The clock generation circuit 151 generates a clock according to the input control signal φ0 and supplies it to the output register 153. The output register 153 supplies the initial value of the held digital code to the offset correction analog circuit 14 via the offset control node CTL according to the supplied clock. That is, the offset correction control circuit 15 sets the initial value of the digital code in the offset correction analog circuit 14. In the offset correction analog circuit 14, the states of the plurality of switches SW1, SW2, SW3, and SW4 are changed according to the initial value of the supplied digital code, and the initial value of the offset voltage according to the initial value of the digital code is set. To.

The setting of the initial value of the offset voltage of the offset variable comparison circuit 11, that is, the generation of the clock φ0 is not limited to the case of synchronizing with the high-level switching signal φSSW, but is synchronized with the high-level switching signals φCSWIN and φCSWP. It may be after these high level switching signals have been generated. Further, the initial value of the offset voltage of the offset variable comparison circuit 11 may be set before the sampling period is started.

At the timing t11, the offset variable comparison circuit 11 performs a comparison operation on the two equipotential input nodes INN and INP according to the clock φ11, and outputs the comparison result. The comparison result output here is a comparison result according to the offset of the offset variable comparison circuit 11 corresponding to the center value "1000 [bin]". After that, the offset correction control circuit 15 determines the digital code of the most significant bit based on the output result of the offset variable comparison circuit 11. Further, the offset correction control circuit 15 sets the second bit digital code to "1".

At the timing t12, the offset variable comparison circuit 11 performs a comparison operation in the same manner as the timing t11 according to the clock φ12, and outputs a comparison result. The comparison result output here is a comparison result according to the offset voltage of the offset variable comparison circuit 11 corresponding to the digital code in which the second bit is set to "1" prior to the timing t12. After that, the offset correction control circuit 15 determines the second bit digital code based on the output result of the offset variable comparison circuit 11.

The offset correction operation at the timings t13 and t14 is the same as the correction operation at the timing t12, and the offset correction control circuit 15 determines the digital code in order from the high-order bit based on the comparison result of the comparison operation according to the clocks φ13 and φ14. ..

As described above with reference to FIG. 4, the offset correction operation is preferably completed within the sampling period set to the required length according to the required accuracy of the A / D conversion. When the offset correction operation is completed within the sampling period, the offset-corrected A / D conversion can be performed without reducing the conversion speed of the A / D conversion. At this time, the offset adjustment period, which is the period during which the offset correction operation is executed, is a period within the sampling period. However, the offset adjustment period is not limited to the period within the sampling period. That is, the timing at which the offset correction operation is started may be the timing at the same time as the sampling start of the A / D conversion target, the timing before the sampling start, or the timing after the sampling start. You may. Further, the timing at which the offset correction operation ends may be the timing at the same time as the end of sampling of the A / D conversion target, the timing before the end of sampling, or the timing after the end of sampling. May be good. However, if the offset correction operation is executed before the start of sampling and / or after the end of sampling, the conversion speed of the A / D conversion is reduced by the offset adjustment period outside the sampling period. Even in this case, the decrease in the conversion speed of the A / D conversion can be suppressed by the amount of the offset adjustment period included in the sampling period. In other words, by executing the offset correction operation during the offset adjustment period that overlaps with the sampling period, it is possible to perform offset-corrected A / D conversion while suppressing a decrease in the conversion speed of the A / D conversion.

Next, the operation in the conversion period (t2 to t3 in FIG. 4) after the offset adjustment period will be described.

At the timing t2, the sampling of the input signal AIN is completed, and the quantization (comparison operation) regarding the sampled input signal AIN (sampling voltage) is started. Specifically, at the timing t2, the A / D conversion control circuit 18 generates a low-level switching signal φSSW and supplies it to the control node of the switch SSW. The switch SSW transitions from the on state to the off state according to the supplied switching signal φSSW. After that, the A / D conversion control circuit 18 generates the clock φ2 and starts the sequential comparison operation regarding the sampling voltage. In the example shown in FIG. 4, the case where the four clocks φ21, φ22, φ23, and φ24 are supplied to the 4-bit sequential comparison register at the four timings t21, t22, t23, and t24 is shown. The A / D conversion control circuit 18 supplies a control signal to the D / A conversion circuit 17 prior to the four timings t21, t22, t23, and t24, and generates a reference voltage according to the control signal. Further, the A / D conversion control circuit 18 generates a high-level switching signal φDSW and supplies it to the control node of the switch DSW to shift the switch DSW from the off state to the on state and use the generated reference voltage. It is supplied to the capacitive element CS1. In this way, in the offset variable comparison circuit 11 shown in FIG. 1, the sum of the sampling voltage and the reference voltage and the reference voltage (ground potential) are sequentially compared, and the input signal AIN (digital signal DOUT) converted to A / D is sequentially compared. ) Is output. Then, at timing t3, the next cycle is started.

As described above, in the offset correction control circuit 15, the offset of the offset variable comparison circuit 11 is calculated from the value of the output from the output node COMPOUT of the offset variable comparison circuit 11 (comparison result when the two input nodes are equal potential). The smallest digital code is searched from the high-order bit by a sequential comparison operation and determined. In other words, the offset correction control circuit 15 causes the offset variable comparison circuit 11 to perform a comparison operation for the number of times according to the number of bits of the digital code. When the offset correction analog circuit 14 and the offset correction control circuit 15 are configured with 4 bits as shown in FIG. 2, the digital code for offset correction can be determined by four comparison operations.

In the offset correction operation according to the embodiment, a preamplifier is provided in the front stage of the variable offset comparison circuit, the offset of the preamplifier is corrected by the auto-zero operation during the sampling period, and the offset of the comparison circuit in the latter stage is corrected by the amplification effect of the preamplifier during the comparison operation. Can be expressed as equivalent to performing auto-zero by digital operation with respect to the offset of the comparison circuit without providing a preamplifier, as opposed to the auto-zero method by analog operation, which is to reduce the size of the entire system.

As described above, the A / D conversion circuit 10 according to the embodiment controls the offset voltage of the offset variable comparison circuit 11 with a digital value during the offset adjustment period that overlaps with the sampling period of the A / D conversion target. An offset correction control circuit 15 for correcting the offset of the offset variable comparison circuit 11 is provided. In other words, the A / D conversion circuit 10 according to the embodiment has a variable offset by digitally controlling the offset voltage of the variable offset comparison circuit 11 during an offset adjustment period that overlaps the sampling period of the A / D conversion target. The offset of the comparison circuit 11 is corrected. More preferably, the A / D conversion circuit 10 according to the embodiment digitally controls the offset voltage of the offset variable comparison circuit 11 during the offset adjustment period within the sampling period of the A / D conversion target, thereby performing offset variable comparison. Correct the offset of the circuit 11. According to this configuration / method, high-precision and high-speed A / D conversion is realized.

More specifically, according to this configuration / method, since the offset voltage of the offset variable comparison circuit 11 is controlled by a digital value, the power consumption is low and the speed is high as compared with the A / D conversion using the preamplifier. A / D conversion can be realized.

Further, according to this configuration / method, the determined digital code need only be held in, for example, the output register 153 of the offset correction control circuit 15. That is, the process of subtracting the preset offset value from the A / D conversion result is unnecessary. Therefore, a high-speed A / D conversion can be realized as compared with the A / D conversion that requires the subtraction process.

Further, according to this configuration / method, since the offset correction operation is performed during the actual operation of the A / D conversion, the conversion operation of the A / D conversion can be performed only once. That is, it is not necessary to perform two A / D conversions such as performing A / D conversion of the reference voltage and obtaining an offset value in advance prior to A / D conversion during actual operation. Therefore, a high-speed A / D conversion can be easily realized as compared with the A / D conversion in the actual operation and the A / D conversion in which the A / D conversion of the reference voltage is required.

Further, according to this configuration / method, since the offset correction operation is performed during the actual operation of the A / D conversion, it is possible to correct the offset fluctuation due to changes in the usage environment such as temperature and voltage. The correction of the offset fluctuation contributes to the suppression of deterioration of the conversion accuracy of the A / D conversion. Therefore, a highly accurate A / D conversion can be realized as compared with the A / D conversion that performs the subtraction process of the preset offset value.

The number of bits of the digital code, that is, the adjustment gradation of the offset voltage by the offset correction analog circuit 14, can be appropriately set according to the required resolution (accuracy) and range of the offset correction.

For example, in the above embodiment, the case where the offset adjusting circuit of the offset correction analog circuit 14 with variable capacitance has four capacitive elements (adjustment gradation of 2 to the 4th power) has been described as an example, but the present invention is not limited to this. The number of capacitive elements included in the variable capacitance offset adjustment circuit may be one, may be a plurality of numbers of three or less, or may be a plurality of numbers of five or more.

For example, in the above embodiment, the four capacitive elements C1, C2, and C3 in which the second input node INP side (non-inverting input node (+) side) of the comparison circuit 111 of the offset variable comparison circuit 11 is binary weighted. , C4, that is, the case where the offset adjustment circuit (offset correction analog circuit 14) having a variable capacitance is provided has been described as an example, but the present invention is not limited to this. The offset adjustment circuit of the offset correction analog circuit 14 with variable capacitance may be provided on the first input node INN side (inverting input node (−) side) of the comparison circuit 111 of the offset variable comparison circuit 11. It may be provided in both of. FIG. 5 is a diagram showing another example of the configuration of the offset variable comparison circuit 11 of FIG. The offset variable comparison circuit 11 shown in FIG. 5 includes a first input node INN, a second input node INP, a clock input node CLK, an output node COMPOUT, a comparison circuit 111-1 and an offset correction analog circuit 14. Here, the comparison circuit 111-1 is another example of the comparison circuit 111, and in the following description, the comparison circuit 111-1 and the comparison circuit 111 may be referred to as the comparison circuit 111 without being distinguished from each other.

The comparison circuit 111-1 is electrically connected to two input nodes INN and INP, an output node COMPOUT and two offset adjustment circuits 14-1 and 14-2. More specifically, the comparison circuit 111-1 has a plurality of NMOS transistors NM11, NM12, NM13, NM14, NM15, and a plurality of NMOS transistors PM11, PM12.

In the NMOS transistor NM11, the gate is electrically connected to the clock input node CLK, the source is electrically connected to the node having the ground potential, and the drain is electrically connected to each source of the NMOS transistors NM12 and NM13.

In the NMOS transistor NM12, the gate is electrically connected to the second input node INP, the source is electrically connected to the drain of the NMOS transistor NM11, and the drain is connected to the source of the NMOS transistor NM14 and the first analog control node ACTL_N. It is electrically connected.

In the NMOS transistor NM13, the gate is electrically connected to the first input node INN, the source is electrically connected to the drain of the NMOS transistor NM11, and the drain is connected to the source of the NMOS transistor NM15 and the second analog control node ACTL_P. It is electrically connected.

The gate of the NMOS transistor NM14 is electrically connected to the gate of the NMOS transistor PM11, the drain of the NMOS transistor NM15, the drain of the NMOS transistor PM12, and the output node COMPOUT, and the source is the drain of the NMOS transistor NM12 and the first analog control node ACTL_N. The drain is electrically connected to the drain of the NMOS transistor PM11, the gate of the NMOS transistor PM12, and the gate of the NMOS transistor NM15.

In the NMOS transistor NM15, the gate is electrically connected to the gate of the NMOS transistor PM12, the drains of the NMOS transistor NM14 and the NMOS transistor PM11, and the source is electrically connected to the drain of the NMOS transistor NM13 and the second analog control node ACTL_P. The drain is electrically connected to the drain of the NMOS transistor PM12, the gate of the NMOS transistor PM11, the gate of the NMOS transistor NM14, and the output node COMPOUT.

In the NMOS transistor PM11, the gate is electrically connected to the gate of the NMOS transistor NM14, the drain of the NMOS transistor PM12, the drain of the NMOS transistor NM15, and the output node COMPOUT, and the source is electrically connected to the node where the power supply potential is obtained. Is electrically connected to the drain of the NMOS transistor NM14, the gate of the NMOS transistor PM12 and the gate of the NMOS transistor NM15.

In the NMOS transistor PM12, the gate is electrically connected to the gate of the NMOS transistor NM15, the drain of the NMOS transistor PM11 and the drain of the NMOS transistor NM14, the source is electrically connected to the node which becomes the power supply potential, and the drain is the NMOS transistor NM15. Is electrically connected to the drain of the NMOS transistor PM11, the gate of the NMOS transistor NM14, and the output node COMPOUT.

The offset correction analog circuit 14 includes a first offset adjustment circuit 14-1 and a second offset adjustment circuit 14-2. The first offset adjustment circuit 14-1 and the second offset adjustment circuit 14-2 are capacity-variable offset adjustment circuits, and are similar to, for example, the capacity-variable offset adjustment circuit of FIG. Specifically, the first offset adjustment circuit 14-1 and the second offset adjustment circuit 14-2 are comparison circuits according to the digital code input from the offset correction control circuit 15 via the offset control node CTL. This is a circuit that changes the offset voltage of 111-1.

The first offset adjustment circuit 14-1 is provided on the second input node INP (non-inverting input (+)) side of the comparison circuit 111-1. The first offset adjustment circuit 14-1 includes a plurality of capacitive elements C1-1, C2-1, C3-1, C4-1 and a plurality of switches SW1-1, SW2-1, SW3-1, SW4-1. Have. The plurality of capacitive elements C1-1, C2-1, C3-1, and C4-1 are similar to, for example, the four binary weighted capacitive elements C1, C2, C3, and C4 in FIG. 2, and the comparison circuit 111. It is the capacity to store the electric charge supplied from -1. One end of each of the plurality of capacitive elements C1-1, C2-1, C3-1, and C4-1 is electrically connected to the first analog control node ACTL_N. The other end of the capacitive element C1-1 is electrically connected to a node (ground wire) that becomes a ground potential via a switch SW1-1. The other end of the capacitive element C2-1 is electrically connected to a node (ground wire) that becomes a ground potential via a switch SW2-1. The other end of the capacitive element C3-1 is electrically connected to a node (ground wire) that becomes a ground potential via a switch SW3-1. The other end of the capacitive element C4-1 is electrically connected to a node (ground wire) that becomes a ground potential via a switch SW4-1. The plurality of switches SW1-1, SW2-1, SW3-1, and SW4-1 are switches that operate according to a switching signal (corresponding bit value of the digital code) supplied via the offset control node CTL. For example, it is the same as the plurality of switches SW1, SW2, SW3, SW4 in FIG. The switch SW1-1 operates in response to the switching signal φSW1-1. The switch SW2-1 operates in response to the switching signal φSW2-1. The switch SW3-1 operates in response to the -1 switching signal φSW3-1. The switch SW4-1 operates in response to the switching signal φSW4-1. As the plurality of switches SW1-1, SW2-1, SW3-1, and SW4-1, for example, a MOS transistor in which each control node (gate) is connected to the offset control node CTL can be used.

The second offset adjustment circuit 14-2 is provided on the first input node INN (inverted input (−)) side of the comparison circuit 111-1. The second offset adjustment circuit 14-2 includes a plurality of capacitive elements C1-2, C2-2, C3-2, C4-2 and a plurality of switches SW1-2, SW2-2, SW3-2, SW4-2. Have. Here, the second offset adjustment circuit 14-2 is the same as the first offset adjustment circuit 14-1. The plurality of capacitance elements C1-2, C2-2, C3-2, C4-2 are the same as the plurality of capacitance elements C1-1, C2-1, C3-1, C4-1, and the comparison circuit 111-1 It is the capacity to store the electric charge supplied from. The plurality of switches SW1-2, SW2-2, SW3-2, SW4-2 are the same as the plurality of switches SW1-1, SW2-1, SW3-1, SW4-1, and are via the offset control node CTL. It is a switch that operates according to the supplied switching signal (corresponding bit value of the digital code). One end of the plurality of capacitive elements C1-2, C2-2, C3-2, and C4-2 is electrically connected to the second analog control node ACTL_P. The other end of the capacitive element C1-2 is electrically connected to a node (ground wire) that becomes a ground potential via a switch SW1-2 that operates in response to a switching signal / φSW1-2. The other end of the capacitive element C2-2 is electrically connected to a node (ground wire) that becomes a ground potential via a switch SW2-2 that operates in response to a switching signal / φSW2-2. The other end of the capacitive element C3-2 is electrically connected to a node (ground wire) that becomes a ground potential via a switch SW3-2 that operates in response to a switching signal / φSW3-2. The other end of the capacitive element C4-2 is electrically connected to a node (ground wire) that becomes a ground potential via a switch SW4-2 that operates in response to a switching signal / φSW4-2.

In the offset correction operation, as the digital code (control value) for the first offset adjustment circuit 14-1 and the second offset adjustment circuit 14-2, one of the two offset adjustment circuits is described above. The digital code determined as described above may be used, and the other one may use the digital code of the opposite phase of the digital code determined as described above. Specifically, the digital code (/ φSW1-1, / φSW2-1, / φSW3-1, / φSW4-1) of the capacity-variable offset adjustment circuit provided on the first input node INN side is as described above. This is the opposite phase of the digital code (φSW1-1, φSW2-1, φSW3-1, φSW4-1) of the offset adjustment circuit with variable capacitance on the second input node INP side determined in. In this case, the digital code can be determined by the same number of comparison operations as when the variable capacitance offset adjustment circuit is provided on either side of the comparison circuit 111-1. The same applies to the case where offset adjustment circuits having variable capacitance are provided on both sides of the comparison circuit 111 of FIG. Of course, the offset adjustment circuits on both sides may be controlled independently by the value of each bit of at least one digital code. In other words, the technique according to this embodiment is not limited to the case where a reverse phase digital code is used.

Even with such a configuration, the same effect as that of the above-described embodiment can be obtained. Further, when the offset adjusting circuits having variable capacitance are provided on both sides of the comparison circuit 111, the range of the offset voltage that can be corrected in the offset correction can be increased.

In the above embodiment, as a method of changing the offset voltage of the offset variable comparison circuit 11, the comparison circuit 111 is divided by controlling the use / non-use of a plurality of capacitive elements with a plurality of switches (plurality of MOS transistors). The method of adjusting the load capacity (capacity compensation) has been described as an example, but the present invention is not limited to this. Each method shown below can be used as appropriate. In addition, each of the following methods can be used in combination as appropriate.

For example, a method in which a MOS transistor is used as a variable capacitance and the load capacitance of the comparison circuit 111 is adjusted (capacity compensation) by an offset correction analog circuit 14 having a plurality of binary-weighted MOS transistors can also be used.

Further, for example, there is also a method in which the load capacitance of the comparison circuit 111 is adjusted (capacity compensation) by an offset correction analog circuit 14 having at least one variable capacitance MOS transistor and a bias generation circuit that applies a bias voltage to the MOS transistor. It can be used. The bias generation circuit generates a bias voltage so that the capacitance corresponds to the determined control value (digital code), and changes the capacitance of the MOS transistor.

In the above embodiment, as a method of changing the offset voltage of the offset variable comparison circuit 11, a method of adjusting the load capacitance of the comparison circuit 111 (capacity compensation) by the offset correction analog circuit 14 has been described as an example. Not exclusively.

For example, it flows through the comparison circuit 111 by an offset correction analog circuit 14 having a bias generation circuit that applies a bias voltage (body voltage) to at least one of the two input nodes INN and INP according to a control value (digital code). A method of adjusting the amount of current (current compensation) can also be used.

Further, for example, with a transistor connected in parallel to at least one of the input differential pairs (NMOS transistors NM2, NM3 or NMOS transistors NM12, NM13 connected to the two input nodes INN, INP) of the comparison circuit 111. It is also possible to use a method of adjusting (current compensation) the amount of current flowing through the comparison circuit 111 by an offset correction analog circuit 14 having a bias generation circuit that applies the gate voltage of the transistor according to a control value (digital code). ..

Further, for example, a method of adjusting binary weighting (charge compensation) for a plurality of capacitance elements by an offset correction analog circuit 14 that injects charges into a plurality of capacitance elements according to a control value (digital code) can also be used. ..

In the offset adjusting circuit of the offset correction analog circuit 14, the capacitance of the plurality of capacitive elements is not limited to binary weighting. A plurality of capacitive elements having a plurality of capacitances may be appropriately used according to the required resolution (accuracy) and range of offset correction. For example, if you want to increase the resolution (larger adjustment gradation) for a part of the offset correction range, set a small difference in capacitance between a plurality of capacitive elements corresponding to that part of the range. Just do it.

Further, in the offset adjusting circuit of the offset correction analog circuit 14 whose capacitance is variable, the weighting of at least two capacitance elements among the plurality of capacitance elements may be set to be the same. For example, all the capacitance elements of the variable capacitance offset adjustment circuit may have the same capacitance, and in this case, the number of capacitance elements corresponding to the determined digital code may be used. Further, for example, some capacitance elements of the offset adjustment circuit having a variable capacitance may have the same capacitance. Capacitive elements having the same capacitance may be determined according to the required resolution (accuracy) and range of offset correction. For example, when it is desired to increase the resolution (increase the adjustment gradation) for a part of the offset correction range, a plurality of capacitive elements corresponding to the part of the range may have the same capacity.

In the above embodiment, the voltage generation circuit 12 connected to the two input nodes INN and INP via the switches CSWAN and CSWP is exemplified as the equipotential circuit, but the present invention is not limited to this. The equipotential circuit is electrically connected to the first input node INN and the second input node INP, and operates according to the control signal supplied from the offset correction control circuit 15 or the A / D conversion control circuit 18. A switch is also available. In this case, for example, the voltage generation circuit 12 may be connected to either one of the two input nodes INN and INP via one of the switches CSWAN and CSWP.

In the above embodiment, the case where the predetermined voltage for offset correction applied to the two input nodes INN and INP is common has been described as an example, but the present invention is not limited to this. For example, different voltages may be applied to the two input nodes INN and INP within an allowable range from the conversion accuracy required. Further, for example, if the above-mentioned offset correction operation is performed with a predetermined potential difference applied to the two input nodes INN and INP, an arbitrary bias (offset) corresponding to the predetermined potential difference is given to the A / D conversion result. It is also possible.

In the above embodiment, the sequential comparison type A / D conversion circuit has been described as an example, but the present invention is not limited to this. The technique according to the embodiment can be applied to other types of A / D conversion circuits such as parallel comparison type, follow-up comparison type, and ΔΣ type.

The A / D conversion method according to the above embodiment is expanded into a memory in a computer having a memory such as Read Only Memory (ROM) and Random Access Memory (RAM) and a processor such as a Central Processing Unit (CPU). It may be realized by the processor executing the executed program.

[Application example]
FIG. 6 is a diagram showing an example of the configuration of the semiconductor device 1 having the A / D conversion circuit 10 of FIG. As shown in FIG. 6, the semiconductor device 1 includes an A / D conversion circuit 10, a sensor circuit 20, and a processing circuit 30.

The sensor circuit 20 is a circuit that supplies an analog signal AIN to the capacitive element CS1 via the switch SSW. Specifically, the output node of the sensor circuit 20 is electrically connected to the input node of the A / D conversion circuit 10. As the sensor circuit 20, for example, various circuits / devices such as a temperature sensor, a humidity sensor, and a luminance sensor that output measured values as analog signals can be used. Instead of the sensor circuit 20, various circuits / devices that output analog signals according to the acquired / received values may be used.

The digital signal DOUT output by the A / D conversion circuit 10 is input to the processing circuit 30. The processing circuit 30 is a circuit that executes signal processing related to the input digital signal DOUT. Specifically, the input node of the processing circuit 30 is electrically connected to the output node of the A / D conversion circuit 10. As the processing circuit 30, various logic circuits capable of inputting digital signals such as Application Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (FPGA) can be used. As the processing circuit 30, a processor such as a CPU that executes a program expanded in a memory such as a ROM or RAM may be used.

According to at least one embodiment described above, the offset of the comparison circuit 111 (comparator) is corrected by controlling the offset voltage of the offset variable comparison circuit 11 with a digital value during the actual operation of the A / D conversion. A D conversion circuit, a semiconductor device, and an A / D conversion method can be provided.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 Semiconductor device, 10 A / D conversion circuit, 20 sensor circuit, 30 processing circuit, 11 offset variable comparison circuit, 12 voltage generation circuit (equalization circuit), 14, 14-1, 14-2 offset correction analog circuit ( Offset adjustment circuit), 15 offset correction control circuit (first control circuit), 17 D / A conversion circuit for A / D conversion, 18 A / D conversion control circuit (second control circuit), 111,111- 1 comparison circuit, 151 clock generation circuit, 152 sequential comparison register, 153 output register, ACTL_N first analog control node, ACTL_P second analog control node, CS1 capacitance element (first capacitance element), CS2 capacitance element (first) 2 capacitive elements), CSWIN switch (first switch), CSWP switch (second switch), CTL offset control node, COMPOUT output node, INN first input node, INP second input node.

Claims (19)

An offset variable comparison circuit having a first input node, a second input node, an offset control node, and an output node that outputs a comparison result of comparison operations relating to the potentials of the two input nodes.
A control signal connected to the output node and the offset control node and executed in an offset adjustment period overlapping the sampling period of the analog signal to be A / D converted is sent to the offset control node according to the comparison result of the comparison operation. An A / D conversion circuit including a first control circuit that controls the offset voltage of the offset variable comparison circuit by supplying the offset voltage. The offset variable comparison circuit is
A comparison circuit that executes the comparison operation that compares the potentials of the two input nodes, and
The A / D conversion circuit according to claim 1, further comprising an offset adjustment circuit connected between the comparison circuit and the offset control node and changing the offset voltage of the comparison circuit according to the control signal. The control signal is a digital code and
The first control circuit determines the bit value of the digital code according to the comparison result of the comparison operation executed during the offset adjustment period.
The A / D conversion circuit according to claim 2. The first control circuit is
A clock generation circuit that generates a clock and
The values are determined in order from the high-order bit according to the comparison result of the comparison operation executed in the offset adjustment period in synchronization with the clock connected to the output node and the clock generation circuit and supplied from the clock generation circuit. Sequential comparison register that performs sequential comparison control and
It is connected to the clock generation circuit and the sequential comparison register, holds the output of the sequential comparison register, and synchronizes with the clock supplied from the clock generation circuit, and the output of the sequential comparison register is used as the digital code to offset the output. The A / D conversion circuit according to claim 3, which has an output register to be supplied to the adjustment circuit. The digital code has a number of bits corresponding to the adjustment gradation of the offset voltage by the offset adjustment circuit.
The comparison circuit executes the comparison operation a number of times according to the number of bits of the digital code during the offset adjustment period.
The first control circuit sequentially determines the digital code in order from the high-order bit of the digital code during the offset adjustment period.
The A / D conversion circuit according to claim 3 or 4. The A according to any one of claims 2 to 5, wherein the offset adjustment circuit changes the offset voltage of the comparison circuit by at least one adjustment method of current compensation, capacitance compensation, and charge compensation. / D conversion circuit. The A / D conversion circuit according to any one of claims 2 to 5, wherein the offset adjustment circuit has at least one capacitance element that changes the offset voltage by capacitance compensation. The first control circuit controls the use or non-use of the at least one capacitive element according to the comparison result of the comparison operation executed during the offset adjustment period.
The A / D conversion circuit according to claim 7. The offset adjustment circuit has at least one capacitive element that changes the offset voltage by capacitance compensation.
The bit value of the digital code is a value indicating whether or not the corresponding capacitive element is used.
The A / D conversion circuit according to any one of claims 3 to 5. The A / D conversion circuit according to any one of claims 2 to 9, wherein the offset adjustment circuit is provided on one of the two input nodes of the comparison circuit. The A / D conversion circuit according to any one of claims 2 to 9, wherein the offset adjustment circuit is provided on both sides of the two input nodes of the comparison circuit. An equipotential circuit that is connected to the two input nodes via a switch that transitions to the ON state during the offset adjustment period and equipotentializes the two input nodes during the offset adjustment period is further provided.
The first control circuit controls the offset adjustment circuit according to the comparison result of the period in which the two input nodes are equipotentialized.
The A / D conversion circuit according to any one of claims 2 to 11. The A / D conversion circuit according to claim 12, wherein the equipotential circuit is a voltage generation circuit that generates a predetermined voltage to be supplied to the two input nodes. A second control circuit connected to the output node is further provided.
The offset variable comparison circuit is the A / D conversion target sampled during the sampling period in a state where the offset voltage of the offset variable comparison circuit is adjusted according to the control signal in the conversion period after the offset adjustment period. Performing the above comparison operation with respect to the analog signal of
The second control circuit determines a digital output signal corresponding to the analog signal to be A / D converted by using the comparison result of the comparison operation executed during the conversion period.
The A / D conversion circuit according to any one of claims 2 to 13. A D / A conversion circuit connected to the second control circuit is further provided.
The offset variable comparison circuit executes the comparison operation a number of times according to the number of bits of the digital output signal during the conversion period.
The second control circuit sequentially determines the digital output signal in order from the high-order bit of the digital output signal during the conversion period.
The D / A conversion circuit sequentially supplies an analog output signal corresponding to the sequentially determined digital output signal to the offset variable comparison circuit.
The A / D conversion circuit according to claim 14. The A / D conversion circuit according to any one of claims 1 to 15, wherein the offset adjustment period is a period within the sampling period. The A / D conversion circuit according to any one of claims 1 to 15, wherein the offset adjustment period is a period including a period before the start and / or after the end of the sampling period. An offset variable comparison circuit having a first input node, a second input node, an offset control node, and an output node for outputting a comparison result of comparison operations relating to the potentials of the two input nodes, and the output node. And in an A / D conversion circuit including a first control circuit connected to the offset control node.
During the offset adjustment period that overlaps with the sampling period of the analog signal to be A / D converted,
Performing the comparison operation by the offset variable comparison circuit and
The first control circuit controls the offset voltage of the offset variable comparison circuit by supplying a control signal according to the comparison result of the comparison operation executed during the offset adjustment period to the offset control node. A / D conversion method including. An offset variable comparison circuit having a first input node, a second input node, an offset control node, and an output node that outputs a comparison result of comparison operations relating to the potentials of the two input nodes.
A control signal connected to the output node and the offset control node and executed in an offset adjustment period overlapping the sampling period of the analog signal to be A / D converted is sent to the offset control node according to the comparison result of the comparison operation. It is connected to the output node with the first control circuit that controls the offset voltage of the offset variable comparison circuit by supplying the offset, and in the conversion period after the offset adjustment period, the offset of the offset variable comparison circuit is performed according to the control signal. An A / D conversion circuit having an output circuit that outputs a digital output signal corresponding to the analog signal to be A / D converted by using the comparison result of the comparison operation executed in a voltage-adjusted state.
A sensor circuit connected to the A / D conversion circuit and supplying the analog signal to be A / D converted to the A / D conversion circuit.
A semiconductor device including a processing circuit connected to the A / D conversion circuit and performing signal processing on the digital output signal.

Images