JP2021044447A - Carrier and method for manufacturing semiconductor device - Google Patents

Abstract

To provide a carrier and a method for manufacturing a semiconductor device, capable of suppressing the peeling of a support substrate before a peeling step during manufacture of a semiconductor device and capable of easily peeling a support substrate in the peeling step.SOLUTION: A carrier according to an embodiment includes a support substrate, a peeling layer provided above the support substrate, and a protective layer provided above the peeling layer. The support substrate has a central part including the center, and an outer peripheral part surrounding the central part. The peeling layer is provided above the central part. The protective layer has: a first portion provided above the peeling layer; and a second portion provided above the outer peripheral part and covering the outer peripheral end of the peeling layer.SELECTED DRAWING: Figure 1

Description

Embodiments of the present invention relate to methods of manufacturing carriers and semiconductor devices.

As a new packaging technology, FO-WLP (Fan Out Wafer Level Package) is being developed. In the manufacture of FO-WLP, after mounting processes such as wiring formation, mounting of semiconductor elements, and sealing are performed on a carrier having a supporting substrate, the supporting substrate is peeled off from the sealed product to obtain the sealed product. The package is completed by individualizing.

In the carrier used for manufacturing such FO-WLP, it is required that the peeling of the support substrate can be suppressed before the peeling step, and the support substrate can be easily peeled in the peeling step.

Japanese Unexamined Patent Publication No. 2018-56560

The problem to be solved by the present invention is a method for manufacturing a carrier and a semiconductor device, which can suppress the peeling of the support substrate before the peeling step at the time of manufacturing the semiconductor device and can easily peel the support substrate in the peeling step. To provide.

The carrier according to the embodiment includes a support substrate, a release layer provided on the support substrate, and a protective layer provided on the release layer. The support substrate has a central portion including a center and an outer peripheral portion surrounding the central portion. The release layer is provided on the central portion. The protective layer has a first portion provided on the peeling layer and a second portion provided on the outer peripheral portion and covering the outer peripheral end portion of the peeling layer.

1 (a) and 1 (b) are a plan view and a cross-sectional view schematically showing the carrier according to the embodiment. 2 (a) to 2 (d) are cross-sectional views schematically showing a method of manufacturing a carrier according to an embodiment. 3 (a) and 3 (b) are a plan view and a cross-sectional view schematically showing a carrier according to a modified example of the embodiment. 4 (a) to 4 (e) are cross-sectional views schematically showing a method of manufacturing a carrier according to a modified example of the embodiment. 5 (a) to 5 (e) are cross-sectional views schematically showing a manufacturing method of the semiconductor device according to the embodiment. 6 (a) to 6 (d) are cross-sectional views schematically showing a manufacturing method of the semiconductor device according to the embodiment. 7 (a) to 7 (d) are cross-sectional views schematically showing a manufacturing method of the semiconductor device according to the embodiment. 8 (a) to 8 (e) are cross-sectional views schematically showing a manufacturing method of a semiconductor device according to a modified example of the embodiment. 9 (a) to 9 (e) are cross-sectional views schematically showing a manufacturing method of a semiconductor device according to a modified example of the embodiment. 10 (a) to 10 (e) are cross-sectional views schematically showing a manufacturing method of a semiconductor device according to a modified example of the embodiment. 11 (a) to 11 (e) are cross-sectional views schematically showing a manufacturing method of a semiconductor device according to a modified example of the embodiment.

Hereinafter, each embodiment of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between the parts, etc. are not always the same as the actual ones. Even if the same part is represented, the dimensions and ratios of each may be represented differently depending on the drawing.
In the present specification and each figure, the same elements as those described above with respect to the above-mentioned figures are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.

1 (a) and 1 (b) are a plan view and a cross-sectional view schematically showing the carrier according to the embodiment.
FIG. 1B is a cross-sectional view taken along the line A1-A2 shown in FIG. 1A.

As shown in FIGS. 1A and 1B, the carrier 100 according to the embodiment is intermediate between the support substrate 10, the adhesion layer 20 provided on the support substrate 10, and the release layer 30. A layer 40 and a protective layer 50 are provided. Each layer is laminated in the order of the adhesion layer 20, the release layer 30, the intermediate layer 40, and the protective layer 50 from the support substrate 10 side.

In the specification of the present application, the stacking direction of each layer is the Z direction. The Z direction is the vertical direction. Further, the direction orthogonal to the Z direction is defined as the X direction, and the Z direction and the direction orthogonal to the X direction are defined as the Y direction.

The support substrate 10 is, for example, a silicon substrate or a glass substrate. The thickness of the support substrate 10 is larger than any of the thickness of the adhesion layer 20, the thickness of the release layer 30, the thickness of the intermediate layer 40, and the thickness of the protective layer 50. The thickness of the support substrate 10 is, for example, about 725 μm.

The shape of the support substrate 10 when viewed from the Z direction is, for example, circular. The diameter of the support substrate 10 when viewed from the Z direction is, for example, about 200 mm. The shape of the support substrate 10 when viewed from the Z direction may be, for example, a polygon such as a quadrangle. In this case, the diameter of the circumscribed circle of the support substrate 10 when viewed from the Z direction is, for example, about 200 mm.

The support substrate 10 has a central portion 10a and an outer peripheral portion 10b. The central portion 10a is a region including the center C1 of the support substrate 10 when viewed from the Z direction. The central portion 10a is, for example, a circular region centered on the center C1 of the support substrate 10 when viewed from the Z direction. The outer peripheral portion 10b is a region surrounding the central portion 10a. The outer peripheral portion 10b is, for example, an annular region including the edge of the support substrate 10 when viewed from the Z direction. The diameter of the central portion 10a when viewed from the Z direction is, for example, about 98% of the diameter of the support substrate 10 when viewed from the Z direction. For example, when the diameter of the support substrate 10 when viewed from the Z direction is 200 mm, the diameter of the central portion 10a when viewed from the Z direction is about 196 mm.

The adhesion layer 20 is provided on the support substrate 10. More specifically, the adhesion layer 20 is provided between the support substrate 10 and the release layer 30 in the Z direction. The adhesion layer 20 covers the entire upper surface of the central portion 10a of the support substrate 10. The adhesion layer 20 is provided only on the central portion 10a of the support substrate 10, for example, and is not provided on the outer peripheral portion 10b of the support substrate 10. In other words, the central portion 10a overlaps with the adhesion layer 20 in the Z direction, and the outer peripheral portion 10b does not overlap with the adhesion layer 20 in the Z direction. The diameter of the adhesion layer 20 when viewed from the Z direction is, for example, the same as the diameter of the central portion 10a when viewed from the Z direction.

The adhesion layer 20 improves the adhesion between the support substrate 10 and the release layer 30, for example. The adhesion layer 20 contains, for example, a metal or a metal oxide. The adhesion layer 20 includes, for example, Al, Ti, V, Cr, Fe, Co, Ni, Cu, Ge, Rb, Y, Zr, Nb, Mo, Rh, Pd, Ag, Sn, Sm, Gd, Dy, Er. , Hf, Ta, W, Re, Os, Ir, Pt, Au, Th, and a metal or oxide containing at least one selected from the group consisting of U. The adhesion layer 20 preferably contains Cu.

The adhesion layer 20 may be one layer or two or more layers. When the adhesion layer 20 is formed of two layers, the layer in contact with the support substrate 10 is formed of a material having high adhesion to the support substrate 10, and the layer in contact with the release layer 30 is made of a material having high adhesion to the release layer 30. It may be formed. Thereby, the adhesion between the support substrate 10 and the release layer 30 can be improved. When the adhesion layer 20 is formed of two layers, as another form, the layer in contact with the support substrate 10 is formed of a material having high adhesion to the support substrate 10, and the layer in contact with the release layer 30 is referred to as the release layer 30. It may be formed of a material having low adhesion. As a result, it becomes possible to peel off at the interface between the adhesion layer 20 and the peeling layer 30 with low stress at the time of peeling.

The thickness of the adhesion layer 20 is 1 μm or less, preferably 0.5 μm or less, for example, about 0.3 μm. When two or more adhesion layers 20 are formed, the thickness of each layer is preferably the above-mentioned thickness. The adhesion layer 20 is provided as needed and can be omitted.

The release layer 30 is provided on the support substrate 10. In this example, the release layer 30 is provided on the adhesion layer 20. More specifically, the release layer 30 is provided between the adhesion layer 20 and the intermediate layer 40 in the Z direction. The release layer 30 covers the entire upper surface of the adhesion layer 20. The release layer 30 is provided only on the central portion 10a of the support substrate 10, and is not provided on the outer peripheral portion 10b of the support substrate 10. In other words, the central portion 10a overlaps the release layer 30 in the Z direction, and the outer peripheral portion 10b does not overlap the release layer 30 in the Z direction. The diameter of the release layer 30 when viewed from the Z direction is the same as the diameter of the central portion 10a when viewed from the Z direction.

The release layer 30 is peeled off in the peeling step when manufacturing the semiconductor device. The release layer 30 contains, for example, carbon as a main component. The release layer 30 contains, for example, 80 atomic% or more of carbon atoms. The release layer 30 is made of, for example, amorphous carbon. By using such a material for the peeling layer 30, the peeling step can be performed by a method of forming a peeling trigger (breaking portion) in the peeling layer 30 with a knife or the like and mechanically peeling. Since the method of mechanically peeling does not use an expensive laser device or the like, the peeling step can be performed at a lower cost than the method of irradiating the peeling layer 30 with laser light to modify the material and peeling. it can.

The release layer 30 is one layer. The thickness of the release layer 30 is 1000 nm or less, preferably 100 nm or less, more preferably 10 nm or less, for example, several nm.

The intermediate layer 40 is provided on the release layer 30. More specifically, the intermediate layer 40 is provided between the release layer 30 and the protective layer 50 in the Z direction. The intermediate layer 40 covers the entire upper surface of the release layer 30. The intermediate layer 40 is provided only on the central portion 10a of the support substrate 10, for example, and is not provided on the outer peripheral portion 10b of the support substrate 10. In other words, the central portion 10a overlaps with the intermediate layer 40 in the Z direction, and the outer peripheral portion 10b does not overlap with the intermediate layer 40 in the Z direction. The diameter of the intermediate layer 40 when viewed from the Z direction is, for example, the same as the diameter of the central portion 10a when viewed from the Z direction.

The intermediate layer 40 improves the adhesion between the release layer 30 and the protective layer 50, for example. Further, the intermediate layer 40 suppresses alteration such as oxidation and moisture absorption of the peeling layer 30 and contamination of the peeling layer 30, for example. The intermediate layer 40 contains, for example, a metal or a metal oxide. As the material of the intermediate layer 40, the same material as that given as an example of the material of the adhesion layer 20 can be used. The intermediate layer 40 is made of, for example, the same material as the adhesion layer 20. The intermediate layer 40 preferably contains Cu.

The intermediate layer 40 may be one layer or two or more layers. When the intermediate layer 40 is formed of two layers, the layer in contact with the release layer 30 is formed of a material having high adhesion to the release layer 30, and the layer in contact with the protective layer 50 is made of a material having high adhesion to the protective layer 50. It may be formed. Thereby, the adhesion between the release layer 30 and the protective layer 50 can be improved. When the intermediate layer 40 is formed of two layers, as another form, the layer in contact with the release layer 30 is formed of a material having low adhesion to the release layer 30, and the layer in contact with the protective layer 50 is the protective layer 50. It may be formed of a material having high adhesion with. As a result, it becomes possible to peel off at the interface between the peeling layer 30 and the intermediate layer 40 with low stress at the time of peeling.

The thickness of the intermediate layer 40 is 1 μm or less, more preferably 0.5 μm or less, for example, about 0.3 μm. When two or more intermediate layers 40 are formed, the thickness of each layer is preferably the above-mentioned thickness. The intermediate layer 40 is provided as needed and can be omitted.

The protective layer 50 is provided on the uppermost layer. The protective layer 50 is provided at least on the release layer 30. In this example, the protective layer 50 is provided above the intermediate layer 40. The protective layer 50 covers the entire upper surface of the intermediate layer 40 and the entire upper surface of the outer peripheral portion 10b of the support substrate 10. The protective layer 50 is provided on the central portion 10a and the outer peripheral portion 10b of the support substrate 10. In other words, the central portion 10a and the outer peripheral portion 10b overlap with the protective layer 50 in the Z direction. The diameter of the protective layer 50 when viewed from the Z direction is, for example, the same as the diameter of the support substrate 10 when viewed from the Z direction.

The protective layer 50 has a first portion 51 and a second portion 52. The first portion 51 is a portion provided on the release layer 30. In this example, the first portion 51 is provided on the intermediate layer 40 and covers the upper surface of the intermediate layer 40. The second portion 52 is a portion provided on the outer peripheral portion 10b of the support substrate 10. The second portion 52 covers the upper surface of the outer peripheral portion 10b. The second portion 52 is in contact with the outer peripheral portion 10b. The second portion 52 covers the outer peripheral end portion 30a of the peeling layer 30, the outer peripheral end portion 20a of the adhesion layer 20, and the outer peripheral end portion 40a of the intermediate layer 40. The second portion 52 is in contact with the outer peripheral end portion 30a of the release layer 30, the outer peripheral end portion 20a of the adhesion layer 20, and the outer peripheral end portion 40a of the intermediate layer 40.

In this example, the second portion 52 is provided so as to follow the step formed by the adhesion layer 20, the release layer 30, and the intermediate layer 40. That is, the upper surface of the protective layer 50 has a step.

The protective layer 50 suppresses the peeling layer 30 from peeling before the peeling step when manufacturing the semiconductor device. The protective layer 50 contains, for example, a metal or a metal oxide. As the material of the protective layer 50, the same material as that given as an example of the material of the adhesive layer 20 can be used.

Further, the protective layer 50 functions as a seed layer when wiring is formed by a plating method when manufacturing a semiconductor device. In this case, in order to stabilize the current distribution in the XY plane during plating, it is preferable to use a material having high electrical conductivity for the protective layer 50. The protective layer 50 preferably contains Cu or Au.

The protective layer 50 may be one layer or two or more layers. When the protective layer 50 is formed of two layers, the layer in contact with the support substrate 10 and the intermediate layer 40 is formed of the intermediate layer 40 or a material having high adhesion to the support substrate 10, and other layers (support substrate 10 and intermediate) are formed. The layer that does not contact the layer 40) is preferably formed of a material such as Cu or Au that is suitable for suppressing the peeling of the peeling layer 30 and fulfilling the function of the seed layer in the plating method.

The protective layer 50 preferably contains the same metal elements as the adhesion layer 20. Thereby, the adhesion between the protective layer 50 and the adhesion layer 20 can be improved. Further, the protective layer 50 preferably contains the same metal element as the intermediate layer 40. Thereby, the adhesion between the protective layer 50 and the intermediate layer 40 can be improved.

From the viewpoint of film forming property, electrical characteristics, and cost, the material of the adhesion layer 20, the intermediate layer 40, and the protective layer 50 is preferably Cu, for example. When the adhesion layer 20 and the protection layer 50 are composed of two or more layers, it is preferable that one or more of the adhesion layers 20 contain Cu and one or more of the protection layers 50 contain Cu.

The thickness of the protective layer 50 is 5 μm or less, preferably 1 μm or less, more preferably 0.5 μm or less, for example, about 0.5 μm. In this example, the thickness of the second portion 52 is the same as the thickness of the first portion 51.

Hereinafter, a method for manufacturing the carrier 100 according to the embodiment will be described.
2 (a) to 2 (d) are cross-sectional views schematically showing a method of manufacturing a carrier according to an embodiment.
The carrier 100 according to the embodiment can be manufactured by, for example, the following method.
First, as shown in FIG. 2A, the adhesion layer 20 is formed on the support substrate 10. The adhesion layer 20 is formed only on the central portion 10a of the support substrate 10. The adhesion layer 20 may be formed by a physical vapor deposition method such as a sputtering method or a vacuum vapor deposition method, or may be formed by a chemical vapor deposition method such as a thermal CVD (Chemical_Vapor_Deposition) method. By forming the adhesion layer 20 by a sputtering method or the like in a state where the mask M is arranged at a position covering the outer peripheral portion 10b of the support substrate 10, the adhesion layer 20 can be formed only on the central portion 10a.

Next, as shown in FIG. 2B, the release layer 30 is formed on the adhesion layer 20. The release layer 30 is formed over the entire upper surface of the adhesion layer 20. The release layer 30 may be formed by a physical vapor deposition method such as a sputtering method or a vacuum vapor deposition method, or may be formed by a chemical vapor deposition method such as a thermal CVD method. By forming the release layer 30 by a sputtering method or the like in a state where the mask M is arranged at the same position as when the adhesion layer 20 is formed (that is, a position covering the outer peripheral portion 10b of the support substrate 10), the adhesion layer 20 is formed. The release layer 30 can be formed over the entire upper surface.

Next, as shown in FIG. 2C, an intermediate layer 40 is formed on the release layer 30. The intermediate layer 40 is formed over the entire upper surface of the release layer 30. The intermediate layer 40 may be formed by a physical vapor deposition method such as a sputtering method or a vacuum vapor deposition method, or may be formed by a chemical vapor deposition method such as a thermal CVD method. The release layer 30 is formed by forming the intermediate layer 40 by a sputtering method or the like in a state where the mask M is arranged at the same position as when the adhesion layer 20 is formed (that is, a position covering the outer peripheral portion 10b of the support substrate 10). The intermediate layer 40 can be formed over the entire upper surface.

Next, as shown in FIG. 2D, the protective layer 50 is formed on the intermediate layer 40 and the outer peripheral portion 10b of the support substrate 10. The protective layer 50 is formed over the entire upper surface of the intermediate layer 40 and the entire upper surface of the outer peripheral portion 10b of the support substrate 10. The protective layer 50 may be formed by a physical vapor deposition method such as a sputtering method or a vacuum vapor deposition method, or may be formed by a chemical vapor deposition method such as a thermal CVD method. Further, the protective layer 50 is formed by forming a seed layer over the entire upper surface of the intermediate layer 40 and the entire outer peripheral portion 10b of the support substrate 10 by a sputtering method, and then forming the protective layer 50 by a plating method or a vacuum vapor deposition method. It may be done by. By using the plating method or the vacuum vapor deposition method, the protective layer 50 can be thickened to the order of several μm to improve the peeling resistance and reduce the current density for forming the rewiring layer.

The adhesion layer 20, the release layer 30, and the intermediate layer 40 can be formed continuously, for example, by a sputtering method in which the target is changed, using the same mask M in the same chamber. In this case, the mask M is removed or the chamber is changed before the protective layer 50 is formed. By forming the intermediate layer 40, it is possible to suppress deterioration such as oxidation and moisture absorption of the peeling layer 30 and contamination of the peeling layer 30 at this time.

3 (a) and 3 (b) are a plan view and a cross-sectional view schematically showing a carrier according to a modified example of the embodiment.
FIG. 3B is a cross-sectional view taken along the line B1-B2 shown in FIG. 3A.

As shown in FIGS. 3A and 3B, the carrier 100A according to the modified example of the embodiment is the carrier 100 shown in FIG. 1 except that the shape of the second portion 52 of the protective layer 50 is different. Is substantially the same as. In this example, the second portion 52 of the protective layer 50 is provided so as to fill the step formed by the adhesion layer 20, the release layer 30, and the intermediate layer 40. That is, the upper surface of the protective layer 50 has no step.

In this example, the thickness of the first portion 51 is 0.1 μm or more, preferably 0.3 μm or more, more preferably 0.5 μm or more, still more preferably 1.0 μm or more. The thickness of the first portion 51 may be the same as the thickness of the protective layer 50 described above. The thickness of the second portion 52 is the sum of the thickness of the adhesion layer 20, the thickness of the release layer 30, the thickness of the intermediate layer 40, and the thickness of the first portion 51. For example, when the thickness of the adhesion layer 20 is 0.3 μm, the thickness of the release layer 30 is several nm, the thickness of the intermediate layer 40 is 0.3 μm, and the thickness of the first portion 51 is 0.4 μm, the second The thickness of the portion 52 is about 1.0 μm.

When manufacturing a semiconductor device, a rewiring layer may be formed on the protective layer 50. When forming the rewiring layer, for example, an insulating layer or a plating resist is formed on the protective layer 50, and a pattern is formed on the insulating layer or the plating resist by patterning by exposure and development to form a metal wiring. To do. The insulating layer and the plating resist are formed, for example, by spin-coating a liquid material on the protective layer 50 and drying it. At this time, if there is a step on the upper surface of the protective layer 50, the thickness of the coating film may vary during spin coating of the material, and a formation abnormality may occur. Therefore, depending on the material used, it is preferable that there is no step on the upper surface of the protective layer 50.

Hereinafter, a method for manufacturing the carrier 100A according to a modified example of the embodiment will be described.
4 (a) to 4 (e) are cross-sectional views schematically showing a method of manufacturing a carrier according to a modified example of the embodiment.
Since the steps of FIGS. 4A to 4C are substantially the same as the steps of FIGS. 2A to 2C, the description thereof will be omitted.

In this example, as shown in FIG. 4D, when the protective layer 50 is formed, the position of the upper surface of the second portion 52 is the position of the first portion 51 (after grinding) when it is actually used. The protective layer 50 is thickly formed so as to be equal to or higher than the above. The protective layer 50 can be formed in the same manner as described above, but is preferably performed by a plating method or a vacuum vapor deposition method.

Next, as shown in FIG. 4 (e), the protective layer 50 is ground to make the positions of the upper surface of the first portion 51 and the upper surface of the second portion 52 the same (flatten). Grinding of the protective layer 50 can be performed by, for example, chemical mechanical polishing (CMP). The surface roughness of the protective layer 50 after grinding (for example, arithmetic average roughness Ra) is 0.5 μm or less, preferably 0.1 μm or less, and more preferably 0.01 μm or less. This makes it possible to prevent the rewiring layer from being cut off when the rewiring layer is formed on the protective layer 50 when the semiconductor device is manufactured.

The thickness of the protective layer 50 (first portion 51 and second portion 52) formed in the step of FIG. 4D is the thickness of the adhesion layer 20, the thickness of the release layer 30, and the thickness of the intermediate layer 40. Is greater than the sum of. For example, the thickness of the adhesion layer 20 is 0.3 μm, the thickness of the release layer 30 is several nm, the thickness of the intermediate layer 40 is 0.3 μm, and the thickness of the first portion 51 in actual use is 0. When the thickness is .4 μm, the protective layer 50 (first portion 51 and second portion 52) is formed with a thickness of about 1.2 μm in the step of FIG. 4 (d). Then, in the step of FIG. 4 (e), the protective layer 50 (first portion 51 and second portion 52) is flattened by grinding the first portion 51 by 0.8 μm, and is shown in FIG. 4 (e). Carrier 100A can be manufactured.

Hereinafter, a method for manufacturing a semiconductor device according to the embodiment will be described.
5 (a) to 5 (e), 6 (a) to 6 (d), and 7 (a) to 7 (d) schematically show a method for manufacturing a semiconductor device according to an embodiment. It is a cross-sectional view represented by.
In the method for manufacturing a semiconductor device according to the embodiment, first, as shown in FIG. 5A, the above-mentioned carrier 100 (or carrier 100A) is prepared.

Next, as shown in FIG. 5B, the insulating layer 110 is formed on the protective layer 50 of the carrier 100. The insulating layer 110 is formed on the first portion 51 and the second portion 52 of the protective layer 50. A first wiring pattern 115 is formed on the insulating layer 110 by patterning by exposure and development. The first wiring pattern 115 is formed on the first portion 51. The insulating layer 110 contains a resin.

Next, as shown in FIG. 5C, the plating resist 120 is formed on the insulating layer 110. A second wiring pattern 125 is formed on the plating resist 120 by patterning by exposure and development. The second wiring pattern 125 is formed on the first portion 51.

Next, as shown in FIG. 5D, the metal wiring 130 is formed in the first wiring pattern 115 and the second wiring pattern 125 by the plating method. In other words, the metal wiring 130 is formed by using the insulating layer 110 and the plating resist 120 as masks. When the metal wiring 130 is formed by the plating method, the protective layer 50 is contacted and an electric current is applied. By optimizing the thickness of the intermediate layer 40 and the thickness of the protective layer 50, the current distribution in the XY plane of the carrier 100 can be reduced, and the variation of the metal wiring 130 can be suppressed.

The metal wiring 130 includes, for example, Al, Ti, V, Cr, Fe, Co, Ni, Cu, Ge, Rb, Y, Zr, Nb, Mo, Rh, Pd, Ag, Sn, Sm, Gd, Dy, Er. , Hf, Ta, W, Re, Os, Ir, Pt, Au, Th, and a metal containing at least one selected from the group consisting of U. The metal wiring 130 is made of, for example, Cu.

Next, as shown in FIG. 5 (e), the plating resist 120 is removed. The rewiring layer 140 is formed by repeatedly forming the plating resist 120, forming the metal wiring 130, and removing the plating resist 120 to form the required number of metal wirings 130, and then forming the insulating layer 110 on the outermost layer. Is formed. The rewiring layer 140 is formed on the first portion 51.

When forming the metal wiring 130 for the second and subsequent layers, a seed layer for plating is formed by using a sputtering method or the like before forming the plating resist. The seed layer may be formed by a physical vapor deposition method such as a sputtering method or a vacuum vapor deposition method, or may be formed by a chemical vapor deposition method such as a thermal CVD method.

Next, as shown in FIG. 6A, the semiconductor element 150 is mounted on the rewiring layer 140. The semiconductor element 150 includes a semiconductor layer 151, an on-semiconductor element wiring layer 152, and an electrode 153. The semiconductor element 150 is mounted with the electrode 153 facing the rewiring layer 140 side. By joining the electrode 153 to the rewiring layer 140, the semiconductor element 150 is electrically connected to the metal wiring 130.

Next, as shown in FIG. 6B, the semiconductor element 150 is covered with the resin material 155 to form the resin plate 160. More specifically, for example, the semiconductor element 150 is covered with an uncured resin material by a transfer molding method, a compression molding method, or the like, and then heated in an oven to cure the resin. A resin plate 160 having a resin material 155 covering the semiconductor element 150 and a resin material 155 can be formed. The resin material includes, for example, a thermosetting resin and a filler such as silica. When viewed from the Z direction, the outer peripheral end portion 155a of the resin material 155 is located inside the outer peripheral end portion 30a of the release layer 30. That is, the resin plate 160 is formed at a position that does not overlap with the outer peripheral end portion 30a of the release layer 30 when viewed from the Z direction.

The resin plate 160 may be formed by filling the space between the semiconductor element 150 and the rewiring layer 140 with the first resin material, and then covering the semiconductor element 150 with the second resin material. Since the space between the semiconductor element 150 and the rewiring layer 140 is narrow, it is preferable that the first resin material has higher fluidity than the second resin material. For example, by using a filler having a smaller particle size than the filler used for the second resin material or by making the filling amount of the filler smaller than that of the second resin material, the fluidity of the first resin material can be made the second resin. Can be higher than the liquidity of.

When filling the space between the semiconductor element 150 and the rewiring layer 140 with the first resin material, for example, the dispense method can be used. When the dispense method is used, a needle having a small hole is connected to a syringe containing the first resin material, and air pressure is applied to the inside of the syringe to supply an appropriate amount of the first resin material from the tip of the needle. The supplied first resin material spreads between the semiconductor element 150 and the rewiring layer 140 due to the capillary phenomenon. As a result, the first resin material can be filled between the semiconductor element 150 and the rewiring layer 140. Then, by filling the first resin material and then heating it in the oven, the first resin material filled between the semiconductor element 150 and the rewiring layer 140 can be cured.

Next, as shown in FIG. 6C, a broken portion 35 is formed on the outside of the resin plate 160, which is a part of the release layer 30. The outside of the resin plate 160 is a position that does not overlap with the resin plate 160 in the Z direction. The broken portion 35 is formed by breaking a portion of the release layer 30 located outside the resin plate 160 using, for example, a jig J such as a knife. The fractured portion 35 may be formed all around the resin plate 160, or may be formed at one or more locations on the outside of the resin plate 160.

Next, as shown in FIG. 6D, the support substrate 10 and the resin plate 160 are separated from each other starting from the fractured portion 35. In other words, the support substrate 10 is peeled from the resin plate 160 starting from the fractured portion 35. The separation (peeling) interface may be between the peeling layer 30 and the intermediate layer 40, between the peeling layer 30 and the adhesion layer 20, or inside the peeling layer 30. May be good. In this example, the separation (peeling) interface is inside the peeling layer 30. For separation (peeling), for example, in a state where the resin plate 160 is fixed on the stage via a dicing tape, the support substrate 10 is vacuum-sucked at a position close to the fractured portion 35 of the peeling layer 30, and the vacuum-sucking position is set. This can be done by gradually moving away from the broken portion 35.

Next, as shown in FIG. 7A, the peeling layer 30, the intermediate layer 40, and the protective layer 50 adhering to the rewiring layer 140 on the resin plate 160 side are removed by, for example, etching. As a result, the surface of the rewiring layer 140 opposite to the surface on which the resin plate 160 is formed is exposed.

Next, as shown in FIG. 7B, a metal film 170 for external connection is formed on a part (pad) of the exposed metal wiring 130. The metal film 170 is formed by, for example, electrolytic plating or electroless plating. Further, if necessary, a metal bump 180 or a solder ball is formed on the metal film 170 as shown in FIG. 7 (c). Then, as shown in FIG. 7D, the resin plate 160 and the rewiring layer 140 are cut. As described above, a plurality of individualized semiconductor devices 200 are manufactured.

8 (a) to 8 (e) and 9 (a) to 9 (e) are cross-sectional views schematically showing a manufacturing method of a semiconductor device according to a modified example of the embodiment.
In this example, after the carrier 100 is prepared as shown in FIG. 8A, the semiconductor element 150 is mounted on the first portion 51 of the protective layer 50 as shown in FIG. 8B. .. In this example, the semiconductor element 150 has a semiconductor layer 151 and an on-semiconductor element wiring layer 152. The semiconductor element 150 is mounted with the on-semiconductor element wiring layer 152 facing the protective layer 50 side.

When mounting the semiconductor element 150, the semiconductor element 150 may be adhered to the protective layer 50 by an adhesive layer, if necessary. When the adhesive layer is used, the semiconductor element 150 may be mounted on the adhesive layer formed on the protective layer 50, or the semiconductor element 150 having the adhesive layer formed on the on-semiconductor element wiring layer 152 is mounted on the protective layer 50. You may.

The adhesive layer contains, for example, a resin. The adhesive layer may have an adhesive force sufficient to fix the semiconductor element 150. The adhesive layer preferably contains a resin whose adhesive strength tends to decrease due to heating or a resin which easily dissolves in a solvent, in consideration of removal in a later step.

Further, in this example, the protective layer 50 may be an insulating film containing a resin. In this case, the resin may be cured before mounting the semiconductor element 150, or the resin may be cured after mounting the semiconductor element 150.

Next, as shown in FIG. 8C, the semiconductor element 150 is covered with the resin material 155 to form the resin plate 160. The resin plate 160 can be formed by the same method as described above.

Next, as shown in FIG. 8D, a fractured portion 35 is formed on the outside of the resin plate 160, which is a part of the release layer 30. The fractured portion 35 can be formed by the same method as described above. Further, as shown in FIG. 8E, the support substrate 10 and the resin plate 160 are separated from each other starting from the fractured portion 35. Separation (peeling) can be performed by the same method as described above.

Next, as shown in FIG. 9A, the release layer 30, the intermediate layer 40, and the protective layer 50 adhering to the resin plate 160 are removed by, for example, etching. When the adhesive layer is provided when the semiconductor element 150 is mounted, the adhesive layer is removed by a method such as mechanically removing the adhesive by lowering the adhesive force by heating or dissolving the adhesive layer in a solvent. As a result, the on-semiconductor element wiring layer 152 of the semiconductor element 150 is exposed.

Next, as shown in FIG. 9B, the rewiring layer 140 is formed on the exposed surface of the on-semiconductor element wiring layer 152 of the semiconductor element 150. The rewiring layer 140 has an insulating layer 110 and a metal wiring 130. The rewiring layer 140 can be formed by the same method as described above.

Next, as shown in FIG. 9 (c), a metal film 170 for external connection is formed on a part (pad) of the exposed metal wiring 130, and if necessary, the table is shown in FIG. 9 (d). As described above, the metal bump 180 and the solder ball are formed on the metal film 170. Then, as shown in FIG. 9E, the resin plate 160 and the rewiring layer 140 are cut. As described above, a plurality of fragmented semiconductor devices 200A are manufactured.

10 (a) to 10 (e) and 11 (a) to 11 (e) are cross-sectional views schematically showing a manufacturing method of a semiconductor device according to a modified example of the embodiment.
In this example, after the carrier 100 is prepared as shown in FIG. 10 (a), the semiconductor element 150 is mounted on the first portion 51 of the protective layer 50 as shown in FIG. 10 (b). .. In this example, the semiconductor element 150 has a semiconductor layer 151, an on-semiconductor element wiring layer 152, and an electrode 153. The semiconductor element 150 is mounted with the semiconductor layer 151 facing the protective layer 50 side.

When mounting the semiconductor element 150, the semiconductor element 150 may be adhered to the protective layer 50 by an adhesive layer, if necessary. As the adhesive layer, the same one as described above can be used.

Next, as shown in FIG. 10C, the semiconductor element 150 is covered with the resin material 155 to form the resin plate 160. The resin plate 160 can be formed by the same method as described above.

Next, as shown in FIG. 10D, the portion of the resin material 155 of the resin plate 160 above the semiconductor element 150 is ground to expose the electrode 153 of the semiconductor element 150. Grinding can be performed by, for example, CMP.

Next, as shown in FIG. 10E, the rewiring layer 140 is formed on the exposed surface of the electrode 153 of the semiconductor element 150. The rewiring layer 140 has an insulating layer 110 and a metal wiring 130. The rewiring layer 140 can be formed by the same method as described above.

Next, as shown in FIG. 11A, a broken portion 35 is formed on the outside of the resin plate 160, which is a part of the release layer 30. The fractured portion 35 can be formed by the same method as described above.

Further, as shown in FIG. 11B, the support substrate 10 and the resin plate 160 are separated from each other starting from the fractured portion 35. Separation (peeling) can be performed by the same method as described above. After separation, the peeling layer 30, the intermediate layer 40, and the protective layer 50 adhering to the rewiring layer 140 on the resin plate 160 side are removed by, for example, etching. Further, the semiconductor layer 151 of the semiconductor element 150 exposed by removing the release layer 30, the intermediate layer 40, and the protective layer 50 is covered with the resin material 155.

Next, as shown in FIG. 11 (c), a metal film 170 for external connection is formed on a part (pad) of the exposed metal wiring 130, and if necessary, the table is shown in FIG. 11 (d). As described above, the metal bump 180 and the solder ball are formed on the metal film 170. Then, as shown in FIG. 11 (e), the resin plate 160 and the rewiring layer 140 are cut. As described above, a plurality of individualized semiconductor devices 200B are manufactured.

Hereinafter, the effects of the method for manufacturing the carrier and the semiconductor device according to the embodiment will be described.
In the manufacture of semiconductor devices such as FO-WLP, after mounting processes such as wiring formation, mounting of semiconductor elements, and sealing are performed on a carrier having a supporting substrate, the supporting substrate is peeled off from the sealed product. The package is completed by individualizing. In the mounting process, for example, heating is performed when the resin material that seals the semiconductor element is cured. When the carrier is heated, the carrier may be warped due to the difference in the coefficient of linear thermal expansion of each member constituting the carrier, the semiconductor element, the resin material, etc., and the carrier may be stressed. Further, when forming metal wiring or the like, the carrier may be warped due to the internal stress, and the carrier may be stressed. When a large stress is applied to the carrier, the support substrate may be peeled off from the portion where the peeling layer is exposed at the outer peripheral end portion of the carrier before the peeling step.

As a means for suppressing unintended peeling before such a peeling step, for example, it is conceivable to make the peeling layer more difficult to peel than before. However, if the peeling layer is made harder to peel than before, the stress applied when peeling the support substrate in the peeling step becomes large, and the semiconductor element, the resin material, the metal wiring, and the like may be damaged. As described above, it is difficult to achieve both suppression of unintended peeling before the peeling step and easy peeling in the peeling step. For this reason, there is a demand for a carrier that can suppress the peeling of the support substrate before the peeling step and can easily peel the support substrate by mechanical peeling in the peeling step.

According to the embodiment, the outer peripheral end portion 30a of the peeling layer 30 is covered with the second portion 52 of the protective layer 50 provided on the outer peripheral portion 10b of the support substrate 10, so that the outer peripheral end portion of the carrier 100 is peeled off. It is possible to prevent the layer 30 from being exposed. As a result, even when a large stress is applied to the carrier 100 in the mounting step before the peeling step, it is possible to suppress the peeling of the support substrate 10 starting from the outer peripheral end portion 30a of the peeling layer 30. Further, with such a structure, it is possible to suppress the peeling of the support substrate 10 before the peeling step without making the peeling layer 30 more difficult to peel than the conventional one. That is, even if the peeling layer 30 capable of easily peeling the support substrate 10 in the peeling step is used, the peeling of the support substrate 10 before the peeling step can be suppressed. Therefore, it is possible to achieve both suppression of unintended peeling before the peeling step and easy peeling in the peeling step.

Further, when the second portion 52 of the protective layer 50 is in contact with the outer peripheral portion 10b of the support substrate 10, the protective layer 50 and the support substrate 10 can be brought into close contact with each other. Thereby, it is possible to further suppress the peeling of the support substrate 10 in the mounting step before the peeling step.

Further, by providing the intermediate layer 40 on the release layer 30, it is possible to improve the resistance to stress from the end portion of the resin material 155 that covers the semiconductor element 150.

As a means for improving the resistance to stress from the end of the resin material 155 covering the semiconductor element 150, for example, it is conceivable to increase the thickness of the intermediate layer 40 without forming the protective layer 50. However, since the outer peripheral end portion 30a of the peeling layer 30 is not covered only by thickening the intermediate layer 40, when a large stress is applied to the carrier 100 in the mounting step before the peeling step, the peeling layer 30 The support substrate 10 is peeled off starting from the outer peripheral end portion 30a. Further, if the thickness of the intermediate layer 40 is increased without forming the protective layer 50, the internal stress of the intermediate layer 40 becomes large, and the peeling layer 30 is easily peeled off.

As described above, according to the embodiment, the carrier and the semiconductor device which can suppress the peeling of the support substrate before the peeling step at the time of manufacturing the semiconductor device and can easily peel the support substrate in the peeling step. A manufacturing method is provided.

Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, changes, etc. can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof. Moreover, each of the above-described embodiments can be implemented in combination with each other.

10 ... Support substrate, 10a ... Central part, 10b ... Outer peripheral part, 20 ... Adhesive layer, 20a ... Outer peripheral end, 30 ... Peeling layer, 30a ... Outer edge, 35 ... Broken part, 40 ... Intermediate layer, 40a ... Outer circumference End, 50 ... Protective layer, 51 ... 1st part, 52 ... 2nd part, 100, 100A ... Carrier, 110 ... Insulation layer, 115 ... 1st wiring pattern, 120 ... Plated resist, 125 ... 2nd wiring pattern, 130 ... metal wiring, 140 ... rewiring layer, 150 ... semiconductor element, 151 ... semiconductor layer, 152 ... on-semiconductor element wiring layer, 153 ... electrode, 155 ... resin material, 155a ... outer peripheral end, 160 ... resin plate, 170 ... Metal film, 180 ... Metal bump, 200, 200A, 200B ... Semiconductor device, J ... Jig, M ... Mask

Claims (9)

Support board and
The release layer provided on the support substrate and
A protective layer provided on the release layer and
With
The support substrate has a central portion including a center and an outer peripheral portion surrounding the central portion.
The release layer is provided on the central portion and is provided.
The protective layer has a first portion provided on the peeling layer and a second portion provided on the outer peripheral portion and covering the outer peripheral end portion of the peeling layer. The carrier according to claim 1, wherein the release layer contains carbon as a main component. The carrier according to claim 1 or 2, further comprising an adhesion layer provided between the support substrate and the release layer. The carrier according to claim 3, wherein the protective layer contains the same metal element as the adhesive layer. The carrier according to claim 3 or 4, wherein the second portion covers the outer peripheral end portion of the adhesion layer. The carrier according to any one of claims 1 to 5, further comprising an intermediate layer provided between the peeling layer and the protective layer. The carrier according to claim 6, wherein the protective layer contains the same metal element as the intermediate layer. The carrier according to claim 6 or 7, wherein the second portion covers the outer peripheral end portion of the intermediate layer. It has a support substrate, a release layer provided on the support substrate, and a protective layer provided on the release layer, and the support substrate has a central portion including a center and the central portion. It has an outer peripheral portion that surrounds the peeling layer, the peeling layer is provided on the central portion, and the protective layer is provided on the first portion provided on the peeling layer and the outer peripheral portion. A step of preparing a carrier having a second portion covering the outer peripheral end portion of the release layer, and
A step of forming a resin plate having a semiconductor element and a resin material covering the semiconductor element on the first portion, and
A step of forming a broken portion on the outside of the resin plate, which is a part of the peeling layer,
A step of separating the support substrate and the resin plate from the broken portion as a starting point,
A method for manufacturing a semiconductor device.

Images