JP2021040079A - Display device and driving method for display device - Google Patents

Abstract

To provide a display device in which the occurrence of lateral leak current is suppressed.SOLUTION: A display device includes a plurality of subpixels included in each of a plurality of pixels, a first electrode provided in accordance with each of the subpixels, a second electrode provided in accordance with each of the subpixels, and a light-emitting layer provided in accordance with each of the subpixels between the first electrode and the second electrode. To the first electrode, voltage based on a video signal is applied. Each of the subpixels includes at least a first subpixel and a second subpixel adjacent to the first subpixel. The second electrode corresponding to the first subpixel and the second electrode corresponding to the second subpixel are insulated electrically from each other. To the second electrode corresponding to the first subpixel, first voltage is applied, and to the second electrode corresponding to the second subpixel, second voltage is applied. The first voltage and the second voltage are different.SELECTED DRAWING: Figure 4

Description

The present invention relates to a display device and a method for driving the display device.

An organic electroluminescence display device (hereinafter referred to as an organic EL display device) is a plurality of transistors, capacitive elements, and organic EL light emitting elements (hereinafter referred to as light emitting elements) in each of a plurality of pixels formed on a substrate. It is composed of. Each pixel is driven by a signal that controls the pixel. By controlling the drive of the transistor of each pixel by a signal, the current value supplied to the light emitting element is controlled, and the display device can display an image.

For example, Patent Document 1 discloses a pixel including a plurality of transistors, one capacitive element, and one light emitting element, and an organic EL display device including the pixel.

Japanese Patent No. 5612988

In an organic EL display device capable of color display, one pixel is generally divided into a plurality of sub-pixel regions, and a light emitting layer is provided in each sub-pixel region. For example, when one pixel is divided into three sub-pixel regions corresponding to RGB, a current flowing through the light emitting layer of each sub-pixel region by a transistor connected in series with the light emitting layer of each sub-pixel region corresponding to RGB. Is controlled, and the brightness and chromaticity of the pixels can be adjusted.

However, it is difficult to electrically insulate adjacent light emitting layers from each other due to the accuracy of the mask vapor deposition method generally used when forming a light emitting layer. When the adjacent light emitting layers are not electrically isolated from each other, there is a problem that the current that should flow to one light emitting layer flows to the adjacent light emitting layer (lateral leakage current), and a desired color cannot be displayed.

In view of such a problem, one of the objects of the present invention is to provide a display device that suppresses the generation of a lateral leakage current. Another object of the present embodiment is to provide a method for driving a display device that suppresses the generation of a lateral leakage current.

The display device according to the embodiment of the present invention includes a plurality of sub-pixels included in each of the plurality of pixels, a first electrode provided corresponding to each of the plurality of sub-pixels, and the plurality of sub-pixels. A second electrode provided corresponding to each of the above, and a light emitting layer provided between the first electrode and the second electrode corresponding to each of the plurality of sub-pixels are provided. A voltage based on a video signal is applied to the first electrode, and each of the plurality of sub-pixels includes at least a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel, and the first sub-pixel is included. The second electrode corresponding to the sub-pixel and the second electrode corresponding to the second sub-pixel are electrically insulated from each other, and a first voltage is applied to the second electrode corresponding to the first sub-pixel. Then, a second voltage is applied to the second electrode corresponding to the second sub-pixel, and the first voltage and the second voltage are different from each other.

A method of driving a display device according to an embodiment of the present invention includes a plurality of sub-pixels included in each of the plurality of pixels, a first electrode provided corresponding to each of the plurality of sub-pixels, and a first electrode.
A second electrode provided corresponding to each of the plurality of sub-pixels, and a light emitting layer provided corresponding to each of the plurality of sub-pixels between the first electrode and the second electrode. Each of the plurality of sub-pixels includes at least a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel, and the second electrode corresponding to the first sub-pixel and the second electrode. It is a method of driving a display device that is electrically isolated from the second electrode corresponding to the second sub-pixel, and a voltage based on a video signal is applied to the first electrode to obtain the first electrode. A first voltage is applied to the second electrode corresponding to one sub-pixel, and a second voltage different from the first voltage is applied to the second electrode corresponding to the second sub-pixel.

It is a schematic plan view of the display device which concerns on one Embodiment of this invention. It is a schematic cross-sectional view of the display device which concerns on one Embodiment of this invention. It is a schematic plan view of the display device which concerns on one Embodiment of this invention. It is a schematic plan view of the display device which concerns on one Embodiment of this invention. It is a circuit diagram of the pixel which the display device which concerns on one Embodiment of this invention has. It is a timing chart of the pixel shown in FIG. It is a schematic diagram which shows the operation state of a pixel at the timing shown in FIG. It is a schematic diagram which shows the operation state of a pixel at the timing shown in FIG. It is a schematic diagram which shows the operation state of a pixel at the timing shown in FIG. It is a schematic diagram which shows the operation state of a pixel at the timing shown in FIG. It is a schematic diagram which shows the operation state of a pixel at the timing shown in FIG. It is a schematic diagram which shows the operation state of a pixel at the timing shown in FIG. It is a schematic diagram which shows the operation state of a pixel at the timing shown in FIG. It is a figure which shows the IV characteristic of the light emitting element of the display device which concerns on one Embodiment of this invention. It is a figure which shows the IV characteristic of the light emitting element of the conventional display device. It is a schematic sectional view of the display device which concerns on another Embodiment of this invention. It is a schematic plan view of the display device which concerns on another Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes and is not construed as being limited to the description of the embodiments illustrated below. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present invention is used. It is not limited. Further, in the present specification and each figure, the same elements as those described above with respect to the above-mentioned figures are designated by the same reference numerals (or reference numerals having a, b, etc. added after the numbers) to provide detailed explanations. It may be omitted as appropriate. The letters "1st" and "2nd" for each element are convenient signs used to distinguish each element, and have more meaning unless otherwise specified. Absent.

As used herein, when a member or region is "above (or below)" another member or region, it is directly above (or directly below) the other member or region, unless otherwise specified. Not only in some cases, but also in the case of being above (or below) the other member or region, that is, including the case where another component is included above (or below) the other member or region. .. In the following description, unless otherwise specified, in cross-sectional view, the side on which the second substrate is arranged is referred to as "upper" or "upper", and the opposite is referred to as "lower" or "lower". Described as "downward".

The first substrate described in the present specification has at least one planar main surface, on which each layer of an insulating layer, a semiconductor layer and a conductive layer, or each element such as a transistor and a display element is formed. Provided. In the following description, in the cross-sectional view, when one main surface of the first substrate is used as a reference and the description is made as "upper", "upper layer", "upper" or "upper surface" with respect to the first substrate, no particular notice is given. Unless otherwise specified, the description shall be made with reference to one main surface of the first substrate.

[First Embodiment]
In the present embodiment, the display device according to the embodiment of the present invention will be described. In the present specification and the like, the display device will be described as an active matrix type organic EL display device.

(Overall configuration of organic EL display device)
FIG. 1 is a schematic plan view of a display device according to an embodiment of the present invention. The display device 100 includes a substrate 101, a display area 103, a peripheral area 105, a video signal line drive circuit 107, a scanning signal line drive circuit 109, a control circuit 111, and a terminal electrode 113. The display area 103, the video signal line drive circuit 107, the scanning signal line drive circuit 109, the control circuit 111, the terminal electrodes 113, and the peripheral area 105 are provided on the upper surface of the substrate 101. The display area 103 has a plurality of pixels 120 for displaying an image on the display device 100. Each pixel 120 has a transistor. By driving the transistor, an image can be displayed on the display device 100.

The peripheral region 105 is provided with a scanning signal line drive circuit 109 and a video signal line drive circuit 107 for controlling the drive of the pixel 120. FIG. 1 shows an example in which the video signal line drive circuit 107 uses an IC chip. A drive circuit formed on a substrate (semiconductor substrate or the like) different from the substrate 101 may be provided on the substrate 101 or a flexible printed circuit (FPC, Flexible Printed Circuit) substrate 115. Further, a part or all of the circuits included in the video signal line drive circuit 107 and the scanning signal line drive circuit 109 may be formed on a substrate different from the substrate 101 and provided on the substrate 101 or the FPC substrate 115. Good. Further, the drive circuit included in the video signal line drive circuit 107 or a part of the drive circuit may be formed directly on the substrate 101. Although not shown in FIG. 1, a display element such as a light emitting element provided in the pixel 120 and various semiconductor elements for controlling the display element are formed on the upper surface of the substrate 101.

The display device 100 further includes a first wiring 201, a contact hole 203, a first terminal wiring 205, a first terminal 207, a second wiring 209, a contact hole 211, a second terminal wiring 213, a second terminal 215, and the like. These are also provided on the upper surface of the substrate 101, similarly to the scanning signal line drive circuit 109.

Although not shown in FIG. 1, for example, a video signal line for supplying a video signal to each pixel 120, a power supply line for supplying power to each pixel 120, a scanning signal line drive circuit 109, and a control circuit 111. Etc. are electrically connected to the first terminal wiring 205 extending from the outside of the display area 103. The first terminal wiring 205 extends out of the display area 103 and is electrically connected to the first terminal wiring 205 via the contact hole 203. The first terminal wiring 205 is exposed near the end of the display device 100 to form the first terminal 207. The first terminal 207 is connected to the FPC board 115.

Although not shown in FIG. 1, similarly, for example, a video signal line for supplying a video signal to each pixel 120, a power supply line for supplying power to each pixel 120, and a scanning signal line drive circuit 109. , The control circuit 111 and the like are electrically connected to the second wiring 209 extending from the outside of the display area 103. The second wiring 209 extends out of the display area 103 and is electrically connected to the second terminal wiring 213 via the contact hole 211. The second terminal wiring 213 is exposed near the end of the display device 100 to form the second terminal 215. The second terminal 215 is connected to the FPC board 115. The second wiring 209 may be the first wiring 201. The contact hole 211 may be the contact hole 203. The second terminal wiring 213 may be the first terminal wiring 205. The second terminal 215 may be the first terminal 207.

The signal is supplied to the pixel 120 from an external circuit (not shown) via the first terminal 207, the scanning signal line drive circuit 109, and the video signal line drive circuit 107. The first terminal 207 can be formed so as to line up along one side of the display device 100. Therefore, the voltage and the signal can be independently supplied to the display area 103 via the single FPC substrate 115.

In this embodiment, the pixel 120 has a first sub-pixel 130, a second sub-pixel 132, and a third sub-pixel 134, respectively. One pixel 120 may be formed by three sub-pixels. Each sub-pixel is provided with one display element such as a light emitting element. The color corresponding to the sub-pixel is determined by the light emitting element. Alternatively, the color corresponding to the sub-pixel may be determined by the characteristics of the color filter provided on the sub-pixel. The sub-pixel is the smallest unit that constitutes a part of the image displayed in the display area 103.

In the present specification, each of the sub-pixels constituting the pixel 120 has one light emitting element and emits different colors from each other. For example, the first sub-pixel 130 may include a light emitting layer that emits blue, the second sub pixel 132 may include a light emitting layer that emits green, and the third sub pixel 134 may include a light emitting layer that emits red. Then, by supplying an arbitrary voltage or current to each of the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134, full-color display can be realized. In FIG. 1, as an example, an example in which the array of sub-pixels constituting the pixel 120 is a stripe array is shown. The arrangement of sub-pixels is not limited to the stripe arrangement, and may be a delta arrangement, a pentile arrangement, or the like. Further, the arrangement of the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134 is not limited.

(Pixel composition)
FIG. 2 is a schematic cross-sectional view of the display device 100. The laminated structure of the display device 100 will be described with reference to FIG.

The display device 100 is provided with a semiconductor layer 142 on the upper surface of the substrate 101 via an underlayer 501 having an arbitrary configuration.

A drive transistor DRT is provided on the upper side of the base film 501. The drive transistor DRT includes a semiconductor layer 142, a gate insulating film 144, a gate electrode 146, and a source or drain electrode 156 described later. The semiconductor layer 142 includes a source region or drain region 154 and a channel region 141. The source region or drain region 154 may be formed by injecting impurities into the semiconductor layer 142. The source or drain region 154 is electrically connected to the source or drain electrode 156. The gate electrode 146 overlaps with the semiconductor layer 142 via the gate insulating film 144. The region where the semiconductor layer 142 and the gate electrode 146 overlap is the channel region 141 of the drive transistor DRT.

In FIG. 2, the drive transistor DRT is shown as a top gate type transistor, but the structure of the drive transistor DRT is not limited. The structure of the drive transistor DRT may be, for example, a bottom gate type transistor, a multi-gate type transistor having a plurality of gate electrodes 146, or a dual gate type transistor having a structure in which the upper and lower sides of the semiconductor layer 142 are sandwiched between two gate electrodes 146. Good. Further, FIG. 2 shows an example in which one drive transistor DRT is provided in each of the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134. However, the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134 may each further have a semiconductor element such as a plurality of transistors and capacitive elements.

An insulating film 108 is provided on the gate electrode 146. The insulating film 108 has a function as a flat film that absorbs irregularities caused by transistors and other semiconductor elements to give a flat surface. As the insulating film 108, an organic compound material selected from acrylic, polyimide, etc., which has excellent flatness on the film surface, can be used.

A first drive power line 428, which will be described later, may be provided on the insulating film 108. A first reset voltage line 412 (not shown in FIG. 2), which will be described later, may be provided on the same layer as the first drive power supply line 428. The first drive power line 428 and a part of the gate electrode 146 are overlapped with each other. The holding capacitance element 438 is formed by a gate electrode 146, an insulating film 108, and a first drive power supply line 428. At this time, the first terminal of the holding capacitance element 438 is the gate electrode 146, and the second terminal of the holding capacitance element 438 is a part of the first drive power supply line 428.

An insulating film 114 is provided on the insulating film 108 so as to cover the first drive power supply line 428. Like the insulating film 108, the insulating film 114 has a function as a flat film that absorbs irregularities caused by transistors and other semiconductor elements to give a flat surface. As the insulating film 114, similarly to the insulating film 108, an organic compound material selected from acrylic, polyimide, or the like having excellent flatness of the film surface can be used.

A source or drain electrode 156 is provided on the insulating film 114. The source or drain electrode 156 is electrically connected to the source or drain region 154 of the semiconductor layer 142 through openings provided in the gate insulating film 144, the insulating film 108, and the insulating film 114.

A conductive layer (not shown) may be provided on the same layer as the source or drain electrode 156. This conductive layer may be connected to a source or drain electrode 156. Further, the first terminal wiring 205 may be provided on the same layer as the source or drain electrode 156. Similarly, a second terminal wiring 213 (not shown) may be provided on the same layer as the source or drain electrode 156.

Subsequently, the insulating film 148 is provided. Further, the inorganic insulating film 150 may be provided on the insulating film 148. The inorganic insulating film 150 has a function as a protective film that protects a semiconductor element such as a transistor. Further, the inorganic insulating film 150 is formed so as to sandwich the pixel electrode (hereinafter, referred to as the first electrode) 162 of the light emitting element 160 described later in the lower layer of the inorganic insulating film 150 and the inorganic insulating film 150 in the lower layer of the inorganic insulating film 150. Electrodes (not shown) may be formed. At this time, a capacitance can be formed between the first electrode 162 and the electrodes (not shown) formed so as to sandwich the inorganic insulating film 150 via the inorganic insulating film 150.

The insulating film 148 and the inorganic insulating film 150 are provided with a plurality of openings. The plurality of openings includes an opening 190. The opening 190 electrically connects the first electrode 162 of the light emitting element 160, which will be described later, with the source or drain electrode 156. The opening 190 may electrically connect the first electrode 162 and the source or drain electrode 156 via a conductive layer.

The plurality of openings further include a contact hole 203. The contact hole 203 electrically connects the first wiring 201 and the first terminal wiring 205. Also, the plurality of openings further includes an opening 158. The opening 158 is provided so as to expose a part of the first terminal 207 connected to the first terminal wiring 205. The first terminal 207 exposed at the opening 158 is connected to the FPC substrate 115 by, for example, an anisotropic conductive film 252.

The light emitting element 160 is formed on the insulating film 114 and the inorganic insulating film 150. The light emitting element 160 includes a first electrode 162, a functional layer 164, and a second electrode 166. More specifically, the first electrode 162 is provided so as to cover the opening 190 and be electrically connected to the source or drain electrode 156. As a result, a current is supplied to the light emitting element 160 via the drive transistor DRT. An insulating film 168 is provided so as to cover the end portion of the first electrode 162. The insulating film 168 is a partition wall. By covering the end portion of the first electrode 162, the partition wall can prevent disconnection of the functional layer 164 and the second electrode 166 provided on the partition wall.

The functional layer 164 is provided so as to cover the first electrode 162 and the partition wall, and the second electrode 166 is provided on the first electrode 162. Carriers are injected into the functional layer 164 from the first electrode 162 and the second electrode 166, respectively, and carrier recombination occurs in the functional layer 164. As a result, the luminescent molecules in the functional layer 164 are in an excited state, and luminescence is obtained through a process in which the luminescent molecules relax to the ground state. Therefore, the region where the first electrode 162 and the functional layer 164 are in contact with each other is the light emitting region in the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134.

The configuration of the functional layer 164 can be appropriately selected. The functional layer 164 may include, for example, a carrier injection layer, a carrier transport layer, a light emitting layer, a carrier blocking layer, an exciton blocking layer, and the like. FIG. 2 shows an example in which the functional layer 164 has three layers 170, 176, 174. In this case, for example, the layer 170 can be a hole injection and hole transport layer, the layer 176 can be a light emitting layer, and the layer 174 can be an electron injection and electron transport layer.

The layer 176, which is a light emitting layer, can be configured to contain different materials for each of the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134. In this case, the other layers 170 and 174 are the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 130 so as to be common to the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134. It can be formed over the sub-pixel 134 and the partition wall 168. By appropriately selecting the material used in the layer 176, different emission colors can be obtained from the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134.

Further, the structure of the layer 174 may be the same for the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134. In this case, the first sub-pixel 130, the second sub-pixel 132, the third sub-pixel 134, and the partition wall so that the layer 174 is also common to the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134. It may be formed over 168. According to such a configuration, the same emission color is output from the layer 176 of the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134. In this case, for example, the layer 176 is configured to be capable of emitting white light, and various colors (for example, red, green, and blue) are set to the first sub-pixel 130, the second sub-pixel 132, and the third sub by using a color filter, respectively. It may be taken out from the pixel 134.

The second electrode 166 is provided corresponding to each of the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134. The adjacent second electrodes 166 are electrically insulated from each other. That is, the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134 are electrically separated from each other. A predetermined voltage (second drive voltage VSS described later) is applied to each of the first sub-pixel 130, the second sub-pixel 132, and the second electrode 166 corresponding to the third sub-pixel 134. The second electrode 166 corresponding to the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134 may be electrically connected to the first wiring 201 and / or the second wiring 209, respectively.

The display device 100 may further have connection electrodes 234 and 236 that cover the contact hole 203 and the opening 158 and are electrically connected to the first wiring 201 and the first terminal wiring 205, respectively. These connection electrodes 234 and 236 may be provided in the same layer as the first electrode 162. By forming the connection electrodes 234 and 236, it is possible to reduce damage to the first terminal wiring 205 in the manufacturing process of the display device 100, and it is possible to realize an electrical connection with low contact resistance. The connection electrode 234 may be electrically connected to the first wiring 201 or the second wiring 209. The first wiring 201 or the second wiring 209 can be formed in the same layer as the first electrode 162, similarly to the connection electrode 234.

A sealing film 180 is provided on the light emitting element 160. The sealing membrane is also called a passivation membrane. The sealing film 180 has a function of preventing impurities (water, oxygen, etc.) from entering the light emitting element 160 and the transistor from the outside. As shown in FIG. 2, the sealing film 180 may include three layers (layer 182, layer 184, layer 186). In the layer 182 and the layer 186, an inorganic film containing an inorganic compound can be used. The layer 182 is also referred to as a first inorganic film 182. The layer 186 is also referred to as a second inorganic film 186. On the other hand, as the layer 184 between the first inorganic film 182 and the second inorganic film 186, a film (organic film) containing an organic compound selected from acrylic, polyimide and the like can be used. Layer 184 is also referred to as organic film 184. The organic film 184 can be formed so as to absorb unevenness caused by the light emitting element 160 and the partition wall 168 to give a flat surface. Therefore, the thickness of the organic film 184 may be thicker than that of the first inorganic film 182 and the second inorganic film 186.

The first inorganic film 182 and the second inorganic film 186 are preferably formed so as to cover at least the display region 103. Further, it is preferable that the first inorganic film 182 and the second inorganic film 186 are formed so as not to overlap with the contact hole 203 and the opening 158. This enables electrical connection between the first terminal wiring 205 and the FPC substrate 115 or the conductive layer with low contact resistance. Further, it is preferable that the first inorganic film 182 and the second inorganic film 186 are in direct contact with each other around the display area 103 (see the area surrounded by the circle 188). Thereby, the organic film 184 having higher hydrophilicity than the first inorganic film 182 and the second inorganic film 186 can be sealed by the first inorganic film 182 and the second inorganic film 186. Therefore, it is possible to more effectively prevent the invasion of impurities from the outside and the diffusion of impurities in the display area 103.

A cover film 268 is provided on the second inorganic film 186. The first terminal wiring 205 is provided so as to be in contact with the substrate 101 and the region (region A) that opens the insulating film 114, the insulating film 108, the gate insulating film 144, and the base film 501. The area A corresponds to a bending area that can be bent by the display device 100. The cover film 268 protects the surface of the display device 100 up to the bendable region. Further, although not shown, a cover film may be provided under the base film 501. This cover film protects the base film 501 from being damaged and also protects the back surface of the display device 100. The cover film provided under the cover film 268 and the base film 501 may be omitted. If the cover film 268 itself is flexible enough for bending, the cover film 268 may extend to a region where it can be folded.

Although not shown, the description of the second wiring 209, the contact hole 211, the second terminal wiring 213, and the second terminal 215 describes the first wiring 201, the contact hole 203, the first terminal wiring 205, and the first terminal 207. Can be applied.

The display device 100 according to the embodiment of the present invention can have the above-mentioned laminated structure. However, the laminated structure of the display device 100 is not limited to the laminated structure described above. For example, the first wiring 201 or the second wiring 209 may be formed in the same layer as the source or drain electrode 156 and the first drive power supply line 428. Further, the first terminal wiring 205 and the second terminal wiring 213 may be provided on the same layer as the gate electrode 146 or the same layer as the first drive power supply line.

3 and 4 are schematic plan views of the display device 100 according to the embodiment of the present invention. A video signal, a timing signal for controlling the operation of the circuit, a power supply, and the like are supplied to the control circuit 111 via the plurality of terminal electrodes 113 shown in FIG. The control circuit 111 supplies each signal, power supply voltage, and the like to the scanning signal line drive circuit 109 and the video signal line drive circuit 107. The control circuit 111 uses the logic circuit (not shown) and the voltage generation circuit (not shown) of the control circuit 111 to generate a new signal or power supply voltage from each signal or power supply voltage, and scan signal lines. It may be supplied to the drive circuit 109 or the video signal line drive circuit 107. The position where the control circuit 111 is arranged is not limited to the substrate 101 shown in FIG. For example, the control circuit 111 may be located on the FPC substrate 115 connected to the terminal electrode 113.

The scanning signal line drive circuit 109 and the video signal line drive circuit 107 use the signals and the power supply voltage supplied from the control circuit 111 to provide the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 130 included in the pixel 120. By driving the light emitting element of each of the sub-pixels 134 and causing the light emitting element to emit light, it plays a role of displaying an image in the display area 103.

The scanning signal line drive circuit 109 commonly supplies the scanning signal SG (n) to all the sub-pixels included in the plurality of pixels 120 located in the n-th row configured in the display area 103. It is composed of. The scanning signal line drive circuit 109 commonly supplies the light emission control signal BG (n) to all the sub-pixels included in the plurality of pixels 120 located in the n-th row configured in the display area 103. It is configured as follows. The scanning signal line drive circuit 109 commonly supplies the initialization control signal IG (n) to all the sub-pixels included in the plurality of pixels 120 located in the n-th row configured in the display area 103. It is configured to do. The scanning signal line drive circuit 109 is configured to supply the first reset signal VL1 to all the sub-pixels included in the plurality of pixels 120, respectively. Here, the voltage of the first reset signal VL1 is referred to as Vrst1. The scanning signal line drive circuit 109 is further configured to supply the second reset signal VL2 to all the sub-pixels included in the plurality of pixels 120, respectively. The voltage of the second reset signal VL2 is referred to as Vini. In this specification, an example in which Vrst1 and Vini have a fixed voltage is shown, but Vrst1 and Vini may fluctuate with time.

Note that FIG. 3 shows an example in which the scanning signal line drive circuit 109 supplies the first reset signal VL1 to all the sub-pixels included in the plurality of pixels 120, but the present invention is not limited to this example. .. The video signal line drive circuit 107 may supply the first reset signal VL1 to the plurality of pixels. Similarly, the video signal line drive circuit 107 may supply the second reset signal VL2 to the plurality of pixels. Further, the first reset signal VL1 and the second reset signal line VL2 may be electrically connected to the terminal electrode 113. At this time, Vrst1 and Vini are supplied from the outside of the display device 100 via the FPC substrate 115. In the present specification and the like, Vrst1 may be referred to as "reset voltage". Further, in the present specification and the like, Vini may be referred to as "initialization voltage".

The video signal line drive circuit 107 commonly supplies the video signal SL (m) to all the sub-pixels included in the plurality of pixels 120 located in the m-th row configured in the display area 103. It is composed of. Hereinafter, the voltage of the video signal will be referred to as Vsig (m), Vsig (n), and the like. The video signal is determined according to the video data displayed in the display area 103. Further, Vsig (n) may be adjusted by a correction method described later. In the present specification and the like, m and n are arbitrary integers of 1 or more.

Further, the video signal line drive circuit 107 is commonly used by the second drive voltage VSS described later for all the sub-pixels included in the plurality of pixels 120 located in the m-th row configured in the display area 103. Is also configured to supply a high voltage first drive voltage VDD. The first drive voltage VDD may be supplied to the sub-pixels via the first drive power supply line 428. The first drive voltage VDD is supplied to the first electrode 162 of the light emitting element 160 via the drive transistor DRT.

As shown in FIG. 4, the second drive voltage VSS is supplied to all the sub-pixels included in the plurality of pixels 120 located in the m-th row configured in the display area 103. The second drive voltage VSS is supplied to each sub-pixel via the second drive power line PVSS. The second drive power line PVSS may be electrically connected to the first wiring 201 electrically connected to the first terminal 207 from a voltage generation circuit (not shown) located on the FPC substrate 115. Further, instead of the first wiring 201 electrically connected to the first terminal 207 and the first terminal 207, the second drive power supply line PVSS is the second wiring 209 electrically connected to the second terminal 215. May be electrically connected to. When the control circuit 111 is provided with a voltage generation circuit, the second drive voltage VSS may be supplied from the control circuit 111. The second drive voltage VSS is supplied to the second electrode 166 of each light emitting element 160.

The second drive voltage VSS is lower than the first drive voltage VDD. The second drive voltage VSS includes at least a first voltage and a second voltage different from the first voltage. In the present embodiment, a case where the second drive voltage VSS includes a first voltage, a second voltage different from the first voltage, and a third voltage different from the first voltage and the second voltage will be described as an example. To do. The second drive voltage VSS (B) commonly applied to the first sub-pixel 130 is defined as the first voltage. The second drive voltage VSS (G) commonly applied to the second sub-pixel 132 is defined as the second voltage. The second drive voltage VSS (R) applied to the supply to the third sub-pixel 134 is defined as the third voltage. Here, the magnitude of the second drive voltage VSS voltage is the second drive voltage VSS (B) (first voltage) <second drive voltage VSS (G) (second voltage) <second drive voltage VSS (R). (Third voltage). The second drive power line PVSS is connected to the first wiring 201 that supplies the second drive voltage VSS according to the color emitted by the sub-pixels located in the corresponding row.

FIG. 5 is a circuit diagram of sub-pixels according to an embodiment of the present invention. FIG. 5 shows a circuit diagram of sub-pixels included in the pixel 120 of n rows and m columns. The sub-pixel shown in FIG. 5 is the first sub-pixel 130.

Each transistor shown in FIG. 5 can have a Group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor characteristics in the channel region. In this embodiment, it has an n-channel type field-effect transistor and a p-channel type field-effect transistor. The circuit configuration shown in FIG. 5 is an example, and is not limited to this configuration. For example, the polarity of each transistor may be reversed, the phase of the control signal may be inverted, and the holding capacitance element Cs may be arranged between the first node and the first drive power supply line P VDD. In addition, the channel regions of these transistors can have a variety of morphologies selected from single crystal, polycrystalline, microcrystal, or amorphous. For example, it may have low temperature polysilicon (LTPS) obtained by melting and recrystallizing amorphous silicon at a relatively low temperature.

As shown in FIG. 5, the pixel 120 includes a drive transistor DRT, a selection transistor SST (first switch), an initialization transistor IST (second switch), a reset transistor RST (third switch), and a light emission control transistor BCT (fourth switch). A switch), a holding capacitance element (second capacitance element) Cs, a light emitting element OLED (light emitting element 160), and an additional capacitance Cel. Each of these transistors has a first electrode (gate electrode) and a pair of terminals (source electrode, drain electrode) including a second electrode and a third electrode. The holding capacitance element Cs (capacitive element) has a pair of terminals (first terminal, second terminal). The additional capacitance Cel has a pair of terminals (first terminal, second terminal). The pair of terminals described above is also referred to as a pair of electrodes. Note that FIG. 5 shows an example in which the additional capacitance Cel is provided in parallel with the light emitting element OLED, but the present invention is not limited to this. The additional capacitance Cel may be a parasitic capacitance of the light emitting element OLED, or may include a capacitance element provided in parallel with the light emitting element OLED and a parasitic capacitance of the light emitting element OLED. As the power source for driving the light emitting element OLED, the first drive voltage VDD is supplied from the first drive power supply line P VDD, and the second drive voltage VSS (B) is supplied from the second drive power supply line PVSS. The potential Vrst of the reset signal VL is smaller than the high potential first drive voltage VDD supplied from the first drive power supply line P VDD and the potential Vcs of the capacitance signal VC. The potential Vrst of the reset signal VL may be substantially the same as the second drive voltage VSS (B).

The drive transistor DRT has a role of passing a current through the light emitting element OLED based on the input video signal to cause the light emitting element OLED to emit light. The selection transistor SST has a role of supplying a video signal to the drive transistor DRT. The initialization transistor IST has a role of supplying Vini to the gate electrode of the drive transistor DRT and resetting the drive transistor DRT. The light emission control transistor BCT controls the connection and disconnection between the drive power supply line P VDD and the drive transistor DRT. It can be said that the light emission control transistor BCT controls the electrical connection and disconnection between the drive transistor DRT and the light emitting element OLED, and the drive transistor DRT and the additional capacitance Cel. That is, the light emission control transistor BCT has a role of controlling light emission and non-light emission of the light emitting element OLED. The reset transistor RST supplies Vrst1 to the first terminal of the light emitting element OLED, and has a role of resetting the source of the drive transistor DRT and the light emitting element OLED.

The first terminal of the light emitting element OLED is the first electrode 162. The holding capacitance element Cs has a role of securing a voltage corresponding to the threshold value of the drive transistor DRT. Further, the holding capacitance element Cs has a role of maintaining a voltage input to the gate of the drive transistor DRT in order for the pixel 120 to emit light. That is, the holding capacitance element Cs has a role of holding the input video signal, more specifically, the gradation level of the input video signal. The light emitting element OLED has diode characteristics. The light emitting element OLED is a light emitting element 160, and is a light emitting layer (functional layer, organic layer) 164 located between the first electrode 162, the second electrode 166, and the first electrode 162 and the second electrode 166. And, including. The additional capacitance Cel is the capacitance included in the light emitting element OLED. In one embodiment of the present invention, the input video signal may be held by the additional capacitance Cel and the capacitance element Cs.

The gate electrode of the initialization transistor IST is electrically connected to the initialization control line 416. The initialization control signal IG (n) is supplied to the initialization control line 416. The initialization transistor IST is controlled in a conductive state and a non-conducting state by a signal supplied to the initialization control signal IG (n). When the signal supplied to the initialization control signal IG (n) is low, the initialization transistor IST is in a non-conducting state. When the signal supplied to the initialization control signal IG (n) is high, the initialization transistor IST is in a conductive state. The source electrode of the initialization transistor IST is electrically connected to the second reset voltage line 414. The second reset signal VL2 is supplied to the second reset voltage line 414. The drain electrode of the initialization transistor IST is electrically connected to the gate electrode of the drive transistor DRT, the drain electrode of the selection transistor SST, and the first terminal of the holding capacitance element Cs. The second terminal of the holding capacitance element Cs is electrically connected to the source electrode of the drive transistor DRT, the drain electrode of the reset transistor RST, the first terminal of the light emitting element OLED, and the first terminal of the additional capacitance Cel.

The gate electrode of the selection transistor SST is electrically connected to the scanning signal line 410. The scanning signal SG (n) is supplied to the scanning signal line 410. The selection transistor SST is controlled in a conductive state and a non-conducting state by a signal supplied to the scanning signal SG (n). When the signal supplied to the scanning signal SG (n) is low, the selection transistor SST is in a non-conducting state. When the signal supplied to the scanning signal SG (n) is high, the selection transistor SST is in a conductive state. The source electrode of the selection transistor SST is electrically connected to the video signal line 409. The video signal SL (m) is supplied to the video signal line 409. The drain electrode of the selection transistor SST is electrically connected to the drain electrode of the drive transistor DRT and the first terminal of the holding capacitance element Cs.

The gate electrode of the light emission control transistor BCT and the gate electrode of the reset transistor RST are electrically connected to the light emission control line 418. A light emission control signal BG (n) is supplied to the light emission control line 418. The light emission control transistor BCT and the reset transistor RST are controlled in a conductive state and a non-conducting state by a signal supplied to the light emission control signal BG (n). When the signal supplied to the light emission control signal BG (n) is low, the light emission control transistor BCT is in a non-conducting state. When the signal supplied to the light emission control signal BG (n) is high, the light emission control transistor BCT is in a conductive state. When the signal supplied to the light emission control signal BG (n) is low, the reset transistor RST is in a conductive state. When the signal supplied to the light emission control signal BG (n) is high, the reset transistor RST is in a non-conducting state. The drain electrode of the light emission control transistor BCT is electrically connected to the drive power supply line P VDD. The drive power line P VDD is a drive power line 428. The source electrode of the light emission control transistor BCT is electrically connected to the drain electrode of the drive transistor DRT. The source electrode of the reset transistor RST is electrically connected to the first reset voltage line 412. The first reset signal VL1 is supplied to the first reset voltage line 412.

The second terminal of the light emitting element OLED and the second terminal of the additional capacitance Cel are electrically connected to the second drive power supply line PVSS. The second drive power line PVSS may be electrically connected to the first wiring 201.

The drain electrode of the initialization transistor IST, the drain electrode of the selection transistor SST, the gate electrode of the drive transistor DRT, and the first terminal of the holding capacitance element Cs are electrically connected to the first node A (n). The drain electrode of the reset transistor RST, the source electrode of the drive transistor DRT, the second terminal of the holding capacitance element Cs, the first terminal of the light emitting element OLED, and the first terminal of the additional capacitance Cel are electrically connected to the second node B (n). Connected to. The drain electrode of the drive transistor DRT and the source electrode of the light emission control transistor BCT are electrically connected to the third node C (n).

The first reset voltage line 412 supplies a voltage Vrst1 common to each sub-pixel. The second reset voltage line 414 supplies a common voltage Vini to each sub-pixel. In addition, Vrst1 and Vini may have substantially the same voltage. Since Vrst1 and Vini are substantially the same, the voltage of the gate electrode of the drive transistor DRT and the voltage of the source electrode of the drive transistor DRT can be substantially the same when the drive transistor DRT is reset. Both the reset and the threshold correction of the drive transistor DRT can be performed with high accuracy.

In the present specification and the like, the conduction state indicates a state in which the source electrode and the drain electrode of the transistor are conductive and a current flows through the transistor, the transistor is on (ON), and the switch is on (ON). And. Further, in the present specification and the like, the non-conducting state means a state in which the source electrode and the drain electrode of the transistor are non-conducting and no current is flowing through the transistor, the transistor is off (OFF), and the switch is off (OFF). ) Shall indicate the state. In each transistor, the source electrode and the drain electrode may be interchanged depending on the voltage of each electrode. Also, those skilled in the art can easily understand that a slight current flows, such as a leak current, even when the transistor or switch does not pass current, does not pass current, or is off. You can do it.

The circuit configuration of the first sub-pixel 130 has been described above with reference to FIG. In the circuit diagram of the second sub-pixel 132 and the third sub-pixel 134, the second drive voltage VSS applied to the second electrode 166 of the light emitting element OLED is the second drive voltage VSS (G) (second voltage). Alternatively, since it is substantially the same as the circuit diagram of the first sub-pixel 130 shown in FIG. 5, except that the second drive voltage is VSS (R) (third voltage), detailed description thereof will be omitted. ..

(Drive method)
Next, a method of driving the display device according to the embodiment of the present invention will be described. FIG. 6 is a timing chart of the sub-pixels in the nth row and the mth column. The sub-pixel in the n-th row and m-th column may be the first sub-pixel 130, the second sub-pixel 132, or the third sub-pixel 134. Here, a case where the sub-pixel in the n-th row and m-th column is the first sub-pixel 130 will be described as an example. The driving method of the second sub-pixel 132 and the third sub-pixel 134 is the same as the driving method of the first sub-pixel 130 described below.

FIG. 7 shows the state of the sub-pixel in the nth row and the mth column in the period T0 of the timing chart shown in FIG. In the period T0, first, a low voltage is supplied to the initialization control signal IG (n), the scanning signal SG (n), and the light emission control signal BG (n). Therefore, the initialization transistor IST, the selection transistor SST, and the light emission control transistor BCT are in a non-conducting state. On the other hand, the reset transistor RST is in a conductive state. The drive transistor DRT is assumed to be in a non-conducting state, but may be in a conducting state. Therefore, Vrst1 supplied to the first reset signal VL1 is the drain electrode of the reset transistor RST, the source electrode of the drive transistor DRT, the second terminal of the holding capacitance element Cs, and the first terminal of the light emitting element OLED (first electrode 162). , And is supplied to the first terminal of the additional capacitance Cel. The voltage of node B (n) is Vrst1.

FIG. 8 shows the state of the sub-pixels in the nth row and the mth column in the period T1 of the timing chart shown in FIG. In the period T1, the voltage supplied to the initialization control signal IG (n) then changes from low voltage to high voltage. Therefore, the initialization transistor IST becomes conductive. The initialization voltage Vini supplied to the initialization control line 416 is supplied to the drain electrode of the initialization transistor IST, the gate electrode of the drive transistor DRT, the drain electrode of the selection transistor SST, and the holding capacitance element Cs first terminal. .. The voltage of node A (n) is Vini.

In the period T1, the source electrode of the drive transistor DRT and the gate electrode of the drive transistor DRT are reset (initialized). The potential of Vini is higher than the potential of Vrst, and the potential difference is larger than the threshold voltage of the drive transistor DRT. Therefore, the operation in the period T1 resets the drive transistor DRT from the state based on the previous video signal and forcibly turns it on.

FIG. 9 shows the state of the sub-pixels in the nth row and the mth column in the period T2 of the timing chart shown in FIG. In the period T2, the voltage supplied to the light emission control signal BG (n) changes from a low voltage to a high voltage. Therefore, the light emission control transistor BCT becomes conductive. Further, the reset transistor RST is in a non-conducting state. Therefore, since the light emission control transistor BCT is connected to the drive power supply line 428, the voltage of the node C (n) becomes the first drive voltage VDD supplied to the drive power supply line 428. Therefore, a current flows through the drive transistor DRT (the drive transistor DRT is brought into a conductive state by the operation in the period T1). Therefore, the source electrode of the drive transistor DRT and the second terminal of the holding capacitance element Cs are charged. The voltage of the node A (n) is Vini, and when the voltage of the source electrode of the drive transistor DRT becomes Vini-Vthn, the drive transistor DRT becomes non-conducting. The voltage of node A (n) maintains Vini. The voltage of node B (n) is Vini-Vthn. The voltage of node C (n) is VDD. Vthn is the threshold voltage of the drive transistor. Therefore, an electric charge corresponding to the threshold voltage of the drive transistor DRT can be held between the node A (n) and the node B (n), that is, in the holding capacitance element Cs. That is, the threshold value of the drive transistor DRT can be corrected in the T2 period. As a result, it is possible to suppress uneven brightness due to variations in the video signal.

FIG. 10 shows the state of the sub-pixels in the nth row and the mth column in the period T3 of the timing chart shown in FIG. During the period T2 and the period T3, the voltage supplied to the initialization control signal IG (n + 1) changes from a high voltage to a low voltage. Therefore, the initialization transistor IST is in a non-conducting state. Further, in the period T3, the voltage supplied to the scanning signal SG (n) changes from a low voltage to a high voltage. Therefore, the selection transistor SST becomes conductive. When the voltage Vsig (n) of the video signal SL (m) is supplied to the video signal line 409, the drain electrode of the selection transistor SST, the drain electrode of the initialization transistor IST, the gate electrode of the drive transistor DRT, and the holding capacitance element Cs. The first terminal of is Vsig (n). That is, the voltage of the node A (n) is Vsig (n). The voltage of node B (n) is Vini-Vthn. The voltage of node C (n) is VDD. At this time, even if the threshold voltage of the drive transistor DRT varies depending on each sub-pixel, the threshold voltage between the node A (n) and the node B (n) of each sub-pixel depends on the previous operation in the T2 period. The potential difference corresponding to is acquired. Therefore, the drive transistor DRT can be controlled so that the video signal Vsig is added to the video signal Vsig, and the drive transistor DRT can flow a current according to the voltage of each video signal.

FIG. 11 shows the state of the sub-pixels in the nth row and the mth column in the period T4 of the timing chart shown in FIG. During the period T3 and the period T4, the voltage supplied to the scanning signal SG (n) changes from a high voltage to a low voltage. Therefore, the selection transistor SST is in a non-conducting state. Therefore, the drive transistor DRT can flow a current according to the voltage of each video signal. Therefore, a current flows from the first drive power supply line 428 to the second drive power supply line PVSS, and the light emitting element OLED emits light.

12 and 13 show the state of the sub-pixels in the nth row and the mth column in the period T5 of the timing chart shown in FIG. FIG. 12 shows the state of the sub-pixels in the nth row and mth column in the period T51 of the timing chart shown in FIG. 6, and FIG. 13 shows the nth row m in the period T52 of the timing chart shown in FIG. The state of the sub-pixels in the column is shown. The period T5 includes a period T51 in which black insertion is performed at intervals of 1/60 second or less. Since the operation in the period T51 is the same as the operation at the beginning of the T1 period, detailed description thereof will be omitted. Further, since the operation in the period T52 is the same as the operation in the period T4, detailed description thereof will be omitted. During the period T5, Vrst1 can be supplied to the pixel electrodes of the light emitting element OLED by making the reset transistor RST conductive. That is, the display device 100 can display black. For example, in 60 Hz, one black insertion is a black display during the non-emission period, and 59 is a black insertion.

The video on one screen is switched for each 1F, with the period including the periods T0 to T5 described above as one frame (1F).

As described above, in the display device 100 according to the embodiment of the present invention, the first sub-pixel 130, the second sub-pixel 132, and the second electrode 166 of the third sub-pixel 134 of the pixel 120 included in the display area 103 are Each is electrically isolated from the second electrode 166 of the adjacent sub-pixel. That is, the light emitting element 160 (light emitting element OLED) of each sub-pixel is electrically insulated from the adjacent light emitting element 160. Further, the magnitude of the second drive voltage VSS supplied to the second electrode 166 of each sub-pixel is such that the second drive voltage VSS (B) (first voltage) <second sub supplied to the first sub-pixel 130. The relationship is that the second drive voltage VSS (G) (second voltage) supplied to the pixel 132 <the second drive voltage VSS (R) (third voltage) supplied to the third sub-pixel 134.

In FIG. 14, the magnitude of the second drive voltage VSS supplied to the second electrode 166 of each sub-pixel is such that the second drive voltage VSS (B) (first voltage) <second drive voltage VSS (G) (first). 2 voltage) <2nd drive voltage VSS (R) (3rd voltage), the first sub-pixel 130 that emits blue, the second sub-pixel 132 that emits green, and the third that emits red. It is a figure which shows the light emitting element OLED (light emitting element 160) IV characteristic which is contained in each of subpixels 134. FIG. 15 shows the blue color included in the blue sub-pixels when the second electrode is shared between adjacent light emitting elements and a common drive voltage (common voltage) Vcom is supplied to the second electrode as in the conventional case. It is a figure which shows the IV characteristic of the light emitting element (B) which emits light, the light emitting element (G) which emits green which is contained in a green sub-pixel, and the light emitting element (R) which emits red which is contained in a red sub-pixel.

Referring to FIG. 14, as in one embodiment of the present invention, the magnitude of the second drive voltage VSS is such that the second drive voltage VSS (B) (first voltage) <second drive voltage VSS (G) (first). When there is a relationship of (2 voltage) <second drive voltage VSS (R) (third voltage), the IV characteristics of the light emitting element OLED of each sub-pixel are substantially the same. Therefore, the threshold voltage at which the current starts to flow in each of the light emitting element OLEDs of the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134 is substantially the same voltage Va. On the other hand, referring to FIG. 15, the threshold voltages at which the current starts to flow in the light emitting element (B), the light emitting element (G), and the light emitting element (R) are different from each other. More specifically, the threshold voltage of the light emitting element (R) is the smallest, and the threshold voltage of the light emitting element (B) is the largest.

Generally, there is a lateral leak path between adjacent organic EL light emitting elements via a hole transport layer. Therefore, as described above, when the threshold voltages of the light emitting elements are different from each other, the second electrode is shared between the adjacent light emitting elements as in the conventional case, and a common drive voltage (common voltage) Vcom is supplied to the second electrode. If this is the case, the current that should flow to the desired light emitting element will flow to the light emitting element having a lower threshold voltage adjacent to the desired light emitting element (lateral leakage current), and the desired image cannot be displayed. As shown in FIG. 15, when the threshold voltage of the light emitting element (R) is the smallest and the threshold voltage of the light emitting element (B) is the largest, for example, in one pixel, only the light emitting element (B) emits light with low gradation. When a lateral leak current is generated at the time of making the light emitting element (B), the light emitting element (G) (green subpixel) or the light emitting element (R) (red subpixel) adjacent to the light emitting element (B) having a lower threshold voltage than the light emitting element (B) ), And the image that should have been displayed in a single blue color shifts to green or red, and the desired image cannot be displayed.

On the other hand, as in one embodiment of the present invention, the magnitude of the second drive voltage VSS is such that the second drive voltage VSS (B) (first voltage) <second drive voltage VSS (G) (second voltage) < When there is a relationship of the second drive voltage VSS (R) (third voltage), the potentials of the first electrodes of the light emitting element (R), the light emitting element (G), and the light emitting element (B) at the start of light emission are the same, preferably. Is 0.2 V or less. As a result, the generation of the lateral leakage current is suppressed, and the current can be passed through the desired light emitting element, so that the hue shift can be prevented.

The value of the second drive voltage VSS in each sub-pixel may be set according to the difference in the threshold voltage of the light emitting element. That is, the difference in potential between the second drive voltage VSS (B) (first voltage), the second drive voltage VSS (G) (second voltage), and the second drive voltage VSS (R) (third voltage) is different. It corresponds to the difference in the threshold voltage of the light emitting element in the sub-pixel.

As described above, according to one embodiment of the present invention, the first sub-pixel 130, the second sub-pixel 132, and the second electrode 166 of the third sub-pixel 134 of the pixel 120 are electrically insulated from each other, thereby laterally insulating the second electrode 166. The generation of leak current can be suppressed. Further, the hue shift is performed by adjusting the magnitude of the second drive voltage VSS supplied to each of the second electrodes 166 of the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134 so as to be different from each other. Can be prevented and a desired image can be displayed. Further, when the white display is performed by appropriately adjusting the magnitude of the second drive voltage VSS applied to each of the second electrodes 166 of the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134. In addition, the magnitude of the applied voltage of each of the first sub-pixel 130, the second sub-pixel 132, and the third sub-pixel 134 of the pixel 120 can be made substantially the same, thereby improving the color purity. Can be made to.

[Second Embodiment]
In the present embodiment, another configuration of the display device according to the embodiment of the present invention will be described. A detailed description of the configuration similar to that of the first embodiment described above will be omitted, and a configuration different from the configuration of the first embodiment will be described.

FIG. 16 is a schematic cross-sectional view of the display device 100A according to the present embodiment. In the display device 100A according to the present embodiment, only the second electrode 166A of the first sub-pixel 130A included in the pixel 120A is electrically insulated from the second electrodes 166 of the second sub-pixel 132A and the third sub-pixel 134A. It is the same as the configuration of the display device 100 of the first embodiment except that the display device 100 is configured. That is, in the display device 100A, of the first sub-pixel 130A, the second sub-pixel 132A, and the third sub-pixel 134A included in the pixel 120A, only the first sub-pixel 130A is the second sub-pixel 132A and the third sub-pixel. It is electrically separated from the pixel 134A.

FIG. 17 is a schematic plan view of the display device 100A according to the present embodiment. A second drive voltage VSS (B) (first voltage) is applied to the second electrode 166A of the first sub-pixel 130A. On the other hand, the second electrodes 166 of the second sub-pixel 132A and the third sub-pixel 134A are electrically connected to each other and have a second drive voltage VSS (R / G) (second voltage) different from the first voltage. Is applied. Here, the magnitude of the second drive voltage VSS is the second drive voltage VSS (B) (first voltage) <second drive voltage VSS (R / G) (second voltage).

In the present embodiment, when it is not necessary to consider the color mixing of the second sub-pixel 132A and the third sub-pixel 134A, for example, a current flows through each light emitting element OLED of the second sub-pixel 132A and the third sub-pixel 134A. It can be applied when the difference between the starting threshold voltages is negligibly small.

According to the present embodiment, the first electrode 166A of the first sub-pixel 130A of the pixel 120A and the second electrode 166 of each of the second sub-pixel 132A and the third sub-pixel 134 are electrically insulated from each other. It is possible to suppress the generation of a lateral leak current from the sub-pixel 130A to the second sub-pixel 132A and the third sub-pixel 134, and it is possible to prevent a hue shift when only the first sub-pixel 130A emits light. Further, since the layout of the second electrode of each sub-pixel can be simplified as compared with the first embodiment, the light emitting element OLED can be further miniaturized.

As an embodiment of the present invention, based on the display device of each of the above-described embodiments, those skilled in the art appropriately add, delete, or change the design, or add, omit, or change the conditions of the process. Those are also included in the scope of the present invention as long as they have the gist of the present invention.

In this specification, an organic EL display device is exemplified as a display device. The size of the display device can be applied from small to medium size to large size without any particular limitation.

Of course, other effects different from the effects brought about by the embodiments of the above-described embodiments that are clear from the description of the present specification or that can be easily predicted by those skilled in the art will naturally occur. It is understood that it is brought about by the present invention.

100, 100A ... Display device, 101 ... Board, 103 ... Display area, 105 ... Peripheral area, 107 ... Video signal line drive circuit, 109 ... Scan signal line drive circuit, 111 ... control circuit, 113 ... terminal electrode, 115 ... FPC substrate, 120 ... pixel, 130 ... first sub-pixel, 132 ... second sub-pixel, 134 ... third Sub-pixel, 201 ... 1st wiring, 203 ... Contact hole, 205 ... 1st terminal wiring, 207 ... 1st terminal, 209 ... 2nd wiring, 211 ... Contact hole, 213 ... 2nd terminal wiring, 215 ... 2nd terminal, 108 ... Insulation film, 114 ... Insulation film, 141 ... Channel area, 142 ... Semiconductor layer, 144 ... Gate Insulating film, 146 ... Gate electrode, 148 ... Insulating film, 150 ... Inorganic insulating film, 154 ... Drain region / source region, 156 ... Drain electrode / source electrode, 160 ... Light emission Elements, 162 ... 1st electrode, 164 ... Functional layer, 166 ... 2nd electrode, 168 ... Insulating film (partition wall), 170 ... Layer, 174 ... Layer, 176 ... -Layer, 180 ... sealing film, 182 ... first inorganic film, 184 ... organic film, 186 ... second inorganic film, 190 ... opening, 234 ... connection electrode, 236 ... connection electrode, 252 ... anisotropic conductive film, 268 ... cover film, 409 ... video signal line, 410 ... scanning signal line, 412 ... first reset voltage line, 414 ... second reset voltage line, 416 ... initialization control line, 418 ... light emission control line, 428 ... drive power supply line, 434 ... drive transistor, 438 ... holding capacitance element, 450 ... 3rd reset voltage line, 452 ... 4th reset voltage line, 501 ... Underlayer, SST ... Selective transistor, DRT ... Drive transistor, BCT ... Emission control transistor, RST ...・ ・ Reset transistor, IST ・ ・ ・ Initialization transistor, PST ・ ・ ・ Power supply transistor, Cel ・ ・ ・ Additional capacitance, Cs ・ ・ ・ Holding capacitance element, OLED ・ ・ ・ Light emitting element, P VDD ・ ・ ・ First drive power supply Line, PVSS: 2nd drive power supply line, IG (n): initialization control signal, BG (n): light emission control signal, SG (n): scanning signal, SL (m) ...・ ・ Video signal, VL1 ・ ・ ・ 1st reset signal, VL2 ・ ・ ・ 2nd reset signal

Claims (16)

Multiple sub-pixels included in each of the multiple pixels,
A first electrode provided corresponding to each of the plurality of sub-pixels,
A second electrode provided corresponding to each of the plurality of sub-pixels,
A light emitting layer provided between the first electrode and the second electrode corresponding to each of the plurality of sub-pixels,
With
A voltage based on the video signal is applied to the first electrode.
Each of the plurality of sub-pixels includes at least a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel.
The second electrode corresponding to the first sub-pixel and the second electrode corresponding to the second sub-pixel are electrically insulated from each other.
A first voltage is applied to the second electrode corresponding to the first sub-pixel, a second voltage is applied to the second electrode corresponding to the second sub-pixel, and the first voltage and the second voltage are Different, display device. Each of the plurality of sub-pixels further includes a third sub-pixel adjacent to at least one of the first sub-pixel and the second sub-pixel.
The second electrode corresponding to the third sub-pixel is electrically insulated from the second electrode corresponding to the first sub-pixel and the second electrode corresponding to the second sub-pixel.
The display device according to claim 1, wherein a third voltage is applied to the second electrode corresponding to the third sub-pixel, and the third voltage is different from the first voltage and the second voltage. Each of the plurality of sub-pixels further includes a third sub-pixel adjacent to at least one of the first sub-pixel and the second sub-pixel.
The display device according to claim 1, wherein the second voltage is applied to the second electrode corresponding to the third sub-pixel. The first sub-pixel displays blue and
The second sub-pixel displays one of red and green, and displays one of them.
The display device according to claim 2, wherein the third sub-pixel displays the other of red and green. The display device according to claim 4, wherein the first voltage is a voltage lower than the second voltage and the third voltage. The first sub-pixel displays blue and
The second sub-pixel displays one of red and green, and displays one of them.
The display device according to claim 3, wherein the third sub-pixel displays the other of red and green. The display device according to claim 6, wherein the first voltage is a voltage lower than the second voltage. When a predetermined pixel among the plurality of pixels displays white, the first electrode corresponding to the first sub pixel included in the predetermined pixel and the first electrode corresponding to the second sub pixel are included. The display device according to any one of claims 2 to 7, wherein substantially the same voltage is supplied to the first electrode corresponding to the third sub-pixel. Multiple sub-pixels included in each of the multiple pixels,
A first electrode provided corresponding to each of the plurality of sub-pixels,
A second electrode provided corresponding to each of the plurality of sub-pixels,
A light emitting layer provided between the first electrode and the second electrode corresponding to each of the plurality of sub-pixels,
With
Each of the plurality of sub-pixels includes at least a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel.
A method for driving a display device, wherein the second electrode corresponding to the first sub-pixel and the second electrode corresponding to the second sub-pixel are electrically insulated from each other.
A voltage based on the video signal is applied to the first electrode.
A display device that applies a first voltage to the second electrode corresponding to the first sub-pixel and applies a second voltage different from the first voltage to the second electrode corresponding to the second sub-pixel. Driving method. Each of the plurality of sub-pixels further includes a third sub-pixel adjacent to at least one of the first sub-pixel and the second sub-pixel.
The second electrode corresponding to the third sub-pixel is electrically insulated from the second electrode corresponding to the first sub-pixel and the second electrode corresponding to the second sub-pixel.
The method for driving a display device according to claim 9, wherein a third voltage different from the first voltage and the second voltage is applied to the second electrode corresponding to the third sub-pixel. Each of the plurality of sub-pixels further includes a third sub-pixel adjacent to at least one of the first sub-pixel and the second sub-pixel.
The method for driving a display device according to claim 9, wherein the second voltage is applied to the second electrode corresponding to the third sub-pixel. The first sub-pixel displays blue and
The second sub-pixel displays one of red and green, and displays one of them.
The method for driving a display device according to claim 10, wherein the third sub-pixel displays the other of red and green. The method for driving a display device according to claim 12, wherein the first voltage is a voltage lower than the second voltage and the third voltage. The first sub-pixel displays blue and
The second sub-pixel displays one of red and green,
The method for driving a display device according to claim 11, wherein the third sub-pixel displays the other of red and green. The method for driving a display device according to claim 14, wherein the first voltage is a voltage lower than the second voltage. When a predetermined pixel among the plurality of pixels displays white, the first electrode corresponding to the first sub pixel included in the predetermined pixel and the first electrode corresponding to the second sub pixel are included. The method for driving a display device according to any one of claims 10 to 15, wherein substantially the same voltage is applied to the first electrode corresponding to the third sub-pixel.

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