JP2021026613A - Calculation device, calculation method and program - Google Patents

Abstract

To eliminate a time required for processing between cores to speed up calculation.SOLUTION: A calculation device comprises a control unit. In a neural network in which calculation in each layer is executed based on a calculation result in a previous layer, the control unit executes the calculations of the layers at predetermined calculation timing in parallel based on the calculation result of the previous layer at previous calculation timing.SELECTED DRAWING: Figure 2

Description

The disclosed embodiments relate to arithmetic units, arithmetic methods and programs.

Conventionally, there are known arithmetic devices that perform calculations for control in power train devices such as engines and brakes, and radar devices that detect objects. Such an arithmetic unit is also called an embedded microcomputer, and incorporates a system designed to control a specific device.

By the way, in recent years, it has been desired to utilize AI (Artificial Intelligence) for the calculation of devices in the embedded field. However, since embedded microcomputers often have only the minimum necessary specifications, it takes time to perform AI processing that performs a large amount of matrix operations, and the processing load also increases. Therefore, it was not suitable for AI treatment.

However, since such embedded microcomputers have become multi-core, it has become possible to reduce the processing load by dividing the arithmetic processing among a plurality of cores (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 05-282272

However, the above-mentioned conventional technique has room for further improvement in eliminating the processing waiting between cores and increasing the speed of calculation.

For example, in the neural network used in AI processing, since the operations for each node are independent, parallel operations in which different cores are assigned to each node are possible. However, in order to perform an operation on a predetermined layer in a neural network, it is necessary that all the nodes in the previous layer have completed the operation. Therefore, depending on the allocation of nodes and cores, synchronous processing that waits for the completion of operations on other cores is required.

In such synchronous processing, if there is a core whose calculation completion is delayed due to interrupt processing or the like, it is necessary for the other cores to wait for the completion, and a useless overhead is generated despite the parallel calculation by the multi-core. ..

One aspect of the embodiment is made in view of the above, and an object of the present invention is to provide an arithmetic unit, an arithmetic method, and a program capable of eliminating the processing waiting between cores and speeding up the arithmetic. And.

The arithmetic unit according to one aspect of the embodiment includes a control unit. In a neural network in which the calculation of each layer is executed based on the calculation result of the previous layer, the control unit performs the calculation of each layer at a predetermined calculation timing and the calculation result of the previous layer at the previous calculation timing. To be executed in parallel based on.

According to one aspect of the embodiment, it is possible to eliminate the processing wait between the cores and speed up the calculation.

FIG. 1A is a schematic explanatory view (No. 1) of the calculation method according to the embodiment. FIG. 1B is a schematic explanatory view (No. 2) of the calculation method according to the embodiment. FIG. 1C is a schematic explanatory view (No. 3) of the calculation method according to the embodiment. FIG. 2 is a block diagram of the in-vehicle device according to the embodiment. FIG. 3 is a diagram showing an operation image of the vehicle-mounted device according to the embodiment. FIG. 4 is an explanatory diagram of the calculation time. FIG. 5 is a flowchart showing a processing procedure executed by the in-vehicle device according to the embodiment.

Hereinafter, embodiments of the arithmetic unit, arithmetic method, and program disclosed in the present application will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments shown below.

Further, in the following, it is assumed that the arithmetic unit has a multi-core configuration and the number of cores is 3. Further, in the following, the case where the arithmetic unit is an in-vehicle device 10 mounted on a vehicle will be described as an example.

Further, in the following, after explaining the outline of the calculation method according to the embodiment with reference to FIGS. 1A to 1C, the specific configuration of the vehicle-mounted device 10 to which the calculation method according to the embodiment is applied will be described with reference to FIGS. 2 to 5. Will be explained using.

First, the outline of the calculation method according to the embodiment will be described with reference to FIGS. 1A to 1C. 1A to 1C are schematic explanatory views (No. 1) to (No. 3) of the calculation method according to the embodiment.

Note that FIGS. 1A and 1B show an example of a neural network. In such a neural network, a circle may be called a "node" and a line connecting the nodes may be called a "side".

In the neural networks of FIGS. 1A and 1B, the values X1 to X3 are input to the input layer, and the values Y1 to Y3 are subsequently added to the first layer of the intermediate layer while responding to the weights associated with each side. The values Z1 to Z3 are calculated in the two layers, and the values A1 to A3 are calculated in the output layer.

By the way, the in-vehicle device 10 according to the embodiment can be applied to, for example, various electronic control devices that electronically control the in-vehicle device. In-vehicle devices controlled by electronic control devices include powertrain devices such as engines, transmissions, and brakes, radar devices that detect objects, body devices such as air conditioners, seat belts, and door locks, and navigation devices. System equipment and safety equipment such as airbags and seat belts.

For example, the in-vehicle device 10 can use the above-mentioned neural network as a method for determining engine knocking with high accuracy. In such a case, the values X1 to X3 are, for example, images showing the waveform of the knock sensor, and the values A1 to A3 are the probabilities of the presence or absence of knocking. Such values A1 to A3 can be used, for example, for failure detection of powertrain equipment. Note that this is just an example, and the estimation by the neural network is not limited to the knocking determination and may be arbitrary.

First, FIG. 1A shows a neural network as a comparative example of the present embodiment. As shown in FIG. 1A, in the neural network according to the comparative example, the operations for each node are independent of each other in each layer after the intermediate layer, so that it is possible to perform parallel operations in which different cores are assigned to each node for a multi-core.

For example, in FIG. 1A, the values Y1, Z1, A1 are calculated on the first core, the values Y2, Z2, A2 are calculated on the second core, and the values Y3, Z3, A3 are calculated on the third core. An example of allocating each core is shown.

However, in the case of such an example, as shown in FIG. 1A, for example, when the calculation of the value Y3 by the third core is incomplete in the first layer of the intermediate layer, the value Y1 in the first core and the value Y1 in the second core. Even if the calculation of the value Y2 is completed, it is necessary to input the value Y3 in the second layer of the intermediate layer in the subsequent stage.

Therefore, the first core that calculates the value Z1 and the second core that calculates the value Z2 need to wait for the completion of the calculation of the value Y3 by the third core. Therefore, the calculation method using the neural network according to the comparative example has a problem that unnecessary overhead is generated in spite of the parallel calculation by the multi-core.

Therefore, in the calculation method according to the embodiment, each core is assigned to each layer of the neural network. Then, on that basis, the calculation at the current calculation timing in each layer is performed by inputting the calculation result of the previous calculation timing in the previous layer (hereinafter, may be referred to as "previous value").

Specifically, as shown in FIG. 1B, in the calculation method according to the embodiment, each core is assigned to each layer after the intermediate layer. For example, FIG. 1B shows an example in which the first core is assigned to the first layer L1 of the intermediate layer, the second core is assigned to the second layer L2, and the third core is assigned to the output layer.

Then, in the calculation method according to the embodiment, as shown in FIG. 1B, the calculation at the current calculation timing t in each layer is performed by inputting the calculation result of the previous calculation timing t-1 in the previous layer. ..

In order to realize this, each node of the intermediate layer (first layer L1 and second layer L2) has double buffers # 0 and # 1 as shown in FIG. 1C. These buffers # 0 and # 1 have two uses, "for storing the calculation result" and "for referring to the input value", respectively, and as shown in FIG. 1C, the buffers # 0 and # 1 are used by switching the use for each calculation timing. Therefore, it is not necessary to transfer data between buffers # 0 and # 1 such as copying the current value to the previous value.

Therefore, as shown in FIG. 1B, even if the calculation of the first layer L1 by the first core is not completed, the calculation of the second layer L2 by the second core in the subsequent stage is the previous time in the first layer L1. _{Since the values Y1 t-1 to} Y3 _t-1 , which are the calculation results of the calculation timing t-1 of, are input, no waiting is required.

The calculation time by each core in each layer is sufficiently shorter than the calculation timing cycle. Therefore, by the next calculation timing, all the operations of each core in each layer can be completed. The calculation timing can be synchronized by, for example, a timer interrupt (time synchronization) or a pulse input interrupt (crank angle synchronization in the case of a power train system).

As described above, in the calculation method according to the embodiment, each core is assigned to each layer of the neural network, and then, for the calculation at the current calculation timing in each layer, the calculation result of the previous calculation timing in the previous layer is input. I decided to do it.

Therefore, according to the calculation method according to the embodiment, it is possible to eliminate the processing waiting between the cores and speed up the calculation.

Hereinafter, the in-vehicle device 10 to which the calculation method according to the above-described embodiment is applied will be described in more detail.

FIG. 2 is a block diagram of the in-vehicle device 10 according to the embodiment. Note that, in FIG. 2, only the components necessary for explaining the features of the present embodiment are represented by functional blocks, and the description of general components is omitted.

In other words, each component shown in FIG. 2 is a functional concept and does not necessarily have to be physically configured as shown. For example, the specific form of distribution / integration of each functional block is not limited to the one shown in the figure, and all or part of the functional blocks are functionally or physically distributed in arbitrary units according to various loads and usage conditions. -It is possible to integrate and configure.

Further, in the description using FIG. 2, the description of the components already described may be simplified or omitted.

As shown in FIG. 2, the in-vehicle device 10 includes a storage unit 11 and a control unit 12. The storage unit 11 is realized by, for example, a semiconductor memory element such as a RAM (Random Access Memory) or a flash memory (Flash Memory), and includes the double buffers 11a and 11b in the example of FIG.

The double buffers 11a and 11b are the double buffers described with reference to FIG. 1C, respectively, and the use of each buffer can be switched between for storing the calculation result and for referring to the input value at each calculation timing.

Although the storage unit 11 and the control unit 12 are shown separately in FIG. 2, for example, a TCM (Tightly Coupled Memory) may be built in the control unit 12 as a part of the storage unit 11.

The control unit 12 is a so-called multi-core CPU (Central Processing Unit), and has a first core 121-1, a second core 121-2, and a third core 121-3.

In the case of the present embodiment, the control unit 12 connects the first core 121-1 to the first layer L1 of the intermediate layer, the second core 121-2 to the second layer L2 of the intermediate layer, and the third core 121-3. Assign to each output layer.

The first core 121-1, the second core 121-2, and the third core 121-3 are controllers, and for example, various programs stored in the storage device inside the in-vehicle device 10 use the RAM as a work area. It is realized by executing as. Further, for example, it can be realized by an integrated circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array).

The first core 121-1 and the second core 121-2 each have a determination unit 121a, a switching unit 121b, and a calculation unit 121c, respectively. The third core 121-3 has a determination unit 121a and a calculation unit 121c.

The determination unit 121a acquires a timer interrupt for synchronizing the above-mentioned calculation timing and a pulse input interrupt, and determines the calculation timing.

When the determination unit 121a determines that the calculation timing is reached, the switching unit 121b switches the use of each buffer between the operation result storage and the input value reference in each of the double buffers 11a and 11b.

The calculation unit 121c executes the calculation of each node in each layer of the assigned neural network. In the case of the present embodiment, the calculation unit 121c of the first core 121-1 inputs the input value to perform the calculation, and is switched for storing the calculation result in the double buffer 11a at the current calculation timing. Store the operation result in the existing buffer.

Further, the calculation unit 121c of the second core 121-2 inputs the previous value of the first core 121-1 from the buffer in the double buffer 11a that has been switched for input value reference at the current calculation timing. .. Then, the calculation is performed based on the previous value, and the calculation result is stored in the buffer switched for storing the calculation result at the current calculation timing in the double buffer 11b.

Further, the calculation unit 121c of the third core 121-3 inputs the previous value of the second core 121-2 from the buffer in the double buffer 11b that has been switched for input value reference at the current calculation timing. .. Then, an operation is performed based on the previous value, and the operation result is output as an output value.

Next, in order to make the explanation so far easy to understand, FIG. 3 shows an operation image at each of the calculation timings t and t + 1. FIG. 3 is a diagram showing an operation image of the in-vehicle device 10 according to the embodiment.

As shown in FIG. 3, at the calculation timing t, the second core 121-2 or the third core 121-3 assigned to the second layer L2 and later of the intermediate layer are the previous values (that is, that is, the previous values in each layer of the previous stage). _{The values Y1 t-1 to} Y3 _t-1 or the values Z1 _{t-1 to} Z3 _t-1 ), which are the calculation results at the previous calculation timing t-1, are input, and the calculation of each node is executed. Further, the first core 121-1 assigned to the first layer L1 of the intermediate layer inputs the input values X1 _{t to} X3 _t and executes the calculation of each node. The operations of each of these cores are executed in parallel.

Then, the calculation results in the intermediate layer (that is, the values Y1 _{t to} Y3 _t or the values Z1 _{t to} Z3 _t ) are stored in the buffers switched for storing the calculation results at the calculation timing t, respectively. Further, the calculation result (that is, the values A1 _{t to} A3 _t ) in the output layer is output.

Further, at the calculation timing t + 1, the use of each buffer is first switched in the double buffers 11a and 11b of the intermediate layer.

The second core 121-2 or the third core 121-3 assigned to the second layer L2 and subsequent layers of the intermediate layer are the previous values in each layer of the previous stage (that is, the calculation results at the previous calculation timing t). Enter the values Y1 _{t to Y3 t} or the values Z1 _{t to} Z3 _t ) and execute the operation of each node. Further, the first core 121-1 assigned to the first layer L1 of the intermediate layer inputs the input values X1 _{t + 1 to} X3 _{t + 1} and executes the calculation of each node. The operations of each of these cores are executed in parallel.

Then, the calculation results in the intermediate layer (that is, the values Y1 _{t + 1 to} Y3 _{t + 1} or the values Z1 _{t + 1 to} Z3 _{t + 1} ) are stored in the buffers switched for storing the calculation results at the calculation timing t + 1, respectively. Further, the calculation result in the output layer (that is, the values A1 _{t + 1 to} A3 _{t + 1} ) is output.

Since the previous value is input and calculated in this way, it takes time for "calculation timing cycle x number of layers after the intermediate layer" to output the output values A1 to A3 with respect to the input values X1 to X3. FIG. 4 is an explanatory diagram of the calculation time.

As shown in FIG. 4, for example, the calculation result of the first core 121-1 at the calculation timing t is finally reflected in the calculation of the third core 121-3 at the calculation timing t + 2. Therefore, when the number of layers after the intermediate layer is 3 as in the present embodiment, if the calculation timing period is 1 ms, the calculation time of the neural network is 3 ms. However, for example, the failure detection cycle of the power train system equipment is 50 ms or more, which is sufficient in time, so that the operation of the vehicle is not hindered.

Next, the processing procedure executed by the in-vehicle device 10 according to the embodiment will be described with reference to FIG. FIG. 5 is a flowchart showing a processing procedure executed by the in-vehicle device 10 according to the embodiment.

As shown in FIG. 5, first, the control unit 12 allocates each core to each layer of the neural network (step S101). Then, the determination unit 121a of each core determines the calculation timing based on the interrupt (step S102).

Here, when it is not the calculation timing (step S102, No), the processing from step S102 is repeated. In the case of calculation timing (step S102, Yes), if the intermediate layer is assigned (step S103, Yes), the switching unit 121b switches each buffer of the double buffers 11a and 11b (step S104).

If the intermediate layer is not assigned (steps S103, No), the process proceeds to step S108.

Subsequently, it is determined whether or not the second and subsequent layers of the intermediate layer are assigned (step S105). Here, when the second and subsequent layers of the intermediate layer are assigned (step S105, Yes), if there is a previous value which is the calculation result of the previous calculation timing in the previous layer (step S106, Yes), the previous time is taken. Enter the value (step S107).

If there is no previous value (step S106, No), the process from step S102 is repeated. Further, in step S105, when the second and subsequent layers of the intermediate layer are not assigned (steps S105, No), that is, when the first layer of the intermediate layer is assigned, input is performed from the input layer (step S108). ).

Then, parallel calculation is executed in each layer (step S109), and the processing from step S102 is repeated.

As described above, the in-vehicle device 10 (corresponding to an example of the "arithmetic device") according to the embodiment includes a control unit 12. In the neural network in which the calculation of each layer is executed based on the calculation result of each previous stage layer, the control unit 12 performs the calculation of each layer at a predetermined calculation timing and the calculation result of the previous stage layer at the previous calculation timing. To be executed in parallel based on.

Therefore, according to the in-vehicle device 10 according to the embodiment, it is possible to eliminate the processing waiting between the cores and speed up the calculation.

Further, the control unit 12 has a first core 121-1, a second core 121-2, and a third core 121-3 (corresponding to an example of "plurality of cores"), and the first core is for each layer of the neural network. The core 121-1, the second core 121-2, and the third core 121-3 are assigned.

Therefore, according to the in-vehicle device 10 according to the embodiment, when a plurality of cores are assigned to each layer, it is not necessary to wait for the calculation in all the cores to be completed in the previous layer. As a result, the waiting time for processing can be reduced and the operation speed can be increased.

Further, the first core 121-1, the second core 121-2, and the third core 121-3 execute the calculation for each layer of the neural network in synchronization with the calculation timing of a predetermined cycle.

Therefore, according to the in-vehicle device 10 according to the embodiment, all the cores synchronously execute the calculation for each layer of the neural network, thereby reducing the occurrence of processing waiting as much as possible and increasing the speed of the calculation. Can be done.

Further, the in-vehicle device 10 according to the embodiment has double buffers 11a and 11b for storing the calculation results at the previous and current calculation timings in the intermediate layer of the neural network.

Therefore, according to the in-vehicle device 10 according to the embodiment, it is possible to execute the calculation of each layer of the neural network at a predetermined calculation timing in parallel based on the calculation result in the previous layer at the previous calculation timing. it can.

Further, the control unit 12 switches the use of the double buffer for each calculation timing.

Therefore, according to the in-vehicle device 10 according to the embodiment, it is possible to eliminate the need for data transfer between buffers, such as copying the current value to the previous value.

In the above-described embodiment, the case where the number of cores of the control unit 12 and the number of layers after the intermediate layer of the neural network are the same is given as an example, but the number does not have to be the same. For example, if the number of cores is larger, one of the cores may be assigned. It may also be dynamically assigned while rotating between cores.

If the number of layers of the neural network is larger, the first core 121-1 → the second core 121-2 → the third core 121-3 → the first core 121- in order from the first layer L1 of the intermediate layer. It may be assigned as 1 ... If one core is assigned to each layer, it may be randomly assigned regardless of the order.

Further, for example, the control unit 12 may monitor the processing state of each core and dynamically change the allocation of each core to each layer of the neural network according to the monitoring result.

As a result, for example, when the processing load of a certain core continues to be high or a runaway state occurs, the availability of the in-vehicle device 10 is achieved by canceling the allocation of the core to the neural network and allocating another core. Can be enhanced.

Further, in the above-described embodiment, the case where the number of cores is 3 is given as an example, but it may be 2 or 4 or more.

Further, in the above-described embodiment, the in-vehicle device 10 is an example of the arithmetic unit, but of course, the use of the arithmetic unit is not limited, and it is applied to various situations where multi-core arithmetic of a neural network is performed. Can be done.

Further effects and variations can be easily derived by those skilled in the art. For this reason, the broader aspects of the invention are not limited to the particular details and representative embodiments expressed and described as described above. Therefore, various modifications can be made without departing from the spirit or scope of the general concept of the invention as defined by the appended claims and their equivalents.

10 In-vehicle device 11 Storage unit 11a, 11b Double buffer 12 Control unit 121-1 1st core 121-2 2nd core 121-3 3rd core 121a Judgment unit 121b Switching unit 121c Calculation unit

Claims (8)

In a neural network in which the operations of each layer are executed based on the operation results of the previous layer, the operations of each layer at a predetermined operation timing are performed in parallel based on the operation results of the previous layer at the previous operation timing. An arithmetic unit characterized by having a control unit to be executed. The control unit
The arithmetic unit according to claim 1, further comprising a plurality of cores and allocating the core to each layer of the neural network. The core is
The arithmetic unit according to claim 2, wherein the arithmetic operation for each layer of the neural network is executed in synchronization with the arithmetic timing of a predetermined period. The arithmetic unit according to claim 2 or 3, further comprising a double buffer for storing the arithmetic results at the previous and current arithmetic timings in the intermediate layer of the neural network. The control unit
The arithmetic unit according to claim 4, wherein the use of the double buffer is switched for each arithmetic timing. The control unit
The arithmetic unit according to any one of claims 2 to 5, wherein the processing state of the core is monitored, and the allocation of the core to each layer of the neural network is changed according to the processing state. In a neural network in which operations of each layer are executed based on the operation results of each previous layer, the operations of each layer at a predetermined operation timing are performed in parallel based on the operation results of the previous layer at the previous operation timing. An arithmetic method characterized by including a control process to be executed. In a neural network in which operations of each layer are executed based on the operation results of the previous layer, the operations of each layer at a predetermined operation timing are performed in parallel based on the operation results of the previous layer at the previous operation timing. A program that causes a computer to execute a control procedure to be executed.

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