JP2021022706A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a silicon carbide semiconductor device with improved mobility.SOLUTION: A silicon carbide semiconductor device according to the present invention includes a silicon carbide crystal region, and a gate insulating film formed on the surface of the silicon carbide crystal region, and at least surface of the gate insulating film in contact with the silicon carbide crystal region is composed of a crystal insulator, and a flat terrace width at the atomic level at the interface of the silicon carbide crystal in contact with the crystal insulator is 3.5 nm or more.SELECTED DRAWING: Figure 8

Description

The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

Conventionally, silicon (Si) semiconductors have been the mainstream semiconductors, but they have the drawback of having a small bandgap. Silicon carbide (SiC) has a bandgap of 3.25 eV, which is 3 times wider than that of Si semiconductors, and a dielectric breakdown electric field strength of 3 MV / cm, which is about 10 times larger (theoretical power loss is 300 times that of Si). 1). In addition, it has excellent thermal conductivity, heat resistance, and chemical resistance, and is more resistant to radiation than Si semiconductors. Therefore, it is expected to be a semiconductor device that is smaller in size, consumes less power, has higher efficiency, has a high frequency element, and has excellent radiation resistance than a Si semiconductor. Therefore, silicon carbide semiconductors are in high demand in the fields of space and nuclear power in addition to electric power, transportation, and home appliances. Recently, as semiconductors for hybrids and electric vehicles, they consume less power and have a heat resistant temperature of 400 ° C, which is higher than that of Si semiconductors. It is expensive and has the advantage of not requiring a heat dissipation device such as a fan for cooling, and has been actively researched and developed, and some of it has already been put into practical use.

However, in silicon carbide semiconductor devices, silicon oxide (SiO ₂ ) is used as an insulating film as a MOS type semiconductor device, but in silicon semiconductor devices, the mobility is realized up to about 50% of the theoretical value. On the other hand, there is an interface defect level at the MOS interface of silicon oxide (SiO ₂ ) / silicon carbide (SiC), and the mobility of practical products is about 20 to 30 cm ² / Vs. At present, it is only 2 to 3% of the value of 1000 cm ² / Vs. Foreign substances such as residual carbon have been proposed and investigated as the cause of the interface defect level existing at the MOS interface, but the exact cause has not yet been clarified, and the improvement of mobility in silicon carbide semiconductor devices has been described. It has become a very important issue for the practical use of silicon carbide semiconductor devices.

Non-Patent Document 1 reports that the mobility of MOSFET is increased to 120 cm ² / Vs by using the (0-33-8) plane of 4H-SiC as a silicon carbide substrate. However, this semiconductor device is a MOSFET and the insulating film is SiO ₂ , which is different from the present invention.

Non-Patent Document 2 reports that the macrostep surface of 4H-SiC was annealed in a Si melt to form a flat terrace at the atomic level, and the mobility of the 4H-SiC MOSFET increased to 102 cm ² / Vs. doing. However, this semiconductor device is a MOSFET and the insulating film is SiO ₂ , which is different from the present invention.

Non-Patent Document 3 discloses the growth of low off-angle silicon carbide crystals. However, Non-Patent Document 3 does not teach the relationship between the atomic level flatness of the crystal surface and the insulating film formed on the crystal surface.

Non-Patent Document 4 discloses a method of etching the surface of a silicon carbide crystal to flatten it at the atomic level. However, Non-Patent Document 4 does not teach the relationship between the atomic level flatness of the crystal surface and the insulating film formed on the crystal surface.

Non-Patent Document 5 reports a mobility of about 150 cm ² / Vs by producing a capacitor having an AlN / 4H-SiC interface and evaluating its electrical characteristics. However, Non-Patent Document 5 does not perform a treatment for flattening the crystal surface of the silicon carbide substrate (4H-SiC) at the atomic level before depositing AlN, and there is no teaching about the necessity and significance thereof.

Materials Science Forum 740, 506 (2013). T. Masuda eta l. "High Channel Mobility of 4H-SiC MOSFET Fabricated on Macro-Stepped Surface", Materials Science Forum Vols. 600-603, Silicon Carbide and Related Materials 2007, pp695-698 Chem. Vap. Deposition 2006, 12, 489-494 Applied Physics Letters 110, 201601 (2017) R.Y.Khosa et al., "Electrical properties of 4H-SiC MIS capacitors with AlN gate dielectric grown by MOCVS", Solid State Electronics 153 (2019) 52-58

The subject of the present invention is to elucidate the cause of the interfacial defect level of the SiO ₂ / SiC structure in the SiC MOSFET, reduce the interfacial defect level, and improve the mobility as compared with the conventional SiC MOSFET. It is to provide a semiconductor device.

In order to solve the above problems, the present invention provides at least the following aspects.
(Aspect 1)
A silicon carbide semiconductor device including a silicon carbide crystal region and a gate insulating film formed on the surface of the silicon carbide crystal region, wherein at least a surface of the gate insulating film in contact with the silicon carbide crystal region is a crystal insulator. A silicon carbide semiconductor device comprising the above, wherein the flat terrace width at the atomic level of the interface of the silicon carbide crystal in contact with the crystal insulator is 3.5 nm or more.

(Aspect 2)
The silicon carbide semiconductor device according to aspect 1, wherein the silicon carbide crystal region is a silicon carbide crystal having an off angle in the range of 0 to 4 degrees.

(Aspect 3)
The silicon carbide semiconductor device according to aspect 1 or 2, wherein the off angle is 0 to 1 degree.

(Aspect 4)
The silicon carbide semiconductor device according to aspect 2 or 3, wherein the flat terrace length at the atomic level is 40 nm or more.

(Aspect 5)
The silicon carbide semiconductor device according to any one of aspects 1 to 4, wherein the difference in lattice constant between the crystal insulator and the silicon carbide crystal is 2% or less.

(Aspect 6)
The crystal insulators are aluminum nitride (AlN), gallium nitride (GaN), aluminum phosphate (AlPO ₄ ), alumina, Be ₃ Al ₂ (SiO ₃ ) ₆ , verium oxide (BeO), RbAl ₁₁ O ₁₇ , Ba ₇ The silicon carbide semiconductor apparatus according to any one of aspects 1 to 5, which is selected from Al ₆₄ O ₁₀₃ , Al ₆ B ₅ (O ₅ F) _3, and a substance obtained by terminating these with hydrogen.

(Aspect 7)
Aspect 1 in which the silicon carbide crystal is 4H-SiC and the surfaces in contact with the crystal insulator are (000-1) surface, (0001) surface, (1-100) surface or (11-20) surface. The silicon carbide semiconductor device according to any one of Items to 6.

(Aspect 8)
The silicon carbide semiconductor according to any one of aspects 1 to 7, wherein the gate insulating film contains a second insulator different from the crystal insulator on the side opposite to the silicon carbide crystal region of the crystal insulator. apparatus.

(Aspect 9)
A method for manufacturing a silicon carbide semiconductor device including a silicon carbide crystal region and a gate insulating film formed on the surface of the silicon carbide crystal region, wherein a surface having a flat terrace width of 3.5 nm or more at the atomic level is formed. A method for manufacturing a silicon carbide semiconductor device, which comprises providing a silicon carbide crystal region having a silicon carbide crystal region and forming a crystal insulating film on the silicon carbide crystal region.

(Aspect 10)
The production method according to aspect 9, wherein the silicon carbide crystal region is composed of silicon carbide crystals having an off angle in the range of 0 to 4 degrees.

(Aspect 11)
The crystal insulating film is aluminum nitride (AlN), gallium nitride (GaN), aluminum phosphate (AlPO ₄ ), alumina, Be ₃ Al ₂ (SiO ₃ ) ₆ , verium oxide (BeO), RbAl ₁₁ O ₁₇ , Ba. ₇ The production method according to aspect 9 or 10, wherein the material is selected from Al ₆₄ O ₁₀₃ , Al ₆ B ₅ (O ₅ F) _3, and a substance obtained by hydrogen-terminating these.

(Aspect 12)
The production method according to any one of aspects 9 to 11, wherein the off angle is 0 to 1 degree.

(Aspect 13)
The silicon carbide crystal region is 4H-SiC, and the surfaces of the 4H-SiC crystal in contact with the crystal insulating film are (000-1) plane, (0001) plane, (1-100) plane, or (11-20) plane. ), And the (000-1), (0001), (1-100), or (11-20) planes of the silicon carbide crystal region are at the atomic level before the crystal insulating film is formed. The production method according to any one of aspects 9 to 12, which comprises a process of flattening with.

(Aspect 14)
Prior to the formation of the crystal insulating film, a treatment for flattening the surface of the silicon carbide crystal region at the atomic level is performed to make the terrace width of the silicon carbide crystal region 3.5 nm or more. 13. The manufacturing method according to any one of 13.

(Aspect 15)
The production method according to any one of aspects 9 to 14, wherein the crystal insulating film is formed by a chemical vapor phase deposition method or a physical deposition method.

According to the present invention, it is possible to provide a silicon carbide semiconductor device having improved mobility as compared with a conventional SiC MOSFET.

FIG. 1 is a cross-sectional view schematically showing an example of a silicon carbide semiconductor device. FIG. 2 is a schematic plan view of the layers constituting the laminate of silicon carbide crystals. FIG. 3 is a schematic perspective view showing a polymorphic crystal structure of a silicon carbide crystal. FIG. 4 is a schematic view of the polymorphic crystal structure of the silicon carbide crystal as viewed from the side. FIG. 5 is a schematic perspective view showing a crystal plane of a silicon carbide crystal. FIG. 6 shows an example of the relationship between the fluctuation of the laminated structure and the energy level at the interface between the silicon dioxide / silicon carbide crystal. FIG. 7 shows another example of the relationship between the fluctuation of the laminated structure and the energy level at the interface between the silicon dioxide / silicon carbide interface. FIG. 8 is a chart showing the calculation results of the interface states in the laminated structure of the silicon oxide / silicon carbide interface of FIGS. 6 and 7. FIG. 9 is a cross-sectional view schematically showing an ideal surface of a silicon carbide crystal having an off angle. FIG. 10 is a cross-sectional view schematically showing a non-ideal surface (with fluctuations in the surface laminated structure) of the silicon carbide crystal.

The silicon carbide semiconductor device of the present invention is a silicon carbide semiconductor device including a silicon carbide crystal region and a gate insulating film formed on the surface of the silicon carbide crystal region, and at least the silicon carbide crystal of the gate insulating film. The surface in contact with the region is composed of a crystal insulator, and the flat terrace width at the atomic level at the interface of the silicon carbide crystal in contact with the crystal insulator is 3.5 nm or more.

In the present disclosure, a "-" in a four-digit number representing a crystal direction [eg, <11-20>] or a crystal plane [eg, (0001)] is a "bar" that should be above the next number. It represents and has a negative meaning.

(Silicon carbide semiconductor device)
FIG. 1 schematically shows a typical example of a silicon carbide semiconductor device. In the example of FIG. 1, there is a silicon carbide semiconductor layer 2 epitaxially grown on a silicon carbide semiconductor substrate 1, and the silicon carbide semiconductor layer 2 is usually doped with n-type or p-type impurities and is n-type or p-type. It is in the semiconductor domain. Impurities may be doped only in a specific region of the silicon carbide semiconductor layer 2 to form an n-type or p-type semiconductor region. In FIG. 1, for example, an n-type silicon carbide semiconductor layer 2 is used. Examples of n-type impurities include nitrogen. A source region 3 and a drain region 4 are formed by doping the n-type silicon carbide semiconductor layer 2 with p-type impurities from its surface. Examples of p-type impurities include aluminum. A gate insulating film 5 is formed on the surface of the n-type silicon carbide semiconductor layer 2 in the region between the source region 3 and the drain region 4, and a gate electrode 6 is formed on the gate insulating film 5. A source electrode and a drain electrode may be formed in the source region 3 and the drain region 4 (not shown). The gate insulating film 5 has been mostly a silicon dioxide film in the past, but in the present invention, at least the surface in contact with the n-type silicon carbide semiconductor layer 2 is composed of a crystal insulator. Since there is an n-type silicon carbide semiconductor layer 2 between the p-type source region 3 and the drain region 4, no current normally flows between the source region 3 and the drain region 4. However, for example, when a voltage is applied to the gate electrode 6, an inversion layer and a p-type conductive region are formed in the n-type silicon carbide semiconductor layer 2 below the gate insulating film 5, so that the source region 3 and the drain region are formed. A current flows between 4. By turning on / off the voltage application to the gate electrode 6 in this way, the MIS field effect transistor (MISFET) can be switched. If the gate insulating film is an oxide, it is called a MOSFET.

The MISFET shown in FIG. 1 is only an example, and the MISFET has various other structures. For example, p-type, n-type, vertical type, horizontal type, composite type, etc. Further, there are other types of semiconductor devices such as tunnel junction type semiconductor devices having a gate insulating film. Further, the impurity-doped active region can be formed by filling the recesses of the semiconductor substrate with a silicon carbide semiconductor containing impurities, in addition to introducing impurities into the semiconductor substrate by ion implantation or the like. The silicon carbide semiconductor device of the present invention is not limited to the example of FIG. 1, and can be applied to any of the silicon carbide semiconductor devices having a gate insulating film. Further, the semiconductor device includes not only a transistor but also a memory device complexed with a capacitor or the like. Silicon carbide semiconductors are usually doped with n-type or p-type impurities, but may contain a genuine region not doped with n-type or p-type impurities.

(Silicon carbide crystal)
Silicon carbide is a covalent (also ionic) compound between carbon and silicon, while silicon carbide crystals are positive with carbon or silicon at the center and silicon or carbon (the other atom) arranged at the four vertices. A tetrahedron is a crystal having a three-dimensionally bonded structure. Silicon carbide crystals form a three-dimensional structure by stacking planar structures formed by bonding with each other via the vertices of a regular tetrahedron. FIG. 2 shows the SiC crystal layer seen from the direction perpendicular to the layer of the laminated body, the black circle is the atom, the atom in the center of the equilateral triangle is the apex of the regular tetrahedron, and the other atoms are the bottom surface of the regular tetrahedron. Atom of. This forms a layer packed with regular tetrahedrons. When the second layer is placed on top of this first layer, the regular tetrahedron of the second layer uses the vertices of the three regular tetrahedrons near the first layer as scaffolding, and at that time, the right end of the figure is shaded. There are two ways of arranging the top and bottom shown. The first layer is the above arrangement. The third layer has two arrangements using the vertices of the three regular tetrahedrons of the second layer as scaffolding. The lamination is repeated in this way, and the crystal polymorphism is formed by the order of each layer to be laminated (the order of repetition).

FIG. 3 shows typical crystal structures of 2H-SiC (Ultz type, AB laminated), 3C-SiC (sphalerite type, ABC laminated), 4H-SiC (ABCB laminated), and 6H-SiC (ABCACB laminated). Shown. In FIG. 3, the stacking direction is horizontal. A, B, and C represent how to stack layers based on the arrangement of central atoms of a regular tetrahedron in a laminated structure.

FIG. 4 shows the crystal structure of the laminated structure viewed from the side, that is, the SiC crystal viewed from the <11-20> direction. In FIG. 4, a large white circle ◯ represents a silicon atom, a small black circle ● represents a carbon atom, k represents a cubic site (k site), and h represents a hexagonal site (h site). In FIG. 4, silicon atoms are arranged in a horizontal row to form layers A, B, and C, and layers A, B, and C are formed according to the arrangement of silicon atoms in the horizontal plane in the stacking. Are distinguished. With reference to FIG. 4, a laminated structure of 2H-SiC (AB laminated), 3C-SiC (ABC laminated), 4H-SiC (ABCB laminated), and 6H-SiC (ABCACB laminated) is shown. The k and h shown by the silicon atom in FIG. 4 indicate that the layer has a cubic laminated structure (k-site or k-plane) and a hexagonal laminated structure (h-site or h-plane). The 2H structure has all h sites, the 3C structure has all k sites, and the 4H structure has h sites and k sites alternately stacked.

The band gaps of the silicon carbide semiconductors 2H-SiC, 3C-SiC, 4H-SiC, and 6H-SiC are 3.33 eV, 2.40 eV, 3.25 eV, and 3,10 eV, respectively, but the band gaps are large. In addition, 4H-SiC is the most promising silicon carbide semiconductor because of its low bulk mobility anisotropy and the possibility of selective crystal growth, and 4H-SiC has actually been put into practical use. There is. Although the present invention is theoretically applicable to other crystal structures that are not necessarily limited to 4H-SiC, the present invention will be described below based on 4H-SiC for practical reasons.

The crystal structure and crystal plane of silicon carbide, particularly 4H-SiC, will be described with reference to FIG. FIG. 5 is a perspective view schematically showing a hexagonal lattice model. In FIG. 5, large white circles ◯ represent silicon atoms, small black circles ● represent carbon atoms, horizontal axes a1, a2, and a3 represent three directions at 120-degree intervals in the same horizontal plane, and vertical axes c represent a1, a2, and a3. The axis is perpendicular to the axis of. The positions of the silicon atom and the carbon atom in FIGS. 5 (a) and 5 (b) are the same, and in FIG. 5 (b), the display of a part of the silicon atom and the carbon atom shown in FIG. 5 (a) is omitted. doing. In the figure, some crystal planes are hatched. The surface on which the silicon atom is exposed is the (0001) surface or the Si surface, and the surface on which the carbon atom is exposed is the (000-1) surface or the C surface. The (1-100) plane and the (11-20) plane, which are perpendicular to the Si plane and the C plane and correspond to the hexagonal side surfaces, are called the m plane and the a plane, respectively. In addition, the Si surface and the C surface have diagonal s and r surfaces.

(Atomic level fluctuation at the interface of silicon carbide crystal)
Silicon carbide semiconductors differ in bandgap by as much as 40% depending on the crystal polymorphism, that is, the laminated structure. The band gaps of 2H-SiC (AB laminated), 3C-SiC (ABC laminated), 4H-SiC (ABCB laminated), and 6H-SiC (ABCACB laminated) are 3.33 eV, 2.40 eV, 3.2 eV, respectively. It is 3.10 eV.

When SiO ₂ is used as the gate insulating film, since it has an amorphous structure, the medium- to long-distance correlation of the interface structure disappears. Therefore, for example, in 4H-SiC, it can be considered that several kinds of interface laminated structures are mixed at the interface. it can. For example, FIG. 6 shows an example of the energy level near the interface between the insulating film and the silicon carbide crystal, and FIG. 6 (a) shows the energy level when the interface is the A layer (k-site), FIG. 6 (b). Schematically shows the energy levels when the interface is the B layer (h site). In FIGS. 6A and 6B, the horizontal axis is the position in the direction perpendicular to the interface, the left side of the figure is the 4H-SiC layer, and the right side is the SiO ₂ layer. The vertical axis represents the energy level, the lower line of the figure shows the lower end of the valence band, and the upper line shows the energy level of the conduction band. At the crystal interface of a cubic laminated structure having a laminated structure of BCBABCBA (A at the right end is the interface) as shown in FIG. 6 (FIG. 6A), if the A layer at the interface is locally missing, BCBABCB ( The rightmost B is the interface), and the 2H structure (CB) appears at the interface. Since the 2H-structured laminated structure (CB) is an h-site (hexagonal laminated structure) (Fig. 6 (b)), this 4H-SiC crystal is cubic even if there are no impurities or defective structures at the interface. The interface state shifts upward at the hexagonal site compared to the crystal site. As described above, due to the difference in the atomic-level laminated structure of the interface, a site where cubic sites and hexagonal sites coexist is generated, and the effective interface potential for electrons fluctuates.

Further, as shown in FIG. 7, at the crystal interface of the laminated structure of BCBABCB (B at the right end is the interface) in which the A layer at the interface is missing (FIG. 7 (b)), the B layer at the interface becomes the A layer. When a defect occurs, it becomes a laminated structure of BCBABCA (A at the right end is the interface) (Fig. 7 (c)), and the interface state of the ABCA laminated structure at the interface is lower than that of the cubic site (Fig. 7 (a)). There is a shift, where the interface state fluctuates with respect to the cubic site.

The effective potential fluctuation caused by the difference in the laminated structure of the crystal interface as described above has not been noticed so far, and SiO ₂ is used as the gate insulating film. Except for special cases for research purposes, the fluctuation of the atomic-level lamination at the interface was not fully considered in the semiconductor device. The present inventor investigated how much the atomic level defects and stacking defects at the crystal interface as described above affect the mobility in the gate channel of the semiconductor device by first-principles calculation. As a result, it was clarified that the influence on the mobility based on the fluctuation of the atomic-level stacking at the interface is unexpectedly large and remarkable.

In the case of having the laminated structure of the above three types (a), (b) and (c) of the interface, the level energy near the interface was actually simulated by the first principle calculation. The details of the calculation are as described in the examples, but the first-principles calculation based on the density functional theory was performed, and the HSE06 functional was used as the exchange correlation energy functional. As a result, all three types of interfacial laminated structures have almost no change in energy, and even the energy difference between the most stable interfacial laminated structure (a) and the most unstable interfacial laminated structure (c) is 5.79 meV. It was as small as / Å ² . Therefore, from a theoretical point of view, it was shown that the interfacial laminated structures (a), (b), and (c) coexist at the actual interface. Local density of states (LDOS) was also calculated to evaluate band alignment at the interface. See FIG.

As a result of the above calculation, as shown in FIG. 8, the interface state energy of the hexagonal laminated interface is as large as +1.2 eV as compared with the case of the cubic laminated interface of (a), and the interface state energy of (c) is increased. In the case of a stacking defect interface, the interface state energy was as small as −0.3 eV. The band gap of silicon dioxide (SiO ₂ ) is 8.95 eV, and it functions as a sufficient insulator for the 4H-SiC layer at any interface. In this way, even if there are no defects or impurities at the interface, the interface state is from CBM-0.3eV to CBM + 1.2eV due to fluctuations in the interfacial laminated structure of silicon carbide. It can be seen that it can change in the range of and behaves as a scattering source of carriers.

Therefore, if the laminated structure fluctuates at the single atomic level at the interface, potential fluctuation may occur in the electronic state at the lower end of the conduction band (CBM), which may affect the characteristics of the semiconductor device (device). That is, at such an interface, the wave function of CBM is localized, reflecting the fluctuation of the SiC laminated structure at the interface (the A layer and the B layer come together), and the electron (hole) It is thought that the effective mass will be affected.

Based on this result, the present inventor further found that a defect in the laminated structure at the monoatomic layer level at the interface of SiO ₂ / 4H-SiC (a structure in which both the A layer and the B layer come together) causes the movement of the 4H-SiC layer. Regarding the effect on mobility, the effective mass of electrons (holes) was calculated from the curvature of the electron band structure obtained by the first-principles calculation. It is known that mobility is inversely proportional to effective mass. Details of the calculation of this effective mass are as described in the examples. First, a SiO ₂ / 4H-SiC interface structure model in which various interface laminated structures coexist was created. Here, as one simplification, a 4H-SiC slab with a thickness of 10 Å was prepared, and a hydrogen-terminated model that imitated the contact surface with SiO ₂ was created. In addition, a model was prepared so that various interfacial laminated structures coexist in the interfacial structure, and the structure was optimized. Then, the electron band structure in the in-plane direction was calculated, and the effective electron (hole) mass was calculated from the curvature.

As a result, the effective mass of the bulk of SiC was 0.3m ₀ (m ₀ is the mass of electrons), but the (0001) plane, (000-1) plane, (1-100) plane or (1-100) plane or ( The effective mass at the ideal interface of the 11-20) plane was also 0.3 m ₀ , and it was found that if the interface is controlled at the atomic level, these planes are also about the same as the effective mass of the bulk. That is, if the interface can be controlled at the atomic level on these crystal planes, there is a possibility that effective mass and mobility equivalent to those of bulk can be realized.

On the other hand, assuming that there is an atomic level defect at the ideal interface of the (000-1) plane, that is, fluctuation of the laminated structure (both k-site and h-site are present at the interface), the effective mass of electrons is assumed. Became 1.8m ₀ . The same applies to the (0001) plane, the (1-100) plane, or the (11-20) plane. The interface of SiC is not controlled at the atomic level, that is, the effective mass of electrons at the interface is 6 times that of the bulk only by the fluctuation of the laminated structure at the interface. That is, it was confirmed that the effective mass and mobility of electrons can be remarkably improved by controlling the interface at the atomic level.

The present invention is effective due to amorphous SiO ₂ by controlling the surface of the SiC crystal before depositing the gate insulating film at the atomic level and using a crystal insulating film instead of the conventional SiO ₂ as the gate insulating film. Prevent the occurrence of potential fluctuations. The crystal insulating film will be described in more detail later, but if a crystal insulating film is used, unlike amorphous SiO _2, it is not affected by dangling bonds and the like, and the laminated structure is controlled to be flat at the atomic level when the gate insulating film is formed. Is possible. If the SiC surface before the formation of the crystal insulating film is an ideal flat surface, the SiC interface can be an ideal flat interface even after the formation of the crystal insulating film. As a result, the effective mass and mobility of the electrons obtained by the above calculation can be improved. In a conventional silicon carbide semiconductor device, many interface defects are present due to fluctuations in the surface laminated structure of silicon carbide that has existed before the formation of the crystal insulating film. If many interface defects at the interface of silicon carbide are reduced, the value of improvement in effective mass and mobility of electrons according to the present invention can be further increased. It is also effective to use a crystal insulating film instead of SiO ₂ in improving the large interface defect of the silicon carbide interface.

The improvement in mobility estimated from the above calculation results is only 6 times as much as the prevention of atomic level fluctuations that may occur at the insulator / SiC interface, and the mobility of the conventional general SiO ₂ / SiC interface is 6 times. based on the 20 to 30 cm ² / Vs, even if simple comparison, 120~180cm ² / Vs is obtained. Further, it is known that the mobility of the SiO ₂ / SiC interface is 30 to 50 cm ² / Vs or more. Therefore, if the present invention is applied to the mobility, the mobility can be improved to 180 to 300 cm ² / Vs. Be expected. Further, according to the present invention, by using the crystalline insulating film in place of the SiO _2, interface defects, for example, polymorphisms caused by SiO ₂ film forming non-defective by the interfacial fluctuation of assumed atomic level above calculation Since it is possible to reduce interfacial defects due to the appearance of crystal regions, non-flatness of silicon carbide crystals, the presence of foreign substances such as carbon, etc., as a result, the improvement of mobility according to the present invention can be further increased. Therefore, it is considered that the improvement of these interfacial defects is no less than the influence on the mobility based on the fluctuation of the atomic-level stacking assumed in the above calculation.

(Gate insulating film)
As described above, according to the first-principles calculation, controlling the laminated structure at the interface of the SiC crystal at the atomic level is extremely important for improving the mobility, but the gate insulating film formed on the SiC substrate is With the conventional SiO ₂ , even if the laminated structure at the atomic level is controlled at the atomic level before film formation, the laminated structure inevitably fluctuates after the film formation. In the present invention, in order to control the laminated structure of the gate insulating film / SiC interface of the semiconductor device at the atomic level, a crystal insulator is used as the gate insulating film instead of the amorphous SiO ₂ .

Since SiO ₂ is amorphous and there is no medium- to long-range correlation in the interface structure, when forming a SiO ₂ film on the surface of a SiC crystal, the lattice constants may differ between SiO ₂ and SiC, even before film formation. Even if the surface of the SiC crystal is controlled at the atomic level, the laminated structure of the SiO ₂ / SiC interface inevitably fluctuates at the atomic level after the SiO ₂ film is formed. Atomic level fluctuations in the laminated structure of the interface occur regardless of whether the SiO ₂ film is formed by thermal oxidation or by the vapor phase deposition method. However, by using a crystal insulator instead of the amorphous SiO ₂ as the gate insulating film, it is possible to maintain the laminated structure of the gate insulating film / SiC interface at the atomic level and control the SiC interface at the atomic level. Will be done. By controlling the laminated structure of the SiC interface at the atomic level, the effective mass can be remarkably reduced and the mobility can be remarkably increased, as shown in the above calculation. According to the above calculation, if the control of the laminated structure of the SiC interface is ideal, the effective mass can be reduced to about 1/6 and the mobility can be increased to about 6 times.

The crystal insulator used for the gate insulating film may be a crystal that functions as an insulator against SiC. To function as an insulator with respect to SiC means that the energy levels of the valence band and conduction band of the substance are offset from the energy levels of the valence band and conduction band of SiC, that is, the insulator. The energy level of the valence band of SiC is lower than the energy level of the conduction band of SiC, and the energy level of the conduction band of the insulator is higher than the energy level of the conduction band of SiC. The size of the energy gap to be offset does not have much influence on the mobility in SiC, and in the present invention, the offset may be sufficient, but a large energy gap is preferable. Whether or not a particular substance is an insulator against SiC is known and is easy to measure.

The gate insulator may be a crystal insulator having a medium- to long-distance correlation. If the gate insulating film is composed of a crystal insulator, when the crystal insulator is formed on the SiC crystal plane, the film can be formed without disturbing the atomic level laminated structure of the SiC crystal plane. Will be done. The fact that the insulator is a crystal means that a peak peculiar to the crystal may be present by X-ray analysis. It may be polycrystalline or single crystal, but it is preferably single crystal.

Examples of crystal insulators include aluminum nitride (AlN), gallium nitride (GaN), aluminum phosphate (AlPO ₄ ), alumina, Be ₃ Al ₂ (SiO ₃ ) ₆ , verium oxide (BeO), RbAl ₁₁ O ₁₇ , Ba ₇ Al ₆₄ O ₁₀₃ , Al ₆ B ₅ (O ₅ F) ₃ , and the like. They may also be combined with hydrogen terminations to remove interfacial dangling bonds. Methods and examples of hydrogen termination are known. It is preferable that the crystal insulator does not contain K and Na because the variation in the threshold voltage is small.

The mismatch of the lattice constants between SiC and the crystal insulator is preferably 2% or less, more preferably 1% or less. The lattice constants of silicon carbide are a = 3.1 Å and c = 10.12 Å. It is considered that the smaller the mismatch of the lattice constants, the smaller the influence of the crystal insulator on the control of the atomic level of the SiC interface. It is preferable that the crystal systems are the same or similar, but the crystal systems do not have to be the same as long as the lattice constant mismatch is small. Aluminum nitride (AlN), gallium nitride (GaN), aluminum phosphate (AlPO ₄ ), alumina, Be ₃ Al ₂ (SiO ₃ ) ₆ , berium oxide (BeO), RbAl ₁₁ O ₁₇ , with small lattice constant mismatch. Ba ₇ Al ₆₄ O ₁₀₃ , Al ₆ B ₅ (O ₅ F) _{3, and the} like are preferable, and aluminum nitride is particularly preferable.

In the present invention, the crystal insulator used for the gate insulating film is in contact with the SiC base material or the SiC crystal region. Since the purpose is to control the atomic level of the surface of the SiC crystal, the crystal insulating film must form an interface with the SiC crystal.

The film thickness of the crystal insulating film may be not less than the thickness of the bilayer, but is preferably 5 nm or more, more preferably 10 nm or more. The upper limit of the film thickness is determined by the characteristics required for the semiconductor device and is not particularly limited, but may be, for example, 40 nm or 50 nm. The crystal insulating film may be composed of a single-layer or multilayer crystal insulating film.

The gate insulating film of the present invention may have a surface in contact with the SiC interface made of a crystal insulating film, and an amorphous insulator, particularly a SiO ₂ film, is laminated on the opposite side of the crystal insulating film from the SiC interface. It may have been done. Laminating the SiO ₂ film is preferable because the characteristics as an insulating film can be improved and the film thickness can be adjusted.

The method for forming a crystal insulating film is not limited. Either a chemical gas phase deposition method such as an organometallic chemical gas phase deposition method or a plasma-assisted chemical gas phase deposition method, or a physical gas phase deposition method such as a sputtering method, a vapor deposition method, or a laser beam sputtering method may be used. .. A film-forming method in which the energy of atoms or molecules deposited on the surface of a SiC substrate during film-forming is small, for example, a chemical gas phase deposition method, an organometallic chemical gas phase deposition method, or an atomic layer chemical gas phase deposition method preferable.

Aluminum nitride is prepared from a nitrogen source such as ammonia and an aluminum source such as alkylaluminum as raw materials in a chemical vapor phase on a SiC substrate in an inert atmosphere or a nitrogen atmosphere, for example, at 1000 to 1200 ° C. May be deposited. Alternatively, aluminum nitride may be deposited directly on the SiC substrate by a sputtering method.

(Atomic level flatness on the surface of SiC substrate)
According to the present invention, by forming a crystal insulating film on a SiC crystal surface that is flat at the atomic level, a semiconductor device having a crystal insulating film / SiC crystal interface that is flat at the atomic level is provided. In the present invention, the atomic level flatness of the crystal insulating film / SiC crystal interface (or SiC crystal surface) is a dimension in which the SiC crystal at the interface (or surface) does not have fluctuations or defects in the atomic level laminated structure. Can be defined as the dimension of the SiC crystal without atomic level defects in the cross section parallel to the off-angle of the SiC crystal at the interface (or surface), that is, the terrace width. The atomic level flatness of the interface (surface) is determined by observing the cross section of the SiC crystal at the interface (surface) parallel to the off-angle with a scanning electron microscope (SEM), atomic force microscope (AFM), etc. It can be obtained by measuring the size (terrace width) of the SiC crystal without the absence. The atomic level flatness (terrace width) of the interface (surface) is measured at any two or more points, preferably three or more points, and the average value thereof is adopted. The measurement dimension in the terrace width direction of the observation field of view in each measurement is generally 40 nm or more, but when the terrace width is large, the measurement dimension is also increased accordingly.

The atomic level flatness of the crystal insulating film / SiC crystal interface in the present invention is the terrace width without atomic level defects. The level difference between the terraces can generally be one layer or at most a few layers, but the level difference between the terraces existing at the crystal insulating film / SiC crystal interface in the present invention is. It is 4 steps or less (not including steps of 5 steps or more). The steps between the terraces are preferably 3 steps or less, 2 steps or less, 1 step or less, and most preferably no steps. Further, it is preferable that the average value of the steps between the terraces is 3.5 or less, 3 or less, 2 or less, and 1 or less.

The atomic-level flat terrace width of the crystal insulating film / SiC crystal interface in the present invention is 3.5 nm or more. The theoretical surface terrace width of a 4 degree off SiC crystal is 37 Å (3.7 nm). The atomic level flatness of the crystal insulating film / SiC crystal interface in the present invention is preferably 3.7 nm or more (or more than 3.7 nm) and 4 nm or more. The higher the atomic level of flatness of the SiC crystal interface, the more preferable it is, but more preferably 10 nm or more, 40 nm or more, 50 nm or more, 100 nm or more, 200 nm or more, 300 nm or more, and further 500 nm or more. There is no upper limit to the flatness, but from the viewpoint of the manufacturability of the semiconductor device, it may be, for example, 2000 nm or less, 1000 nm or less, 500 nm or less.

Further, the atomic level flat terrace width of the crystal insulating film / SiC crystal interface is preferably 1/20 or more of the gate channel length, and 1/10 or more, 1/5 or more, and 1/3 or more. More preferably, it is more than half. The gate channel length is not limited, but may be, for example, 10 nm to 10 μm, 10 nm to 1 μm, and further 40 nm to 100 nm. For example, when the gate channel length is 1 μm, the flatness at the atomic level is preferably 50 nm or more, more preferably 100 nm or more, and it can be realized at an off angle of about 0.15 degrees without defects at the atomic level. Further, if the gate channel length is 100 nm, the atomic level flatness is 100 nm in SiC having an off-angle of about 0.15 degrees without atomic level defects, that is, atomic level defects in the overall length of the gate channel. It is possible to realize an interface without. For example, when the gate channel length is 40 nm to 100 nm, it is particularly preferable that the atomic level flat terrace width is 40 nm to 100 nm, which is the same as the total length of the gate channel length.

According to the present invention, the flatness at the atomic level at the crystal insulating film / SiC crystal interface is enhanced, and the flat terrace width at the atomic level is set to 3.5 nm or more, whereby the interface state is lowered as compared with the conventional semiconductor device. It is possible to increase the mobility.

To set the atomic level flat terrace width at the crystal insulating film / SiC crystal interface to 3.5 nm or more, use a SiC base material having a surface atomic level flat terrace width of 3.5 nm or more as the SiC base material. This is possible by forming a crystal insulating film as a gate insulating film to be formed on the SiC substrate. By forming a crystal insulating film, the flatness is maintained at the atomic level on the surface of the SiC base material, and at least the decrease in flatness at the atomic level is significantly reduced as compared with the case where SiO ₂ is formed. Is possible.

A SiC base material having a flat terrace width of 3.5 nm or more at the atomic level on the surface is created by using a SiC base material with a small off-angle and by performing a treatment to flatten the surface of the SiC base material at the atomic level. can do.

SiC substrates with a small off-angle are treated by a method for growing SiC with a low off-angle (eg, Chem. Vap. Deposition 2006, 12, 489-494), or by polishing or etching the surface of the SiC substrate. It may be created by a method of reducing the off-angle, or by a combination thereof.

The process of flattening at the atomic level aims to increase the terrace width, narrow the step, eliminate the atomic level defects on the terrace surface, and improve the flatness of the SiC substrate having the same off-angle. The process of flattening at the atomic level may be a process of performing the SiC base material at the same off-angle, or at the same time, a process of reducing the off-angle. Especially when the off angle is 0 degrees or close to 0 degrees, the treatment of flattening at the atomic level aims to eliminate defects at the atomic level on the surface and improve the flatness. The method of flattening the SiC crystal surface at the atomic level is not limited, but for example, a method of annealing the SiC crystal surface in an atmosphere of an inert gas such as argon, or a method of depositing Si on the SiC crystal surface and then exceeding the melting point of Si. A method of etching and removing Si with an acid after annealing at the above temperature (see Non-Patent Document 2), and a catalyst etching method (Catalyst-Referred Etching (CARE method)) which is a chemical etching with hydrofluoric acid or pure water under platinum catalyst assist. ; See APL 110, 201601 (2017)). These methods may be repeated or combined.

There are many other proposals for the production of silicon carbide crystals with low off-angle and the method of flattening the surface of silicon carbide crystals at the atomic level. ) Is often not reported. In the present invention, before forming the crystal insulating film, the atomic level flatness of the silicon carbide crystal surface, that is, the atomic level flat terrace width is set to a predetermined size, 3.5 nm or more, preferably more than that. It is necessary to. Therefore, after concretely performing the flattening treatment, the flat terrace width is measured at the atomic level of the silicon carbide crystal surface to confirm that the terrace width is a predetermined size. It is desirable to make sure that provides a terrace width of a given size.

Conventionally, various methods for growing SiC with a low off-angle and flattening the surface of a SiC crystal have been independently studied, but with a SiO ₂ film subsequently formed on the surface of a SiC crystal. There is no example in which its significance was examined in connection. In addition, although there is an example of examining the formation of an AlN film on the surface of a SiC crystal, it has not been investigated in relation to the atomic level flatness (fluctuation of lamination) on the surface of a SiC crystal, so that an AlN film is formed. The importance of flattening the surface of the SiC crystal before this is not recognized. In the present invention, as a result of actually evaluating the influence of the fluctuation of the atomic level lamination on the SiC crystal surface on the mobility by the first-principles calculation, the fluctuation of the atomic level lamination on the SiC crystal surface is eliminated or reduced (the surface is changed). It has been found that the mobility of a MIS semiconductor device can be remarkably improved at a level not previously expected by forming a crystal insulating film on the crystal insulating film (after flattening it at the atomic level).

(Off angle of SiC base material)
According to the present invention, the mobility is improved by using a crystal insulator as the gate insulating film and controlling the laminated structure of the surface of the SiC base material itself at the atomic level. Conventionally, SiC having an off-angle of 0 to 8 degrees or more can be produced as a SiC crystal base material, but recently, SiC having an off-angle of 4 degrees is often used. This means that the fluctuation of the atomic level lamination of the laminated structure based on the off angle of the SiC interface is not considered to be a big problem in relation to the mobility. This is probably because the influence of SiO ₂ is large at the SiO ₂ / SiC interface and the influence of the off angle disappears. Non-Patent Document 5 also uses SiC with a 4 degree off-angle, and does not consider the atomic level defects on the surface of the SiC substrate before AlN film formation, so that the mobility can be improved as expected. Not realized.

According to a preferred embodiment of the present invention, it is effective to reduce the off-angle of the SiC substrate in order to control the atomic level flatness of the SiC surface. The off angle of the SiC base material is preferably 4 degrees or less. The smaller the off-angle of the SiC base material, the smaller the atomic level fluctuation of the laminated structure at the SiC interface, and the higher the mobility. Here, the off-angle of the SiC substrate is the off-angle of the SiC crystal at the crystal insulator / SiC interface, and if the SiC substrate is a crystal layer or a crystal region epitaxially grown on the SiC substrate, the epitaxial crystal layer thereof. Alternatively, it is the off-angle of the crystal region, not the off-angle of the SiC substrate, which is the substrate for growing the epitaxial crystal layer or the crystal region. For example, even if the SiC substrate is off by more than 4 degrees, the off angle of the epitaxial crystal layer or the crystal region can be preferably 0 to 4 degrees.

Adjusting the off-angle of the SiC substrate adjusts the off-angle of the SiC substrate itself, causes an epitaxial crystal layer to grow on the SiC substrate having a predetermined off-angle, or grows on the SiC substrate or the SiC substrate. It is possible to adjust the off-angle of the epitaxial crystal layer ex post facto, and to combine these. Methods for producing SiC substrates and epitaxial crystal layers having a specific off-angle are known. As a method of ex post-adjusting the off-angle of the surface of the SiC substrate or the epitaxial crystal layer, a method of tilting and fixing the base material at a predetermined angle and etching the surface to form a predetermined off-angle is known. Has been done.

The off-angle of the SiC substrate in the present invention is preferably in the range of 0 to 4 degrees, and may be in the range of 0 to 3.5 degrees. Generally, it is preferable that the off angle is small. For example, 0 to 1 degree is preferable, 0 to 0.1 degree is more preferable, and 0 to 0.05 degree and 0 to 0.015 degree are particularly preferable. The off angle of the SiC base material is the angle formed between the lamination of the SiC crystals and the interface at the crystal insulator / SiC interface. The off-angle of the SiC base material can be measured by observing the cross section of the crystal insulator / SiC interface with a TEM, AFM, or the like and measuring the angle at which the SiC crystal is laminated with respect to the interface. The interface may be a line that minimizes the unevenness in the cross section of the interface, and in the present invention, the average value of the unevenness at the atomic level. The measurement (calculation) method for measuring the average surface roughness of a flat surface may be referred to. The angle formed by the lamination of the SiC crystals and the interface varies depending on the cross-sectional direction of the SiC base material, but the maximum angle is the off angle.

FIG. 9 shows a schematic cross section of the ideal interface of SiC having an off angle θ. In this figure, the surface (for example, (0001) surface) 22 of the SiC crystal 21 having an off angle θ is ideally a flat surface (indicated by the virtual line 22), and the step is the minimum (only for one laminated layer). I'm drawing the case. The parallel lines inside the SiC crystal 21 represent each layer of the stack, and the angle θ between the surface (virtual line) 22 of the crystal and each layer of the stack represents the off angle. However, FIG. 9 is a schematic diagram for explanation, and the off-angle and the spacing between each layer are exaggerated. The SiC crystal 21 with an off-angle θ has a terrace 23 and a step 24. In this figure, the terrace is an ideal surface, that is, flat at the atomic level, and the step 24 is drawn perpendicular to the terrace 23. There is. The dimension of the terrace 23 having no defects at the atomic level in the cross section in the off direction is called "terrace width". FIG. 9 shows the terrace width Wt.

FIG. 10 schematically shows an example of a non-ideal (surface stacking fluctuation) surface of a SiC crystal. In FIG. 10, 25-1, 25-2, ... 25-7, 25-8 are flat terraces, for example, terraces 25-1, 25-3 are terraces that are even higher than terraces 25-2. , Terrace 25-6 is two levels higher than Terrace 25-5 and is a stepped terrace higher than Terrace 25-7. W ₁ , W ₂ , ... W ₇ represent the terrace width. Each of the terraces 25-1, 25-2, ... 25-7 has the structure of any one of (a), (b), and (c) of FIG.

(Manufacturing method of semiconductor device)
The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a silicon carbide semiconductor device including a silicon carbide crystal region and a gate insulating film formed on the surface of the silicon carbide crystal region, and has a flat terrace width at the atomic level. It is characterized by providing a silicon carbide crystal region having a surface having a surface value of 3.5 nm or more, and comprising forming a crystal insulating film on the silicon carbide crystal region.

By using a SiC base material having a flat terrace width of 3.5 nm or more at the atomic level on the surface as the SiC base material and using a crystal insulating film as the gate insulating film to be formed on the SiC base material, the crystal insulating film / The atomic level flat terrace width at the SiC crystal interface can be 3.5 nm or more. By forming a crystal insulating film instead of the conventional amorphous SiO ₂ film, it is possible to prevent defects from being induced on the surface of the SiC substrate which is flat at the atomic level after the film formation, and at least at the atomic level. Defects can be substantially reduced as compared with the case of using a SiO ₂ film.

A SiC base material having a flat terrace width of 3.5 nm or more at the atomic level on the surface is created by using a SiC base material with a small off-angle and by performing a treatment to flatten the surface of the SiC base material at the atomic level. can do.

For SiC substrates with a small off-angle, the off-angle can be reduced by carrying out the growth of SiC at a low off-angle, or by polishing or etching the surface of the SiC substrate to reduce the off-angle. Can be created in combination. As a method for carrying out the growth of SiC at a low off-angle, for example, Chem. Vap. Deposition 2006, 12, 489-494 is known, but the low-off-angle SiC substrate obtained by this method has a low off-angle. At the same time as the off-angle, it is also excellent in the atomic level flatness of the surface.

The process of flattening at the atomic level aims to increase the terrace width, narrow the step, eliminate the atomic level defects on the terrace surface, and improve the flatness of the SiC substrate having the same off-angle. The process of flattening at the atomic level may be a process of performing the SiC base material at the same off-angle, or at the same time, a process of reducing the off-angle. Methods for flattening the surface of a SiC crystal at the atomic level include the above-mentioned methods (Catalyst-Referred Etching (CARE method); APL 110, 201601 (2017)). These methods may be repeated or combined. The SiC base material obtained by the flattening treatment method can have a low off-angle and at the same time have excellent surface flatness at the atomic level.

In one preferred embodiment, the silicon carbide crystal region is 4H-SiC and the surface of the 4H-SiC crystal in contact with the crystal insulating film is the (000-1) plane, (0001) plane, (1-100) plane or (1-100) plane. It is the 11-20) plane, and the (000-1) plane, (0001) plane, (0-110) plane, or (11-20) plane of the silicon carbide crystal region is atomized before forming the crystal insulating film. Includes processing to flatten at the level.

In one preferred embodiment, the crystal insulating film is formed by a chemical vapor phase deposition method or a physical deposition method. The method for forming the crystal insulating film may be a known method, but the chemical gas phase deposition method, the organic chemical gas phase deposition method, and the atomic layer chemical gas phase deposition method, which have low deposition energy, are used. preferable.

It should be noted that the semiconductor device, the silicon carbide crystal region, the flatness at the atomic level, the gate insulating film, the crystal insulating film, the off-angle, and the like have already been described in relation to the semiconductor device.

The semiconductor device of the present invention is a silicon carbide semiconductor device including a silicon carbide crystal region and a gate insulating film formed on the surface of the silicon carbide crystal region, and is a silicon carbide crystal region and a gate insulating film formed on the surface thereof. Other than that, as described above, any conventional silicon carbide semiconductor device may be used. In the example of FIG. 1, after depositing a crystal insulating film on the surface of the silicon carbide crystal region, the crystal insulating film is patterned to form a gate insulating film, and then a gate electrode is formed (deposited) on the gate insulating film. And patterning). Then, an interlayer insulating film is deposited as a whole, the interlayer insulating film is patterned, a window for forming a source region and a drain region is opened in the interlayer insulating film, and the source region and the drain region are selectively formed through the window. Impurities are diffused or doped to form a source region and a drain region. Then, the source electrode and the drain electrode in contact with the source region and the drain region are formed.

First-principles calculations were performed on the effect of atomic-level flatness at the insulator / silicon carbide crystal interface on the interface state.

Silicon carbide semiconductors have different band gaps depending on the crystal polymorphism, that is, the laminated structure. For example, a 4H-SiC crystal contains k-sites (cubic-based laminated structure) and h-sites (hexagonal-based laminated structure), and k-sites and h-sites are alternately arranged.

FIG. 6 shows the energy level near the interface between the insulating film and the silicon carbide crystal. FIG. 6A schematically shows the energy level when the interface is the A layer (k site), and FIG. 6B schematically shows the energy level when the interface is the B layer (h site). In FIGS. 6A and 6B, the horizontal axis is the position in the direction perpendicular to the interface, the left side of the figure is the 4H-SiC layer, and the right side is the SiO ₂ layer. The vertical axis represents the energy level, the lower line of the figure shows the lower end of the valence band, and the upper line shows the energy level of the conduction band.

The laminated structure of the interface shown in FIG. 6A is BCBABCBA (the right end is the interface) and is the interface A layer (k site), and FIG. 6B is the interface A of the laminated structure shown in FIG. 6A. Laminated structure BCBABCB (the right end is the interface) where the B layer (h site), which has been further oxidized from the layer, appears at the interface.
It is an interface B layer (h site). In the laminated structure BCBABCB (the right end is the interface), a laminated 2H structure appears locally at the interface. The interface state (bandgap) in the lamination of the 2H structure in the case of the interface B layer (h site) is higher than the interface state (bandgap) in the case of the interface A layer (k site). As described above, when (a) and (b) of FIG. 7 are present, the energy levels are different when the interface is the A layer and when the interface is the B layer.

(A) and (b) of FIG. 7 correspond to (a) and (b) of FIG. 6, and (c) of FIG. 7 is the interface B layer (h site) of FIGS. 6 (b) and 7 (b). In contrast to the laminated structure BCBABCB (the right end is the interface) in the case of the above case, the laminated structure BCBABCA (the right end is the interface) of the laminated defect interface where a stacking defect occurs in the B layer of the interface and becomes the A layer is shown. In the case of the stacking defect interface of FIG. 7 (c), the interface state of the laminated structure ABCA (the interface at the right end) is lower than the interface state of the cubic crystal (k-site), and thus the interface state is laminated. It can be seen that the interface state differs and fluctuates just by changing the structure.

In the case of having the laminated structures (a) to (c) of the three types of interfaces shown in FIGS. 6 and 7, the result of actually simulating the level energy near the interface by the first principle calculation is shown in FIG. (A) to (c) are shown. Compared with the case of the cubic interface A layer of FIG. 6 (a), the interface state energy of the hexagonal interface B layer of FIG. 6 (b) is as large as +1.2 eV, and that of FIG. 7 (c). In the case of the hexagonal laminated defect A layer, the interface state energy is as small as −0.3 eV. The band gap of silicon dioxide (SiO ₂ ) is 8.95 eV, and it functions as a sufficient insulator for the 4H-SiC layer at any interface.

This first-principles calculation is as follows. In the case of having a laminated structure of the above three types (a), (b) and (c) interfaces, the level energy near the interface was actually simulated by first-principles calculation. The outline of the calculation is as follows.

First-principles calculations based on density functional theory were performed. As the calculation code, the Vienna Ab initio simulation package (VASP) was used. In fact, in the calculation code, the following eigenvalue problem called Kohn-Sham equation was solved using the conjugate gradient method.
It is divided into. In this calculation, the bandgap of 4H-SiC of 3.2 eV was quantitatively reproduced by using 0.2 [Å ^-1 ] as μ.
Paper [1] J. Perdew, K. Burke, and M. Ernzerhof, Physical Review Letters 77, 3865 (1996).
Paper [2] J. Heyd, GE Scuseria, and M. Ernzerhof, Journal of Chemical Physics 118, 8207 (2003).

The computer used was Supercomputer System C, Institute for Solid State Physics, University of Tokyo. The details of the computer are HPE SGI 8600, Intel Xeon 6148 20 core 2.4 GHz x2 CPU, and 4X EDR InfiniBand x1 as Network. The F4cpu queue was used as the job class.

A SiO ₂ / 4H-SiC (0001) interface structure model was prepared by the following procedure.
For the thickness of the slab model, 8 bilayers were laminated with the SiC atomic layer in the c-axis vertical plane (FIG. 5 (a)) as a unit (called 1 bilayer). For the in-plane direction, we assumed a periodicity of √3x√3. The slab thickness corresponds to 21 Å. In addition, periodic boundary conditions were imposed on the calculated cells. In order to reduce the artificial interaction between the c-axis slab and the adjacent slab, the distance between the c-axis slabs was set to 20 Å to ensure a sufficient distance between the slabs. In the 4H-SiC slab model prepared in this way, the dangling bond on the 4H-SiC (000-1) plane was terminated with a hydrogen atom. On the other hand, α-quartz with a thickness of 10 Å was placed on the 4H-SiC (0001) surface, and structural optimization was applied to construct a SiO ₂ / 4H-SiC (0001) interface structure. In addition, three interface structures were prepared so that the laminated structure of the 4H-SiC (0001) interface would be as shown in FIG. The parameters used in the calculation are as follows. The cutoff energy value was 400 eV, and the sample k points were 5x5x1. Also, in the structural optimization, the force convergence was set to 10 ^-1 eVÅ ^-1 .

As a result, all three types of interfacial laminated structures are energetically unchanged, and even the energy difference between the most stable interfacial laminated structure (a) and the most unstable interfacial laminated structure (c) among the three. It was as small as 5.79 meV / Å ² . Therefore, from a theoretical point of view, it was shown that the interfacial laminated structures (a), (b), and (c) coexist at the actual interface.

In addition, in order to calculate the band alignment as shown in Fig. 7, the local density of states (LDOS) defined below was calculated and plotted, and the calculation result in Fig. 8 was obtained.

As described above, the first-principles calculation based on the density functional theory was performed, and the HSE06 functional was used as the exchange correlation energy functional. As a result, all three types of interfacial laminated structures have almost no change in energy, and even the energy difference between the most stable interfacial laminated structure (a) and the most unstable interfacial laminated structure (c) is 5.79 meV. It was as small as / Å ² . Therefore, from a theoretical point of view, it was shown that the interface laminated structures (a), (b), and (c) coexist at the actual interface. Local density of states (LDOS) was also calculated to evaluate band alignment at the interface. See FIG.

Thus, even if there are no general defect structures or impurities at the interface, the interface state is sensitive to fluctuations in the laminated structure (atomic level defects) at the interface of silicon carbide, and the electrons at the lower end of the conduction band (CBM). It was revealed that the interface state can change in the range from CBM-0.3 eV to CBM + 1.2 eV. Therefore, if the laminated structure fluctuates in the A layer or B layer at the single atomic level at the interface, potential fluctuation occurs in the electronic state at the lower end of the conduction band (CBM), which has a significant effect on the characteristics of the semiconductor device (device). Conceivable. That is, at such an interface, the wave function of CBM is localized, reflecting the fluctuation of the SiC laminated structure at the interface (there are both k-site and h-site), and the electron (hole) is effective. It is thought that the mass will be greatly affected.

Here, FIGS. 6 to 8 show the interface state related to the uniformity at the monoatomic layer level of the interface, and the general defect structure (several tens of atomic levels or more) at the interface in the conventional general knowledge. It is a story at a level that is essentially different from the interface state based on impurities. That is, FIGS. 6 and 7 are at the monoatomic layer level of the interface, which is originally considered to be flat at the atomic level, even if there is no general defect structure or impurities at the interface conventionally considered. It shows that the difference in the laminated structure (fluctuation of the laminated structure at the interface) affects the interface level.

Based on the above findings, the effect of defects in the monoatomic layer level laminated structure at the interface of SiO ₂ / 4H-SiC (structure in which both layers A and B are present) on the mobility of the 4H-SiC layer is discussed. Since the mobility is known to be inversely proportional to the effective mass, the effective mass of electrons (holes) was calculated by the first-principles calculation based on the wave function. The outline of the calculation of this effective mass is as follows.

Based on the above findings, the effect of defects in the monoatomic layer-level laminated structure at the SiO ₂ / 4H-SiC interface (structure in which both layers A and B appear at the interface) on the mobility of the 4H-SiC layer. Since the mobility is known to be half proportional to the effective mass, the effective mass of electrons (holes) was calculated by the first-principles calculation based on the wave function. The outline of the calculation of this effective mass is as follows.

First-principles calculations based on density functional theory were performed. VASP was used as the calculation code. The PAW method was used, and the HSE06 functional was used as the exchange correlation functional. In addition, in this calculation, 0.2 [Å ^-1 ] was used as μ as the parameter μ that divides the short-range and long-range interactions between electrons in the HSE06 functional. Coulomb interaction 1 / r using error function erf and complementary error function erfc
It is divided into. It was confirmed that the bandgap of 3.2 eV of 4H-SiC can be quantitatively reproduced by using this HSE06.

The computer used was Supercomputer System C, Institute for Solid State Physics, University of Tokyo. The details of the computer are HPE SGI 8600, Intel Xeon 6148 20 core 2.4 GHz x2 CPU, and 4X EDR InfiniBand x1 as Network. The F4cpu queue was used as the job class.

A SiO ₂ / 4H-SiC (0001) interface structure model with interface structure fluctuation was created by the following procedure.
For the thickness of the slab model, 6 bilayers were laminated in the c-axis direction. The slab thickness corresponds to 16 Å. As for the in-plane direction, a 6x1 periodicity was assumed, and an interface structure having interfacial fluctuation in the one-dimensional direction was considered. In addition, periodic boundary conditions were imposed on the calculated cells. In order to reduce the artificial interaction between the c-axis slab and the adjacent slab, the distance between the c-axis slabs was set to 20 Å to ensure a sufficient distance between the slabs. In the 4H-SiC slab model prepared in this way, the dangling bond on the 4H-SiC (0001) plane was terminated with a hydrogen atom. Next, the interface laminated structure fluctuation was introduced on the 4H-SiC (000-1) plane. An interface structure in which cubic and hexagonal layers are mixed at a ratio of 1: 1 and an interface structure in which cubic and hexagonal layers are mixed at a ratio of 7: 3, and (for comparison) 100% of cubic layers are covered. Three types of interface structures were prepared. In addition, after introducing the fluctuation of the interfacial laminated structure, the dangling bond at the SiC (000-1) interface was terminated with hydrogen to optimize the structure. The parameters used in the calculation are as follows. The cutoff energy value was 400 eV, and the sample k points were 1x6x1. Also, in the structural optimization, the force convergence was set to 10 ^-1 eVÅ ^-1 .

The electron band is developed around the vicinity of the minimum point pole as follows.
In this formula, the atomic unit system was used. Here, m * is what is called the effective mass of electrons (or holes). The wave number k is plotted on the x-axis and the energy level of the electron band is plotted on the y-axis, and the quadratic coefficient of k around the maximum and minimum points of the electron holes is obtained from the electron band structure by fitting. Can be calculated by In this calculation, the quadratic coefficient was extracted by fitting the in-plane electron band structure obtained by the above slab calculation with a sixth-order function, and the effective mass of electrons and holes was calculated from it.

In the above, a SiO ₂ / 4H-SiC interface structure model in which various interfacial laminated structures coexist is created, and as one simplification, a slab with a thickness of 4H-SiC of 10 Å is prepared, and the contact surface with SiO ₂ is prepared. A mimicked hydrogen-terminated model was created. In addition, a model was prepared so that various interfacial laminated structures coexist in the interfacial structure, and the structure was optimized. Then, the electron band structure in the in-plane direction was calculated, and the effective electron (hole) mass was calculated from the curvature.

As a result, the effective mass of the bulk of SiC was 0.3m ₀ (m ₀ is the mass of electrons), but the ideal (0001) plane, (000-1) plane or (1-100) plane. The effective mass at the interface of the surfaces is also 0.3 m ₀ , and it was found that if the interface is controlled at the atomic level, these surfaces are also about the same as the effective mass of the bulk. That is, if the interface can be controlled at the atomic level on these crystal planes, there is a possibility that effective mass and mobility equivalent to those of bulk can be realized.

On the other hand, assuming that there are atomic level defects on the ideal surface of the (000-1) plane, that is, fluctuations in the laminated structure (both k-site and h-site at the interface), the effective mass is 1.8 m ₀ . .. The same applies to the (0001) plane or the (10-10) plane. If the SiC interface was not controlled at the atomic level, the effective mass at the interface was six times that of the bulk. That is, it was confirmed that the effective mass and mobility can be remarkably improved by controlling the interface at the atomic level.

The improvement in mobility estimated from the above calculation results is 6 times, and even a simple comparison is 120 to 180 cm based on the conventional general mobility of the SiO ₂ / SiC interface of 20 to 30 cm ² / Vs. ² / Vs is obtained. Further, since the mobility of the SiO ₂ / SiC interface is known to be 30 to 50 cm2 / Vs or more, it is expected that the mobility can be further improved by applying the present invention to it.

Furthermore, it is considered that even the atomic level flatness of the interface defects (defects at the layered one layer level) assumed in the above calculation is not realized at the conventional general SiO ₂ / SiC interface, and thus the disclosure of the present invention. Therefore, it is easily possible to improve the atomic level flatness corresponding to the difference between the conventional general SiO ₂ / SiC interface and the atomic level flatness assumed in the above calculation, and thus the mobility. It is clear that the improvement of can be further increased.

Further, in the conventional general SiO ₂ / SiC interface, the interface that lowers the conventional interface state such as general interface defects (including polymorphism) other than the atomic level defects of the SiC interface and the presence of carbon foreign matter. It is known that there are defects. Most of the conventional interface defects are caused by the film formation of SiO ₂ , and by using a crystal insulating film, it is possible to eliminate these conventional causes of lowering the interface state, and as a result, the mobility It is thought that the degree of improvement can be further increased.

Since the mobility of the silicon semiconductor is realized up to 50% of the theoretical value, theoretically, it is expected that the mobility close to that is improved by the disclosure of the present invention.

For comparison, when the prior art is reviewed in accordance with the disclosure of the present invention, the 4H-SiC having the (0-33-8) plane as the interface as taught in Non-Patent Document 1 is always terraced (laminated). Since structural fluctuations occur, even assuming that the terrace is an ideal interface (flat, defect-free at the atomic level), the effective mass is calculated to be 1.7 m ₀ (mobility 180 cm ² /). Corresponds to Vs). That is, the (0-33-8) plane is a crystal plane in which the A layer and the B layer appear in a mixed manner even if the SiC crystal is controlled at the atomic level to cut out an ideal interface, and the plane is laminated at the interface. Since there is always a fluctuation in the structure, according to the disclosure of the present invention, it increases the effective mass. Therefore, in the (0-33-8) plane SiC taught in Patent Document 1, the effective mass is 1.7 m ₀ at the maximum even if the flatness of the interface is controlled at the atomic level, and the bulk Since it is about 5.7 times the effective mass, it is clear that there is a limit to the improvement of mobility. Further, Non-Patent Document 1 does not teach about a process of flattening the surface of a SiC base material at the atomic level before forming an insulating film. The mobility reported by Non-Patent Document 1 is 120 cm ² / Vs.

Further, Non-Patent Document 2 reports that the mobility was improved to 102 cm ² / Vs by treating the terrace of a 4H-SiC crystal having a 4 degree off angle with a Si melt. Non-Patent Document 2 teaches that the mobility is improved by performing a process of flattening a SiC macro terrace (the number of layers of stepped portions is 5 or more, actually more than 5). However, in Non-Patent Document 2, it is a macro terrace, and since the number of laminated steps is as large as 5 or more, not only the interface state is large, but also the off angle is 4 degrees, and above all, on the SiC substrate. Since SiO ₂ is deposited, as a result, the SiC substrate has a macro step, and fluctuations are introduced into the laminated structure of the interface including the terrace on the surface of the SiC crystal, and the SiC / SiO ₂ interface. Atomic level control is not sufficient. In Non-Patent Document 2, it is considered that in MOSFET, the terrace width in the definition of the present invention is actually smaller than the ideal width, and the laminated structure fluctuates at the atomic level.

In Non-Patent Document 5, AlN is used as the insulating film, but the atomic level flatness of the surface of the SiC base material before forming the AlN film is not considered, and the off angle of the SiC base material is 4 degrees. Therefore, no treatment for flattening the surface of the SiC base material at the atomic level is performed before film formation. As a result, the surface of the SiC crystal used and the obtained AlN / SiC interface have fluctuations in the lamination at the atomic level, the terrace width is smaller than 3.5 nm, and the effective mass of the charge is reduced and the mobility is improved. It is considered that there is a limit. In fact, in Non-Patent Document 5, the reported mobility is about 150 cm ² / Vs.

An example of manufacturing a silicon carbide semiconductor device will be described below.
As the silicon carbide substrate, a mirror-polished 4H-SiC single crystal is used, and a surface polished by tilting once in the <11-20> direction from the (0001) surface is used.

After cleaning the silicon carbide substrate by cleaning with an organic solvent and an acid, the substrate is placed on a susceptor with the Si side on which the thin film grows epitaxially faces up. The susceptor on which the substrate is placed is inserted into a quartz reaction tube and evacuated to a vacuum of 1 Pa or less. Next, in order to perform gas phase etching of the substrate, it is heated to 1400 ° C. while flowing a mixed gas in which hydrogen (H ₂ ) and hydrochloric acid gas (HCl) are mixed. Heating is by induction heating the susceptor at high frequency (200 kHz). Subsequently, a mixture of H ₂ , monosilane (SiH ₄ ), and propane (C ₃ H ₈ ) at a predetermined flow rate ratio was introduced into the reaction tube, and when heated at 1550 ° C. for 2 hours, 4H type silicon carbide was placed on the substrate. The layer grows epitaxially. The silicon carbide epitaxial layer is n-type.

The surface of the silicon carbide epitaxial layer is polished at an angle of 4 degrees off and 1 degree off in the <11-20> direction from the (0001) Si surface, and SiC having a silicon carbide layer having a 4 degree off surface and a 1 degree off surface. Create a substrate.

Catalyst-Referred Etching (CARE method); with reference to APL 110,201601 (2017), in an etching tank containing hydrofluoric acid or pure water, a platinum electrode layer (working electrode) on the substrate surface, an Ag / AgCl electrode, and Using a Pt plate (counter electrode), under platinum catalyst assist, the above SiC base material held in the holder is rotated and pressed against the platinum electrode layer (working electrode) for chemical etching to raise the surface of the epitaxial layer at the atomic level. A flat crystal surface is obtained at the atomic level, which has a terrace structure having only one step of the laminated layer. The terrace widths of the 4 degree off surface are 3.5 nm and about 3.7 nm, and the terrace widths of the 1 degree off surface are 14.8 nm and about 15.2 nm.

Next, an aluminum nitride film is formed on the silicon carbide epitaxial layer which has been flattened and whose terrace width has been confirmed by a chemical vapor phase deposition method. By forming an aluminum nitride film, it is possible to obtain a terrace width of silicon carbide at the silicon carbide / aluminum nitride interface of 3.5 nm or more on the 4 degree off surface and 14.8 nm or more on the 1 degree off surface. Be made.

Obtain a commercially available silicon carbide substrate with an on-angle (off-angle of 0 degrees), flatten the surface of the on-angle as described above, and flatten the on-angle at the atomic level (terrace width is infinite or By forming a silicon carbide substrate of (substrate dimensions) and then forming a film of aluminum nitride on the surface as described above, a flat silicon carbide / silicon nitride interface can be obtained at the atomic level.

After that, a semiconductor device as shown in FIG. 1 is manufactured by a known method. A titanium alloy is deposited on the aluminum nitride film, and a gate electrode is formed by patterning with a mask. After depositing an interlayer insulating film on the entire surface of the substrate including the gate electrode, the interlayer insulating film is patterned to open the source and drain regions, and the opened silicon carbide epitaxial region is selectively doped with aluminum as a p-type impurity. Form the source and drain regions. After that, the source and drain electrodes are formed.

1 Silicon Carbide Semiconductor Substrate 2 Silicon Carbide Semiconductor Layer 3 Source Area 4 Drain Area 5 Gate Insulating Film 6 Gate Electrode 21 SiC Crystal 22 SiC Crystal Surface 23 Terrace 24 Steps 25-1 to 25-7 Terrace θ Off Angle Wt Terrace Width

Claims (15)

A silicon carbide semiconductor device including a silicon carbide crystal region and a gate insulating film formed on the surface of the silicon carbide crystal region, wherein at least a surface of the gate insulating film in contact with the silicon carbide crystal region is a crystal insulator. A silicon carbide semiconductor device comprising the above, wherein the flat terrace width at the atomic level of the interface of the silicon carbide crystal in contact with the crystal insulator is 3.5 nm or more. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide crystal region is a silicon carbide crystal having an off angle in the range of 0 to 4 degrees. The silicon carbide semiconductor device according to claim 1 or 2, wherein the off angle is 0 to 1 degree. The silicon carbide semiconductor device according to claim 2 or 3, wherein the flatness at the atomic level is 40 nm or more. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the difference in lattice constant between the crystal insulator and the silicon carbide crystal is 2% or less. The crystal insulators are aluminum nitride (AlN), gallium nitride (GaN), aluminum phosphate (AlPO ₄ ), alumina, Be ₃ Al ₂ (SiO ₃ ) ₆ , verium oxide (BeO), RbAl ₁₁ O ₁₇ , Ba. _{7 The} silicon carbide semiconductor apparatus according to any one of claims 1 to 5, which is selected from Al ₆₄ O ₁₀₃ , Al ₆ B ₅ (O ₅ F) _3, and a substance obtained by terminating these with hydrogen. The claim that the silicon carbide crystal is 4H-SiC, and the planes in contact with the crystal insulator are the (000-1) plane, the (0001) plane, the (1-100) plane, or the (11-20) plane. The silicon carbide semiconductor device according to any one of 1 to 6. The silicon carbide according to any one of claims 1 to 7, wherein the gate insulating film contains a second insulator different from the crystal insulator on the side opposite to the silicon carbide crystal region of the crystal insulator. Semiconductor device. A method for manufacturing a silicon carbide semiconductor device including a silicon carbide crystal region and a gate insulating film formed on the surface of the silicon carbide crystal region, wherein a surface having a flat terrace width of 3.5 nm or more at the atomic level is formed. A method for manufacturing a silicon carbide semiconductor device, which comprises providing a silicon carbide crystal region having a silicon carbide crystal region and forming a crystal insulating film on the silicon carbide crystal region. The production method according to claim 9, wherein the silicon carbide crystal region is composed of silicon carbide crystals having an off angle in the range of 0 to 4 degrees. The crystal insulating film is aluminum nitride (AlN), gallium nitride (GaN), aluminum phosphate (AlPO ₄ ), alumina, Be ₃ Al ₂ (SiO ₃ ) ₆ , verium oxide (BeO), RbAl ₁₁ O ₁₇ , Ba. ₇ The production method according to claim 9 or 10, which is a material selected from Al ₆₄ O ₁₀₃ , Al ₆ B ₅ (O ₅ F) _3, and a substance obtained by hydrogen-terminating these. The manufacturing method according to any one of claims 9 to 11, wherein the off angle is 0 to 1 degree. The silicon carbide crystal region is 4H-SiC, and the surfaces of the 4H-SiC crystal in contact with the crystal insulating film are (000-1) plane, (0001) plane, (0-110) plane, or (11-20) plane. ) Plane, and the (000-1) plane, (0001) plane, (0-110) plane, or (11-20) plane of the silicon carbide crystal region is at the atomic level before the crystal insulating film is formed. The production method according to any one of claims 9 to 12, which comprises a process of flattening with. 9. A claim 9 in which a treatment for flattening the surface of the silicon carbide crystal region at the atomic level is performed before the formation of the crystal insulating film to make the terrace width of the silicon carbide crystal region 3.5 nm or more. The production method according to any one of 13 to 13. The production method according to any one of claims 9 to 14, wherein the crystal insulating film is formed by a chemical vapor phase deposition method or a physical deposition method.