JP2021022597A - Capacitor forming system and capacitor forming method - Google Patents
Capacitor forming system and capacitor forming method Download PDFInfo
- Publication number
- JP2021022597A JP2021022597A JP2019136392A JP2019136392A JP2021022597A JP 2021022597 A JP2021022597 A JP 2021022597A JP 2019136392 A JP2019136392 A JP 2019136392A JP 2019136392 A JP2019136392 A JP 2019136392A JP 2021022597 A JP2021022597 A JP 2021022597A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- lower electrode
- dielectric film
- laser
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 60
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 16
- 238000002407 reforming Methods 0.000 claims description 15
- 230000001678 irradiating effect Effects 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 230000007246 mechanism Effects 0.000 description 12
- 230000032258 transport Effects 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 5
- 229910052736 halogen Inorganic materials 0.000 description 5
- 150000002367 halogens Chemical class 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000001878 scanning electron micrograph Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- ZLOKVAIRQVQRGC-UHFFFAOYSA-N CN(C)[Ti] Chemical compound CN(C)[Ti] ZLOKVAIRQVQRGC-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- NFHFRUOZVGFOOS-UHFFFAOYSA-N palladium;triphenylphosphane Chemical compound [Pd].C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1 NFHFRUOZVGFOOS-UHFFFAOYSA-N 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/56—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
Abstract
Description
本開示は、キャパシタ形成システム及びキャパシタ形成方法に関する。 The present disclosure relates to a capacitor forming system and a capacitor forming method.
例えば、チャンバ内を真空雰囲気に制御し、チャンバ内に処理ガスを供給して、チャンバ内の基板に所望の処理を施す基板処理装置が知られている。 For example, there is known a substrate processing apparatus that controls the inside of a chamber to a vacuum atmosphere, supplies a processing gas into the chamber, and performs a desired treatment on the substrate in the chamber.
特許文献１には、容量部電極形成用の多結晶シリコン膜の表面をエッチングして表面積を拡大する半導体装置の製造方法が開示されている。 Patent Document 1 discloses a method for manufacturing a semiconductor device that increases the surface area by etching the surface of a polycrystalline silicon film for forming a capacitive electrode.
一の側面では、本開示は、表面積を増大するキャパシタ形成システム及びキャパシタ形成方法を提供する。 In one aspect, the present disclosure provides a capacitor forming system and a method of forming a capacitor that increase the surface area.
上記課題を解決するために、一の態様によれば、基板に下部電極を形成する下部電極形成装置と、前記基板に誘電膜を成膜する誘電膜成膜装置と、前記基板に上部電極を形成する上部電極形成装置と、前記下部電極及び前記誘電膜の少なくともいずれかにレーザを照射する改質装置と、を備え、前記下部電極、前記誘電膜、前記上部電極を有するキャパシタを形成する、キャパシタ形成システムが提供される。 In order to solve the above problems, according to one embodiment, a lower electrode forming apparatus for forming a lower electrode on a substrate, a dielectric film forming apparatus for forming a dielectric film on the substrate, and an upper electrode on the substrate are provided. An upper electrode forming device to be formed and a reforming device for irradiating at least one of the lower electrode and the dielectric film with a laser are provided to form a capacitor having the lower electrode, the dielectric film, and the upper electrode. A capacitor forming system is provided.
一の側面によれば、表面積を増大するキャパシタ形成システム及びキャパシタ形成方法を提供することができる。 According to one aspect, it is possible to provide a capacitor forming system and a capacitor forming method that increase the surface area.
以下、図面を参照して本開示を実施するための形態について説明する。各図面において、同一構成部分には同一符号を付し、重複した説明を省略する場合がある。 Hereinafter, embodiments for carrying out the present disclosure will be described with reference to the drawings. In each drawing, the same components may be designated by the same reference numerals and duplicate description may be omitted.
＜キャパシタ形成システム＞
本実施形態に係るキャパシタ形成システム１００について、図１を用いて説明する。図１は、本実施形態に係るキャパシタ形成システム１００の構成の一例を示す模式図である。
<Capacitor formation system>
The capacitor forming system 100 according to the present embodiment will be described with reference to FIG. FIG. 1 is a schematic view showing an example of the configuration of the capacitor forming system 100 according to the present embodiment.
キャパシタ形成システム１００は、下部電極形成装置１０１と、改質装置１０２と、誘電膜成膜装置１０３と、上部電極形成装置１０４と、搬送装置１０５〜１０７と、制御装置１０８と、を備えている。 The capacitor forming system 100 includes a lower electrode forming device 101, a reforming device 102, a dielectric film forming device 103, an upper electrode forming device 104, a transfer device 105 to 107, and a control device 108. ..
下部電極形成装置１０１は、基板Ｗにキャパシタの下部電極を形成する装置である。以下の説明おいて、下部電極形成装置１０１は、下部電極として基板Ｗ上にＴｉＮ膜を成膜する場合を例に説明する。なお、下部電極形成装置１０１は、ピラー形状、シリンダ形状の下部電極を形成する装置であってもよい。また、下部電極の材料もＴｉＮに限られない。例えば、ＴｉＮ、Ｍｏ、ＭｏＮ、Ｎｂ、ＮｂＯ、Ｒｕ、ＲｕＯ等のうちの何れか１つを含む電極材料であってもよい。 The lower electrode forming device 101 is a device for forming a lower electrode of a capacitor on a substrate W. In the following description, the case where the lower electrode forming apparatus 101 forms a TiN film on the substrate W as the lower electrode will be described as an example. The lower electrode forming device 101 may be a device for forming a pillar-shaped or cylinder-shaped lower electrode. Further, the material of the lower electrode is not limited to TiN. For example, the electrode material may contain any one of TiN, Mo, MoN, Nb, NbO, Ru, RuO and the like.
改質装置１０２は、下部電極の表面にレーザを照射して、下部電極の表面を改質する装置である。これにより、下部電極の表面が多孔質化する。なお、改質装置１０２については、図２を用いて後述する。 The reforming device 102 is a device that irradiates the surface of the lower electrode with a laser to reform the surface of the lower electrode. As a result, the surface of the lower electrode becomes porous. The reformer 102 will be described later with reference to FIG.
誘電膜成膜装置１０３は、下部電極の表面に絶縁体（誘電体）からなる誘電膜を成膜する装置である。なお、誘電膜は、例えば、ＡｌＯ、ＨｆＯ２、ＺｒＯ２、等を用いることができる。 The dielectric film forming apparatus 103 is an apparatus for forming a dielectric film made of an insulator (dielectric) on the surface of the lower electrode. As the dielectric film, for example, AlO, HfO 2 , ZrO 2 , or the like can be used.
上部電極形成装置１０４は、誘電膜の表面に上部電極を形成する装置である。例えば、上部電極として、誘電膜の表面にＴｉＮ膜を成膜する。また、上部電極の材料もＴｉＮに限られない。例えば、ＴｉＮ、Ｍｏ、ＭｏＮ、Ｎｂ、ＮｂＯ、Ｒｕ、ＲｕＯ等のうちの何れか１つを含む電極材料であってもよい。また、上部電極の材料は、下部電極の材料と同じ材料であってもよく、異なっていてもよい。なお、下部電極形成装置１０１、誘電膜成膜装置１０３、上部電極形成装置１０４は、例えば、ＡＬＤ（Atomic Layer Deposition）装置、ＣＶＤ（Chemical Vapor Deposition）装置により実現される。 The upper electrode forming device 104 is a device for forming an upper electrode on the surface of the dielectric film. For example, as an upper electrode, a TiN film is formed on the surface of the dielectric film. Further, the material of the upper electrode is not limited to TiN. For example, the electrode material may contain any one of TiN, Mo, MoN, Nb, NbO, Ru, RuO and the like. Further, the material of the upper electrode may be the same as the material of the lower electrode, or may be different. The lower electrode forming apparatus 101, the dielectric film forming apparatus 103, and the upper electrode forming apparatus 104 are realized by, for example, an ALD (Atomic Layer Deposition) apparatus and a CVD (Chemical Vapor Deposition) apparatus.
搬送装置１０５は、下部電極形成装置１０１と改質装置１０２との間で基板Ｗまたは基板Ｗを収容したキャリアを搬送する。搬送装置１０６は、改質装置１０２と誘電膜成膜装置１０３との間で基板Ｗまたは基板Ｗを収容したキャリアを搬送する。搬送装置１０７は、誘電膜成膜装置１０３と上部電極形成装置１０４との間で基板Ｗまたは基板Ｗを収容したキャリアを搬送する。 The transport device 105 transports the substrate W or the carrier accommodating the substrate W between the lower electrode forming device 101 and the reforming device 102. The transport device 106 transports the substrate W or the carrier accommodating the substrate W between the reformer 102 and the dielectric film film forming apparatus 103. The transport device 107 transports the substrate W or the carrier accommodating the substrate W between the dielectric film film forming apparatus 103 and the upper electrode forming apparatus 104.
制御装置１０８は、これら各構成装置を制御することにより、キャパシタ形成システム１００による処理全体を制御する。制御装置１０８は、ＣＰＵ（Central Processing Unit）、ＲＯＭ（Read Only Memory）及びＲＡＭ（Random Access Memory）を有している。ＣＰＵは、ＲＡＭ等の記憶領域に格納されたレシピに従って、所望の処理を実行する。レシピにはプロセス条件に対する装置の制御情報であるプロセス時間、各種ガス流量、圧力（ガスの排気）などが設定されている。 The control device 108 controls the entire processing by the capacitor forming system 100 by controlling each of these constituent devices. The control device 108 has a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). The CPU executes a desired process according to a recipe stored in a storage area such as RAM. In the recipe, process time, various gas flow rates, pressure (gas exhaust), etc., which are control information of the device for process conditions, are set.
＜改質装置１０２＞
次に、改質装置１０２について、図２を用いて更に説明する。図２は、改質装置１０２の構成図である。基板Ｗを載置するステージ１１と、レーザ照射装置１２と、走査機構１３と、を備える。
<Reformer 102>
Next, the reformer 102 will be further described with reference to FIG. FIG. 2 is a block diagram of the reformer 102. A stage 11 on which the substrate W is placed, a laser irradiation device 12, and a scanning mechanism 13 are provided.
改質装置１０２は、基板Ｗを載置するステージ１１を備える。 The reformer 102 includes a stage 11 on which the substrate W is placed.
改質装置１０２は、ステージ１１に載置された基板Ｗにパルスレーザを照射するレーザ照射装置１２を備える。ここで、照射するレーザは、ＫｒＦエキシマレーザ（波長：２４８ｎｍ）を用いることができる。レーザ装置の各パラメータは、以下の通りである。
エキシマレーザ（ＫｒＦ）２４８ｎｍ，光学パルスストレッチャ（ＯＰＳ；Optical Pulse Stretcher）７ｍ，照射フルエンス２００ｍＪ／ｃｍ２，２０ｓｈｏｔ／ｌｏｃａｔｉｏｎ
The reformer 102 includes a laser irradiation device 12 that irradiates the substrate W mounted on the stage 11 with a pulse laser. Here, as the laser to irradiate, a KrF excimer laser (wavelength: 248 nm) can be used. Each parameter of the laser device is as follows.
Excimer laser (KrF) 248 nm, optical pulse stretcher (OPS) 7 m, irradiation fluence 200 m J / cm 2 , 20 shot / location
改質装置１０２は、レーザを基板Ｗ上で走査させるための走査機構１３を備える。例えば、走査機構１３は、ステージ１１に載置された基板Ｗを水平方向に移動可能なＸＹテーブルとして構成されていてもよい。この構成では、レーザ照射装置１２を固定し、ＸＹテーブルで基板Ｗを移動させることにより、レーザを基板Ｗ上で走査させる。また、走査機構１３は、レーザ照射装置１２を水平方向に移動可能な移動機構として構成されていてもよい。この構成では、ステージ１１を固定し、移動機構でレーザ照射装置１２を移動させることにより、レーザを基板Ｗ上で走査させる。また、走査機構１３は、角度制御可能なミラーとして構成されていてもよい。この構成では、レーザ照射装置１２から照射されたレーザはミラーで反射されステージ１１に載置された基板Ｗに照射される。この際、ミラーの角度を制御することにより、レーザを基板Ｗ上で走査させる。 The reformer 102 includes a scanning mechanism 13 for scanning the laser on the substrate W. For example, the scanning mechanism 13 may be configured as an XY table in which the substrate W mounted on the stage 11 can be moved in the horizontal direction. In this configuration, the laser irradiation device 12 is fixed and the substrate W is moved on the XY table to scan the laser on the substrate W. Further, the scanning mechanism 13 may be configured as a moving mechanism capable of moving the laser irradiation device 12 in the horizontal direction. In this configuration, the stage 11 is fixed and the laser irradiation device 12 is moved by the moving mechanism to scan the laser on the substrate W. Further, the scanning mechanism 13 may be configured as a mirror whose angle can be controlled. In this configuration, the laser emitted from the laser irradiation device 12 is reflected by the mirror and is irradiated to the substrate W mounted on the stage 11. At this time, the laser is scanned on the substrate W by controlling the angle of the mirror.
このような構成により、改質装置１０２は、基板Ｗ上の所望の位置にレーザを照射することができる。 With such a configuration, the reformer 102 can irradiate the laser at a desired position on the substrate W.
なお、改質装置１０２は、大気雰囲気で基板Ｗにレーザを照射してもよい。また、ステージ１１を収容するチャンバを備えていてもよい。また、改質装置１０２は、チャンバ内からガスを排気する排気装置を備えていてもよい。これにより、基板Ｗの照射雰囲気を真空雰囲気としてもよい。また、改質装置１０２は、チャンバ内にガスを供給するガス供給装置を備えていてもよい。これにより、基板Ｗの照射雰囲気を所望のガス雰囲気としてもよい。なお、レーザ照射装置１２は、チャンバ内に配置されていてもよい。また、レーザ照射装置１２は、チャンバ外に配置され、チャンバに設けられた窓を介してチャンバ内の基板Ｗにレーザを照射してもよい。 The reformer 102 may irradiate the substrate W with a laser in an atmospheric atmosphere. Further, a chamber for accommodating the stage 11 may be provided. Further, the reformer 102 may include an exhaust device for exhausting gas from the chamber. As a result, the irradiation atmosphere of the substrate W may be a vacuum atmosphere. Further, the reformer 102 may include a gas supply device for supplying gas into the chamber. As a result, the irradiation atmosphere of the substrate W may be a desired gas atmosphere. The laser irradiation device 12 may be arranged in the chamber. Further, the laser irradiation device 12 may be arranged outside the chamber and may irradiate the substrate W in the chamber with a laser through a window provided in the chamber.
＜キャパシタ形成システム１００の動作＞
次に、キャパシタ形成システム１００の動作について、図３及び図４を用いて説明する。図３は、キャパシタ形成処理を説明するフローチャートである。図４は、各工程における基板Ｗの断面模式図である。
<Operation of Capacitor Formation System 100>
Next, the operation of the capacitor forming system 100 will be described with reference to FIGS. 3 and 4. FIG. 3 is a flowchart illustrating a capacitor forming process. FIG. 4 is a schematic cross-sectional view of the substrate W in each step.
図４（ａ）に示すように、基板Ｗは、例えば、Ｓｉ、ＳｉＯ２からなる基体２０を有する。基板Ｗは、下部電極形成装置１０１にセットされる。 As shown in FIG. 4A, the substrate W has, for example, a substrate 20 made of Si and SiO 2 . The substrate W is set in the lower electrode forming device 101.
ステップＳ１において、制御装置１０８は、下部電極形成装置１０１を制御して、基板Ｗに下部電極２１を形成する。図４（ｂ）に示すように、基体２０の上に下部電極２１としてＴｉＮ膜を成膜する。 In step S1, the control device 108 controls the lower electrode forming device 101 to form the lower electrode 21 on the substrate W. As shown in FIG. 4B, a TiN film is formed on the substrate 20 as the lower electrode 21.
下部電極形成装置１０１による処理が完了すると、制御装置１０８は、搬送装置１０５を制御して、基板Ｗを下部電極形成装置１０１から改質装置１０２へと搬送し、ステージ１１に載置させる。 When the processing by the lower electrode forming device 101 is completed, the control device 108 controls the transfer device 105 to transfer the substrate W from the lower electrode forming device 101 to the reforming device 102 and place it on the stage 11.
ステップＳ２において、制御装置１０８は、改質装置１０２を制御して、基板Ｗに形成された下部電極２１にレーザを照射する。 In step S2, the control device 108 controls the reforming device 102 to irradiate the lower electrode 21 formed on the substrate W with a laser.
図５は、基板ＷのＳＥＭ（Scanning Electron Microscope）画像の一例を示す。（ａ）はレーザ未照射部分のＳＥＭ画像の一例を示し、（ｂ）はレーザ照射部分のＳＥＭ画像の一例を示す。なお、図５の例において、１０ｎｍのＴｉＮ膜を成膜し、ＫｒＦエキシマレーザを２４８ｎｍ，２００ｍＪ／ｃｍ２，２０ｓｈｏｔ／ｌｏｃａｔｉｏｎで照射した。 FIG. 5 shows an example of an SEM (Scanning Electron Microscope) image of the substrate W. (A) shows an example of an SEM image of a laser-irradiated portion, and (b) shows an example of an SEM image of a laser-irradiated portion. In the example of FIG. 5, a 10 nm TiN film was formed and irradiated with a KrF excimer laser at 248 nm, 200 mJ / cm 2 , 20 shot / location.
図５（ａ）及び図５（ｂ）を対比して示すように、レーザを照射することにより、下部電極２１の上面２１ａが多孔質化する。 As shown in comparison with FIGS. 5A and 5B, the upper surface 21a of the lower electrode 21 is made porous by irradiating the laser.
改質装置１０２による処理が完了すると、制御装置１０８は、搬送装置１０６を制御して、基板Ｗを改質装置１０２から誘電膜成膜装置１０３へと搬送する。 When the processing by the reformer 102 is completed, the control device 108 controls the transport device 106 to transport the substrate W from the reformer 102 to the dielectric film forming apparatus 103.
ステップＳ３において、制御装置１０８は、誘電膜成膜装置１０３を制御して、基板Ｗに誘電膜２２を成膜する。ここで、誘電膜２２の下面２２ａは、多孔質化した下部電極２１の上面２１ａに沿って形成される。このため、下部電極２１に改質装置１０２による処理を施さない場合と比較して、誘電膜２２の下面２２ａの表面積を増加させることができる。 In step S3, the control device 108 controls the dielectric film forming apparatus 103 to form the dielectric film 22 on the substrate W. Here, the lower surface 22a of the dielectric film 22 is formed along the upper surface 21a of the porous lower electrode 21. Therefore, the surface area of the lower surface 22a of the dielectric film 22 can be increased as compared with the case where the lower electrode 21 is not treated by the reformer 102.
誘電膜成膜装置１０３による処理が完了すると、制御装置１０８は、搬送装置１０７を制御して、基板Ｗを誘電膜成膜装置１０３から上部電極形成装置１０４へと搬送する。 When the processing by the dielectric film forming apparatus 103 is completed, the control device 108 controls the conveying device 107 to convey the substrate W from the dielectric film forming apparatus 103 to the upper electrode forming apparatus 104.
ステップＳ４において、制御装置１０８は、上部電極形成装置１０４を制御して、基板Ｗに上部電極２３を形成する。ここでは、図４（ｅ）に示すように、誘電膜２２の上にＴｉＮ膜を成膜する。 In step S4, the control device 108 controls the upper electrode forming device 104 to form the upper electrode 23 on the substrate W. Here, as shown in FIG. 4 (e), a TiN film is formed on the dielectric film 22.
上部電極形成装置１０４による処理が完了すると、制御装置１０８は、搬送装置１０７を制御して、基板Ｗを上部電極形成装置１０４から搬出する。 When the processing by the upper electrode forming device 104 is completed, the control device 108 controls the transport device 107 to carry out the substrate W from the upper electrode forming device 104.
以上、本実施形態に係るキャパシタ形成システム１００によれば、下部電極２１、誘電膜２２、上部電極２３からなるキャパシタを形成することができる。また、誘電膜２２の下面２２ａの表面積が増加することにより、比誘電率を上げることができ、キャパシタの静電容量を増加させることができる。換言すれば、所望の静電容量に対してキャパシタを小型化することができる。 As described above, according to the capacitor forming system 100 according to the present embodiment, it is possible to form a capacitor composed of a lower electrode 21, a dielectric film 22, and an upper electrode 23. Further, by increasing the surface area of the lower surface 22a of the dielectric film 22, the relative permittivity can be increased and the capacitance of the capacitor can be increased. In other words, the capacitor can be miniaturized for the desired capacitance.
図６は、上部電極２３にレーザを照射した際の照射フルエンスとシート抵抗の関係を示すグラフの一例である。ここでは、１０ｎｍのＴｉＮ膜を成膜した。その後、ＴｉＮ膜にＫｒＦエキシマレーザを各照射フルエンスにおいて２０ｓｈｏｔｓ／ｌｏｃａｔｉｏｎ照射した。 FIG. 6 is an example of a graph showing the relationship between the irradiation fluence and the sheet resistance when the upper electrode 23 is irradiated with the laser. Here, a 10 nm TiN film was formed. Then, the TiN film was irradiated with a KrF excimer laser at 20 shots / location at each irradiation fluence.
ここで、ＴｉＮ膜は、例えば、原料ガスとしてＴｉＣｌ４、還元ガスとしてＮＨ３を用い、ＡＬＤ（Atomic Layer Deposition）プロセスにより成膜される。また、ＴｉＮ膜は、例えば、原料ガスとしてテトラキスジメチルアミノチタン（ＴＤＭＡＴ）、還元ガスとしてＮＨ３を用い、ＡＬＤプロセスにより成膜される。このため、ＴｉＮ膜中には不純物としてハロゲンや炭素を含む。 Here, the TiN film is formed by an ALD (Atomic Layer Deposition) process using, for example, TiCl 4 as a raw material gas and NH 3 as a reducing gas. Further, the TiN film is formed by an ALD process using, for example, tetrakis dimethylaminotitanium (TDMAT) as a raw material gas and NH 3 as a reducing gas. Therefore, the TiN film contains halogen and carbon as impurities.
これに対し、本実施形態に係るキャパシタ形成システム１００によれば、ＴｉＮ膜（下部電極２１）にレーザを照射することにより、ＴｉＮ膜中の不純物（ハロゲン、炭素）を除去させることができる。図６に示す例では、２００ｍＪ／ｃｍ２の条件において、シート抵抗が低下することが確認できた。なお、照射フルエンスが小さい（例えば、１００ｍＪ／ｃｍ２未満）場合、ＴｉＮ膜中の不純物（ハロゲン、炭素）を好適に除去することができず、シート抵抗を下げることができない。一方、照射フルエンスが大きい（例えば、３００ｍＪ／ｃｍ２以上）場合、ＴｉＮ膜が荒れるため、シート抵抗を下げることができない。このため、照射フルエンスは１５０ｍＪ／ｃｍ２以上２５０ｍＪ／ｃｍ２以下とすることが好ましい。 On the other hand, according to the capacitor forming system 100 according to the present embodiment, impurities (halogen, carbon) in the TiN film can be removed by irradiating the TiN film (lower electrode 21) with a laser. In the example shown in FIG. 6, it was confirmed that the sheet resistance was reduced under the condition of 200 mJ / cm 2 . When the irradiation fluence is small (for example, less than 100 mJ / cm 2 ), impurities (halogen, carbon) in the TiN film cannot be suitably removed, and the sheet resistance cannot be lowered. On the other hand, when the irradiation fluence is large (for example, 300 mJ / cm 2 or more), the TiN film becomes rough and the sheet resistance cannot be lowered. Therefore, the irradiation fluence is preferably 150 mJ / cm 2 or more and 250 mJ / cm 2 or less.
従来、ＴｉＮ膜中の不純物（ハロゲン、炭素）を除去させる際は、例えば、プラズマ処理やアニール処理が必要となる。しかし、膜の材質や電気特性の観点より、基板Ｗに高温での熱処理を施せない場合やプラズマダメージの観点からプラズマを使用することができない場合がある。これに対し、本実施形態では、レーザ照射により改質することができるので、高温での熱処理を不要とすることができる。また、所望の位置を選択して照射することができる。 Conventionally, when removing impurities (halogen, carbon) in the TiN film, for example, plasma treatment or annealing treatment is required. However, from the viewpoint of the film material and electrical characteristics, the substrate W may not be heat-treated at a high temperature, or plasma may not be used from the viewpoint of plasma damage. On the other hand, in the present embodiment, since it can be modified by laser irradiation, heat treatment at a high temperature can be unnecessary. Moreover, a desired position can be selected and irradiated.
なお、ＴｉＮからなる下部電極２１にレーザを照射する際は、基板Ｗを還元ガス雰囲気としてもよい。例えば、ガス供給装置からチャンバ内にＨ２ガス、ＮＨ３ガスを供給してもよい。これにより、雰囲気中の酸素を低減して、下部電極２１の酸化によるシート抵抗の増加を抑制することができる。また、ＴｉＮ膜中の不純物（ハロゲン、炭素）を好適に除去させることにより、低抵抗な膜とすることができる。 When irradiating the lower electrode 21 made of TiN with a laser, the substrate W may be used as a reducing gas atmosphere. For example, H 2 gas and NH 3 gas may be supplied into the chamber from the gas supply device. As a result, oxygen in the atmosphere can be reduced, and an increase in sheet resistance due to oxidation of the lower electrode 21 can be suppressed. Further, by preferably removing impurities (halogen, carbon) in the TiN film, a low resistance film can be obtained.
また、本実施形態に係るキャパシタ形成システム１００は、誘電膜２２を成膜する前の下部電極２１にレーザを照射するものとして説明したが、これに限られるものではない。例えば、上部電極２３を形成する前の誘電膜２２にレーザを照射してもよい。誘電膜２２の上面が多孔質化して、表面積が増加することにより、静電容量を増加させることができる。換言すれば、所望の静電容量に対してキャパシタを小型化することができる。 Further, the capacitor forming system 100 according to the present embodiment has been described as irradiating the lower electrode 21 before forming the dielectric film 22 with a laser, but the present invention is not limited to this. For example, the dielectric film 22 before forming the upper electrode 23 may be irradiated with a laser. The capacitance can be increased by making the upper surface of the dielectric film 22 porous and increasing the surface area. In other words, the capacitor can be miniaturized for the desired capacitance.
なお、酸化物からなる誘電膜２２にレーザを照射する際は、基板Ｗを酸素雰囲気としてもよい。これにより、高温での熱処理を行うことなく、低温での酸化処理を実現することが可能となる。 When irradiating the dielectric film 22 made of an oxide with a laser, the substrate W may have an oxygen atmosphere. This makes it possible to realize an oxidation treatment at a low temperature without performing a heat treatment at a high temperature.
また、下部電極２１にレーザを照射するとともに、誘電膜２２にレーザを照射してもよい。これにより、誘電膜２２の下面及び上面の表面積を増加させることができ、静電容量を増加させることができる。 Further, the lower electrode 21 may be irradiated with the laser and the dielectric film 22 may be irradiated with the laser. As a result, the surface areas of the lower surface and the upper surface of the dielectric film 22 can be increased, and the capacitance can be increased.
以上、キャパシタ形成システム１００の実施形態等について説明したが、本開示は上記実施形態等に限定されるものではなく、特許請求の範囲に記載された本開示の要旨の範囲内において、種々の変形、改良が可能である。 Although the embodiments of the capacitor forming system 100 have been described above, the present disclosure is not limited to the above embodiments and the like, and various modifications are made within the scope of the gist of the present disclosure described in the claims. , Improvement is possible.
下部電極形成装置１０１と改質装置１０２とは、別個に設ける場合を例に説明したが、下部電極形成装置１０１に改質装置１０２のレーザ照射装置１２及び走査機構１３を搭載して、下部電極形成（図３ステップＳ１）及び下部電極の表面改質（図３ステップＳ２）を同一チャンバプロセスで行ってもよい。また、改質装置１０２と誘電膜成膜装置１０３は、別個に設ける場合を例に説明したが、誘電膜成膜装置１０３に改質装置１０２のレーザ照射装置１２及び走査機構１３を搭載して、下部電極の表面改質（図３ステップＳ２）及び誘電膜成膜（図３ステップＳ３）を同一チャンバプロセスで行ってもよい。 Although the case where the lower electrode forming device 101 and the reforming device 102 are provided separately has been described as an example, the lower electrode forming device 101 is equipped with the laser irradiation device 12 and the scanning mechanism 13 of the reforming device 102 to form the lower electrode. The formation (step S1 of FIG. 3) and the surface modification of the lower electrode (step S2 of FIG. 3) may be performed in the same chamber process. Further, although the case where the reforming device 102 and the dielectric film forming apparatus 103 are provided separately has been described as an example, the reforming apparatus 102 is equipped with the laser irradiation device 12 and the scanning mechanism 13 of the reforming apparatus 102. , The surface modification of the lower electrode (step S2 in FIG. 3) and the film formation of the dielectric film (step S3 in FIG. 3) may be performed in the same chamber process.
また、誘電膜２２にレーザを照射する構成においても、誘電膜成膜装置１０３と改質装置１０２を別個に設ける構成としてもよく、同一チャンバの構成としてもよい。即ち、誘電膜成膜装置１０３に改質装置１０２のレーザ照射装置１２及び走査機構１３を搭載して、誘電膜成膜及び誘電膜の表面改質を同一チャンバプロセスで行ってもよい。また、上部電極形成装置１０４に改質装置１０２のレーザ照射装置１２及び走査機構１３を搭載して、誘電膜の表面改質及び上部電極形成を同一チャンバプロセスで行ってもよい。 Further, in the configuration in which the dielectric film 22 is irradiated with the laser, the dielectric film film forming apparatus 103 and the reforming apparatus 102 may be provided separately, or the same chamber may be configured. That is, the dielectric film film forming device 103 may be equipped with the laser irradiation device 12 and the scanning mechanism 13 of the reforming device 102, and the dielectric film film forming and the surface modification of the dielectric film may be performed in the same chamber process. Further, the laser irradiation device 12 and the scanning mechanism 13 of the reforming device 102 may be mounted on the upper electrode forming device 104 to modify the surface of the dielectric film and form the upper electrode in the same chamber process.
また、キャパシタ形成システム１００は、真空搬送室を介して基板Ｗを搬送するInsituシステムとしてもよい。即ち、下部電極を形成する工程から上部電極を形成する工程までを真空を破らずに行う。また、キャパシタ形成システム１００は、大気搬送室を介して基板Ｗを搬送するExsituシステムとしてもよい。 Further, the capacitor forming system 100 may be an in situ system in which the substrate W is conveyed via the vacuum transfer chamber. That is, the steps from the step of forming the lower electrode to the step of forming the upper electrode are performed without breaking the vacuum. Further, the capacitor forming system 100 may be an Exsitu system that transports the substrate W via the atmospheric transport chamber.
１１ ステージ
１２ レーザ照射装置
１３ 走査機構
２０ 基体
２１ 下部電極
２１ａ 上面
２２ 誘電膜
２２ａ 下面
２３ 上部電極
１００ キャパシタ形成システム
１０１ 下部電極形成装置
１０２ 改質装置
１０３ 誘電膜成膜装置
１０４ 上部電極形成装置
１０５〜１０７ 搬送装置
Ｗ 基板
11 Stage 12 Laser irradiation device 13 Scanning mechanism 20 Base 21 Lower electrode 21a Upper surface 22 Dielectric film 22a Lower surface 23 Upper electrode 100 Capacitor forming system 101 Lower electrode forming device 102 Modification device 103 Dielectric film forming device 104 Upper electrode forming device 105- 107 Conveyor W board
Claims (17)
前記基板に誘電膜を成膜する誘電膜成膜装置と、
前記基板に上部電極を形成する上部電極形成装置と、
前記下部電極及び前記誘電膜の少なくともいずれかにレーザを照射する改質装置と、を備え、前記下部電極、前記誘電膜、前記上部電極を有するキャパシタを形成する、キャパシタ形成システム。 A lower electrode forming device that forms a lower electrode on a substrate,
A dielectric film forming apparatus for forming a dielectric film on the substrate and
An upper electrode forming device for forming an upper electrode on the substrate and
A capacitor forming system comprising a reforming device for irradiating at least one of the lower electrode and the dielectric film with a laser, and forming a capacitor having the lower electrode, the dielectric film, and the upper electrode.
前記下部電極にレーザを照射し、表面を改質する、
請求項１に記載のキャパシタ形成システム。 The reformer
Irradiate the lower electrode with a laser to modify the surface.
The capacitor forming system according to claim 1.
前記基板を還元ガス雰囲気で前記下部電極にレーザを照射する、
請求項２に記載のキャパシタ形成システム。 The reformer
Irradiate the lower electrode with a laser in a reducing gas atmosphere on the substrate.
The capacitor forming system according to claim 2.
前記誘電膜にレーザを照射し、表面を改質する、
請求項１乃至請求項３のいずれか１項に記載のキャパシタ形成システム。 The reformer
Irradiate the dielectric film with a laser to modify the surface.
The capacitor forming system according to any one of claims 1 to 3.
前記基板を酸素雰囲気で前記誘電膜にレーザを照射する、
請求項４に記載のキャパシタ形成システム。 The reformer
Irradiate the dielectric film with a laser in an oxygen atmosphere on the substrate.
The capacitor forming system according to claim 4.
レーザを照射した前記表面を多孔質化させ、表面積を増やす、
請求項２乃至請求項５のいずれか１項に記載のキャパシタ形成システム。 The reformer makes the surface irradiated with the laser porous and increases the surface area.
The capacitor forming system according to any one of claims 2 to 5.
ＫｒＦエキシマレーザを有する、
請求項１乃至請求項６のいずれか１項に記載のキャパシタ形成システム。 The reformer
Has a KrF excimer laser,
The capacitor forming system according to any one of claims 1 to 6.
前記下部電極にレーザを照射して表面を改質する工程と、
表面が改質された前記下部電極に誘電膜を成膜する工程と、
前記誘電膜に上部電極を形成する工程と、を有する、
キャパシタ形成方法。 The process of forming the lower electrode on the substrate and
The process of irradiating the lower electrode with a laser to modify the surface and
A step of forming a dielectric film on the lower electrode whose surface has been modified, and
A step of forming an upper electrode on the dielectric film.
Capacitor forming method.
前記下部電極に誘電膜を成膜する工程と、
前記誘電膜にレーザを照射して表面を改質する工程と、
表面が改質された前記誘電膜に上部電極を形成する工程と、を有する、
キャパシタ形成方法。 The process of forming the lower electrode on the substrate and
The process of forming a dielectric film on the lower electrode and
The step of irradiating the dielectric film with a laser to modify the surface and
It comprises a step of forming an upper electrode on the dielectric film having a modified surface.
Capacitor forming method.
前記下部電極にレーザを照射して表面を改質する工程と、
表面が改質された前記下部電極に誘電膜を成膜する工程と、
前記誘電膜にレーザを照射して表面を改質する工程と、
表面が改質された前記誘電膜に上部電極を形成する工程と、を有する、
キャパシタ形成方法。 The process of forming the lower electrode on the substrate and
The process of irradiating the lower electrode with a laser to modify the surface and
A step of forming a dielectric film on the lower electrode whose surface has been modified, and
The step of irradiating the dielectric film with a laser to modify the surface and
It comprises a step of forming an upper electrode on the dielectric film having a modified surface.
Capacitor forming method.
レーザを照射した前記表面を多孔質化させ、表面積を増やす、
請求項８乃至請求項１０のいずれか１項に記載のキャパシタ形成方法。 The step of modifying the surface is
Porous the surface irradiated with the laser to increase the surface area.
The capacitor forming method according to any one of claims 8 to 10.
請求項８または請求項１０に記載のキャパシタ形成方法。 The step of forming the lower electrode and the step of modifying the surface of the lower electrode are performed by the same apparatus.
The capacitor forming method according to claim 8 or 10.
請求項９または請求項１０に記載のキャパシタ形成方法。 The step of forming the dielectric film and the step of modifying the surface of the dielectric film are performed by the same apparatus.
The capacitor forming method according to claim 9 or 10.
請求項９乃至請求項１３のいずれか１項に記載のキャパシタ形成方法。 The step of forming the lower electrode, the step of modifying the surface, the step of forming the dielectric film, and the step of forming the upper electrode are performed without breaking the vacuum.
The capacitor forming method according to any one of claims 9 to 13.
請求項９乃至請求項１４のいずれか１項に記載のキャパシタ形成方法。 The lower electrode and the upper electrode are made of the same material.
The capacitor forming method according to any one of claims 9 to 14.
請求項９乃至請求項１５のいずれか１項に記載のキャパシタ形成方法。 The material of the lower electrode and / or the upper electrode includes any one of TiN, Mo, MoN, Nb, NbO, Ru, and RuO.
The capacitor forming method according to any one of claims 9 to 15.
請求項９乃至請求項１３のいずれか１項に記載のキャパシタ形成方法。 The irradiation fluence of the laser in the step of modifying the surface is 150 mJ / cm 2 or more and 250 mJ / cm 2 or less.
The capacitor forming method according to any one of claims 9 to 13.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019136392A JP2021022597A (en) | 2019-07-24 | 2019-07-24 | Capacitor forming system and capacitor forming method |
| PCT/JP2020/027131 WO2021015019A1 (en) | 2019-07-24 | 2020-07-10 | Capacitor-forming system and capacitor-forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019136392A JP2021022597A (en) | 2019-07-24 | 2019-07-24 | Capacitor forming system and capacitor forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2021022597A true JP2021022597A (en) | 2021-02-18 |
Family
ID=74193058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019136392A Pending JP2021022597A (en) | 2019-07-24 | 2019-07-24 | Capacitor forming system and capacitor forming method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2021022597A (en) |
| WO (1) | WO2021015019A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04335568A (en) * | 1991-05-10 | 1992-11-24 | Nippon Steel Corp | Manufacture of dynamic memory cell |
| JP2002164514A (en) * | 2000-11-24 | 2002-06-07 | Nec Corp | Method for manufacturing semiconductor device |
| JP4545433B2 (en) * | 2003-12-26 | 2010-09-15 | 東京エレクトロン株式会社 | Deposition method |
| JP2013058559A (en) * | 2011-09-07 | 2013-03-28 | Tokyo Electron Ltd | Manufacturing method of semiconductor device and substrate processing system |
-
2019
- 2019-07-24 JP JP2019136392A patent/JP2021022597A/en active Pending
-
2020
- 2020-07-10 WO PCT/JP2020/027131 patent/WO2021015019A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021015019A1 (en) | 2021-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI565829B (en) | A semiconductor device manufacturing method, a substrate processing apparatus, a substrate processing system, and a recording medium | |
| JP5306295B2 (en) | Semiconductor device manufacturing method and substrate processing apparatus | |
| WO2014148551A1 (en) | Semiconductor device manufacturing method, substrate processing device and recording medium | |
| KR20090086407A (en) | Method and device for forming silicon dot and silicon dot and method and device for forming substrate with insulating film | |
| KR20160025591A (en) | Substrate processing device, method for producing semiconductor device, and recording medium | |
| US20070077759A1 (en) | Method for forming dielectric film and method for manufacturing semiconductor device by using the same | |
| JP6815158B2 (en) | Titanium oxide film forming method and hard mask forming method | |
| US8071446B2 (en) | Manufacturing method of semiconductor device and substrate processing apparatus | |
| JPH09186085A (en) | Laser annealing method and laser annealing apparatus | |
| WO2021015019A1 (en) | Capacitor-forming system and capacitor-forming method | |
| JP2007201083A (en) | Process for fabricating capacitor | |
| JP4789412B2 (en) | Plasma processing equipment | |
| JP6092676B2 (en) | Semiconductor device manufacturing method, substrate processing apparatus, and program | |
| JP2006278619A (en) | Semiconductor-manufacturing apparatus | |
| KR100538865B1 (en) | Single-substrate-heat-processing apparatus and method for performing reformation and crystallization | |
| WO2021015142A1 (en) | Substrate processing method, substrate processing device, and wiring pattern forming system | |
| CN112740376A (en) | Method for manufacturing semiconductor device, substrate processing apparatus, and program | |
| KR20230124008A (en) | Substrate processing method and substrate processing apparatus | |
| KR20210045296A (en) | Processing method for substrate | |
| JP2018129330A (en) | Substrate processing apparatus, method of manufacturing semiconductor device and program | |
| JPH09162138A (en) | Laser annealing method and laser annealer | |
| JP2003013232A (en) | Method for cleaning reaction vessel, and film forming apparatus | |
| JP2011066187A (en) | Film formation method and processing system | |
| US6989338B2 (en) | Method for forming a multi-layered structure of a semiconductor device and methods for forming a capacitor and a gate insulation layer using the multi-layered structure | |
| JP4001645B2 (en) | Crystalline silicon film manufacturing method and laser irradiation apparatus |