JP2021010784A - Game machine - Google Patents

Abstract

To provide a game machine that can increase a free area of ROM of a main control circuit by reducing space for a processing program, a table and the like managed by the main control circuit, and use the increased free area of ROM to enhance game amusement.SOLUTION: A game machine has a specific state as a state controlled by the execution of arithmetic processing by arithmetic processing means. For the specific state, there are two cases at least: first, it continues until the lapse of a first period, and second, it continues until the lapse of a second period longer than the first period. At a timing from the start of the specific state before the lapse of the first period, it can be suggested that the specific state continues until the lapse of at least the second period. The arithmetic processing means executes a predetermined update instruction by which an update instruction, a lower limit determination instruction, and a determination branching instruction can be executed by a single instruction in counting of a timer value of a 2 byte software timer.SELECTED DRAWING: Figure 107

Description

The present invention relates to a game machine.

Conventionally, a game called pachislot is provided with a plurality of reels having a plurality of symbols provided on their respective surfaces, a start switch, a stop switch, a stepping motor provided corresponding to each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter, also referred to as "start operation") after the game medium such as a medal or coin is inserted into the game machine, and the rotation of all reels is rotated. Outputs a signal requesting a start. The stop switch detects that the stop button provided corresponding to each reel is pressed by the player (hereinafter, also referred to as "stop operation"), and outputs a signal requesting that the rotation of the corresponding reel be stopped. To do. The stepping motor transmits its driving force to the corresponding reels. Further, the control unit controls the operation of the stepping motor based on the signals output by the start switch and the stop switch, and performs the rotation operation and the stop operation of each reel.

In such a game machine, when a start operation is detected, a lottery process using random numbers (hereinafter referred to as "internal lottery process") is performed on the program, and the result of the lottery (hereinafter, "internal winning combination") is performed. The rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all reels is stopped and the combination of symbols (display combination) related to the establishment of the winning is displayed, the player is given a privilege corresponding to the combination of the symbols. As an example of the privilege given to the player, the payout of the game medium (medals, etc.) and the operation of the re-game (hereinafter, also referred to as "replay") in which the internal lottery process is performed again without consuming the game medium. , The operation of a special game state (bonus game) in which the opportunity to pay out the game medium is increased.

Further, in such a game machine, a function of navigating the establishment of a predetermined combination (for example, a predetermined small combination that is a combination related to the payout of the game medium) with a lamp or the like, that is, an assist time (hereinafter referred to as "AT"). ) Is provided. Further, such a game machine is provided with a function of operating a gaming state in which the winning probability of replay is higher than normal when a specific operating condition is satisfied, that is, a function of replay time (hereinafter referred to as "RT"). There is also. Further, there is also one provided with an assist replay time (hereinafter referred to as "ART") function in which such AT and RT operate at the same time.

Further, in such a game machine, a game machine controlled by a timer subtraction process by software is known (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2004-041261

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above problems by reducing the capacity of processing programs and tables managed by the main control circuit to increase the free capacity of the ROM of the main control circuit, and by the increased capacity. It is an object of the present invention to provide a gaming machine capable of enhancing game playability by utilizing the free area of the ROM of the above.

The gaming machine of the present invention
A game control means that controls the game,
A production control means that controls the production and
In a game machine equipped with an effect execution means capable of executing an effect
The game control means
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a game, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
There is a specific state as a state controlled by the execution of the arithmetic processing by the arithmetic processing means.
The specific state may at least continue from the start of the specific state to the elapse of the first period, or may continue from the start of the specific state to the elapse of a second period longer than the first period.
The effect executing means can suggest that the specific state continues at least until the lapse of the second period at a timing from the start of the specific state to before the lapse of the first period.
The arithmetic processing means
In the timer value counting process of a 2-byte soft timer (for example, timer update process)
By executing a predetermined update instruction (for example, "DCPWLD" instruction) that can execute an update instruction, a lower limit determination instruction, and a determination branch instruction with one instruction, the current timer value of the soft timer and the lower limit of the timer value are executed. While comparing with the value, if the current timer value of the soft timer is larger than the lower limit value, the timer value of the soft timer is subtracted and updated, and if the current timer value of the soft timer is equal to or less than the lower limit value. , The timer value of the soft timer is held at the lower limit value,
After that, the update start address of the soft timer in the second storage means is updated by 2 bytes.

According to the gaming machine of the present invention having the above configuration, the capacity of the processing program and the table managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the increased capacity is increased. The playability can be improved by using the free area of the ROM of the minute.

It is a figure for demonstrating the functional flow of the game machine in one Embodiment of this invention. It is a perspective view which shows the appearance structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the schematic structure of the various display screens displayed on the sub-display device of one Embodiment of this invention. It is a figure which shows the transition example of the display screen of the sub display device in one Embodiment of this invention. It is a block diagram which shows the whole structure of the circuit provided in the gaming machine of one Embodiment of this invention. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram which shows the internal structure of the microprocessor in one Embodiment of this invention. It is a block diagram which shows the internal structure of the sub-control circuit in one Embodiment of this invention. It is a block diagram of various registers which a main CPU has in one Embodiment of this invention. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure which shows the transition flow of the gaming state between the bonus state and the non-bonus state of pachislot in one Embodiment of this invention. It is a figure which shows the transition flow of the gaming state between the ART gaming state and the non-ART gaming state of the pachislot in one Embodiment of this invention. It is a figure which shows an example of the symbol arrangement table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the internal winning combination, the stop operation order (batting order), the display combination, etc. in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the internal winning combination, the stop operation order (batting order), the display combination, etc. in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the internal winning combination, the stop operation order (batting order), the display combination, etc. in one Embodiment of this invention. It is a figure which shows the structure of the hit request flag storage area, and the winning operation flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the carry-over combination storage area in one Embodiment of this invention. It is a figure which shows the structure of the game state flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the operation stop button storage area in one Embodiment of this invention. It is a figure which shows the structure of the pressing order storage area in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one Embodiment of this invention. It is a figure for demonstrating the normal mode and ART mode in one Embodiment of this invention. It is a figure which shows an example of the normal ART lottery table in one Embodiment of this invention. It is a figure which shows an example of the normal mode transition lottery table in one Embodiment of this invention. It is a figure which shows an example of the CP acquisition lottery table in the CP specialization zone in one Embodiment of this invention. It is a figure which shows an example of the CP acquisition lottery table in a double specialization zone in one Embodiment of this invention. (A) is a diagram showing an example of a double specialization zone start state lottery table in one embodiment of the present invention, and (B) is a double specialization zone middle blue 7:00 CP in one embodiment of the present invention. It is a figure which shows an example of the acquisition lottery table, (C) is a figure which shows an example of the double special zone middle blue 7 fake lottery table in one Embodiment of this invention, (D) is one of the present invention. It is a figure which shows an example of the double specialization zone end lottery table in embodiment. It is a figure for demonstrating the determination value for special effect lottery in one Embodiment of this invention. It is a figure which shows an example of the normal special effect reservation lottery table in one Embodiment of this invention. It is a flowchart which shows an example of the power-on (reset interrupt) processing executed by the main control circuit of the game machine in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the power-on processing in one Embodiment of this invention. It is a flowchart which shows the example of the game return processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the game return processing in one Embodiment of this invention. It is a flowchart which shows the example of the setting change confirmation processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the setting change confirmation process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change command generation storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the setting change command generation storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the communication data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data pointer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the communication data pointer update process in one Embodiment of this invention. It is a flowchart which shows the example of the (external) processing at the time of power failure in one Embodiment of this invention. It is a flowchart which shows the example of the checksum generation process (non-standard) in one Embodiment of this invention. An example of a source program for executing various processes in the flowchart of the checksum generation process according to the embodiment of the present invention, a stack pointer update operation executed in the checksum generation process, and a data read operation to a register. It is a figure which shows the state of. It is a flowchart which shows the example of the sum check process (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the sum check process (non-standard) in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the checksum process in one Embodiment of this invention. It is a flowchart which shows the example of the main processing (main operation processing) executed by the main control circuit of a game machine in one Embodiment of this invention. It is a flowchart which shows the example of the medal acceptance / start check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the medal acceptance / start check processing in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the medal insertion process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the medal insertion check process in one Embodiment of this invention. It is a flowchart which shows the example of the error processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the error table which is actually referred to on the source program of error processing in one Embodiment of this invention. It is a flowchart which shows the example of the random number acquisition processing in one Embodiment of this invention. It is a flowchart which shows the example of the internal lottery processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the internal lottery processing in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board control processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board output processing in one Embodiment of this invention. It is a flowchart which shows the example of the control processing by state in one Embodiment of this invention. It is a flowchart which shows the example of the start-time processing in a double specialization zone in one Embodiment of this invention. It is a flowchart which shows the example of the start-time processing in a double specialization zone in one Embodiment of this invention. It is a flowchart which shows the example of the process at the start of continuous challenge in one Embodiment of this invention. It is a flowchart which shows the example of the process at the start of promotion chance in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the pull-in priority order storage process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol code acquisition processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the symbol code acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the logical product operation processing in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the pull-in priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop control processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the reel stop control processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the reel stop control processing in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal OFF processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal ON processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the non-standard port output processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the non-standard port output processing in one Embodiment of this invention. It is a flowchart which shows the example of the winning search processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the prize search process in one Embodiment of this invention. It is a flowchart which shows the example of the illegal hit check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the illegal hit check processing in one Embodiment of this invention. It is a flowchart which shows the example of the winning check, medal payout processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the prize check / medal payout process in one Embodiment of this invention. It is a flowchart which shows the example of the medal payout number check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the medal payout number check process in one Embodiment of this invention. It is a flowchart which shows the example of the bonus check process in one Embodiment of this invention. It is a flowchart which shows the example of RT check processing in one Embodiment of this invention. It is a flowchart which shows the example of the control process according to the state at the end of a game in one Embodiment of this invention. It is a flowchart which shows the example of the processing at the end of a continuous challenge in one embodiment of the present invention. It is a flowchart which shows the example of the interrupt process executed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the 7-segment LED drive processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of 7-segment LED drive processing in one Embodiment of this invention. It is a flowchart which shows the example of the 7-segment display data generation processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of 7-segment display data generation processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the 7-segment cathode table which is actually referred to on the source program of the 7-segment display data generation processing in one Embodiment of this invention. It is a flowchart which shows the example of the timer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the timer update process in one Embodiment of this invention. It is a flowchart which shows the example of the test firing test signal control processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the rotation cylinder braking signal generation processing in one Embodiment of this invention. It is a flowchart which shows the example of the prize signal control processing in one Embodiment of this invention. It is a flowchart which shows the example of the condition device signal control processing in one Embodiment of this invention. It is a flowchart which shows the example of the condition device signal control processing in one Embodiment of this invention. It is a flowchart which shows an example of the power-on processing of a sub CPU executed by the sub-control circuit of a game machine in one Embodiment of this invention. It is a flowchart which shows the example of the power interruption interrupt process of the sub CPU executed by the sub-control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the processing of the main board communication task in one Embodiment of this invention. It is a flowchart which shows the example of the sub-side navigation control processing in one Embodiment of this invention. It is a flowchart which shows the example of the player registration process in one Embodiment of this invention. It is a flowchart which shows the example of the history management processing in one Embodiment of this invention. It is a flowchart which shows the example of the effect determination process in one Embodiment of this invention. It is a flowchart which shows the example of the production decision processing during promotion chance in one Embodiment of this invention. It is a flowchart which shows the example of the special effect reservation processing in one Embodiment of this invention. It is a flowchart which shows the example of the special effect execution processing in one Embodiment of this invention. It is a figure which shows an example of the effect display during the promotion chance in one Embodiment of this invention. It is a figure which shows an example of the effect display during the promotion chance in one Embodiment of this invention. It is a figure which shows an example of the effect display during the promotion chance in one Embodiment of this invention. It is a figure for demonstrating the numerical variation display control of pachislot in one Embodiment of this invention.

Hereinafter, a pachi-slot machine will be taken as an example of a gaming machine according to an embodiment of the present invention, and its configuration and operation will be described with reference to the drawings. In this embodiment, a pachislot machine having a bonus operation function and an ART function will be described.

<Function flow>
First, the functional flow of the pachislot machine will be described with reference to FIG. In the pachislot machine of the present embodiment, a medal is used as a game medium for playing a game. In addition to medals, coins, game balls, point data for games, tokens, and the like can also be applied as the game medium. In addition, the game medium may be referred to as "game value" or "game value".

When a medal is inserted into the pachislot machine by the player and the start lever is operated, one value (hereinafter referred to as a random number value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

The internal lottery means draws a lot based on the extracted random number value, and determines the internal winning combination. This internal lottery means is one of various processing means (processing functions) included in the main control circuit described later. By determining the internal winning combination, the combination of symbols that are permitted to be displayed (display is allowed) is determined along the valid line (winning judgment line) described later. The types of symbol combinations include those related to "winning" in which benefits such as medal payout, replay operation, bonus operation, etc. are given to the player, and other so-called "missing". Such things are provided. In the following, the role related to the payout of medals will be referred to as a "small role", and the role related to the operation of the replay (replay) will be referred to as a "replay role". In addition, the role related to the operation of the bonus (bonus game) is referred to as a "bonus role". In addition, a winning combination (that is, a combination of symbols that are allowed to be established) may be simply referred to as a "winning combination", and the internal winning combination is a "winning combination", a "predetermined result", or Sometimes referred to as "derivation tolerance". Further, the internal lottery means may be referred to as a "combination determining means", a "winning combination determining means", a "predetermining means", or a "derivation allowable condition determining means".

Further, when the start lever is operated, a plurality of reels are rotated. After that, when the stop button corresponding to the predetermined reel is pressed by the player, the reel stop control means controls to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. This reel stop control means is one of various processing means (processing functions) included in the main control circuit described later. The operation means for performing the start operation is not limited to a lever shape such as a start lever, and any operation means may be used as long as the player can perform the start operation. .. Further, the operation means for performing the stop operation is not limited to a button shape such as a stop button, and any operation means may be used as long as the player can perform the stop operation. ..

In pachislot, basically, control is performed to stop the rotation of the corresponding reel within a specified time (190 msec or 75 msec) from the time when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within this specified time is referred to as the "number of sliding pieces". In the present embodiment, when the specified time is 190 msec, the maximum number of sliding pieces (maximum number of sliding pieces) is set for four symbols, and when the specified time is 75 msec, the maximum number of sliding pieces is set. The number is set for one symbol. The specified time is usually 190 msec, and the maximum number of sliding pieces is four symbols on each reel, but while a specific bonus (middle bonus: called MB) is operating, it is specified for a specific reel. The time is 75 msec, and the maximum number of sliding pieces is one symbol.

When the internal winning combination that allows the display of the combination of symbols related to the winning is determined, the reel stop control means usually has the combination of the symbols valid within the specified time of 190 msec (for 4 symbols). Stop the rotation of the reel so that it is displayed as much as possible along. In addition, the reel stop control means uses a predetermined time to stop the rotation of the reel so that the combination of symbols whose display is not permitted by the internal winning combination is not displayed along the effective line. The symbol displayed when the rotation of the reel is stopped may be referred to as "stop display" or "display result". Further, displaying a symbol on the effective line when the rotation of the reel is stopped may be expressed as "derivation of stop display" or "derivation of display result".

Further, the reel stop control means automatically stops each reel when a predetermined automatic stop time elapses after the reels rotate, even if the player does not perform the stop operation. Stop control may be performed. In this case, the reels are stopped without the player's stop operation, so even if one of the internal winning combinations is decided, the combination of symbols related to any winning is effective. It is desirable to stop the rotation of the reel so that it is not displayed along the line.

In this way, when all the rotations of the plurality of reels are stopped, the winning determination means determines whether or not the combination of symbols displayed along the effective line is related to winning. This winning determination means is also one of various processing means (processing functions) included in the main control circuit described later. Then, when it is determined by the winning determination means that the combination of the displayed symbols is related to the winning, a privilege such as a medal payout is given to the player. In pachislot, the above-mentioned series of flows is performed as one game (unit game).

The winning determination means determines whether or not the combination of symbols displayed along the valid line simply corresponds to any combination of symbols among a plurality of predetermined combinations of symbols. It may be present, or it may be determined whether or not it corresponds to the combination of symbols related to the internal winning combination determined by the internal lottery means. That is, in the former, it may be determined whether or not it is a combination of symbols related to winning, separately from the internal winning combination. In this case, as long as the reel stop control means appropriately stops and controls the stop, the prevention of the occurrence of erroneous winning can be sufficiently ensured, so that the control burden related to the detection of erroneous winning can be reduced. On the other hand, in the latter case, it is possible to determine whether or not the combination of symbols related to winning is a combination of symbols for which winning is permitted, so that if an erroneous winning occurs due to a reel defect or the like, the erroneous winning is performed. Can be detected, so that security can be improved.

Further, in pachislot, in the flow of the above-mentioned series of game operations, various effects are produced by displaying an image by a display device, outputting light by various lamps, outputting sound by a speaker, or a combination of these. Is done.

Specifically, when the start lever is operated, a random value for production is extracted in addition to the random value used for determining the internal winning combination described above. When the random value for the effect is extracted, the effect content determining means determines the effect to be executed this time from a plurality of types of effect contents associated with the internal winning combination by lottery. This effect content determining means is one of various processing means (processing functions) included in the sub-control circuit described later.

Next, when the effect content is determined by the effect content determining means, the effect execution means responds in conjunction with each opportunity such as when the reel starts rotating, when each reel stops rotating, and when it is determined whether or not there is a prize. To execute. In this way, in pachislot, for example, by executing the production content associated with the internal winning combination, the opportunity to know or anticipate the determined internal winning combination (in other words, the combination of symbols to be aimed at) is a game. It is provided to the player and can improve the interest of the player.

<Structure of pachislot>
Next, the structure of the pachislot machine according to the embodiment of the present invention will be described with reference to FIGS. 2 to 4.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachislot machine 1.

As shown in FIG. 2, the pachislot machine 1 includes an exterior body (game machine main body) 2. The exterior body 2 has a cabinet 2a for accommodating a reel, a circuit board, and the like, and a front door 2b to which an opening of the cabinet 2a can be opened and closed.

Inside the cabinet 2a, three reels 3L, 3C, 3R (variable display means, display row) are provided side by side in a horizontal row. Hereinafter, each reel 3L, 3C, 3R (main reel) is also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 20) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction (rotation direction of the reel). In addition, each reel 3L, 3C, 3R may be expressed as "design display means", "variable display means", "variable display" and the like. Further, as these components, the symbol display area 4 described later may be included. Further, the "design" may be any information that can be visually identified by the player, and may be expressed as "identification information" in that sense.

The front door 2b includes a door body 9, a front panel 10, a lumbar panel 12, and a pedestal portion 13. The door body 9 is attached to the cabinet 2a so as to be openable and closable using a hinge (not shown). The hinge is provided at the left side end of the door body 9 when viewed from the front side (player side) of the pachislot machine 1. The cabinet 2a can be simply referred to as a "box body", and the front door 2b can be simply referred to as a "door" or a "front door". Further, since the cabinet 2a functions as a frame body for supporting or fixing the front door 2b, it may be expressed as a "support body", a "support frame", or a "fixed frame". Further, the front door 2b may be composed of a plurality of door members. For example, it may be composed of an upper door member attached to the upper side of the opening of the cabinet 2a and a lower door member attached to the lower side of the opening of the cabinet 2a, or may be configured when viewed from the front side of the gaming machine. The inner door member attached to the opening side of the cabinet 2a and the outer door member attached to the front side of the game machine may be used.

The front panel 10 is provided on the upper part of the door body 9. The front panel 10 is composed of a frame-shaped member having an opening 10a. The opening 10a of the front panel 10 is closed by the display device cover 30, and the display device cover 30 is arranged to face the display device 11 which will be described later and is arranged inside the cabinet 2a.

The display device cover 30 is made of a black translucent synthetic resin. Therefore, the player can visually recognize the image (image) displayed by the display device 11 described later through the display device cover 30. Further, in the present embodiment, by forming the display device cover 30 with a black translucent synthetic resin, the entry of external light into the cabinet 2a is suppressed, and the image (image) displayed by the display device 11 is suppressed. Is clearly visible.

A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, lamps 21a and 21b provided on the upper part of the front panel 10 when viewed from the player side. Each lamp constituting the lamp group 21 is composed of an LED (Light Emitting Diode) or the like (see LED group 85 in FIG. 7 described later), and lights are turned on and off in a pattern corresponding to the effect content.

The waist panel 12 is provided at a substantially central portion of the door body 9. The waist panel 12 has a decorative panel on which an arbitrary image is drawn, and a light source (LED included in the LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

The pedestal portion 13 is provided between the front panel 10 and the lumbar panel 12. The pedestal portion 13 has a symbol display area 4, various devices (medal insertion slot 14, MAX bet button 15a, 1 bet button 15b, start lever 16, 3 stop buttons 17L, 17C, which are to be operated by the player. 17R, settlement button (not shown), etc.) are provided.

The symbol display area 4 is an area that overlaps the three reels 3L, 3C, 3R when viewed from the front, and is arranged at a position on the player side of the three reels 3L, 3C, 3R, and the three reels. It has a size that makes 3L, 3C, and 3R visible. The symbol display area 4 functions as a display window, and has a configuration in which the reels 3L, 3C, and 3R provided behind the symbol display area 4 can be visually recognized. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

The reel display window 4 is arranged continuously among a plurality of symbols provided on the peripheral surface of each reel when the rotation of the three reels 3L, 3C, 3R provided behind the reel display window 4 is stopped. It is configured so that one symbol is displayed in the frame. That is, when the rotation of the three reels 3L, 3C, and 3R is stopped, one symbol is set in each of the upper, middle, and lower regions for each reel in the frame of the reel display window 4 (three in total). ) Is displayed (in the frame of the reel display window 4, the design is displayed in the form of 3 rows × 3 columns). Then, in the present embodiment, in the frame of the reel display window 4, a pseudo line (center line) connecting the middle stage region of the left reel 3L, the middle stage region of the middle reel 3C, and the middle stage region of the right reel 3R is formed. It is defined as an effective line for judging whether or not a prize is won.

The reel display window 4 is formed by the opening of the frame member 31 provided in the pedestal portion 13. Further, a pedestal region having a substantially horizontal plane is provided below the frame member 31 that defines the reel display window 4. When viewed from the player side, the medal insertion slot 14 is provided on the right side of the pedestal area, and the MAX bet button 15a and the 1-bet button 15b are provided on the left side.

The medal slot 14 is provided to receive medals dropped on the pachislot machine 1 from the outside by the player. The medals received from the medal slot 14 are used in one game up to a preset predetermined number (for example, 3), and the number of medals exceeding the predetermined number is deposited inside the pachislot machine 1. (So-called credit function (game medium storage means)).

The MAX bet button 15a and the 1-bet button 15b are provided to determine the number of medals to be used in one game from the medals deposited inside the cabinet 2a. Inside the MAX bet button 15a, a bet button LED (not shown) that lights up when a medal can be inserted is provided. In addition, the checkout button is provided to pull out (discharge) the medals deposited inside the pachislot machine 1 to the outside.

When the player presses the MAX bet button 15a, medals for the number of bets (3) in the unit game are inserted and the effective line is activated. On the other hand, one medal is inserted each time the 1-bet button 15b is pressed once. When the 1-bet button 15b is operated three times, medals for the number of bets (3) in the unit game are inserted and the effective line is activated.

In the following, the operation of the MAX bet button 15a, the operation of the 1-bet button 15b, and the operation of inserting medals into the medal insertion slot 14 (operations of inserting medals to perform a game) are all referred to as "insertion operations".

The start lever 16 is provided to start the rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, and 17R are provided corresponding to the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are also referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

Further, an information display 6 is provided at substantially the center of the pedestal region on the substantially horizontal plane below the reel display window 4. The information display 6 is covered with a transparent window cover (not shown).

The information display 6 is a 2-digit 7-segment LED for digitally displaying (notifying) information on the number of medals to be paid out to the player (hereinafter referred to as "the number of medals to be paid out") as a privilege. For digitally displaying (notifying) information such as (hereinafter referred to as "7-segment LED") and the number of medals deposited inside the pachislot 1 (hereinafter referred to as "credit number") to the player. A 2-digit 7-segment LED is provided. In the present embodiment, the 2-digit 7-segment LED for displaying the number of medals to be paid out is a 2-digit 7-segment LED for digitally displaying (notifying) information on the occurrence of an error and the error type to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the number of medals to be paid out is switched from the display mode of the number of medals to be paid out to the display mode of the error type information.

Further, the information display 6 is provided with an instruction monitor (not shown) for notifying information on the stop operation necessary for displaying the symbol combination according to the winning combination determined as the internal winning combination along the effective line. ing. The instruction monitor (instruction display) is composed of, for example, a 2-digit 7-segment LED. Then, the instruction monitor notifies the player of the necessary stop operation information by turning on, blinking, or turning off the two-digit 7-segment LED in a manner uniquely corresponding to the stop operation information to be notified. To do.

The mode that uniquely corresponds to the information of the stop operation to be notified here is, for example, when the push order "1st (the first stop operation is performed on the left reel 3L)" is notified. When the numerical value "1" is displayed on the instruction monitor and the push order "2nd (perform the first stop operation on the middle reel 3C)" is notified, the numerical value "2" is displayed on the instruction monitor and the push order is displayed. When notifying "3rd (performing the first stop operation on the right reel 3R)", the numerical value "3" is displayed on the instruction monitor. The mode of notifying the information of the stop operation on the instruction monitor (navigation data determined on the main side described later) will be described in detail later with reference to FIGS. 19 to 21 described later.

As shown in FIG. 7 described later, the information display 6 is electrically connected to the main control board 71 via the door relay board 68 and the game operation display board 81, and the display operation of the information display 6 is mainly controlled. It is controlled by the main control circuit 90 described later in the board 71. Further, the control method of the various 7-segment LEDs described above is dynamic lighting control.

In the pachi-slot machine 1 of the present embodiment, in addition to the instruction monitor controlled by the main control board 71, another means controlled by the sub-control board 72 is used to notify the information of the stop operation. Specifically, the information on the stop operation is notified by the display device 11 described later, which is composed of the projector mechanism 211 and the display unit 212 (see FIGS. 3 and 7 described later) described later.

When such a configuration is applied, the mode of notification in the instruction monitor and the mode of notification in other means controlled by the sub-control board 72 may be different from each other. That is, the instruction monitor may be notified in a manner uniquely corresponding to the information of the stop operation to be notified, and it is not always necessary to directly notify the information of the stop operation (for example, the numerical value "1" in the instruction monitor. Even if is displayed, it may not be possible to specify the content of the notification depending on the player, so it cannot be said that the notification is direct). On the other hand, in the notification on the sub side (sub control board side) by other means such as the display device 11 described later, the information of the stop operation may be directly notified. For example, when the push order "1st" is notified, the instruction monitor displays a numerical value "1" that uniquely corresponds to the push order to be notified, but other means (for example, the display device 11 or the like) display the left reel 3L. The instruction information for performing the first stop operation may be directly notified to the user.

In the pachi-slot machine 1 having such a configuration, not only the control of the sub-control board 72 but also the control of the main control board 71 can be used to notify the information of the necessary stop operation according to the internal winning combination. Further, the presence / absence of notification of such stop operation information may be controlled according to the game state (control state). For example, in the non-ART game state (see FIG. 14 described later), the stop operation information may not be notified, but in the ART game state (see FIG. 14 described later), the stop operation information may be notified.

Further, a sub display device 18 is provided on the left side of the reel display window 4 when viewed from the player side. As shown in FIG. 2, the sub-display device 18 is provided so as to stand substantially perpendicular to the pedestal region of the pedestal portion 13 in the substantially horizontal plane of the front portion of the door body 9. The sub-display device 18 is composed of a liquid crystal display and an organic EL (Electro-Luminescence) display, and displays various information.

Further, a touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 7 described later). The touch sensor 19 operates according to a predetermined operating principle such as a capacitance method, and when it receives an operation of a player, it outputs a signal corresponding to the operation as touch input information. The pachi-slot machine 1 of the present embodiment has a function of enabling the display of the sub-display device 18 to be switched according to the player's operation (touch input information output from the touch sensor 19) received via the touch sensor 19. Has. The sub display device 18 is controlled by the sub control board 72 (see FIG. 7 described later) based on the touch input information output from the touch sensor 19.

A medal payout outlet 24, a medal tray 25, two speaker holes 20L, 20R, and the like are provided in the lower part of the door body 9. The medal payout outlet 24 guides the medals discharged by driving the medal payout device 51, which will be described later, to the outside. The medal tray 25 stores medals discharged from the medal payout outlet 24. Further, sound effects such as sound effects and music corresponding to the contents of the production are output from the two speaker holes 20L and 20R.

[Internal structure]
Next, the internal structure of the pachislot machine 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a diagram showing the internal structure of the cabinet 2a, and FIG. 4 is a diagram showing the internal structure of the front door 2b on the back surface side.

As shown in FIG. 3, the cabinet 2a has a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. A display device 11 is arranged in the upper part of the cabinet 2a.

The display device 11 has a projector mechanism 211 and a box-shaped projected member 212a on which the image light projected from the projector mechanism 211 is projected, and displays an image by projection mapping. Specifically, the display device 11 generates image light based on the position (projection distance, angle, etc.) and shape of the projected member 212a, which is a three-dimensional object, and the image light is emitted by the projector mechanism 211 to the projected member. It is projected on the surface of 212a. By providing such an effect function, it is possible to perform an advanced and powerful effect. Further, although not shown in FIG. 3, another projected member having a curved display surface is provided on the back side of the box-shaped projected member 212a, and one of the projected members is provided depending on the gaming state. , Used as a screen on which video light is projected. Therefore, the inside of the cabinet 2a is also provided with a function (not shown) for switching the projected member according to the gaming state.

A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are arranged in the lower part of the cabinet 2a.

The hopper device 51 is attached to the central portion of the bottom plate 27b in the cabinet 2a. The hopper device 51 has a structure capable of accommodating a large number of medals and ejecting them one by one. The hopper device 51 pays out medals when the number of stored medals exceeds, for example, 50, or when the settlement button is pressed and the settlement of medals is executed. Then, the medals paid out by the hopper device 51 are discharged from the medal payout outlet 24 (see FIG. 2).

The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is arranged on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. Further, the medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

The power supply device 53 includes a power supply switch 53a and a power supply board 53b (power supply means) (see FIG. 7 described later). The power supply device 53 is arranged on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 27c. The power supply device 53 converts the AC voltage 100V power supplied from the sub power supply device (not shown) into the DC voltage power required by each part, and supplies the converted power to each part.

Further, above the power supply device 53 in the cabinet 2a, a sub-control board case 57 for accommodating the sub-control board 72 (see FIG. 7 described later) is arranged. A sub-control circuit 200 (see FIG. 10 to be described later) described later is mounted on the sub-control board 72 housed in the sub-control board case 57. The sub-control circuit 200 is a circuit that controls the execution of an effect by displaying an image or the like. The specific configuration of the sub-control circuit 200 will be described later.

The sub-relay board 61 is arranged above the sub-control board case 57 in the cabinet 2a. The sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72 and the main control board 71, which will be described later, is mounted. Further, the sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72 and the boards arranged around the sub-control board 72 and various device units (units) is mounted.

Further, although not shown in FIG. 3, a cabinet-side relay board 44 (see FIG. 7 described later) is arranged in the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 7 described later), a hopper device 51, a game medal auxiliary storage switch 77 (see FIG. 7 described later), and a medal payout count switch (not shown). It is a relay board on which wiring for connecting to and is mounted.

As shown in FIG. 4, a middle door 41 is arranged at the center of the front door 2b on the back surface side, and a reel display window 4 (see FIG. 2) is attached so as to be openable and closable from the back side. Although not shown in FIG. 4, three reels 3L, 3C, and 3R are attached to the reel display window 4 side of the middle door 41, and the main control is on the side opposite to the reel display window 4 side of the middle door 41. A main control board case 55 in which the board 71 (see FIG. 7 described later) is housed is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, and 3R via gears having a predetermined reduction ratio.

The main control board 71 housed in the main control board case 55 has a main control circuit 90 (see FIG. 9 described later) described later. The main control circuit 90 (main control means) is a circuit that controls the main flow of the game in the pachislot machine 1, such as determining the internal winning combination, rotating and stopping the reels 3L, 3C, and 3R, and determining whether or not there is a prize. .. Further, in the present embodiment, for example, the main control circuit 90 also controls the lottery process of whether or not the ART is determined, the display process of the navigation information on the instruction monitor, the transmission process of various test signals, and the like. The specific configuration of the main control circuit 90 will be described later.

Speakers 65L and 65R are arranged below the middle door 41 on the back surface side of the front door 2b. The speakers 65L and 65R are arranged at positions facing the speaker holes 20L and 20R (see FIG. 2), respectively.

A selector 66 and a door open / close monitoring switch 67 are arranged above the speaker 65L. The selector 66 is a device for selecting whether or not the material and shape of medals are appropriate, and guides the appropriate medals inserted into the medal insertion slot 14 to the hopper device 51. A medal sensor (game medium detecting means: not shown) for detecting that a proper medal has passed is provided on the path through which the medal passes in the selector 66.

The door open / close monitoring switch 67 is arranged diagonally to the lower left of the selector 66 when the front door 2b is viewed from the back surface side. The door open / close monitoring switch 67 outputs a security signal for notifying the open / close of the front door 2b to the outside of the pachislot machine 1.

Further, although not shown in FIG. 4, a door relay terminal plate 68 is arranged on the back surface of the front door 2b, which is a region opened and closed by the middle door 41 and below the reel display window 4 (FIG. 4 described later). 7). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a testing machine, and the like. This is a relay board on which wiring for connecting each of the second interface boards 302 for a testing machine is mounted. Examples of various buttons and switches include a MAX bet button 15a, a 1-bet button 15b, a door open / close monitoring switch 67, a BET switch 77 described later, and a start switch 79.

<Display example of sub display device>
Here, various display screens displayed on the sub-display device 18 will be described with reference to FIGS. 5A to 5E. 5A is a diagram showing a top screen 221 displayed on the sub display device 18, and FIG. 5B is a diagram showing a menu screen 222 displayed on the sub display device 18. 5C to 5E are diagrams showing game information screens 223, 224, and 225 displayed on the sub display device 18.

Various display screens are displayed on the sub-display device 18 by a player's touch operation, and as shown in FIGS. 5A to 5E, various display screens including a top screen 221 and a menu screen 222 and a game information screen 223, 224, 225 are included. The display screen is displayed. These display screens are switched based on the player's operation signal received via the touch sensor 19.

The top screen 221 is an initial screen among the display screens displayed on the sub display device 18, and the top screen 221 displays the “MENU” button 221a and the outline game history 221b. The "MENU" button 221a is an operation button for calling the menu screen 222 shown in FIG. 5B, and when a player performs a predetermined operation (for example, tapping) on the "MENU" button 221a, the menu screen 222 is called. Is done. Further, on the top screen 221, a part of the game history (summary game history) of the pachislot machine 1 is displayed as the summary game history 221b. In the present embodiment, for example, the number of bonuses, the number of ARTs, and the number of games (number of games) are displayed as the outline game history 221b.

The menu screen 222 is a screen for displaying a menu that can be displayed on the sub display device 18, and on the menu screen 222, a “back” button 222a, a “registration” button 222b, an “explanation” button 222c, and an “array dividend” button 222d , The "reach eye" button 222e, the "WEB site" button 222f, and the "volume" button 222g are displayed. The "back" button 222a is an operation button for calling the top screen 221. When the player operates the "back" button 222a, the top screen 221 is called. Further, the "register" button 222b to the "volume" button 222g are operation buttons for calling the display screen of the corresponding menu content, and when the player operates each button, the corresponding menu content is displayed. The display screen is called.

For example, when the "register" button 222b is operated by the player on the menu screen 222, a registration screen (not shown) for registering the player during the game is called on the display screen of the sub display device 18. In recent pachislot machines, a service is widely provided in which a player is registered for each model and various information such as the achievement status of a predetermined mission is managed from the past game history of the player. The registration screen called by the "registration" button 222b is a display screen for registering a player when receiving the provision of this service.

Further, for example, when the "explanation" button 222c is operated by the player on the menu screen 222, the explanation screen (not shown) of the pachislot machine 1 is called up on the display screen of the sub display device 18. The information displayed on the explanation screen includes, for example, an explanation about the specifications of the pachislot machine 1 such as a bonus winning probability and an ART winning probability for each set value, and an introduction explanation of a character appearing in the production of the pachislot machine 1.

Further, for example, when the "array payout" button 222d is operated by the player on the menu screen 222, the array payout screen (not shown) of the pachislot machine 1 is called on the display screen of the sub display device 18. On the array payout screen, for example, the correspondence between the combination of symbols judged to be winning in Pachislot 1 and the privilege when it is judged to be winning (dividend table) and drawn on each reel 3L, 3C, 3R. The symbol sequence (reel arrangement) and the like are displayed.

Further, for example, when the "reach eye" button 222e is operated by the player on the menu screen 222, the reach eye screen (not shown) of the pachislot machine 1 is called on the display screen of the sub display device 18. On the reach-eye screen, information on a symbol combination called "reach-eye" set in the pachi-slot machine 1 is displayed. In addition, it is definite that the symbol combination called "reach eye" is given a special privilege (for example, a bonus state or transition to ART) by displaying the symbol combination along the effective line. It is a symbol combination notified to.

Further, for example, when the "WEB site" button 222f is operated by the player on the menu screen 222, the WEB introduction screen (not shown) of the pachislot machine 1 is called on the display screen of the sub display device 18. On the WEB introduction screen, for example, a two-dimensional code (for example, QR code (registered trademark)) indicating the URL of an arbitrary WEB site such as a special WEB site provided for each model of pachislot 1 or a WEB site of a pachislot 1 manufacturer). Is displayed. The player can access the corresponding WEB site by reading the two-dimensional code displayed on the WEB introduction screen with a mobile phone or the like.

Further, for example, when the "volume" button 222g is operated by the player on the menu screen 222, a volume adjustment screen (not shown) capable of adjusting the volume of the sound output from the speakers 65L and 65R is a sub display device. Called to the display screen of 18. The player can adjust the volume of the effect sound of the pachi-slot machine 1 via the volume adjustment screen.

Since the sub-display device 18 is provided separately from the above-mentioned display device 11 (projector mechanism 211 and display unit 212), it can be controlled separately from the display device 11. Therefore, in the pachi-slot machine 1 of the present embodiment, the display screen of the sub-display device 18 can be switched by the operation of the player even during the game (during the execution of the effect by the display device 11). As a result, for example, when the player wants to know the character appearing in the production of the display device 11, the player operates the "explanation" button 222c to call the explanation screen, and the inter-characters. Information such as the relationship between the two can be grasped during the game. Also, for example, when the player wants to grasp the symbol that should be used as a guide for winning the rare role during the reel rotation when the so-called "rare role" is won during the game, the player may ask. The reel arrangement can be grasped by operating the "arrangement payout" button 222d to call the arrangement distribution screen.

The game information screens 223, 224, and 225 are display screens that display detailed game history information including an outline game history to be displayed on the top screen 221 of the game history of the pachislot machine 1.

On the game information screen 223, a "back" button 223a, a "MENU" button 223b, a "previous" button 223c, a "next" button 223d, and a game history 223e are displayed. The "back" button 223a and the "MENU" button 223b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively, and are supported by the player operating each button. The display screen is called. Further, the "previous" button 223c and the "next" button 223d are operation buttons for switching the game information screen in a predetermined order, and when the "previous" button 223c is operated by the player, the display screen is displayed. Is switched from the game information screen 223 to the game information screen 225, and when the "Next" button 223d is operated by the player, the display screen is switched from the game information screen 223 to the game information screen 224. Further, as the game history 223e, as shown in FIG. 5C, the number of games (number of games), the number of bonuses, the number of ARTs, and the number of CZs (chance zones) are displayed.

On the game information screen 224, a "back" button 224a, a "MENU" button 224b, a "previous" button 224c, a "next" button 224d, and a game history 214e are displayed. The "back" button 224a and the "MENU" button 224b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively, and are supported by the player operating each button. The display screen is called. Further, the "previous" button 224c and the "next" button 224d are operation buttons for switching the game information screen in a predetermined order, and when the "previous" button 224c is operated by the player, the display screen is displayed for the game. When the information screen 224 is switched to the game information screen 223 and the "Next" button 224d is operated by the player, the display screen is switched from the game information screen 224 to the game information screen 225. Further, as the game history 224e, as shown in FIG. 5D, the number of rushes and successes of the CZ (chance zone) described later, the number of rushes of the promotion chance described later, the number of rushes of the special zone described later, and the like are displayed. To.

On the game information screen 225, a "back" button 225a, a "MENU" button 225b, a "previous" button 225c, a "next" button 225d, and a game history 225e are displayed. The "back" button 225a and the "MENU" button 225b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively, and are supported by the player operating each button. The display screen is called. Further, the "previous" button 225c and the "next" button 225d are operation buttons for switching the game information screens in a predetermined order, and when the "previous" button 225c is operated by the player, the display screen is displayed. Is switched from the game information screen 225 to the game information screen 224, and when the "Next" button 225d is operated by the player, the display screen is switched from the game information screen 225 to the game information screen 223. Further, as the game history 225e, as shown in FIG. 5E, a specific internal winning combination (for example, “F_black BAR” described later, “F_SP rips A to C” described later, “F_MB” described later, etc.) The number of wins and the probability of winning (a fraction of one numerator) are displayed.

As a display screen switching method displayed on the sub-display device 18, for example, a method of switching based on a tap operation for an operation button displayed on each display screen may be adopted, or, for example, A method of switching based on a swipe operation on the display screen may be adopted.

<Various switching functions of the display screen of the sub display device>
Next, various switching functions of the display screen of the sub-display device 18 in the pachi-slot machine 1 of the present embodiment will be described.

[Example of transition of display screen of sub display device]
First, a transition example (switching mode) of the display screen of the sub-display device 18 in the pachi-slot machine 1 of the present embodiment will be described with reference to FIGS. 6A and 6B. Note that FIG. 6A is a diagram showing a transition example of the display screen of the sub-display device 18 in a situation where the player registration state is not set, and FIG. 6B is a sub-display in a situation where the player registration state is set. It is a figure which shows the transition example of the display screen of the apparatus 18.

In the situation where the player registration state is not set, as shown in FIG. 6A, the display screen of the sub display device 18 transitions between the top screen 221 and the menu screen 222, and from the menu screen 222 and the menu screen 222. Transitions can be made only to and from various possible display screens, and the transition between these display screens is controlled by the sub-control board 72 (sub-CPU 201 described later). For example, the sub-control board 72 is placed between the top screen 221 and the menu screen 222 based on a touch operation (for example, a tap operation for a predetermined button or a swipe operation on the display screen) acquired via the touch sensor 19. Switch the display screen. However, in the situation where the player registration state is not set, the sub-control board 72 controls so that the game information screens 223, 224, and 225 cannot be displayed. That is, in the situation where the player registration state is not set, the player cannot display the game information screens 223, 224, and 225 on the sub display device 18.

On the other hand, in the situation where the player registration state is set, as shown in FIG. 6B, the display screen of the sub display device 18 is between the top screen 221 and the menu screen 222, and the menu screen 222 and the menu screen 222. In addition to the transition between the various display screens that can be transitioned from, the transition between the menu screen 222 and the game information screens 223, 224, 225 is also possible, and the transition between these display screens is the sub-control board 72 (subs described later). It is controlled by CPU201). That is, the sub-control board 72 is not only between the top screen 221 and the menu screen 222, but also between the top screen 221 and the menu screen 222 and the game information screen based on the touch operation acquired via the touch sensor 19. The display screen can also be switched between 223, 224, and 225. Therefore, in the present embodiment, when the player registration state is set, the player can display the game information screens 223, 224, and 225 on the sub display device 18.

As shown in FIG. 6B, the transition order of the display screens between the top screen 221 and the menu screen 222 and the game information screens 223, 224, and 225 is arbitrary. Therefore, for example, the top screen 221 may be configured to directly transition to the game information screens 223, 224, 225, or the top screen 221 to the game information screens 223, 224, 225 only via the menu screen 222. The configuration may be such that transition is possible.

In the pachislot machine 1 of the present embodiment, the top screen 221 can be transitioned to the game information screen 223, 224, 225 only via the menu screen 222 (the top screen 221 cannot be directly transitioned to the game information screen 223, 224, 225). ) Is adopted. In the pachislot machine 1 of the present embodiment, on the menu screen 222, the player swipes the display screen (not the menu selection operation) to display the display screen from the menu screen 222 to the game information screens 223 and 224. , 225 can be transitioned.

In the present embodiment, the game information screens 223, 224, and 225 are display screens provided completely independently of the menu screen 222. That is, in the pachi-slot machine 1 of the present embodiment, the game history, which is information indicating the result of the game in which the player has a strong interest during the game, is independent as information irrelevant to the result of the game such as the payout arrangement and the volume control. To display. Then, in the present embodiment, in the situation where the player registration state is set, the game information screens 223, 224, and 225 can be displayed without the player performing a menu selection operation on the menu screen 222. .. Therefore, in the present embodiment, when the player registration state is set, it is possible to easily access the emotional game history information desired by the player.

Further, in the present embodiment, in the menu selection operation for the menu screen 222, the display screen cannot be changed to the game information screens 223, 224, and 225, and the swipe operation for the menu screen 222 (specified in the menu display). The display screen cannot be changed to the game information screens 223, 224, and 225 unless the operation is not performed. Therefore, in the pachi-slot machine 1 of the present embodiment, the swipe operation for transitioning the display screen to the game information screens 223, 224, 225 can be handled as a hidden command in the situation where the player registration state is set. In this case, from the player's own knowledge of pachislot 1, more detailed game history information that cannot be seen by other players with little knowledge can be seen, so that the player can see more detailed game history information than the other players. It is possible to play the game advantageously, and as a result, it can be expected that the player actively plays the game.

[Display switching function from the game information screen to the top screen]
The pachi-slot machine 1 of the present embodiment has a function of shifting the display screen of the sub-display device 18 from the game information screens 223, 224, 225 to the top screen 221 manually or automatically by the player. Specifically, in the present embodiment, when the "back" button is operated on the game information screens 223, 224, 225, the display screen transitions from the game information screen 223, 224, 225 to the top screen 221 (manual transition). function). Further, in the present embodiment, when a predetermined condition is satisfied while the game information screens 223, 224, and 225 are displayed, the display screen is automatically changed to the top screen 221 regardless of the operation of the player. Transition (automatic transition function).

More specifically, in the pachislot machine 1, when the game information screens 223, 224, and 225 are displayed, the insertion operation (operation to the MAX bet button 15a, operation to the 1 bet button 15b, and the medal insertion slot 14 is performed. When the operation of inserting medals) is performed, the display screen of the sub display device 18 automatically transitions to the top screen 221. In a gaming state (high lip state) in which the probability that the replay combination is determined as the internal winning combination is high, such as in the ART gaming state, medals are automatically inserted due to the operation of the replay accompanying the replay combination winning. As a result, in the high lip state, the opportunity to display the game information screens 223, 224, and 225 may be limited. Therefore, in the pachislot machine 1 of the present embodiment, when a medal is automatically inserted by the operation of the re-game, the display screen is automatically displayed on the game information screen 223, not by the operation of inserting the medal but by the start operation. , 224, 225 transitions to the top screen 221.

That is, in the present embodiment, when the re-game is activated and the game information screens 223, 224, 225 are displayed, the display screen is automatically changed to the game information screens 223, 224, triggered by the start operation. , 225 transitions to the top screen 221. On the other hand, when the re-game operation is not performed, the display screen automatically transitions from the game information screen 223, 224, 225 to the top screen 221 triggered by the input operation.

[Display switching function from the menu content display screen to the top screen (or menu screen)]
In the pachi-slot machine 1 of the present embodiment, the display screen of the sub-display device 18 can be changed by a menu selection operation on the menu screen 222, and various menu content display screens (registration screen, explanation screen, array dividend screen, reach screen, WEB introduction). It has a function of manually or automatically transitioning from the screen (screen and volume adjustment screen) to the top screen 221 (or menu screen 222). Specifically, in the present embodiment, when a predetermined button (for example, the "return to TOP" button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the top screen 221 ( Manual transition function). Further, in the present embodiment, when a specific button (for example, a "back" button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the menu screen 222 (manual transition). function).

Further, in the present embodiment, when a predetermined time elapses while the menu content display screen is displayed, the display screen automatically changes to the top screen 221 (or menu screen 222) regardless of the operation of the player. Transition (automatic transition function). At this time, the predetermined time that triggers the automatic transition to the top screen 221 (or the menu screen 222) differs depending on the type of the menu content display screen currently displayed. For example, if the volume adjustment screen for adjusting the volume output from the pachislot machine 1 is displayed for a long time, not only the volume may be adjusted to an unintended volume due to an erroneous operation, but also another player may be affected by the erroneous operation. It may be uncomfortable. Therefore, the volume adjustment screen is set to automatically transition to the top screen 221 (or menu screen 222) in a shorter time than other menu content display screens. On the other hand, the registration screen is set to automatically transition to the top screen 221 (or menu screen 222) in a longer time than other menu content display screens in order to facilitate registration of players. ..

That is, on each menu content display screen, an elapsed time (automatic transition time) that triggers an automatic transition to the top screen 221 (or menu screen 222) is appropriately set according to the type of the menu content display screen. , The volume adjustment screen is set to an automatic transition time shorter than that of other menu content display screens, and the registration screen is set to an automatic transition time longer than that of other menu content display screens.

[Menu operation enable / disable selection function]
In the pachi-slot machine 1 of the present embodiment, the display screen of the sub-display device 18 is changed from the menu screen 222 to the registration screen, the explanation screen, the arrangement payout screen, the reach eye screen, the WEB introduction screen, and the volume adjustment screen. A person can perform various operations according to these menu content display screens, and can confirm various information. It should be noted that a function (a function for selecting whether or not the menu can be operated) may be provided so that the function that the player can select the menu can be restricted according to the setting on the game store side.

For example, the display screen may not be transitioned from the menu screen 222 to the volume control screen (for example, the "volume" button 222g may not be displayed on the menu screen 222) by the setting on the game store side. In this case, the volume control by the player can be disabled.

<Control system of pachislot>
Next, the control system included in the pachi-slot machine 1 will be described with reference to FIG. 7. FIG. 7 is a circuit block diagram showing the configuration of the control system of the pachislot machine 1.

The pachi-slot machine 1 has a main control board 71 provided on the middle door 41 and a sub control board 72 provided on the front door 2b. Further, the pachi-slot machine 1 has a reel relay terminal board 74, a setting key type switch 54 (setting switch), and a cabinet-side relay board 44 connected to the main control board 71. Further, the pachi-slot machine 1 has an external centralized terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76, and a power supply device 53 connected to the main control board 71 via a cabinet-side relay board 44. Since the configuration of the hopper device 51 has been described above, the description thereof will be omitted here.

The reel relay terminal plate 74 is arranged inside the reel main body of each reel 3L, 3C, 3R. The reel relay terminal plate 74 is electrically connected to a stepping motor (not shown) of each reel 3L, 3C, 3R, and relays a signal output from the main control board 71 to the stepping motor.

The setting key type switch 54 is provided in the main control board case 55. The setting key type switch 54 is used when changing the setting of the pachi-slot 1 (settings 1 to 6) or when confirming the setting of the pachi-slot 1.

The cabinet-side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external centralized terminal board 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. Is. The external centralized terminal plate 47 is provided to output signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52, and detects whether or not the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachislot machine 1.

The power supply device 53 includes a power supply board 53b and a power supply switch 53a connected to the power supply board 53b. The power switch 53a is pressed when supplying the necessary power to the pachi-slot machine 1. The power supply board 53b is connected to the main control board 71 via the cabinet side relay board 44, and is also connected to the sub control board 72 via the sub relay board 61.

Further, the pachi-slot machine 1 has a selector 66, a door open / close monitoring switch 67, a BET switch 77, a checkout switch 78, which are connected to the main control board 71 via the door relay terminal plate 68 and the door relay terminal plate 68. It has a start switch 79, a stop switch board 80, a game operation display board 81, an auxiliary relay board 61, a first interface board 301 for a testing machine, and a second interface board 302 for a testing machine. Since the selector 66, the door open / close monitoring switch 67, and the sub-relay board 61 have been described above, their description will be omitted here.

The BET switch 77 (throwing operation detecting means) detects that the MAX bet button 15a or the 1-bet button 15b is pressed by the player. The settlement switch 78 detects that the settlement button (not shown) has been pressed by the player. The start switch 79 (start operation detecting means) detects that the start lever 16 has been operated by the player (start operation).

The stop switch board 80 (stop operation detecting means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stoptable main reel by an LED or the like. Further, the stop switch board 80 is provided with a stop switch (not shown). The stop switch detects that each of the stop buttons 17L, 17C, 17R is pressed by the player (stop operation).

The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. The LED 82 has, for example, three LEDs (hereinafter, "first LED" to "1st LED") for displaying the number of medals inserted, which are lit according to the number of medals inserted in this game (hereinafter referred to as "the number of inserted medals"). An LED that lights a mark indicating that medals can be inserted, a mark indicating the start of a game, a mark for replaying a game, etc., based on a signal input from the game operation display board 81 (referred to as "third LED"). Etc. are included. In the first LED to the third LED (display means), when one medal is inserted, the first LED lights up, and when two medals are inserted, the first and second LEDs light up, and three medals (game). When the number of startable medals is turned on, the first LED to the third LED are turned on. Since the information display 6 has been described above, the description thereof will be omitted here.

Both the first interface board 301 for the testing machine and the second interface board 302 for the testing machine are relay boards used when outputting various signals related to the game to the testing machine in the certification test (test firing test) of the pachislot 1. Since these relay boards are not mounted on the Pachislot 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for the testing machine and the testing machine. Various electronic components required for connecting to the second interface board 302 for use are also not mounted). For example, a test signal for controlling a main operation related to a game (for example, internal lottery, reel stop control, etc.) is output via a first interface board 301 for a testing machine, and is determined by, for example, a main control board 71. The test signal and the like related to the pushed order navigation are output via the second interface board 302 for the testing machine.

The sub-control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub-relay board 61. Further, the pachi-slot machine 1 has a speaker group 84, an LED group 85, a 24h door open / close monitoring unit 63, a touch sensor 19 and a display unit 212 connected to the sub-control board 72 via the sub-relay board 61. Since the touch sensor 19 has been described above, the description thereof will be omitted here.

The speaker group 84 includes speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10, a light source that emits light for illuminating the decorative panel of the lumbar panel 12 from the back side, and the like. The 24h door open / close monitoring unit 63 stores the open / close history information of the middle door 41. Further, the 24h door open / close monitoring unit 63 outputs a signal for displaying an error by the display device 11 to the sub control board 72 (sub control circuit 200) when the middle door 41 is opened. The display unit 212 includes, for example, a projected member 212a constituting the display device 11 and another projected member having a curved display surface provided on the back side of the projected member 212a.

Further, the pachi-slot machine 1 has a ROM cartridge board 86 and a liquid crystal relay board 87 connected to the sub-control board 72. The ROM cartridge board 86 and the liquid crystal relay board 87 are housed in the sub-control board case 57 together with the sub-control board 72.

The ROM cartridge board 86 is a board for managing various control programs executed by the sub CPU 102, image (video) for production, audio (speaker group 84), light (LED group 85), and communication data. .. The liquid crystal relay board 87 is a board that relays the connection wiring between the sub-control board 72, the projector mechanism 211 constituting the display device 11, and the sub-display device 18. Since the projector mechanism 211 and the sub-display device 18 have been described above, their description will be omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. FIG. 8 is a block diagram showing a configuration example of the main control circuit 90 of the pachislot machine 1.

The main control circuit 90 includes a microprocessor 91, a clock pulse generation circuit 92, a power management circuit 93, and a switching regulator 94 (power supply means).

The microprocessor 91 is a microprocessor with a security function for a game machine. In the microprocessor 91 of the present embodiment, as will be described later, various instruction codes specific to the microprocessor 91 that can be specified in the source program (for example, "LDQ" instruction and the like described later: hereinafter, "main CPU 101". Dedicated instruction code ") is provided. In the present embodiment, the processing efficiency is improved and the program capacity is reduced by using the instruction code dedicated to the main CPU 101. The internal configuration of the microprocessor 91 will be described in detail with reference to FIG. 9 described later, and the instruction code dedicated to the main CPU 101 provided in the microprocessor 91 will be described in detail in various processes executed by the main control circuit described later. To do.

The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes a control program based on the input clock pulse signal.

The power management circuit 93 manages fluctuations in the DC 12V power supply voltage supplied from the power supply board 53b (see FIG. 7). Then, the power management circuit 93 outputs a reset signal to the "XSRST" terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the starting voltage value (10V) from 0V). When a power failure occurs (when the power supply voltage falls below the power failure voltage value (10.5V) from 12V), the power failure detection signal is output to the "XINT" terminal of the microprocessor 91. That is, the power management circuit 93 is a means (starting means) for outputting a reset signal (starting signal) to the microprocessor 91 when the power is turned on, and a power failure detection signal (power failure signal) to the microprocessor 91 when a power failure occurs. Also serves as a means for outputting (power failure means).

The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (power supply voltage of DC 5 V) of the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

<Microprocessor>
Next, the internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 9 is a block diagram showing an internal configuration of the microprocessor 91.

The microprocessor 91 includes a main CPU 101, a main ROM 102 (first storage means), a main RAM 103 (second storage means), an external bus interface 104, a clock circuit 105, a reset controller 105, an arithmetic circuit 107, and the like. It has a random number circuit 110, a parallel port 111, an interrupt controller 112, a timer circuit 113, a first serial communication circuit 114, and a second serial communication circuit 115. Each of these parts constituting the microprocessor 91 is connected to each other via a signal bus 116.

The main CPU 101 executes various control programs based on the clock pulse generated by the clock circuit 105 to control the game operation in general. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

The main CPU 101 counts the number of times a pulse is output to the stepping motors of each reel 3L, 3C, 3L (main reel) after detecting the reel index. As a result, the main CPU 101 manages the rotation angle of each reel (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has made one revolution. This reel index is, for example, an optical sensor having a light emitting portion and a light receiving portion, and a detection piece provided at a predetermined position on each reel and interposed between the light emitting portion and the light receiving portion due to rotation of each main reel. It is detected by the provided reel position detection unit (not shown).

Here, the management of the rotation angle of each reel 3L, 3C, 3L (main reel) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Then, each time the output of a predetermined number of pulses required for the rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 103 is added one by one. The symbol counter is provided according to each reel. The value of the symbol counter is cleared when the reel index is detected by the reel position detection unit (not shown).

That is, in the present embodiment, by managing the symbol counter, it is possible to manage how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control commands (commands) to the sub-control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as internal winning combinations determined by executing the control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail with reference to FIG. 12 described later.

The external bus interface 104 is for electrically connecting the microprocessor 104 to an external signal bus (not shown) to which various components (for example, reels and the like) provided outside the microprocessor 91 are connected. It is an interface circuit. The clock circuit 105 is configured to include, for example, a frequency divider (not shown), and a clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is transmitted by another component (for example, a timer circuit 113). Convert to a clock pulse signal of the frequency used. The clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

The reset controller 106 resets the IAT (Illegal Address Trap) and the WDT (watchdog timer) based on the reset signal input from the power supply management circuit 93. The arithmetic circuit 107 is configured to include a multiplication circuit and a division circuit. For example, when the "MUL" instruction described later (see FIG. 93B described later) is executed on the source program, the arithmetic circuit 107 executes the multiplication process based on the "MUL" instruction.

The random number circuit 110 generates random numbers in a predetermined range (for example, 0 to 65535 or 0 to 255). Although not shown, the random number circuit 110 uses random number registers 0 for obtaining 2-byte hard-latch random numbers, random number registers 1 to 3 for obtaining 2-byte soft-latch random numbers, and 1-byte soft-latch random numbers. It is composed of random number registers 4 to 7 for obtaining. The main CPU 101 extracts one value from the random numbers in a predetermined range generated by the random number circuit 110, for example, as a random number value for internal lottery. The parallel port 111 is a signal port (memory map I / O) input / output between the microprocessor 91 and various circuits (for example, power management circuit 93, etc.) provided outside the microprocessor 91. .. The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is connected to any of the input ports of PI0 to PI4 of the parallel port 111, and at the timing (on-edge) when the start switch 79 is turned on, a latch signal is sent from the parallel port 111 to the random number register 0 of the random number circuit 110. Is output. Then, in the random number circuit 110, the random number register 0 is latched by the input of the latch signal, and a 2-byte hard latch random number is acquired.

The interrupt controller 112 interrupts processing by the main CPU 101 based on a power failure detection signal input from the power management circuit 93 via the parallel port 111 or a timeout signal input from the timer circuit 113 at a cycle of 1.1172 ms. Controls the execution timing of. When a power failure detection signal is input from the power management circuit 93, or when a timeout signal is input from the timer circuit 113, the interrupt controller 112 sends an interrupt request signal indicating an interrupt processing start command to the main CPU 101. Output to. The main CPU 101 has an input port check process, a reel control process, a communication data transmission process, a 7-segment LED drive process, and a timer based on an interrupt request signal input from the interrupt controller 112 in response to a timeout signal from the timer circuit 103. Various interrupt processing such as update processing (see FIG. 100 described later) is performed.

The timer circuit 113 (PTC) operates with a clock pulse signal generated by the clock circuit 105 (a clock pulse signal having a frequency obtained by dividing the clock pulse signal for operating the main CPU by a divider (not shown)) ( Count the elapsed time). Then, the timer circuit 113 outputs a timeout signal (trigger signal) to the interrupt controller 112 at a cycle of 1.1172 msec.

The first serial communication circuit 114 is a circuit that controls a serial transmission operation when data (various control commands (commands)) are transmitted from the main control board 71 to the sub control board 72. The second serial communication circuit 115 is a circuit that controls the serial transmission operation when data is transmitted from the main control board 71 to the second interface board 302 for the testing machine.

<Sub-control circuit>
Next, the configuration of the sub-control circuit 200 (sub-control means) mounted on the sub-control board 72 will be described with reference to FIG. FIG. 10 is a block diagram showing a configuration example of the sub-control circuit 200 of the pachi-slot machine 1.

The sub control circuit 200 is electrically connected to the main control circuit 90, and performs processing such as determination and execution of the effect content based on a command transmitted from the main control circuit 90. The sub control circuit 200 basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

The sub CPU 201 is connected to the ROM cartridge board 86. The driver 205 is connected to the liquid crystal relay board 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub display device 18 via the liquid crystal relay board 87.

The sub CPU 201 controls the output of video, sound, and light according to the control program stored in the ROM cartridge board 86 in response to the command transmitted from the main control circuit 90. The ROM cartridge board 86 is basically composed of a program storage area and a data storage area.

The control program executed by the sub CPU 201 is stored in the program storage area. For example, in the control program, the main board communication task for controlling the communication with the main control circuit 90 and the effect registration for extracting the random value for the effect and determining and registering the effect content (effect data). Includes various programs for executing tasks. Further, the control program includes an animation task that controls the display of an image by the display device 11 based on the determined effect content, a lamp control task that controls the output of light by a light source such as the LED group 85, and a sound by the speaker group 84. It also includes various programs for executing sound control tasks that control the output.

The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to video creation. The data storage area also includes a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to a pattern of turning on and off light, and the like.

The sub RAM 202 is provided with a storage area for registering the determined effect content and effect data, and a storage area for storing various data such as internal winning combinations and navigation data transmitted from the main control circuit 90.

The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create an image according to the animation data specified by the effect content, and display the created image on the display device 11 (projector mechanism 211) and /. Alternatively, it is displayed on the sub display device 18. The display device 11 (projector mechanism 211) and the sub-display device 18 are individually controlled by the sub-control board 72.

Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM according to the sound data specified by the effect content. Further, the sub CPU 201 controls the lighting and extinguishing of the LED group 85 according to the lamp data specified by the effect content.

<Various registers of the main CPU>
Next, various registers included in the main CPU 101 will be described with reference to FIG. Note that FIG. 11 is a schematic configuration diagram of various registers included in the main CPU 101.

As the main register, the main CPU 101 includes an accumulator A (hereinafter referred to as "A register"), a flag register F (flag register), a general-purpose register B (hereinafter referred to as "B register"), and a general-purpose register C (hereinafter referred to as "B register"). General-purpose register D (hereinafter referred to as "D register"), general-purpose register E (hereinafter referred to as "E register"), general-purpose register H (hereinafter referred to as "H register"), and general-purpose register L (hereinafter referred to as "H register"). , "L register"). Further, the main CPU 101 has, as sub-registers, an accumulator A', a flag register F', a general-purpose register B', a general-purpose register C', a general-purpose register D', a general-purpose register E', a general-purpose register H', and a general-purpose register L'. As a general-purpose register. Each register is composed of 1-byte registers.

Further, in the present embodiment, the B register and the C register are used as a pair register (hereinafter referred to as "BC register"), and the D register and the E register are used as a pair register (hereinafter referred to as "DE register"). Further, in the present embodiment, the H register and the L register are used as a pair register (hereinafter, referred to as "HL register").

As shown in FIG. 11, predetermined flag information indicating the result of arithmetic processing and the like is set in each bit of the flag registers F and F'. For example, bit 6 (D6) is set with data (zero flag) indicating whether or not the calculation result is "0" in the calculation result determination process. Specifically, when the calculation result is "0", the data "1" is set in the bit 6, and when the calculation result is not "0", the data "0" is set in the bit 6. Then, in the calculation result determination process, the main CPU 101 makes a determination (YES / NO) with reference to the bit 6 data “0” / “1”.

Further, the main CPU 101 has an expansion register Q (hereinafter, referred to as “Q register”). The Q register is composed of a 1-byte register. In this embodiment, as will be described in various processing flows described later, various main CPU 101 dedicated instruction codes for specifying an address using this Q register are provided on the source program, and this instruction code is provided. By using the above, processing efficiency is improved and the capacity of the main ROM 102 is reduced. In various main CPU 101 dedicated instruction codes that specify an address using the Q register, the address data (address value) on the upper side of the address is stored in the Q register. Immediately after the reset of the main CPU 101, "F0H" is set in the Q register as an initial value. Further, in the "LD Q, n (8-bit data)" instruction using the Q register, the value of the Q register is changed by setting arbitrary 1-byte data in "n" and executing the instruction. be able to.

Further, the main CPU 101 includes an interrupt page address register I and a memory refresh register R composed of 1-byte registers, and an index register IX and an index register IY composed of 2-byte registers. , The stack pointer SP and the program counter PC are provided as dedicated registers.

<Internal configuration of main ROM and main RAM (memory map)>
Next, the internal configurations (hereinafter referred to as “memory maps”) of the main ROM 102 and the main RAM 103 included in the main control circuit 90 (microprocessor 91) will be described with reference to FIGS. 12A to 12C. Note that FIG. 12A is a diagram showing a memory map of the entire memory, FIG. 12B is a diagram showing a memory map of the main ROM 102, and FIG. 12C is a diagram showing a memory map of the main RAM 103.

In the memory map of the entire memory included in the main control circuit 90 (microprocessor 91), as shown in FIG. 12A, from the head (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the built-in register area, and The XCS decoding areas are arranged at predetermined addresses in this order with an unused area in between.

In the memory map of the main ROM 102, as shown in FIG. 12B, the program area, the data area, the non-standard area, the trademark recording area, the program management area, and the security setting area are displayed from the head (0000H) side of the address of the main ROM 102. They are placed at predetermined addresses in order.

In the program area, control programs for various processes executed by the main CPU 101 in various control processes related to the playability of the game performed by the player are stored. In the data area, various data used by the main CPU 101 in various control processes related to the playability of the game performed by the player (for example, various data tables such as an internal lottery table and various sub-control circuits 200). Data for transmitting control commands (commands), etc.) are stored. That is, the game ROM area (game storage area) composed of the program area and the data area is necessary for the control process (process related to the game property) related to the game playability of the game actually performed by the player at the game store. Various programs and various data are stored.

Further, in the non-standard area, control programs and data of various processes (processes that do not affect the playability) that are not directly related to the playability of the game performed by the player are stored. For example, programs and data used in the pachislot 1 certification test (test firing test), control programs and data used in checksum generation processing at the time of power failure and thumb check processing at power recovery, and fraud countermeasure programs. And the data required for it are stored in the non-standard area.

In the memory map of the main RAM 103, as shown in FIG. 12C, the game RAM area (predetermined storage area, game temporary storage area) and the non-standard RAM area (non-standard temporary) from the head (F000H) side of the address of the main RAM 103. Storage areas) are arranged at predetermined addresses in this order.

The game RAM area is provided with a work area and a stack area for temporarily storing various data such as internal winning combinations determined by executing a control program related to the game playability performed by the player. .. Then, each of the various data is stored in the work area of a predetermined address in the game RAM area.

Further, the non-standard RAM area is provided with a non-standard work area that is a work area for various processes that are not directly related to the playability of the game performed by the player, and a non-standard stack. In the present embodiment, using this non-standard RAM area, various processes that are not directly related to the playability of the game performed by the player, such as a checksum process, are executed.

As described above, in the pachislot machine 1 of the present embodiment, various programs and various data (tables) used for various processes not directly related to the playability of the game performed by the player are used for the game in the main ROM 102. It is stored in a non-standard ROM area (non-standard storage area) located at an address different from the ROM area. In addition, various processes that are not directly related to the playability of the game performed by such a player are performed in the main RAM 103 using an out-of-specification RAM area arranged at an address different from the game RAM area. ..

In such a configuration of the main ROM 102, programs and data unnecessary for the game itself actually played by the player are arranged in the ROM area (non-standard ROM area) where the program or the like cannot be arranged according to the conventional rules. can do. Therefore, in the present embodiment, it is possible to avoid pressure on the capacity of the gaming ROM area.

<Transition flow of game state>
Next, various gaming states managed by the main control circuit 90 (main CPU 101) of the pachislot machine 1 of the present embodiment and their transition flows will be described with reference to FIGS. 13 and 14. Note that FIG. 13 is a transition flow diagram of the basic gaming state of the pachislot machine 1. Further, FIG. 14A is a transition flow diagram of a gaming state in consideration of whether or not the notification (ART) function is activated, and FIG. 14B is a table summarizing the transition conditions of the gaming state.

[Basic game state transition flow]
In the pachislot machine 1 of the present embodiment, a big bonus (hereinafter referred to as "BB") and a middle bonus (hereinafter referred to as "MB") are provided as types of bonus games. BB is a character continuous operation device related to a type 1 special character that continuously operates a regular bonus (hereinafter referred to as "RB") called a type 1 special character, and MB is a type 2 special character. It is a bonus continuous operation device related to the second type special bonus that continuously operates a challenge bonus (hereinafter referred to as "CB") called a special bonus.

In the pachislot machine 1 of the present embodiment, the basic game state can be roughly divided into a bonus state and a non-bonus state. The bonus state is a state in which the above-mentioned BB is operating (BB gaming state, hereinafter also referred to as "BB operating"), or a state in which the MB is operating (MB gaming state, hereinafter, "MB operating"). Also referred to as), the non-bonus state means a state in which BB and MB are not operating (general game state, hereinafter also referred to as "normal"). If the BB is won in the non-bonus state, the winning of the BB is carried over until the BB is activated (winning), and the state in which the BB is carried over is the bonus winning state (in this embodiment, in the present embodiment). The RT4 state described later is also referred to as "between flags"). That is, the non-bonus state is further divided into a bonus winning state in which the BB is won (carried over) and a bonus non-winning state in which the BB is not won (carried over). Can be distinguished.

In the BB game state (more specifically, the RB game state in which the player is continuously operating), the winning probability of a predetermined small winning combination (for example, "F_common bell" described later) is higher than that in the non-bonus state. It is a state (see FIGS. 16 and 17 described later), which is an advantageous gaming state for the player who can increase the number of medals.

Further, the MB game state (more specifically, the CB game state in which the game is continuously operated) is the maximum for a specific reel (reel 3R in the present embodiment) when the stop operation is performed by the player. The number of sliding pieces is reduced from 4 symbols (1st symbol number) to 1 symbol (2nd symbol number), and all the small winning combinations (specifically, the number of internal winning combinations) that can be determined are reduced. , NML01-23), which will be described later, is a gaming state in which the internal winning combination is determined (see FIGS. 18 and 64, which will be described later), and is an advantageous gaming state for the player who can increase the number of medals. Even in the MB game state, for the replay combination, the winning probability of the RT state in the non-bonus state (see FIGS. 16 and 17 described later) is taken over and the internal lottery process is performed.

In addition, the non-bonus state is composed of a plurality of RT states in which a part or all of the winning probabilities of a plurality of types of replay combinations can be changed. In the present embodiment, the RT states include an RT0 state (RT0 gaming state, hereinafter simply referred to as "RT0"), an RT1 state (RT1 gaming state, hereinafter simply referred to as "RT1"), and an RT2 state (RT2 gaming state, Hereinafter, it is composed of an RT3 state (hereinafter, also simply referred to as “RT2”), an RT3 state (RT3 gaming state, hereinafter, also simply referred to as “RT3”), and an RT4 state (RT4 gaming state, hereinafter, also simply referred to as “RT4”).

As shown in FIG. 13, in the pachislot machine 1 of the present embodiment, when the set value is changed (see FIG. 40 described later) (setting change), the RT state is shifted to the RT0 state (RT0). In that sense, the RT0 state (RT0) can be said to be the initial gaming state. Also, when the BB game state ends, the RT state is shifted to the RT0 state (RT0).

Further, in the RT0 state (RT0), when the "bell spilled eye" is displayed on the effective line, the RT state is shifted to the RT1 state (RT1). The "bell spilled eye" indicates a combination of symbols of "S_RT1 transition A", "S_RT1 transition B", and "S_RT1 transition C" described later (see FIG. 18 described later).

Further, in the RT1 state (RT1), when the "RT2 transition lip" is displayed on the effective line, the RT state is shifted to the RT2 state (RT2). The "RT2 transition lip" indicates a combination of symbols of the "C_RT2 lip" described later (see FIG. 18 described later). Further, in the RT1 state (RT1), when the "RT3 transition lip" is displayed on the effective line, the RT state is shifted to the RT3 state (RT3). The "RT3 transition lip" indicates a combination of symbols of "S_RT3 lip", "C_SP_CL lip", "C_SP_XU lip" and "C_SP_XD lip" described later (see FIG. 18 described later).

Further, in the RT2 state (RT2), when the above-mentioned "RT3 transition lip" is displayed on the effective line, the RT state is shifted to the RT3 state (RT3). Further, in the RT2 state (RT2) and the RT3 state (RT3), when the above-mentioned "bell spilled eye" or "RT1 transition lip" is displayed on the effective line, the RT state is shifted to the RT1 state (RT1). The "RT1 transition lip" indicates a combination of symbols of "S_RT1 lip A" and "S_RT1 lip B" described later (see FIG. 18 described later).

Further, when BB is determined as an internal winning combination in the RT0 state (RT0), RT1 state (RT1), RT2 state (RT2), and RT3 state (RT3) (condition device operation related to "BB"), RT The state is shifted to the RT4 state (RT4). This RT4 state (RT4) is the above-mentioned bonus winning state (inside the BB), and is maintained until the BB is activated (winning).

Further, in the RT4 state (RT4), when the BB operates (wins), that is, the combination of the symbols of "C_BB" (see FIG. 18 described later) is displayed on the valid line (display of the symbol combination of "BB"). , The gaming state is shifted to the BB gaming state, and in this BB gaming state (BB operating), the RB gaming state (RB operating) until a predetermined end condition is satisfied (there is a payout of more than 144 cards). ), And when the predetermined end condition is satisfied, the BB game state and the RB game state are ended, and as described above, the state shifts to the RT0 state (RT0) among the non-bonus states.

Further, when the MB is determined as the internal winning combination in the RT0 state (RT0), the RT1 state (RT1), the RT2 state (RT2), and the RT3 state (RT3) (condition device operation related to "MB"), RT The state does not change, and the winning of the MB is carried over until the MB is activated (winning). However, in the pachislot machine 1 of the present embodiment, the symbol arrangement (see FIG. 15 described later) and the combination of symbols (see FIG. 18 described later) are specified so that the MB always operates (wins) in the winning game. Therefore, the gaming state as a bonus winning state is not specified.

In the RT0 state (RT0), RT1 state (RT1), RT2 state (RT2), and RT3 state (RT3), the MB operates (wins), that is, the combination of the symbols of "C_MB" (see FIG. 18 described later). Is displayed on the valid line (“MB” symbol combination display), the game state is shifted to the MB game state, and in this MB game state (MB is in operation), a predetermined end condition is satisfied. It is controlled to the CB game state (CB is operating) until (there are more than 13 payouts), and when the predetermined end condition is satisfied, the MB game state and the CB game state are ended, and the non-bonus state is also included. It shifts to the RT state with.

The presence or absence of winning of the bonus combination is managed based on the data stored in the hit request flag storage area (see FIG. 22 described later) and the carry-over combination storage area (see FIG. 23 described later) provided in the main RAM 103. Will be done. Further, each of the above-mentioned game states is managed based on the data stored in the game state flag storage area (see FIG. 24 described later) provided in the main RAM 103.

[Transition flow of game state considering whether or not the notification (ART) function is activated]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not a function (ART function) for notifying a stop operation advantageous to the player is activated. Therefore, in the present embodiment, the activated / non-activated state of the ART function is also managed as a gaming state. In addition, in FIG. 14, in order to distinguish from each of the gaming states described in FIG. 13, the gaming state related to the activated / non-activated state of the ART function will be described as the “directed gaming state”.

In the pachislot machine 1 of the present embodiment, the basic production game state can be roughly divided into an ART game state (ART) and a non-ART game state (non-ART). The ART gaming state refers to a state in which the ART function is operating (that is, a directing gaming state for notifying information on a stop operation advantageous to the player, which is advantageous to the player), and is referred to as a non-ART gaming state. Refers to a state in which the ART function is not operating (that is, a production game state in which information on a stop operation advantageous to the player is not notified, and a disadvantageous state disadvantageous to the player).

Further, as shown in FIG. 14A, the non-ART gaming state is composed of the production gaming states of "normal time", "BB medium history specialization zone", and "chance zone (CZ)", and the ART gaming state is It consists of the production states of "Normal ART", "Continuous Challenge", "BB Medium CP Specialized Zone", and "Double Specialized Zone". In addition, as another effect game state, there is a "promotion chance" which is an effect game state for determining (adding) the number of continuous games (the number of ART games) in the ART game state. However, as will be described later, the "promotion chance" is substantially included in the ART gaming state because it is a directed gaming state in which the transition to the ART gaming state has already been determined.

("Normal time")
The production game state "normal time" (normal game state) is the most disadvantageous game state for the player, and the player usually starts the game from this "normal time". In the "normal time", the ART lottery is performed based on the normal mode and the internal winning combination, and by winning the ART lottery, the directed game state shifts to the ART game state (ART winning). Details of the normal mode and the ART lottery will be described later with reference to FIGS. 28 to 30 described later. In addition, in the "normal time", when the ART lottery is won, a promotion lottery for whether or not to shift to the promotion chance is further performed, and by winning this promotion lottery, prior to the transition to the ART gaming state. , The production game state shifts to "promotion chance" (part of ART winning).

Further, in the "normal time", when the BB operates (wins), that is, when the combination of the symbols of "C_BB" (see FIG. 18 described later) is displayed on the effective line, the BB game state is the effect game state. It becomes "BB middle history specialization zone" (BB prize).

Further, in the "normal time", the CZ lottery is performed based on the CZ mode and the internal winning combination, and by winning the CZ lottery, the production game state shifts to the "chance zone" (CZ winning). In the CZ mode, as in the normal mode, the transition lottery is performed based on the current CZ mode and the internal winning combination. For example, as the CZ mode, "normal", "high accuracy", and "ultra-high accuracy" are performed. A CZ mode such as "" can be provided. If the CZ mode is "normal", the winning probability of the CZ lottery is relatively low (or the CZ lottery is not won), and if the CZ mode is "high accuracy", the winning probability of the CZ lottery is relatively low. If it is relatively high and the CZ mode is "ultra-high accuracy", it can be configured so that the winning probability of the CZ lottery is the highest.

("BB medium history specialization zone")
The directed game state "BB medium history specialization zone" is a game state that is more advantageous to the player than the "normal time" in that it is a BB game state, but is not an ART game state (or an ART game state). It is a disadvantageous game state for the player in that he has not acquired the right to move to. As described above, the transition to the "BB medium history specialization zone" is made when the BB is activated (winning) in the "normal time".

In the "BB medium history specialization zone", ART lottery is performed based on the winning history (or winning history) of the internal winning combination for a predetermined number of games (for example, 5 games). By winning the ART lottery, the directed game state shifts to the ART game state after the end of the "BB medium history specialization zone" (that is, after the end of the BB game state) (ART win). In addition, in the "BB medium history specialization zone", if the ART lottery is won, a promotion lottery for whether or not to shift to the promotion chance is further performed, and by winning this promotion lottery, the ART game state is entered. Prior to the transition, the production game state shifts to the "promotion chance" (a part of the ART winning).

To show an example of ART lottery based on the winning history of the internal winning combination, in the "BB medium history specialized zone", when the "F_common bell" (see FIG. 17 described later) is won, the first history Is stored, and when the following "F_BB medium chance combination A", "F_BB medium chance combination B", and "F_BB medium chance combination C" (see FIG. 17 described later) are won, the second history is stored. To. Then, when the stored second history satisfies a specific condition (for example, when the number is 3 or more in the winning history for 5 games), the ART lottery is performed. It should be noted that a plurality of these specific conditions can be set, and the degree of expectation for winning the ART lottery can be made different. In addition, depending on this specific condition, the winning probability of the promotion lottery as to whether or not to shift to the promotion chance can be made different.

In addition, in the "BB medium history specialization zone", if the BB game state ends before winning the ART lottery, the effect game state shifts to the "normal time".

("Chance Zone" (CZ))
The directed gaming state "chance zone" is a gaming state that is more advantageous to the player than the "normal time" in that the degree of expectation for the transition to the ART gaming state is high, but it is not an ART gaming state (or ART). It is a disadvantageous gaming state for the player in that it does not have the right to shift to the gaming state). As described above, the "chance zone" shifts to the case where the CZ lottery is won in the "normal time".

The "chance zone" is designed to continue for a predetermined number of games (for example, 5 games) from the start, and during that time, there is a higher probability than the "normal time" (see FIG. 29 described later), and the internal winning is achieved. ART lottery is performed based on the role. For example, in the "chance zone", ART is won with a probability of about 1/8 on average for each game. Then, by winning the ART lottery, the directed game state shifts to the ART game state (ART winning). In addition, in the "chance zone", when the ART lottery is won, a promotion lottery for whether or not to shift to the promotion chance is further performed, and by winning this promotion lottery, prior to the transition to the ART gaming state. , The production game state shifts to "promotion chance" (part of ART winning).

Here, when the ART lottery is won in the "chance zone", the probability of winning the promotion lottery as to whether or not to shift to the promotion chance is higher than when the ART lottery is won in other non-ART gaming states. It is supposed to be. Therefore, in that sense as well, it can be said that the "chance zone" is more advantageous than other non-ART gaming states.

Further, in the "chance zone", if the ART lottery is not won even after the above-mentioned predetermined number of games has been exhausted, the directed game state shifts to the "normal time". However, in the "chance zone", after the above-mentioned predetermined number of games have been exhausted, a lottery to end each game is performed, and if the end lottery is won, the "chance zone" is ended, but the end lottery is not won. In that case, the "chance zone" may be continued.

In the non-ART gaming state (more specifically, "normal time" and "chance zone"), when the "F_SP rip A", "F_SP rip B", and "F_SP rip C" described later are won, the game is played. As the state shifts to the RT3 state (RT3), the production game state shifts to the "double specialization zone" (the role of Blue 7 is established). That is, the internal winning combination of "F_SP Lip A", "F_SP Lip B", and "F_SP Lip C", which will be described later, is one of the definite combinations that are determined to shift to the ART gaming state.

Here, in the internal winning combination of "F_SP Lip A", regardless of the procedure of the stop operation, the "blue 7" symbol described later has the middle stage area of the left reel 3L, the middle stage area of the middle reel 3C, and the right reel 3R. It is an internal winning combination that makes it possible to line up on the line (center line) connecting the middle areas, and the internal winning combination of "F_SP Lip B" has the "Blue 7" symbol described later regardless of the stop operation procedure. , It is an internal winning combination that makes it possible to line up on the line (cross-up line) connecting the lower area of the left reel 3L, the middle area of the middle reel 3C, and the upper area of the right reel 3R, and of "F_SP Lip C". Regardless of the stop operation procedure, the internal winning combination is a line (crossdown) in which the "blue 7" symbol described later connects the upper area of the left reel 3L, the middle area of the middle reel 3C, and the lower area of the right reel 3R. It is an internal winning combination that makes it possible to line up on the line) (see FIG. 19 described later). Therefore, the player can recognize that the transition to the ART gaming state is confirmed by arranging the "blue 7" symbols.

Further, in the non-ART gaming state, when the "F_black BAR" described later is won, it is confirmed that the directed gaming state shifts to the ART gaming state. That is, the internal winning combination of "F_black BAR", which will be described later, is one of the definite winning combinations that are determined to shift to the ART gaming state. Further, the internal winning combination of "F_black BAR" is an internal winning combination that enables the "black BAR" symbol described later to be lined up in the center line described above regardless of the procedure of the stop operation (see the figure described later). 20). In addition, when the player wins the "F_black BAR" and shifts to the ART game state, "100" games are given as the initial number of ART games and "3" is given as the number of ART stocks. ing. Therefore, the player can not only recognize that the transition to the ART gaming state is confirmed by arranging the "black BAR" symbols, but also can recognize that a plurality of ART stocks have been given.

As described above, in the pachislot machine 1 of the present embodiment, the internal winning combination of "F_black BAR", which will be described later, has the highest expectation of the transition of the ART gaming state and the acquisition of the gaming medium accompanying the transition, and thus the player. It is positioned as a special internal winning role (premium role) that is of most interest to us.

Here, "ART stock" means that when a predetermined number of ART games (50 games in this embodiment) is set as one set, the right to play a game in the ART game state of the one set is defined. means. That is, "ART stock" is a right that enables a game to be played in "normal ART" described later for at least 50 games. Therefore, "3" is given as the number of ART stocks, which is synonymous with the right to play (3 sets) of ART games of at least 150 games. However, as will be described later, the number of ART games per set may be added, so that the number of ART games per set is actually indefinite. In the present embodiment, the addition of the number of ART games (or the number of sets) may be described as extending the game period in the ART game state.

In addition, in the non-ART gaming state (more specifically, "normal time" and "chance zone"), when in the MB gaming state, the MB middle lock effect lottery is performed, and when the MB medium lock effect lottery is won. , It is confirmed that the lock effect during MB is executed and the effect game state shifts to the ART game state. This MB middle lock effect invalidates the player's game operation (for example, stop operation) for a predetermined period (for example, about 10 seconds), and within this predetermined period, any of the "black BAR" symbols described later is used. The display window is produced by operating the reels 3L, 3C, and 3R so as to line up with a line (not limited to the center line, which is an effective line, but may be another line, for example, a cross-up line or a cross-down line). 4 is an effect that makes it possible to temporarily stop the "black BAR" described later. In addition, when the lock effect during MB is executed and the game shifts to the ART game state, "100" games are given as the initial number of ART games, and "3" is given as the number of ART stocks. There is. Therefore, the player can recognize that the transition to the ART gaming state is confirmed by the fact that the "black BAR" symbols are lined up (temporarily stopped), as in the case of winning the "F_black BAR" described later. Not only that, it can be recognized that a plurality of ART stocks have been given.

Here, in the pachislot machine 1 of the present embodiment, the probability that the later-described "F_black BAR" is determined as the internal winning combination is defined as "8/65536" (that is, 1/8192) except for the MB game state. (See FIG. 17 described later). Then, in the MB game state, the probability that the above-mentioned MB middle lock effect is determined to be executed is defined as "8/65536" (that is, 1/8192).

As described above, in the pachislot machine 1 of the present embodiment, in a gaming state different from the special gaming state (for example, MB gaming state), a specific combination (for example, "F_black") that triggers the operation of the advantageous state (for example, during ART) The winning probability of "BAR") and the execution probability of a specific lock effect that triggers the operation of the advantageous state in the special gaming state are configured to be the same probability (for example, 8/65536). That is, regardless of which gaming state the gaming state is, the activation trigger of the advantageous state can be obtained with a certain probability. Therefore, it is possible to improve the interest of the game.

Further, in the pachi-slot machine 1 of the present embodiment, when a specific lock effect is executed in a special gaming state (for example, MB gaming state), a combination of symbols related to a specific combination (for example, "C_black BAR") The combination of symbols) is configured to temporarily stop. That is, if the combination of symbols related to the specific combination is displayed regardless of which game state the game state is, the player can be made aware that the operation trigger of the advantageous state has been established. ing. Therefore, for example, in the special game state, even if there are restrictions on the determination of the internal winning combination and the stop control of the reel, the player can easily feel that the operation trigger of the advantageous state has been established. , Further, the interest of the game can be improved.

("Normal ART")
The directed game state "normal ART" is a game state in which an ART game is performed by consuming the acquired number of ART games. That is, it is a basic gaming state in the ART gaming state.

When shifting from the non-ART gaming state to the "normal ART", for example, if the current RT state is the RT1 state, the RT state shifts to the RT3 state by the notification of the stop operation information (see FIG. 13). ), The acquired number of ART games is not consumed (that is, not subtracted), and the number of ART games is consumed from the time when the RT state becomes the RT3 state. The game state during this period can be defined as an "ART preparation state" (that is, a state in which only the AT function is activated and the RT function is not yet activated), and in fact, such an effect game state is provided. The game state may be managed. The same applies to the case of shifting from the “CB medium CP specialization zone” or “promotion chance” to “normal ART”, which will be described later.

To "normal ART", as described above, when the ART lottery is won in the non-ART game state and the promotion lottery is not won (ART winning), or when the "promotion chance" is completed (non-promotion winning). And, when it is decided that the ART game state will continue when the "continuation challenge" ends (CP = 0 and there is an ART game (stock of the number of sets)).

Further, although not shown in FIG. 14, as described above, when the "F_black BAR" described later is won in the non-ART game state, when the MB middle lock effect is executed, "BB middle CP". When the "specialized zone" ends and when the "double specialized zone" ends, the production game state shifts to "normal ART".

In the present embodiment, the basic number of ART games per set is set to "50" games, and the number of ART games is 0 in "normal ART" (that is, 50 games when additions are not considered). (Digest), the "normal ART" in the set ends. Here, when the "normal ART" in the set ends, if the CP is acquired, the production game state shifts to the "continuation challenge" (normal ART end and CP> 0).

Here, "CP" is an abbreviation for "challenge point", and it is determined whether or not to add the number of ART games (that is, the number of games of "normal ART") in the "continuous challenge" described later. Is the right to allow. In that sense, it is not a right that makes it possible to directly continue the ART gaming state, but it is a right that has value for the player. As with the ART stock described above, a plurality of CPs can be held in the ART gaming state.

Further, even if the CP is not acquired when the "normal ART" in the set ends, if the above-mentioned ART stock is acquired, the ART stock is consumed (that is, the ART stock counter). The value of is subtracted by 1), and the game can be played in "normal ART" (that is, the next set is started) until 50 games are exhausted again.

In addition, at this time (that is, when the next set is started), a promotion lottery for whether or not to shift to the promotion chance is performed, and by winning this promotion lottery, the production is performed prior to the start of "normal ART". The game state shifts to "promotion chance" (part at the start of the next ART set). In addition, when the ART stock is acquired, if it is the one that confirms that the ART stock will shift to the promotion chance (special ART stock), the promotion lottery is not performed and the "normal ART" is started prior to the start. Then, the production game state shifts to "promotion chance" (a part of the start of the next ART set). It should be noted that the special ART stock is likely to be acquired mainly when the "F_black BAR" described later is won or when the lock effect during MB is executed.

Here, when the player has acquired both the ART stock and the CP at the end of the "normal ART" in the set (that is, the value of the ART stock counter is "1" or more, and the value of the CP counter (If it is "1" or more), before consuming ART stock and moving to the next set, first determine whether to consume CP and continue (extend) the set. The game state shifts to "continuation challenge".

Further, when the "normal ART" in the set ends, the player has neither acquired the ART stock nor the CP (that is, the value of the ART stock counter is "0", and the value of the CP counter is also "". When it is "0"), the ART gaming state ends, and the player shifts to a non-ART gaming state (more specifically, "normal time").

The CP can be acquired mainly in the "CB medium CP specialization zone" or the "double specialization zone" described later, but even in the "normal ART", it is based on the internal winning combination. The CP acquisition lottery is performed, and if the CP acquisition lottery is won, the CP can be acquired even during the "normal ART".

In addition, ART stock can be acquired mainly in the "double specialization zone" described later, and as described above, when "F_black BAR" described later is determined as an internal winning combination. It can be acquired even when the lock effect during the MB is executed, but even during the "normal ART", the ART stock lottery is performed based on the internal winning combination, and this ART If you win the stock lottery, you can get ART stock even during "normal ART".

In addition, in the "normal ART", a lottery for adding the number of ART games to directly add and draw the number of ART games is performed based on the internal winning combination, and when the lottery for adding the number of ART games is won, the lottery is performed. , The number of ART games can be added.

Further, in the "normal ART", when the BB operates (wins), that is, when the combination of the symbols of "C_BB" (see FIG. 18 described later) is displayed on the valid line, the BB game state is the effect game state. It becomes a "CP specialization zone during BB" (BB prize during ART).

In addition, in the "normal ART", when the "F_SP rip A", "F_SP rip B", and "F_SP rip C" described later are won, the production game state shifts to the "double specialization zone" (blue 7 role). Established).

("Continued Challenge")
The directed game state "continuation challenge" is a game state in which it is determined whether or not to continue the ART game state (more specifically, "normal ART" in the set) by consuming the acquired CP. As described above, the transition to the "continuation challenge" is made when the CP has been acquired when the "normal ART" in the set ends.

In the "Continuous Challenge", as long as there is a CP that has been acquired, if you win the replay role (for example, RT3 Lip described later), you will be challenged to aim for a specific symbol (in this case, the "blue BAR" symbol). (A production that suggests that the display should be stopped) is performed. Then, when the "blue BAR" symbol is lined up on a specific line (in this embodiment, it is a line different from the effective line, but it may be an effective line), CP is not consumed (that is, CP is subtracted). (Not), a predetermined number of ART games (for example, 50 games) is given. On the other hand, when the "blue BAR" symbols do not line up on a specific line, CP is consumed (that is, CP is subtracted) and the number of ART games is not given. However, regardless of whether the "blue BAR" symbol is lined up in a specific line, CP is always consumed (that is, CP is subtracted) when one challenge effect is executed. You may.

Then, the execution of this challenge effect is repeated until the CP becomes 0, and when the CP becomes 0, if the number of ART games has been acquired, the number of the acquired ART games is used as the "" in the set. Return to "normal ART". Also, even if you have not acquired the number of ART games, if you have acquired the ART stock, you will consume the acquired ART stock and shift to "normal ART" in the next set (CP = 0 and the number of ART games). (Stock of the number of sets) Yes). On the other hand, when the CP becomes 0, if neither the number of ART games nor the ART stock is acquired, the ART game state ends and the game shifts to the non-ART game state (more specifically, "normal time"). To do.

Further, in the "continuation challenge", when a predetermined replay role (for example, RT3 Lip C described later) is won, a special activation lottery (transition lottery) of the "promotion chance" is performed, and if the special activation lottery is won. , A definite challenge effect that deterministically notifies that a specific symbol (in this case, the "blue 7" symbol) is lined up in a specific line (that is, a notification until the push order in which the specific symbol is lined up in a specific line) The production to be performed) is performed, and based on the final challenge production being performed, the production game state shifts to the "promotion chance" (a part of the addition during the continuous challenge).

Further, in the "continuous challenge", when a specific replay role (for example, RT3 rip B described later) is won, the above-mentioned confirmed challenge effect (however, the specific symbol in this case is the "blue BAR" symbol) A predetermined number of ART games (for example, 50 games) is given based on the fact that the final challenge effect is performed. In addition, at this time, an activation lottery (transition lottery) of "promotion chance" is performed, and when this activation lottery is won, the production game state shifts to "promotion chance" (a part of the addition during the continuous challenge).

That is, in the "continuation challenge", an additional lottery for whether or not to add the number of ART games is performed based on the acquired CP, and a lottery for shifting to the "promotion chance" is also performed. ..

The mode of the additional lottery for the number of ART games based on the acquired CP in the "continuation challenge" is not limited to the above. For example, in the "continuation challenge", a lottery is drawn to determine whether to add the number of ART games based on each game and internal winning combination, and if the winning is won, the CP is not consumed, and if the winning is not done, the CP is consumed. This may be repeated until CP becomes 0.

Further, when it is decided to add the number of ART games, the number of ART games to be added may be further determined by lottery.

In the "continuation challenge", the mode of the lottery for transition to the "promotion chance" based on the acquired CP is not limited to the above. For example, when the lottery for transition to the "promotion chance" is won, the initial value of the "number of continuations" described later in the "promotion chance" may be further determined by the lottery.

As described above, in the pachislot machine 1 of the present embodiment, the advantageous state (for example, during ART) is configured to include the first advantageous state (for example, normal ART) and the second advantageous state (for example, continuous challenge). In the advantageous state, it is possible to grant a plurality of specific rights (for example, CP) for performing an additional lottery (determination of whether to extend the game period) in the number of games in the first advantageous state in the second advantageous state. It is configured to be possible.

In addition, when a specific right is granted when the first advantageous state ends, the process shifts to the second advantageous state, and in the second advantageous state, the specific right is consumed to obtain the first advantageous state. When an additional lottery for the number of games (decision on whether to extend the game period) is performed and the additional lottery is won (when it is decided to extend the game period), the first advantageous state is continued. It is configured to be able to.

Then, when a plurality of specific rights are acquired, the specific rights are not wasted, and all of them are added to the number of games in the first advantageous state (decision as to whether or not to extend the game period). ) Is configured to be used. Therefore, in the second advantageous state, not only is it decided whether or not to continue the advantageous state, but also it is possible to create the possibility that a large number of games are added at one time. The sex can be varied and the interest of the game can be improved.

Further, in the pachi-slot machine 1 of the present embodiment, the advantageous state (for example, during ART) is configured to include the first advantageous state (for example, normal ART) and the second advantageous state (for example, continuous challenge), and the advantageous state is included. Then, the first right to continue the first advantageous state (for example, ART stock), and the additional lottery of the number of games of the first advantageous state in the second advantageous state (decision of whether to extend the game period). A second right (eg, CP) to do so is configured to be grantable.

Then, when the first advantageous state ends, if both the first right and the second right are granted, the control is configured to give priority to the transition to the second advantageous state. Has been done. That is, the second right is preferentially digested over the first right.

In this case, in the second advantageous state, when the second right is consumed and an additional lottery (decision as to whether or not to extend the game period) is performed for the number of games in the first advantageous state, and the additional lottery is won ( If it is decided to extend the game period), the first advantageous state can be continued without consuming the first right, and if the additional lottery is not won (the game period can be extended). Even if it is not decided), the first right can be consumed to continue the first advantageous state. Therefore, it is possible to make the game playability various while ensuring a sense of security regarding the continuation of the advantageous state, and it is possible to improve the interest of the game.

Further, even if the state shifts to the second advantageous state when the first advantageous state ends, the first advantageous state continues due to the consumption of the second right or the consumption of the first right. Since the possibility can be left, the expectation for the continuation of the advantageous state can be maintained.

Further, in the pachi-slot machine 1 of the present embodiment, it is possible to acquire a plurality of second rights in an advantageous state, and when a plurality of second rights are acquired, the second rights are acquired. Is not wasted, and all of them are provided for an additional lottery (determination of whether or not to extend the game period) for the number of games in the first advantageous state. Therefore, in the second advantageous state, not only is it decided whether or not to continue the advantageous state, but it is also possible to create the possibility that a large number of games are added at one time, so that the game playability is more diverse. It is possible to improve the interest of the game.

("CB Special Zone in BB")
The production game state "BP special zone during BB" is a game state in which the BB is activated (winning) in the ART game state (BB prize during ART), and is basically a BB game state. .. In the "BB medium CP specialization zone", the internal state (for example, "state 1" or "state 2" described later) is determined at the start of the zone, and CP is acquired based on the determined internal state and the internal winning combination. If a lottery is held and the CP acquisition lottery is won, CP will be awarded.

Then, when the BB game state ends, the "BB medium CP special zone" ends, and the directed game state shifts to the "normal ART" with the given CP. In addition, when the above-mentioned "ART preparation state" is provided, the production game state shifts (returns) to "normal ART" through this "ART preparation state".

("Double specialization zone")
The directed game state "double specialization zone" is a non-ART game state (more specifically, excluding the "BB medium history specialization zone" which is a BB game state) or an ART game state (more specifically, a BB game state). (Excluding the "BP special zone in BB"), a game that shifts to the case of winning the "F_SP Lip A", "F_SP Lip B", and "F_SP Lip C" described later (establishment of the blue 7 role). It is a state, and is a gaming state in which both the CP acquisition lottery and the ART stock acquisition lottery are drawn. In that sense, it is called a "double specialization zone".

In the "double specialization zone", the basic number of guaranteed games that guarantees stay is set to "10" games, and when the number of guaranteed games is exhausted, an end lottery is performed, and when the end lottery is won, If the "double specialization zone" ends and the production game state before the transition is "promotion chance", it shifts to the "promotion chance", and if the production game state before the transition is "continuation challenge", it is "continuation challenge". If the effect game state before the transition is another effect game state, the process shifts to "normal ART".

Further, in the "double specialization zone", an internal state (for example, "state 1" or "state 2" described later) is determined at the start of the zone, and an end lottery is performed based on the internal state. However, if the blue 7 fake notification described later is performed, if ART stock is acquired, or if an internal winning combination other than the "normal role" is determined, the end lottery will not be performed and the "double specialization zone" Continues. The "normal role" referred to here refers to the "normal role 1" and the "normal role 2" described later (see FIG. 29).

Further, in the "double specialization zone", when a predetermined replay combination (for example, RT3 Lip A described later) is won, a blue 7 fake notification lottery is performed, and when the blue 7 fake notification lottery is won, a reverse push is made. (That is, the right reel 3R is stopped first), and a blue 7 challenge effect (an effect suggesting that the stop display should be displayed) is performed to aim at a specific symbol (in this case, the "blue 7" symbol). However, this predetermined replay role is an internal winning role in which the "blue 7" symbol is a so-called "tempai" on a specific line, but does not line up on the specific line. Therefore, if the Blue 7 Challenge production based on the Blue 7 Fake Notification Lottery is executed, there is no case of acquiring ART stock or CP, but the privilege that the "double specialization zone" will continue. You can get it.

Further, in the "double specialization zone", when a specific replay role (for example, RT3 Lip C described later) is won, ART stock is given and a CP acquisition lottery is performed, and this CP acquisition lottery is used. If you win, CP will also be given. At this time, the blue 7 challenge effect described above is performed. And, in this specific replay role, the "blue 7" symbol is an internal winning role in which the "blue 7" symbol is lined up on a specific line. Therefore, when the Blue 7 Challenge production based on the winning of this specific replay role is executed, the privilege of acquiring ART stock and the privilege of continuing the "double specialization zone" can be obtained. You may be able to get the benefit of earning CP.

Further, in the "double specialization zone", when other internal winning combinations are decided, a CP acquisition lottery is performed, and when the CP acquisition lottery is won, CP is given. Even in this case, the end lottery may not be performed and the "double specialization zone" may continue.

("Promotion chance")
The production game state "promotion chance" is "normal ART" when the ART lottery is won (or it is confirmed that the game will be transferred to ART) in the non-ART game state, and the promotion lottery is also won (a part of the ART win). If you win the promotion lottery at the start of the set (part at the start of the ART next set), or if you win the activation lottery (transition lottery) in the "continuation challenge" (part of the addition during the continuation challenge) It is in a gaming state. In the "promotion chance", information on the stop operation that is advantageous for the player is notified as in the ART game state. In that sense, the "promotion chance" can be said to be one of the ART gaming states.

In the "promotion chance", a continuous lottery of this "promotion chance" is performed, and if the continuous lottery is won, the "promotion chance" is continued, and if the continuous lottery is not won, the "promotion chance" is given. If the effect game state before the transition is "continuation challenge", the process shifts to the "continuation challenge", and if the effect game state before the transition is another effect game state, the game shifts to the "normal ART". In the "promotion chance", it is possible to decide in advance whether or not to continue the plurality of consecutive games.

As for this continuous lottery method, various methods can be adopted. For example, at the time of transition of "promotion chance", the number of games to be continued may be determined in advance, or in the game during "promotion chance", "promotion chance" is given at least until the next and next games. You may decide whether or not to continue. It is also possible to simply perform a continuous lottery for each game to determine whether or not to continue the "promotion chance".

In addition, in the "promotion chance", the number of ART games is added each time the game continues. For example, if the initial value "50" of the number of ART games is given at the start of the "promotion chance", the number of ART games is added to "111" in the first game, and the "promotion chance" is the second time. If the game is continued, the number of ART games is added to "222", and if the "promotion chance" is continued until the third game, the number of ART games is added to "333". That is, in the "promotion chance", the number of ART games obtained by multiplying the number of games played in the "promotion chance" by "111" is sequentially set.

The method of adding the number of ART games in the "promotion chance" is not limited to the above. If the game continues in the "promotion chance", a predetermined number of ART games (for example, 50 games) may be added, or the game is added when the game continues in the "promotion chance". The number of ART games may be determined by lottery, and the determined number of ART games may be added.

As described above, in the pachislot machine 1 of the present embodiment, in the non-ART gaming state and the ART gaming state, the above-mentioned production gaming states are set to enhance the playability.

In the ART game state, when "F_black BAR" is determined as the internal winning combination, or when the lock effect during MB is executed, the number of ART games is "100" as in the non-ART game state. Along with being added to the game, "3" is given as the number of ART stocks. However, in the ART game state, when "F_black BAR" is determined as the internal winning combination, and when the lock effect during MB is executed, a profit different from the non-ART game state is given. Good.

Further, in the present embodiment, as a management method in the ART game state (more specifically, "normal ART"), the number of sets (that is, the predetermined number of ART games is set as one unit) is managed. However, it is not limited to this. For example, it may be managed only by the number of ART games instead of the number of sets. That is, in the scene where the ART stock is given, the same number of ART games may be given.

Further, for example, one set may be managed by the difference number (that is, the net increase number obtained by subtracting the input number from the payout number), or the number of notifications of the push order combination (for example, the batting order bell) (that is, actually). It may be managed by the number of times the information of the stop operation which is advantageous for the player related to the payout of medals is notified). In these cases, when an addition occurs, the difference number of sheets and the number of notifications may be added.

Here, to continue (add or extend) the ART game state is not limited to the above-mentioned addition of the number of ART games and ART stock, and the addition of the difference number and the number of notifications, and the continuation probability (continuation) of the ART game state. It may be to increase the rate). For example, when a continuous lottery (end lottery) is performed every time one set is completed, the continuation probability can be increased so that the continuous lottery can be substantially added.

Further, for example, when the ART gaming state and the BB gaming state, or only the ART gaming state is managed as a series of advantageous sections and the number of continuations of the advantageous section reaches a predetermined number of games (for example, 1500 games), Even if the number of ART games, ART stock, and CP still remain, the ART game state may be forcibly terminated to shift to the "normal time". That is, a certain limiter may be set for the continuation of the advantageous section that is advantageous to the player. With such a configuration, it is possible to prevent the player from being excessively absorbed in the game.

<Structure of data table stored in main ROM>
Next, the configurations of various data tables stored in the main ROM 102 will be described with reference to FIGS. 15 to 21. The configuration of various data tables related to the ART function will be described later with reference to FIGS. 28 to 33.

[Design arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table is composed of the positions of the symbols in the rotation directions of the left reel 3L, the middle reel 3C, and the right reel 3R, and the data for specifying the type of the symbols arranged at each position (hereinafter referred to as the symbol code). Specify the correspondence.

In the symbol arrangement table, when the reel index is detected, the position of the symbol located in the middle region of each reel in the frame of the reel display window 4 is defined as "0". Then, in each reel, in the order of proceeding in the reel rotation direction (direction from the symbol position "19" in FIG. 15 toward the symbol position "0") with the symbol position "0" as a reference, " "0" to "19" are assigned to each symbol as the symbol position.

That is, by referring to the value of the symbol counter ("0" to "19") and the symbol arrangement table, it is displayed in the upper region, the middle region, and the lower region of each reel in the frame of the reel display window 4. It is possible to specify the type of symbol. In this embodiment, as the symbols, "blue BAR", "black BAR", "blue 7", "white 7", "bell 1", "bell 2", "bell 3", "bell 4", And 9 kinds of "rip" symbols are used.

Further, in the present embodiment, as the symbol code, the symbol "blue BAR" (symbol code 1) is assigned "00000001" as data, and the symbol "black BAR" (symbol code 2) is assigned "00000010" as data. Is assigned, the symbol "blue 7" (symbol code 3) is assigned "000000111" as data, and the symbol "white 7" (symbol code 4) is assigned "00000100" as data. ..

Further, the symbol "bell 1" (symbol code 5) is assigned "00000011" as data, and the symbol "bell 2" (symbol code 6) is assigned "00000011" as data, and the symbol "bell 3" is assigned. (Symbol code 7) is assigned "000000111" as data, the symbol "Bell 4" (symbol code 8) is assigned "00001000" as data, and the symbol "Rip" (symbol code 9) is assigned. Is assigned "000001001" as data.

[Internal lottery table]
Next, with reference to FIGS. 16 and 17, the internal lottery table referred to when determining the internal winning combination will be described.

The internal lottery table is provided for each game state, and defines the correspondence between various internal winning combinations and the lottery value when each internal winning combination is determined. The lottery value is defined for each set value (set values 1 to 6) for adjusting the expected value of the internal winning such as a preset bonus combination or small combination. This set value is changed by using, for example, the reset switch 76 and the setting key type switch 54 (see FIG. 7).

In the internal lottery process of the present embodiment, first, a random number value extracted from a predetermined numerical range (for example, 0 to 65535) by the random number register 0 of the random number circuit 110 is assigned to each internal winning combination. Add in sequence at the specified lottery value. Next, it is determined whether or not the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result overflows). Then, when the lottery result exceeds 65535 in the predetermined internal winning combination, it is determined that the internal winning combination has won. In the internal lottery process of the present embodiment, an example of adding the lottery value to the extracted random number value to perform the lottery has been described, but the internal lottery process of the present embodiment is not limited to this, and the lottery value is calculated from the random number value. May be subtracted to determine whether or not the subtraction result (lottery result) is less than "0" (whether or not the lottery result is underflowed), and the winning / non-winning of the internal lottery may be determined.

Therefore, in the internal lottery process of the present embodiment, the larger the numerical value defined as the lottery value, the higher the probability that the internal lottery combination will be determined. The winning probability of each internal winning combination can be expressed by "the lottery value specified in each winning number / the number of all random number values that may be extracted (random number denominator: 65536)".

As shown in FIGS. 16 and 17, in the present embodiment, as the internal winning combination, "F_normal lip" (win number "1"), "F_RT1_RT2U lip 1" to "F_RT1_RT2U lip 6" (win number "2") ~ "7"), "F_RT2_RT3U Lip 1" ~ "F_RT2_RT3U Lip 6" (win numbers "8" ~ "13"), "F_RT2 maintenance lip 1" ~ "F_RT2 maintenance lip 6" (win numbers "14" ~ " 19 ")," F_RT3 Lip A1 "to" F_RT3 Lip A4 "(win numbers" 20 "to" 23 ")," F_RT3 Lip B1 "to" F_RT3 Lip B4 "(win numbers" 24 "to" 27 "), "F_RT3 Lip C1" to "F_RT3 Lip C4" (win number "28" to "31"), "F_SP Lip A" (win number "32"), "F_SP Lip B" (win number "33"), " F_SP Fake Lip C (winning number "34"), "F_SP Fake Lip A" (winning number "35"), "F_SP Fake Lip B" (winning number "36"), "F_Chance Lip A" (winning number "37") ) And "F_Chance Lip B" (winning number "38") are specified.

In addition, since "F_RT1_RT2U lip 1" to "F_RT1_RT2U lip 6" are mainly internal winning combinations determined in the RT1 state, in the present embodiment, they may be simply described as "RT1 lip" (RP1 middle lip). is there.

Further, since "F_RT2_RT3U Lip 1" to "F_RT2_RT3U Lip 6" and "F_RT2 Maintenance Lip 1" to "F_RT2 Maintenance Lip 6" are mainly internal winning combinations determined in the RT2 state, in the present embodiment, It may be described simply as "RT2 lip" (RP2 medium lip).

Further, "F_RT3 rip A1" to "F_RT3 rip A4", "F_RT3 rip B1" to "F_RT3 rip B4", and "F_RT3 rip C1" to "F_RT3 rip C4" are mainly internal winnings determined in the RT3 state. Since it is a role, in the present embodiment, it may be simply described as "RT3 lip" (RT3 medium lip). Further, "F_RT3 rip A1" to "F_RT3 rip A4" may be simply described as "RT3 rip A" (Rip A in RT3), and "F_RT3 rip B1" to "F_RT3 rip B4" are simply "RT3". It may be described as "Rip B" (Rip B in RT3), and "F_RT3 Lip C1" to "F_RT3 Lip C4" may be simply described as "RT3 Lip C" (Rip C in RT3).

Further, in the present embodiment, "F_Batting order bell 1A" to "F_Batting order bell 6A" and "F_Batting order bell 1B" to "F_Batting order bell 6B" (winning numbers "39" to "50") are used as internal winning combinations. , "F_1 piece role" (win number "51"), "F_weak chance role" (win number "52"), "F_medium chance role" (win number "53"), "F_strong bell" (win number) "54"), "F_common bell" (winning number "55"), "F_black BAR" (winning number "56"), "F_special role A" (winning number "57"), "F_special role B" (Winning number "58"), "F_special role C" (winning number "59"), "F_BB middle chance role A" (winning number "60"), "F_BB middle chance role B" (winning number "61" ")," F_BB middle chance role C "(win number" 62 ")," F_MB "(win number" 63 ")," F_BB + F_chance lip B "(win number" 64 ")," F_BB + F_special role A "( The winning number "65"), "F_BB + F_special role B" (winning number "66"), and "F_BB + F_special role C" (winning number "67") are specified.

In the present embodiment, in each game state or in common to each game state, the lottery values shown in FIGS. 16 and 17 are defined for these internal winning combinations, and the above-mentioned arithmetic processing using the lottery values. By doing so, the internal winning role is decided.

As described above, in the MB game state, for the replay combination, the winning probability of the current RT state (that is, the lottery value shown in FIGS. 16 and 17) is taken over and the lottery is performed, while the small combination and the small combination and All small winning combinations can be determined as internal winning winning combinations without drawing lots for bonus winning combinations (see FIG. 64 below). In the internal lottery table of the MB game state (in MB) shown in FIG. 17, "-" is described in the columns of the winning numbers "39" to "67" in that sense. However, "0" is defined as the lottery value corresponding to these winning numbers, and although the winning is not actually won, the lottery process may be common in each game state.

Further, the method of determining the internal winning combination in the MB game state is not limited to this. For example, in the MB game state, the internal lottery table corresponding to the current RT state is referred to (that is, the internal lottery table in the MB game state (in MB) is not specified), and all the above-mentioned winning numbers are specified. It may be possible to determine whether or not the winning combination is based on the lottery value obtained, and then all the small winning combinations may be further determined as the internal winning combination. At this time, for example, when "F_BB + F_special combination A" (winning number "65") is won, only "F_special combination A" is determined as the internal winning combination (that is, "F_BB"). It may be set so that it is not stored in the hit request flag storage area (see FIG. 22 described later) or the carry-over combination storage area (see FIG. 23 described later). As a result, the data capacity related to the internal lottery table can be reduced.

In addition, in the MB gaming state, the internal winning combination that can be determined in the MB gaming state (that is, only all the small winning combinations or any of all the small winning combinations and each replay combination) is combined to form the internal winning combination in the MB gaming state. The internal lottery table in the MB game state (during MB) may be provided by specifying the lottery value according to the RT state for each internal winning combination in the MB game state. In this case, for example, if the current RT state is the RT0 state, as the internal lottery table in the MB game state, the "corresponding symbol combination" is NML01 to NML23, which will be described later, and the internal winning combination (that is, only all small combinations). "56558" is specified in the lottery value of (determine), and the "corresponding symbol combination" is NML01 to NML23 and REP02, which will be described later, for the internal winning combination (that is, all small combinations + "F_normal lip" is determined). "8332" is specified as the lottery value, and the lottery value of the internal winning combination (that is, all small winning combinations + "F_chance lip A" is determined) in which the "corresponding symbol combination" is NML01 to NML23 and REP01 described later. "504" is defined, and "142" is set as the lottery value of the internal winning combination (that is, all small winning combinations + "F_chance lip B" is determined) in which the "corresponding symbol combination" is NML01 to NML23 and REP20 described later. It suffices to provide an internal lottery table in which is specified.

That is, when the internal lottery table in the MB game state (in MB) is provided, the inside is a combination of all the small winning combinations and the replay winning combinations (win numbers "1" to "38") shown in FIGS. 16 and 17. The winning combination is specified, and for the internal winning combination, the same lottery value as the lottery value specified for each replay combination is specified for each RT state, and the lottery value specified for each RT state is specified from "65536". The value obtained by subtracting the total value may be defined as the lottery value of the internal winning combination in which only all the small winning combinations are determined. As a result, in the internal lottery process (see 64 described later), it is not necessary to perform control specific to the MB game state (S319 and S320 described later), so that the control load in the internal lottery process can be reduced, and the MB game state can be reduced. Since the processing procedure of the internal lottery process can be standardized regardless of whether or not the above is provided, the design man-hours can be reduced. In this case, the winning number of the internal winning combination in the MB gaming state is the winning number following the winning numbers "1" to "67" defined in the other gaming states (for example, the winning numbers "68" to "105". ), Or the same winning numbers as in other gaming states (for example, winning numbers "1" to "38") can be specified. In the latter case, it is sufficient to separately specify data that can identify that the "corresponding symbol combination" changes depending on the winning number between the MB gaming state and other gaming states.

Further, in the present embodiment, when the internal winning combination is determined, it is permitted (allowed) that a combination of one or a plurality of symbols is displayed on the effective line. The symbol combinations that are allowed to be displayed on the valid line are as shown in "corresponding symbol combinations" shown in FIGS. 16 and 17.

For example, "F_normal lip" is an internal winning combination that allows a combination of symbols of "REP02" (name: C_TL lip) described later to be displayed on the effective line (see FIG. 18 described later), and is a game. When the state is the RT0 state, it is determined as the internal winning combination with a probability of "8332/65536", and when the game state is the RT4 state, it is determined as the internal winning combination with the probability of "18041/65536", and other games In the state, it is not determined as an internal winning combination (that is, "0" is specified in the lottery value). However, as described above, in the MB game state, the lottery value in the RT state is inherited and the lottery of the replay combination is performed. Therefore, in the MB game state and the RT0 state, "8332/65536". It is determined as an internal winning combination with a probability of "", and when it is in the MB game state and in the RT1 to RT3 states, it is not determined as an internal winning combination (that is, "0" is specified in the lottery value). Since the RT4 state is between the BB flags (inside the BB), there is no case of shifting to the MB game state.

Further, for example, "F_strike order bell 1A" is described later as "NML01" (name: S_L1st miss A), "MNL04" (name: S_L1st miss D), "NML05" (name: S_C1st miss A), "NML08". (Name: S_C1st Miss D), "NML09" (Name: S_R1st Miss A), "NML12" (Name: S_R1st Miss D), and "NML15" (Name: S_BL Bell) are displayed on the valid line. It is an internal winning combination that is permitted to be played (see FIG. 18 described later), and when the gaming state is the RT0 to RT4 state (that is, the non-bonus state), it is determined as the internal winning combination with a probability of "962/65536". In other gaming states (ie, bonus states), it is not determined as an internal winning combination (ie, the lottery value is defined as "0").

Although details will be described later, in the present embodiment, "F_batting order bell 1A" to "F_batting order bell 6A" and "F_batting order bell 1B" to "F_batting order bell 6B" are determined as internal winning combinations. Therefore, when a so-called "missing" occurs, a combination of any of the symbols "S_RT1 transition A", "S_RT1 transition B", and "S_RT1 transition B" described later is displayed on the valid line. There is. In that sense, "F_Batting Order Bell 1A" to "F_Batting Order Bell 6A" and "F_Batting Order Bell 1B" to "F_Batting Order Bell 6B" are "S_RT1 Transition A", "S_RT1 Transition B", and "S_RT1 Transition B". It can also be said to be an internal winning combination that allows the combination of symbols of "" to be displayed on the effective line.

Further, although not shown, the lottery value of at least a part of the replay combination and / or the small combination changes due to the change of the set value. However, the bonus combination may also be able to change the lottery value. Specifically, when a predetermined probability fluctuation start condition is satisfied, the lottery value of the bonus combination is high (that is, the bonus combination is drawn with a high probability) until the predetermined probability fluctuation end condition is satisfied. It is also possible to allow the internal lottery process to be performed by the table. In this case, the predetermined probability fluctuation start condition and the predetermined probability fluctuation end condition can be appropriately set as arbitrary conditions during the game.

[Design combination table]
Next, with reference to FIG. 18, a symbol combination table that defines combinations of symbols related to winning and operation in the present embodiment will be described.

As shown in FIG. 18, the symbol combination table defines a plurality of symbol combinations related to winning and operation, and data indicating the types of these symbol combinations is defined as a display combination (winning operation flag). There is. Further, the symbol combination table is composed of 7 bytes of data so as to correspond to the hit request flag storage area, the winning operation flag storage area (see FIG. 22 described later), and the symbol code storage area (see FIG. 27 described later). At the same time, data indicating a different display combination (winning operation flag) is specified for each bit of each storage area.

The display combination (winning operation flag) "C_BB" and "C_MB" are a combination of symbols related to the bonus combination, and are "C_CL lip", "S_TL lip", "S_BL lip", "S_RT1 lip A", "S_RT1 Lip B", "C_RT2 Lip", "S_RT3 Lip", "C_SP_CL Lip", "S_SP_XU Lip", "S_SP_XD Lip", "S_SP_TL Lip", "C_TT_BL Lip", "S_TT_XD Lip", "S_TT_XD Lip" "S_Fake Lip F" and "C_Chance Lip" are combinations of symbols related to the replay combination.

In addition, the display combination (winning operation flag) "S_L1st Miss A" to "S_L1st Miss D", "S_C1st Miss A" to "S_C1st Miss D", "S_R1st Miss A" to "S_R1st Miss D", "C_Special Combination" , "S_CL Bell", "S_BL Bell", "C_CB 1", "C_CB 2", "C_Black BAR", "S_Weak Chance", "S_Medium Chance", and "S_Chance 1"-"S_ "Chance 3" is a combination of symbols related to a small winning combination, and "S_RT1 transition A", "S_RT1 transition B", and "S_RT1 transition B" are out-of-order symbol combinations, but the RT state is shifted to the RT1 state. It is a combination of symbols to be made.

For example, when the combination of the symbols of "blue BAR-blue BAR-blue BAR" is displayed on the valid line, the display combination (winning operation flag) is "C_BB" in the winning search process (winning determination process) described later. After that, the process for shifting the gaming state to the BB gaming state is performed.

Also, for example, "Black BAR-Bell 1-Blue BAR", "Black BAR-Bell 1-White 7", "Black BAR-Bell 2-Blue BAR", "Black BAR-Bell 2-White 7", "Black". Any combination of symbols of "BAR-Bell 3-Blue BAR", "Black BAR-Bell 3-White 7", "Black BAR-Bell 4-Blue BAR", and "Black BAR-Bell 4-White 7" When it is displayed on the valid line, it is determined that the display combination (winning operation flag) is "S_TL lip" (REP02) in the winning search process (winning determination process) described later, and then the re-game is activated. Will be processed.

In FIG. 18, for example, in "S_TL Lip" (REP02), the symbol of the middle reel 3C is described as "bells 1 to 4" because, as described above, the symbol of the middle reel 3C is " It means that any of "bell 1", "bell 2", "bell 3", and "bell 4" may be used, and the fact that the design of the right reel 3R is displayed as "blue BAR / white 7" is described above. As described above, it means that the design of the right reel 3R may be either "blue BAR" or "white 7".

Further, for example, when the combination of the symbols of "black BAR-black BAR-black BAR" is displayed on the valid line, the display combination (winning operation flag) is set to "C_black" in the winning search process (winning determination process) described later. It is determined that it is "BAR", and after that, a process for paying out seven medals will be performed. That is, when a numerical value is specified as the payout (number of payouts), the numerical value means the number of medals to be paid out when a prize is won. The symbol combination table shown in FIG. 18 defines the number of medals to be paid out when the number of medals inserted is three.

[Correspondence table between internal winning combination, stop operation order (batting order), display combination, etc.]
Next, with reference to FIGS. 19 to 21, the correspondence between the internal winning combination, the stop operation order (batting order), the display combination, and the like will be described. 19 and 20 are diagrams showing a correspondence table between the internal winning combination, the stop operation order (batting order), the display combination, etc. in the gaming state excluding the MB gaming state, and FIG. 21 is a diagram showing the correspondence table in the MB gaming state. , It is a figure which shows the correspondence table of an internal winning combination, a stop operation order (batting order), a display combination and the like.

In the pachi-slot machine 1 of the present embodiment, a so-called "pushing order combination" is provided in which the symbol combinations displayed are different according to the stop operation order (pushing order) of the player. Since the stop buttons 17L, 17C, 17R corresponding to the reels 3L, 3C, 3R are provided, there are a maximum of six stop operation orders (pushing order).

In FIGS. 19 to 21, it is indicated as "batting order 1" that the stop operation order (push order) is "left, middle, right", and the stop operation order (push order) is "left, right, middle". "Batting order 2" indicates that the order is "Batting order 2", and the stop operation order (pushing order) is indicated as "middle, left, right" as "Batting order 3", and the stop operation order (pushing order) is The order of "middle, right, left" is indicated as "batting order 4", and the stop operation order (pushing order) is indicated as "right, left, middle" as "batting order 5", and the stop operation is performed. The order (pushing order) is "right, middle, left", which is indicated as "batting order 6".

As shown in FIGS. 19 and 20, in the gaming states (more specifically, the RT0 state and the RT4 state) excluding the MB gaming state, the "F_normal lip" is determined not as a push order combination but as an internal winning combination. If so, the "S_TL lip" (upper lip) is established regardless of the stop operation order and the stop operation timing.

In the left reel 3L, the symbol "black BAR" constituting the combination of the symbols of "S_TL lip" is arranged within 5 frames (within the range of 5 symbols), and in the middle reel 3C, "S_TL lip". The symbols "Bell 1" to "Bell 4" that make up the combination of symbols are arranged within 5 frames (within the range of 5 symbols), and the combination of the symbols of "S_TL Lip" is formed on the right reel 3R. The symbols "blue BAR" and "white 7" are arranged within 5 frames (within the range of 5 symbols). That is, "regardless of the timing of the stop operation" means, in principle (that is, when the effective line is one line of the "center line" and the maximum number of sliding pieces is "4"), within 5 pieces (design). It means that the symbols are arranged within the range of 5 pieces). Hereinafter, the same applies to other display combinations (winning operation flags) and the like.

Further, in the game state (more specifically, the RT1 state) excluding the MB game state, "F_RT1_RT2U lip 1" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 1". If "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than "batting order 1", the other winning replay combination is established regardless of the stop operation timing, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintenance).

Further, in the game state (more specifically, the RT1 state) excluding the MB game state, "F_RT1_RT2U lip 2" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 2". If "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than "batting order 2", the other winning replay combination is established regardless of the stop operation timing, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintenance).

Further, in the game state (more specifically, the RT1 state) excluding the MB game state, "F_RT1_RT2U lip 3" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 3". If "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than "batting order 3", the other winning replay combination is established regardless of the stop operation timing, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintenance).

Further, in the game state (more specifically, the RT1 state) excluding the MB game state, "F_RT1_RT2U lip 4" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 4". If "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than "batting order 4", the other winning replay combination is established regardless of the stop operation timing, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintenance).

Further, in the game state (more specifically, the RT1 state) excluding the MB game state, "F_RT1_RT2U lip 5" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 5". If "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than "batting order 5", the other winning replay combination is established regardless of the stop operation timing, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintenance).

Further, in the game state (more specifically, the RT1 state) excluding the MB game state, "F_RT1_RT2U lip 6" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 6". If "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than "batting order 6", the other winning replay combination is established regardless of the stop operation timing, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintenance).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_RT3U lip 1" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 1". If "", "S_RT3 lip" is established regardless of the timing of the stop operation, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than "batting order 1", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_RT3U lip 2" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 2". If "", "S_RT3 lip" is established regardless of the timing of the stop operation, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than "batting order 2", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_RT3U lip 3" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 3". If "", "S_RT3 lip" is established regardless of the timing of the stop operation, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than "batting order 3", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_RT3U lip 4" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 4". If "", "S_RT3 lip" is established regardless of the timing of the stop operation, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than "batting order 4", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_RT3U lip 5" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 5". If "", "S_RT3 lip" is established regardless of the timing of the stop operation, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than "batting order 5", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_RT3U lip 6" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 6". If "", "S_RT3 lip" is established regardless of the timing of the stop operation, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than "batting order 6", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_maintenance lip 1" is a batting order, and when it is determined as an internal winning combination, the stop operation order is "batting order". If it is "1", "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than "batting order 1", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_maintenance lip 2" is a batting order, and when it is determined as an internal winning combination, the stop operation order is "batting order". If it is "2", "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than "batting order 2", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_maintenance lip 3" is a batting order, and when it is determined as an internal winning combination, the stop operation order is "batting order". If it is "3", "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than "batting order 3", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_maintenance lip 4" is a batting order, and when it is determined as an internal winning combination, the stop operation order is "batting order". If it is "4", "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than "batting order 4", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_maintenance lip 5" is a batting order, and when it is determined as an internal winning combination, the stop operation order is "batting order". If it is "5", "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than "batting order 5", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT2 state) excluding the MB game state, "F_RT2_maintenance lip 6" is a batting order, and when it is determined as an internal winning combination, the stop operation order is "batting order". If it is "6", "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than "batting order 6", the winning "S_RT1 lip A" or "S_RT1 lip B" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

Further, in the game state (more specifically, the RT3 state) excluding the MB game state, "F_RT3_lip A1" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 1". If, "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). If the stop operation order is "batting order 3" and "batting order 4" (that is, the middle reel 3C is first stopped), the winning "S_fake lip A" to "S_" are selected regardless of the timing of the stop operation. One of "Fake Clip C" is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (fake)). On the other hand, if the stop operation order is other than "batting order 1", "batting order 3" and "batting order 4", the winning "S_RT1 lip A" or "S_RT1 lip B" is displayed regardless of the timing of the stop operation. It is established and the RT state shifts to the RT1 state (RT1).

Further, in the game state (more specifically, the RT3 state) excluding the MB game state, "F_RT3_lip A2" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 2". If, "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). If the stop operation order is "batting order 5" and "batting order 6" (that is, the right reel 3R is first stopped), the winning "S_fake lip A" to "S_" are selected regardless of the stop operation timing. One of "Fake Clip C" is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (fake)). On the other hand, if the stop operation order is other than "batting order 2", "batting order 5" and "batting order 6", the winning "S_RT1 lip A" or "S_RT1 lip B" is displayed regardless of the timing of the stop operation. It is established and the RT state shifts to the RT1 state (RT1).

Further, in the game state (more specifically, the RT3 state) excluding the MB game state, "F_RT3_lip A3" is a batting order, and when it is determined as an internal winning combination, the stop operation order is "batting order 1". If, "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). If the stop operation order is "batting order 5" and "batting order 6" (that is, the right reel 3R is first stopped), the winning "S_fake lip A" to "S_" are selected regardless of the stop operation timing. One of "Fake Clip C" is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (fake)). On the other hand, if the stop operation order is other than "batting order 1", "batting order 5" and "batting order 6", the winning "S_RT1 lip A" or "S_RT1 lip B" is displayed regardless of the timing of the stop operation. It is established and the RT state shifts to the RT1 state (RT1).

Further, in the game state (more specifically, the RT3 state) excluding the MB game state, "F_RT3_lip A4" is a batting order, and when it is determined as an internal winning combination, the stop operation order is "batting order 2". If "," S_TL lip "is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). If the stop operation order is "batting order 3" and "batting order 4" (that is, the middle reel 3C is first stopped), the winning "S_fake lip A" to "S_" are selected regardless of the timing of the stop operation. One of "Fake Clip C" is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (fake)). On the other hand, if the stop operation order is other than "batting order 2", "batting order 3" and "batting order 4", the winning "S_RT1 lip A" or "S_RT1 lip B" is displayed regardless of the timing of the stop operation. It is established and the RT state shifts to the RT1 state (RT1).

In addition, "maintenance (fake)" means that a specific symbol (in this case, a "blue BAR" symbol) is on a specific line different from the effective line, although a so-called "tempai" is applied to the specific line. It means not to line up. However, this specific line may be the same line as the effective line.

Further, in the game state (more specifically, the RT3 state) excluding the MB game state, "F_RT3_lip B1" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 1". If, "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). If the stop operation order is "batting order 3" and "batting order 4" (that is, the middle reel 3C is first stopped), the winning "C_TT_BL lip" or "S_TT_XD" is selected regardless of the stop operation timing. The "rip" is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (BAR)). On the other hand, if the stop operation order is other than "batting order 1", "batting order 3" and "batting order 4", the winning "S_RT1 lip A" or "S_RT1 lip B" is displayed regardless of the timing of the stop operation. It is established and the RT state shifts to the RT1 state (RT1).

Further, in the game state (more specifically, the RT3 state) excluding the MB game state, "F_RT3_lip B2" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 2". If, "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). If the stop operation order is "batting order 5" and "batting order 6" (that is, the right reel 3C is stopped first), the winning "C_TT_BL lip" or "S_TT_XD" is selected regardless of the timing of the stop operation. The "rip" is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (BAR)). On the other hand, if the stop operation order is other than "batting order 2", "batting order 5" and "batting order 6", the winning "S_RT1 lip A" or "S_RT1 lip B" is displayed regardless of the timing of the stop operation. It is established and the RT state shifts to the RT1 state (RT1).

Further, in the game state (more specifically, the RT3 state) excluding the MB game state, "F_RT3_lip B3" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 1". If, "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). If the stop operation order is "batting order 5" and "batting order 6" (that is, the right reel 3C is stopped first), the winning "C_TT_BL lip" or "S_TT_XD" is selected regardless of the timing of the stop operation. The "rip" is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (BAR)). On the other hand, if the stop operation order is other than "batting order 1", "batting order 5" and "batting order 6", the winning "S_RT1 lip A" or "S_RT1 lip B" is displayed regardless of the timing of the stop operation. It is established and the RT state shifts to the RT1 state (RT1).

Further, in the game state (more specifically, the RT3 state) excluding the MB game state, "F_RT3_lip B4" is a batting order, and when it is determined as an internal winning order, the stop operation order is "batting order 2". If, "S_TL lip" is established regardless of the timing of the stop operation, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). If the stop operation order is "batting order 3" and "batting order 4" (that is, the middle reel 3C is first stopped), the winning "C_TT_BL lip" or "S_TT_XD" is selected regardless of the stop operation timing. The "rip" is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (BAR)). On the other hand, if the stop operation order is other than "batting order 2", "batting order 3" and "batting order 4", the winning "S_RT1 lip A" or "S_RT1 lip B" is displayed regardless of the timing of the stop operation. It is established and the RT state shifts to the RT1 state (RT1).

Note that "maintenance (BAR)" means that a specific symbol (in this case, a "blue BAR" symbol) is lined up on a specific line different from the effective line. However, this specific line may be the same line as the effective line.

Further, in the game state (more specifically, the RT3 state) excluding the MB game state, "F_RT3_lip C1" and "F_RT3_lip C4" are batting order and stop when determined as an internal winning combination. If the operation order is "batting order 1" and "batting order 2" (that is, the left reel 3L is stopped first), "S_TL lip" is established regardless of the timing of the stop operation, and the RT3 state is maintained (that is, the RT3 state is maintained. Maintain). If the stop operation order is "batting order 3" and "batting order 4" (that is, the middle reel 3C is first stopped), the winning "S_fake lip A" to "S_" are selected regardless of the timing of the stop operation. One of "Fake C" is established, and the RT3 state is maintained (maintenance (fake)). If the stop operation order is "batting order 5" and "batting order 6" (that is, the right reel 3R is first stopped), the winning "C_SP_CL lip" and "S_SP_XU lip" are selected regardless of the stop operation timing. , Or "S_SP_TL lip" is established, and the RT3 state is maintained (maintenance (blue 7)).

In addition, in the gaming state (more specifically, the RT3 state) excluding the MB gaming state, "F_RT3_lip C2" and "F_RT3_lip C3" are batting orders and stop when determined as an internal winning combination. If the operation order is "batting order 1" and "batting order 2" (that is, the left reel 3L is stopped first), "S_TL lip" is established regardless of the timing of the stop operation, and the RT3 state is maintained (that is, the RT3 state is maintained. Maintain). If the stop operation order is "batting order 5" and "batting order 6" (that is, the right reel 3R is first stopped), the winning "S_fake lip A" to "S_" are selected regardless of the stop operation timing. One of "Fake C" is established, and the RT3 state is maintained (maintenance (fake)). If the stop operation order is "batting order 3" and "batting order 4" (that is, the middle reel 3C is first stopped), the winning "C_SP_CL lip" and "S_SP_XU lip" are selected regardless of the stop operation timing. , Or "S_SP_TL lip" is established, and the RT3 state is maintained (maintenance (blue 7)).

In addition, "maintenance (blue 7)" means that a specific symbol (in this case, the "blue 7" symbol) is lined up on an effective line or a specific line different from the effective line.

Further, in the game state (more specifically, RT1 state to RT3 state) excluding the MB game state, when "F_SP lip A" is determined not as a push order but as an internal winning combination, the stop operation order, And, regardless of the timing of the stop operation, "C_SP_CL lip" (blue 7 middle stage) is established. In this case, if the RT state is the RT1 state or the RT2 state, the state shifts to the RT3 state (RT3).

Further, in the game state (more specifically, RT1 state to RT3 state) excluding the MB game state, when "F_SP lip B" is determined not as a push order but as an internal winning combination, the stop operation order, And, regardless of the timing of the stop operation, "S_SP_XU lip" (blue 7 upper right) is established. In this case, if the RT state is the RT1 state or the RT2 state, the state shifts to the RT3 state (RT3).

Further, in the game state (more specifically, RT1 state to RT3 state) excluding the MB game state, when "F_SP lip C" is determined not as a push order but as an internal winning combination, the stop operation order, And, regardless of the timing of the stop operation, "S_SP_XD lip" (blue 7 lower right) is established. In this case, if the RT state is the RT1 state or the RT2 state, the state shifts to the RT3 state (RT3).

Further, in the game state (more specifically, RT1 state to RT3 state) excluding the MB game state, when "F_SP fake rip A" is determined not as a push order but as an internal winning combination, the stop operation order, And, regardless of the timing of the stop operation, "S_fake rip E" or "S_fake rip F" (blue 7 upper right fake) is established.

Further, in the gaming state excluding the MB gaming state (more specifically, RT1 state to RT3 state), when "F_SP fake rip B" is determined as an internal winning combination instead of a pushing order, the stop operation order, And, regardless of the timing of the stop operation, "S_fake clip B" or "S_fake clip D" (blue 7 lower right fake) is established.

Further, in the game state (more specifically, RT0 state to RT3 state) excluding the MB game state, when "F_chance lip A" is determined not as a push order but as an internal winning combination, the stop operation order , And regardless of the timing of the stop operation, "C_CL lip" (middle stage lip) is established.

Further, in the game state (more specifically, RT0 state to RT3 state) excluding the MB game state, "F_Batting order bell_1A" and "F_Batting order bell_1B" are push order combinations and are determined as internal winning combinations. In that case, if the stop operation order is "batting order 1", "S_BL bell" (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than "batting order 1", and if the stop operation timing is appropriate, the winning single-card combination (any of NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not appropriate, one of "S_RT1 transition A", "S_RT1 transition B", and "S_RT1 transition B" is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Whether or not the timing of the stop operation is appropriate is set as the timing when 1/2 of all the timings of the stop operation is appropriate and the timing of the other 1/2 is not appropriate. Has been done.

Further, in the gaming state (more specifically, RT0 state to RT3 state) excluding the MB game state, "F_batting order bell_2A" and "F_batting order bell_2B" are push order combinations and are determined as internal winning combinations. In this case, if the stop operation order is "batting order 2", the "S_BL bell" (lower bell) is established regardless of the stop operation timing, and nine medals are paid out. On the other hand, if the stop operation order is other than "batting order 2", and if the stop operation timing is appropriate, the winning single-card combination (any of NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not appropriate, one of "S_RT1 transition A", "S_RT1 transition B", and "S_RT1 transition B" is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Whether or not the timing of the stop operation is appropriate is set as the timing when 1/2 of all the timings of the stop operation is appropriate and the timing of the other 1/2 is not appropriate. Has been done.

Further, in the game state (more specifically, RT0 state to RT3 state) excluding the MB game state, "F_Batting order bell_3A" and "F_Batting order bell_3B" are push order combinations and are determined as internal winning combinations. In that case, if the stop operation order is "batting order 3", "S_BL bell" (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than "batting order 3", and if the stop operation timing is appropriate, the winning single-card combination (any of NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not appropriate, one of "S_RT1 transition A", "S_RT1 transition B", and "S_RT1 transition B" is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Whether or not the timing of the stop operation is appropriate is set as the timing when 1/2 of all the timings of the stop operation is appropriate and the timing of the other 1/2 is not appropriate. Has been done.

Further, in the game state (more specifically, RT0 state to RT3 state) excluding the MB game state, "F_Batting order bell_4A" and "F_Batting order bell_4B" are push order combinations and are determined as internal winning combinations. In that case, if the stop operation order is "batting order 4", "S_BL bell" (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than "batting order 4", and if the stop operation timing is appropriate, the winning single-card combination (any of NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not appropriate, one of "S_RT1 transition A", "S_RT1 transition B", and "S_RT1 transition B" is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Whether or not the timing of the stop operation is appropriate is set as the timing when 1/2 of all the timings of the stop operation is appropriate and the timing of the other 1/2 is not appropriate. Has been done.

Further, in the game state (more specifically, RT0 state to RT3 state) excluding the MB game state, "F_Batting order bell_5A" and "F_Batting order bell_5B" are push order combinations and are determined as internal winning combinations. In that case, if the stop operation order is "batting order 5", "S_BL bell" (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than "batting order 5", and if the stop operation timing is appropriate, the winning single-card combination (any of NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not appropriate, one of "S_RT1 transition A", "S_RT1 transition B", and "S_RT1 transition B" is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Whether or not the timing of the stop operation is appropriate is set as the timing when 1/2 of all the timings of the stop operation is appropriate and the timing of the other 1/2 is not appropriate. Has been done.

Further, in the game state (more specifically, RT0 state to RT3 state) excluding the MB game state, "F_Batting order bell_6A" and "F_Batting order bell_6B" are push order combinations and are determined as internal winning combinations. In that case, if the stop operation order is "batting order 6", "S_BL bell" (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than "batting order 6", and if the stop operation timing is appropriate, the winning single-card combination (any of NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not appropriate, one of "S_RT1 transition A", "S_RT1 transition B", and "S_RT1 transition B" is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Whether or not the timing of the stop operation is appropriate is set as the timing when 1/2 of all the timings of the stop operation is appropriate and the timing of the other 1/2 is not appropriate. Has been done.

In the RT4 state, "F_Batting order bell_1A" to "F_Batting order bell_6B" are no longer push order combinations, and when they are determined as internal winning combinations, regardless of the stop operation order and the stop operation timing. "S_BL bell" (lower bell) is established and 9 medals are paid out.

Further, in the gaming state excluding the MB gaming state (more specifically, the RT0 state to the RT4 state), when the "F_1 card combination" is determined not as a push order combination but as an internal winning combination, the stop operation order, Regardless of the timing of the stop operation and the stop operation, one medal combination (any of NML01 to NML12; see FIG. 18) is established, and one medal is paid out.

Further, in the gaming state excluding the MB gaming state (more specifically, the RT0 state to the RT4 state), the "F_weak chance combination" is not a push order combination but a stop operation order when it is determined as an internal winning combination. , And regardless of the timing of the stop operation, "S_weak chance" is established and three medals are paid out.

Further, in the gaming state excluding the MB gaming state (more specifically, RT0 state to RT4 state), the "F_medium chance combination" is not a push order combination but a stop operation order when it is determined as an internal winning combination. , And regardless of the timing of the stop operation, "S_Middle Chance" (upper right) is established and three medals are paid out.

Further, in the gaming state excluding the MB gaming state (more specifically, the RT0 state to the RT3 state), when the "F_strong bell" is determined not as a push order combination but as an internal winning combination, the stop operation order, And regardless of the timing of the stop operation, "S_CL bell" (middle) is established and 9 medals are paid out. In the RT4 state, "S_BL bell" (lower row) is established regardless of the stop operation order and the stop operation timing, and nine medals are paid out.

Further, in the gaming state excluding the MB gaming state, when the "F_common bell" is determined not as a push order combination but as an internal winning combination, the "S_BL bell" is determined regardless of the stop operation order and the stop operation timing. "(Lower row) is established, and nine medals are paid out.

In addition, in the game state excluding the MB game state (more specifically, the RT0 state to the RT3 state, and the BB game state), "F_black BAR" is determined not as a push order combination but as an internal winning combination. , The stop operation order, and the stop operation timing, "C_black BAR" is established and 7 medals are paid out. In the RT4 state, one medal combination (any of NML01 to NML12; see FIG. 18) is established regardless of the stop operation order and the stop operation timing, and one medal is paid out.

Further, in the gaming state excluding the MB gaming state (more specifically, the RT4 state and the BB gaming state), "F_special combination A" is stopped when it is determined as an internal winning combination instead of a push order combination. Regardless of the operation order and the timing of the stop operation, "1 for C_CB" is established and 14 medals are paid out.

Further, in the gaming state (more specifically, the RT4 state) excluding the MB gaming state, when the "F_special combination B" is determined not as a pushing order combination but as an internal winning combination, the stop operation order and stop Regardless of the timing of the operation, "2 for C_CB" is established and 13 medals are paid out.

Further, in the gaming state (more specifically, the RT4 state) excluding the MB gaming state, when the "F_special combination C" is determined not as a pushing order combination but as an internal winning combination, the stop operation order and stop Regardless of the timing of the operation, "C_special role" is established and one medal is paid out.

In addition, in the gaming state excluding the MB gaming state (more specifically, the BB gaming state), when the "F_BB medium chance combination A" is determined as an internal winning combination instead of a pushing order, the stop operation order, And regardless of the timing of the stop operation, "S_Chance 1" (Chance 1 during BB) is established and 9 medals are paid out.

Further, in the gaming state excluding the MB gaming state (more specifically, the BB gaming state), when the "F_BB middle chance combination B" is determined as an internal winning combination instead of a pushing order, the stop operation order, And regardless of the timing of the stop operation, "S_Chance 2" (Chance 2 during BB) is established and 9 medals are paid out.

Further, in the gaming state excluding the MB gaming state (more specifically, the BB gaming state), when the "F_BB middle chance combination C" is determined as an internal winning combination instead of a pushing order combination, the stop operation order, And regardless of the timing of the stop operation, "S_Chance 3" (Chance 3 during BB) is established and 9 medals are paid out.

Further, in the gaming state excluding the MB gaming state (more specifically, the RT0 state to the RT3 state), when "F_MB" is determined not as a push order combination but as an internal winning combination, the stop operation order and stop Regardless of the timing of the operation, "C_MB" (MB) is established and the MB game state is activated.

Further, in the gaming state excluding the MB gaming state (more specifically, RT0 state to RT3 state), "BB + F_chance lip B" is "F_BB" when it is determined as an internal winning combination instead of a push order combination. Is carried over as a carry-over combination, the RT state shifts to the RT4 state, and "C_chance lip" (special lip) is established regardless of the stop operation order and the stop operation timing.

In the present embodiment, when the replay combination and the bonus combination are determined as the internal winning combination (including the case where the bonus combination is carried over), the replay combination is preferentially established over the bonus combination. Stop control is performed. However, it is also possible to perform stop control in which the bonus combination is preferentially established over the replay combination.

Further, in the gaming state excluding the MB gaming state (more specifically, RT0 state to RT3 state), "BB + F_special combination A" is "F_BB" when it is determined as an internal winning combination instead of a push order combination. Is carried over as a carry-over combination, the RT state shifts to the RT4 state, and "1 for C_CB" is established regardless of the stop operation order and the stop operation timing, and 14 medals are paid out.

In addition, in the gaming state (more specifically, RT0 state to RT3 state) excluding the MB gaming state, "BB + F_special combination B" is "F_BB" when it is determined as an internal winning combination instead of a push order combination. Is carried over as a carry-over combination, the RT state shifts to the RT4 state, and "2 for C_CB" is established regardless of the stop operation order and the stop operation timing, and 13 medals are paid out.

In addition, in the gaming state excluding the MB gaming state (more specifically, RT0 state to RT3 state), "BB + F_special combination C" is "F_BB" when it is determined as an internal winning combination instead of a push order combination. Is carried over as a carry-over combination, the RT state shifts to the RT4 state, and "C_special combination" is established regardless of the stop operation order and the stop operation timing, and one medal is paid out.

In the present embodiment, when the small winning combination and the bonus winning combination are determined as the internal winning combination (including the case where the bonus combination is carried over), the small winning combination is preferentially established over the bonus combination. Stop control is performed. However, it is also possible to perform stop control for preferentially establishing a bonus combination over a small combination.

As shown in FIG. 21, in the MB game state, "F_normal lip", "F_RT1_RT2U lip 1" to "F_RT1_RT2U lip 6", "F_RT2_RT3U lip 1" to "F_RT2_RT3U lip 6", "F_RT2 maintenance lip 1" to " "F_RT2 maintenance rip 6", "F_SP rip A", "F_SP rip B", "F_SP rip C", "F_SP fake rip A", "F_SP fake rip B", "F_chance rip A" are not push order. When determined as an internal winning combination, "1 for C_CB" is established regardless of the stop operation order and the stop operation timing, and 14 medals are paid out.

Further, in the MB game state, "F_RT3 lip A1", "F_RT3 lip B1", and "F_RT3 lip C1" are push order combinations, and the stop operation order is "batting order 1" and "batting order 2" (that is, left). If the reel 3L is first stopped), “2 for C_CB” is established regardless of the timing of the stop operation, and 13 medals are paid out. On the other hand, if the stop operation order is other than "batting order 1" and "batting order 2", "1 for C_CB" is established regardless of the timing of the stop operation, and 14 medals are paid out.

Further, in the MB game state, "F_RT3 lip A2", "F_RT3 lip B2", and "F_RT3 lip C2" are push order combinations, and the stop operation order is "batting order 3" and "batting order 4" (that is, medium). If the reel 3C is stopped first), "2 for C_CB" is established regardless of the timing of the stop operation, and 13 medals are paid out. On the other hand, if the stop operation order is other than "batting order 3" and "batting order 4", "1 for C_CB" is established regardless of the timing of the stop operation, and 14 medals are paid out.

Further, in the MB game state, "F_RT3 rip A3", "F_RT3 rip A4", "F_RT3 rip B3", "F_RT3 rip B4", "F_RT3 rip C3", and "F_RT3 rip C4" are batting orders. If the stop operation order is "batting order 5" and "batting order 6" (that is, the right reel 3R is stopped first), "2 for C_CB" is established regardless of the timing of the stop operation, and 13 medals are awarded. It will be paid out. On the other hand, if the stop operation order is other than "batting order 5" and "batting order 6", "1 for C_CB" is established regardless of the timing of the stop operation, and 14 medals are paid out.

Here, in the MB game state, it is considered that the push order in which 14 medals are always paid out is advantageous for the player, but in the present embodiment, the payout of medals in which the MB game state exceeds "13" is paid out. Since it is configured to end with, if 13 medals are paid out in the first game in the MB game state, the second game in the MB game state can be performed, and further 14 You will be able to receive a payout of medals. Therefore, if the above-mentioned push order combination is determined as the internal winning combination in the first game in the MB game state, the push order in which 13 medals are paid out is an advantageous stop operation for the player. It becomes information, and if the above-mentioned push order combination is determined as the internal winning combination in the second game in the MB game state, the push order in which 14 medals are paid out is an advantageous stop operation for the player. It becomes the information of.

In the present embodiment, whether or not the timing of the stop operation is appropriate in both the case where 13 medals are paid out and the case where 14 medals are paid out in the MB game state is determined. It is configured so that it is not required, but if the timing of the stop operation is appropriate so that the technical intervention of the game can be enhanced and the soundness of the game can be ensured, 13 or 14 cards will be used. However, if the timing of the stop operation is not appropriate, 13 or 14 medals may not be paid out.

Further, in the present embodiment, when the replay combination and the small combination are determined as the internal winning combination in the MB game state, the stop control for preferentially establishing the small combination over the replay combination is performed. Although it is configured, it can also be configured so that stop control is performed so that the replay combination is preferentially established over the small combination.

As described above with reference to FIGS. 19 to 21, the pushing order is uniquely defined in the pushing order, which is advantageous for the player. In the present embodiment, when the gaming state is the ART gaming state, the information of the stop operation indicating the pushing order which is advantageous for the player is notified. That is, in the RT4 state which is the bonus winning state and the gaming state other than the BB gaming state which is the bonus state, the RT state shifts to the RT3 state and the RT state is maintained in the RT3 state. In addition, the stop operation order is notified as stop operation information so that the player can receive more medals to be paid out.

In the present embodiment, the stop operation information that is advantageous to the player is transmitted by the instruction monitor controlled by the main control board 71 and other means (for example, the display device 11) controlled by the sub control board 72. Be notified.

For example, when "batting order 1" and "batting order 2" are batting orders that are advantageous to the player, the numerical value "1" is displayed on the instruction monitor, and the pressing order "1--" is displayed on the display device 11. Is displayed, and when "batting order 3" and "batting order 4" are the batting order that is advantageous to the player, the numerical value "2" is displayed on the instruction monitor, and the pressing order "2" is displayed on the display device 11. When "-1-" is displayed and "batting order 5" and "batting order 6" are pushing orders that are advantageous to the player, the numerical value "3" is displayed on the instruction monitor and the display device 11 displays. The batting order "--1" is displayed.

Further, for example, when the "hit order 1" is a push order that is advantageous to the player, the numerical value "4" is displayed on the instruction monitor, and the push order "123" is displayed on the display device 11. When the "hit order 2" is a push order that is advantageous to the player, the numerical value "5" is displayed on the instruction monitor, the push order "132" is displayed on the display device 11, and the "hit order 3" is displayed. However, when the push order is advantageous for the player, the numerical value "6" is displayed on the instruction monitor, the push order "213" is displayed on the display device 11, and the "hit order 4" is the player. When the push order is advantageous to the player, the numerical value "7" is displayed on the instruction monitor, the push order "312" is displayed on the display device 11, and the "hit order 5" is advantageous to the player. In the case of the push order, the numerical value "8" is displayed on the instruction monitor, the push order "231" is displayed on the display device 11, and the "hit order 6" is a push order that is advantageous to the player. In this case, the numerical value "9" is displayed on the instruction monitor, and the pressing order "321" is displayed on the display device 11.

Of course, the mode in which the push order that is advantageous to the player is notified is not limited to the above-mentioned one, and any mode may be used as long as the player can recognize the push order that is advantageous to the player. For example, instead of, or in combination with the instruction monitor and / or display device 11, the sub-display device 18, the LED group 85, the speaker group 84, and the like can be used to notify the player of the pressing order that is advantageous to the player. ..

As long as there is no disadvantage to the player, the instruction monitor and / or the display device 11 notifies the pressing order other than the pressing order that is advantageous to the player for the purpose of enhancing the playability and the effect of the effect. You can also do it. An example thereof will be described later with reference to FIGS. 33 (c), 69, and 70, which will be described later.

Here, the reel stop control (method for determining the stop symbol position) in the pachi-slot machine 1 of the present embodiment will be briefly described. In the present embodiment, after the stop operation is detected by the stop switch, the reel stop control is performed so that the rotation of the corresponding reel is stopped within 190 msec (within 75 msec for a specific reel in the MB gaming state). Specifically, the value of the symbol counter corresponding to the corresponding reel when the stop operation is detected is the number of sliding pieces "0" to "4" ("0" or "1" for a specific reel in the MB game state. ”) Is added, and the symbol position corresponding to the obtained value is determined as the symbol position where the rotation of the reel stops (hereinafter, referred to as“ scheduled stop position ”). The symbol position corresponding to the value of the symbol counter corresponding to the corresponding reel when the stop operation is detected is the symbol position where the rotation of the reel is started (hereinafter, referred to as "stop start position").

That is, the number of sliding pieces is the amount of rotation of the reel from the time when the stop operation is detected by the stop switch until the rotation of the corresponding reel is stopped. In other words, it is the number of symbols that pass through the middle region of the corresponding reel of the reel display window 4 in the period from the detection of the stop operation by the stop switch to the stop of the rotation of the corresponding reel. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

With reference to a stop table (not shown), the number of sliding pieces is acquired according to the stop start position of each reel. In the present embodiment, the number of sliding pieces is acquired based on the stop table, but this is tentative, and the acquired number of sliding pieces does not immediately determine the scheduled stop position of the reel. In the present embodiment, when there is a more appropriate number of sliding pieces than the number of sliding pieces acquired based on the stop table (hereinafter referred to as “sliding piece number determination data”), a pull-in priority table (not shown) is referred to. And change the number of sliding pieces. Then, the sliding piece number determination data compares the priority order of each symbol from the stop start position to the symbol position of 4 points ahead (1 point ahead for a specific reel in the MB game state) which is the maximum number of sliding pieces. Referenced to determine the search order when doing so.

<Structure of storage area provided in main RAM>
Next, the configurations of various storage areas provided in the main RAM 103 will be described with reference to FIGS. 22 to 27.

[Hit request flag storage area and winning operation flag storage area]
First, with reference to FIG. 22, the configuration of the hit request flag storage area (internal winning combination storage area) and the winning operation flag storage area (display combination storage area) will be described. In the present embodiment, the hit request flag storage area (flag data storage area, winning flag data storage area) and the winning operation flag storage area (winning flag data storage area) have the same configuration.

In the present embodiment, the hit request flag storage area is composed of the hit request storage areas 1 to 7 each represented by 1 byte of data, and the winning operation flag storage area is each represented by 1 byte of data. It is composed of storage areas 1 to 7. The data stored in each storage area of the hit request flag storage area and the winning operation flag storage area is only the 1-byte data in the "data" column in FIG. 22, but in FIG. 22, for convenience of explanation, each data is stored. "Combination" indicating the symbol combination of each reel associated with the bit of the storage area (in the figure, the symbol of the left reel 3L, the symbol of the middle reel 3C, and the symbol of the right reel 3R are described in this order), and the symbol thereof. The contents (see FIG. 18) are also described.

When "1" is stored in a predetermined bit in each of the hit request flag storage areas 1 to 7, it indicates that the internal winning combination corresponding to the predetermined bit has won the internal winning. Further, when "1" is stored in a predetermined bit in each of the winning operation storage areas 1 to 7, it indicates that the display combination (winning operation flag) corresponding to the predetermined bit has won a prize. That is, when "1" is stored in the predetermined bit, it indicates that the symbol combination corresponding to the predetermined bit is displayed on the valid line.

Further, in the hit request flag storage area and the winning operation flag storage area, as shown in FIG. 22, a plurality of symbol combinations (combinations) are assigned to one bit (flag) in each storage area. There is also (see FIG. 18). That is, for such a flag, it means that there are a plurality of symbol combinations (combinations that can win a prize) that can be stopped and displayed.

[Carryover storage area]
Next, the configuration of the carry-over combination storage area will be described with reference to FIG. 23. In the present embodiment, the carry-over combination storage area is composed of a 1-byte data storage area.

When the internal winning combination "F_BB" or "F_MB" is determined as a result of the internal lottery, the internal winning combination (bonus combination) is stored in the carry-over combination storage area as a carry-over combination. The carry-over combination stored in the carry-over combination storage area is retained without being cleared until the corresponding symbol combination is displayed on the valid line. Further, while the carry-over combination is stored in the carry-over combination storage area, the carry-over combination is stored in the winning request storage area in addition to the internal winning combination determined by the internal lottery.

[Game status flag storage area]
Next, the configuration of the game state flag storage area will be described with reference to FIG. 24. The game state flag storage area is composed of a 1-byte data storage area. In the present embodiment, as shown in FIG. 24, a unique bonus type or RT type is assigned to each bit in the game state flag storage area.

When "1" is stored in a predetermined bit in the game state flag storage area, it indicates that the bonus game or RT corresponding to the predetermined bit is being operated. For example, when "1" is stored in bit 0 of the game state flag storage area, the big bonus "BB" is being operated, indicating that the game state is the BB game state. Further, for example, when "1" is stored in bit 6 of the game state flag storage area, it indicates that the game state is the RT3 state.

[Operation stop button storage area]
Next, the configuration of the operation stop button storage area will be described with reference to FIG. The operation stop button storage area is composed of a 1-byte data storage area, and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operation state of the stop button is assigned to each bit.

For example, when the left stop button 17L is the stop button pressed this time, that is, the operation stop button, "1" is stored in bit 0 of the operation stop button storage area. Further, for example, when the left stop button 17L is a stop button that has not yet been pressed, that is, an effective stop button, "1" is stored in bit 4. The main CPU 101 distinguishes between the stop button pressed this time and the stop button that has not yet been pressed, based on the data stored in the operation stop button storage area.

[Press order storage area]
Next, the configuration of the pressing order storage area will be described with reference to FIG. The press order storage area is composed of a 1-byte data storage area, and stores a 1-byte press order flag.

In the pressing order flag, each bit is assigned the type of pressing order of the stop button. For example, when the pressing order of the stop buttons is "left, middle, right", "1" is stored in bit 0 of the pressing order storage area.

[Design code storage area]
Next, the configuration of the symbol code storage area will be described with reference to FIG. 27. In the present embodiment, each of the symbol code storage areas is composed of symbol code storage areas 1 to 7 represented by 1 byte of data. The symbol code storage area has the same configuration as the hit request flag storage area and the winning operation flag storage area (see FIG. 22).

In the symbol code storage area, "1" is stored in the bit corresponding to the symbol combination (combination) that can be stopped on the effective line. After all the reels are stopped, the symbol code corresponding to the display combination (winning operation flag) is stored in the symbol code storage areas 1 to 7.

<Data table configuration related to ART function>
Next, with reference to FIGS. 28 to 33, the configurations of various data tables stored in the main ROM 102 and related to the ART function will be described.

[Specific internal state related to ART function]
First, with reference to FIG. 28, a specific internal state (hereinafter, simply referred to as “mode”) which is one lottery element at the time of lottery related to the ART function in the present embodiment will be described.

In the pachislot machine 1 of the present embodiment, as the non-ART gaming state mode (normal mode), "low probability 1", "low probability 2", "heaven preparation", "heaven short", "heaven long", and "heaven long" It defines "super heaven" and is managed by the main CPU 101. Further, although not shown in FIG. 28, as a normal mode, a "precursor mode" is defined in which the transition to the ART gaming state is determined, but the transition to the ART gaming state is awaited. , Managed by the main CPU 101. The "precursor mode" can further define a plurality of "precursor modes" in which the number of precursor games (that is, the number of games until the transition to the ART gaming state) is different. During the "precursor mode", a continuous effect (that is, an effect executed over a plurality of games) for increasing the expectation of the player to shift to the ART game state is mainly executed according to the number of precursor games.

The contents of the normal mode are as shown in FIG. 28, and the degree of expectation of the ART game state transition (ART stock acquisition) is different in each normal mode. Specifically, the lottery state is relatively disadvantageous to the player in the order of "low probability 1", "low probability 2", "heaven preparation", "heaven short", "heaven long", and "super heaven". It is configured so that the lottery state is relatively advantageous for the player.

Further, in the pachi-slot machine 1 of the present embodiment, "low accuracy", "high accuracy preparation", "high accuracy", and "ultra-high accuracy" are defined as the ART gaming state mode (ART mode), and the main CPU 101 Managed by.

The contents of the ART mode are as shown in FIG. 28, and the degree of expectation of the continuation of the ART gaming state (CP acquisition) is different in each ART mode. Specifically, in the order of "low accuracy", "high accuracy preparation", "high accuracy", and "ultra-high accuracy", the lottery state that is relatively disadvantageous to the player is changed to the lottery that is relatively advantageous to the player. It is configured to be in a state.

It should be noted that the ART mode may not only have different expectations for CP acquisition, but may also have different expectations for the addition of the number of ART games and the addition of ART stock, in order to make these expectations different. In addition, a plurality of different modes (for example, additional modes) may be specified.

[Normal ART lottery table]
Next, the lottery table used in the ART lottery performed in the "normal time" will be described with reference to FIG. 29. FIG. 29 is a diagram showing an example of a normal ART lottery table when the set value is “1” and the probability denominator is “256”. It should be noted that this normal ART lottery table is a table that is referred to at the time of the ART lottery performed every game in the normal middle start processing (see S415 of FIG. 68 described later).

In FIG. 29, "normal role 1" is "missing" (winning number "0"), "F_normal lip" (winning number "1"), "F_RT1_RT2U lip 1" to "F_RT1_RT2U lip 6" (winning number "1"). 2 "to" 7 ")," F_RT2_RT3U Lip 1 "to" F_RT2_RT3U Lip 6 "(win numbers" 8 "to" 13 ")," F_RT2 maintenance lip 1 "to" F_RT2 maintenance lip 6 "(win number" 14 " ~ "19"), "F_RT3 Lip A1" ~ "F_RT3 Lip A4" (win numbers "20" ~ "23"), "F_RT3 Lip B1" ~ "F_RT3 Lip B4" (win numbers "24" ~ "27" ), And "F_RT3 Lip C1" to "F_RT3 Lip C4" (win numbers "28" to "31").

Further, in FIG. 29, "normal role 2" is "F_batting order bell 1A" to "F_batting order bell 6A" and "F_batting order bell 1B" to "F_batting order bell 6B" (win numbers "39" to "50"). ), "F_1 card combination" (winning number "51"), "F_common bell" (winning number "55"), "F_special role A" (winning number "57"), "F_special role B" (winning) The numbers "58"), "F_special role C" (winning number "59"), and "F_MB" (winning number "63") are indicated.

Further, in FIG. 29, "chance lip" includes "F_SP fake lip A" (win number "35"), "F_SP fake lip B" (win number "36"), and "F_chance lip A" (win number "37"). ") Is shown.

Further, in FIG. 29, “strong bell” indicates “F_strong bell” (win number “54”).

Further, in FIG. 29, the “weak chance combination” indicates “F_weak chance combination” (win number “52”).

Further, in FIG. 29, the “middle chance combination” indicates “F_middle chance combination” (winning number “53”).

Further, in FIG. 29, the “MB combination” indicates that all the small combinations have been established in the MB game state.

In the pachi-slot machine 1 of the present embodiment, the lottery related to the ART function is performed on the main control circuit 90 side. Therefore, in order to reduce the control burden in the lottery related to the ART function, when the above-mentioned internal winning combination is determined, information (grouping information) for grouping these internal winning combinations is generated (that is, internal). The information related to the winning combination may be compressed), and the lottery related to the ART function may be performed based on the generated grouping information.

For example, when the internal winning combination corresponding to the above-mentioned "normal combination 1" is determined, "0" is generated as grouping information, and when the internal winning combination corresponding to the "normal combination 2" is determined, the group. When "1" is generated as the conversion information and the internal winning combination corresponding to the "chance lip" is determined, "2" is generated as the grouping information and the internal winning combination corresponding to the "strong bell" is determined. In that case, "3" is generated as the grouping information, and when the internal winning combination corresponding to the "weak chance combination" is determined, "4" is generated as the grouping information and corresponds to the "medium chance combination". When the internal winning combination is determined, "5" is generated as the grouping information, and when the internal winning combination corresponding to the "MB combination" is determined, "6" is generated as the grouping information, and these groups The ART lottery may be performed based on the information. The same applies to the mode transition lottery shown in FIG. 30 described later and the CP acquisition lottery shown in FIG. 32 described later.

In the normal time ART lottery table shown in FIG. 29, the player shifts to the ART game state (winning) or does not shift to the ART game state based on the internal winning combination, the current normal mode, and the random value for production. (Non-win) is decided.

[Normal mode transition lottery table]
Next, with reference to FIG. 30, a lottery table used in the mode transition lottery performed in the “normal time” will be described. FIG. 30 is a diagram showing an example of a normal mode transition lottery table when the set value is “1” and the probability denominator is “256”. It should be noted that this normal mode transition lottery table is a table that is referred to at the time of the mode transition lottery performed every game in the normal middle start processing (see S415 of FIG. 68 described later).

In FIG. 30, “normal role 1”, “normal role 2”, “chance lip”, “strong bell”, “weak chance role”, “medium chance role”, and “MB role” are described in FIG. 29. As already mentioned in.

In the normal time ART lottery table shown in FIG. 30, the normal mode (transition destination) of the migration destination is determined based on the internal winning combination, the current normal mode, and the random value for effect.

[CP acquisition lottery table in CP special zone]
Next, with reference to FIG. 31, the lottery table used in the CP acquisition lottery performed in the “CB medium CP specialization zone” will be described. FIG. 31 is a diagram showing an example of a CP acquisition lottery table in the CP specialization zone when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. In addition, this CP acquisition lottery table in the CP special zone is a table referred to at the time of the CP acquisition lottery performed every game in the start time processing in the CP special zone in BB (see S405 in FIG. 68 described later). is there.

In FIG. 31, "normal role" indicates "F_common bell" (win number "55"), and "rare role" is "F_BB middle chance role A" (win number "60"), " F_BB middle chance role B "(win number" 61 ") and" F_BB middle chance role C "(win number" 62 ") are shown, and" special role "is" F_special role A "(win number). It indicates "57").

As described above, the grouping information may be generated also in the "CB special zone in BB" (that is, the BB game state). For example, when the internal winning combination corresponding to the "normal combination" is determined, "0" is generated as the grouping information, and when the internal winning combination corresponding to the "rare combination" is determined, "0" is generated as the grouping information. When "1" is generated and the internal winning combination corresponding to the "special combination" is determined, "2" is generated as grouping information so that the CP acquisition lottery is performed based on these grouping information. May be good.

In the CP acquisition lottery table in the CP specialization zone shown in FIG. 31, CP is added (winning) or CP is not added based on the internal winning combination, the current state, and the random value for production (winning). Non-winning) is decided. In the present embodiment, when it is decided to add CP (winning), CP can be acquired by "1" (that is, the CP counter is added by "1").

Although not shown, a state lottery is performed even at the start of the "BB medium CP specialization zone" as described later with reference to FIG. 33 (A), and the lottery result is obtained. Therefore, the internal state of "state 1" or "state 2" is set. Then, as shown in FIG. 31, CP is more easily acquired when "state 2" is set than when "state 1" is set. In that sense, "state 2" is an internal state that is more advantageous to the player than "state 1".

[CP acquisition lottery table in double specialization zone]
Next, with reference to FIG. 32, the lottery table used in the CP acquisition lottery performed in the “double specialization zone” will be described. FIG. 32 is a diagram showing an example of a CP acquisition lottery table in the double specialization zone when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. The CP acquisition lottery table in the double specialization zone is a table referred to at the time of the CP acquisition lottery performed in S433 of the start processing in the double specialization zone, which will be described later with reference to FIGS. 69 and 70. is there.

In FIG. 32, “normal role 1”, “normal role 2”, “chance lip”, “strong bell”, “weak chance role”, “medium chance role”, and “MB role” are described in FIG. 29. As already mentioned in.

In the CP acquisition lottery table in the double specialization zone shown in FIG. 32, it is decided whether to add CP (win) or not to add CP (non-win) based on the internal winning combination and the random value for production. Will be done. In the present embodiment, when it is decided to add CP (winning), CP can be acquired by "1" (that is, the CP counter is added by "1").

[State lottery table at the start of the double specialization zone]
Next, a lottery table used in the state lottery performed at the start of the "double specialization zone" will be described with reference to FIG. 33 (A). FIG. 33A is a diagram showing an example of a double specialization zone start state lottery table when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. Is. The double-specialized zone start state lottery table is a table referred to at the time of the state lottery performed in S422 of the double-specialized zone start-time processing described later with reference to FIGS. 69 and 70. ..

As will be described later with reference to FIG. 33 (D), the "double specialization zone" ends when "state 2" is set rather than when "state 1" is set. It's getting harder. In that sense, "state 2" is an internal state that is more advantageous to the player than "state 1".

In the double specialization zone start state lottery table shown in FIG. 33A, "state 1" or "state 2" is determined as the internal state in the double specialization zone based on the random value for production. ..

[Double special zone middle blue 7 o'clock CP acquisition lottery table]
Next, referring to FIG. 33 (B), in the "double specialization zone", when "RT3 lip C" (that is, "F_RT3_lip C1" to "F_RT3_lip C4") is determined as an internal winning combination. The lottery table used in the CP acquisition lottery performed in the above will be described. FIG. 33 (B) shows an example of a blue 7 o'clock CP acquisition lottery table in the double special zone when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. It is a figure which shows. It should be noted that this double special zone middle blue 7 o'clock CP acquisition lottery table is referred to at the time of the CP acquisition lottery performed in S430 of the double special zone middle start processing described later with reference to FIGS. 69 and 70. It is a table.

In the double special zone middle blue 7 o'clock CP acquisition lottery table shown in FIG. 33 (B), it is decided to add CP (winning) or not to add CP (non-winning) based on the random value for production. Will be done. In the present embodiment, when it is decided to add CP (winning), CP can be acquired by "1" (that is, the CP counter is added by "1").

[Double Special Zone Medium Blue 7 Fake Lottery Table]
Next, with reference to FIG. 33 (C), when "RT3 lip A" (that is, "F_RT3_lip A1" to "F_RT3_lip A4") is determined as an internal winning combination in the "double specialization zone". The lottery table used in the blue 7 fake notification lottery performed in 1) will be described. FIG. 33C shows an example of a blue 7 fake lottery table in the double specialization zone when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. It is a figure. The blue 7 fake lottery table in the double special zone is referred to at the time of the blue 7 fake notification lottery performed in S424 of the start processing in the double special zone, which will be described later with reference to FIGS. 69 and 70. It is a table.

In the double special zone middle blue 7 fake lottery table shown in FIG. 33 (C), blue 7 fake notification is performed (winning) or blue 7 fake notification is not performed (non-winning) based on the random value for production. ) Is determined. In this embodiment, when it is decided to perform the blue 7 fake notification (winning), the "double specialization zone" does not end. That is, although the privilege of being able to acquire ART stock is not received, the privilege of not ending the "double specialization zone" is received when the blue fake notification is made. Details will be described later with reference to FIGS. 69 and 70.

The data structure of the double special zone middle blue 7 o'clock CP acquisition lottery table shown in FIG. 33 (B) and the double special zone middle blue 7 fake lottery table shown in FIG. 33 (C) are the same. Therefore, it may be defined as a common lottery table (that is, one table) in which the same address is referred to when each lottery is performed. With this specification, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to enhance the playability.

[Double special zone end lottery table]
Next, the lottery table used in the end lottery of the "double specialization zone" will be described with reference to FIG. 33 (D). FIG. 33 (D) is a diagram showing an example of a double specialization zone end lottery table when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. .. The double special zone end lottery table is a table referred to at the time of the end lottery performed in S441 of the double special zone middle start process described later with reference to FIGS. 69 and 70.

In the double specialization zone end lottery table shown in FIG. 33 (D), the double specialization zone is not ended (winning) or the double specialization zone is not ended based on the current state and the random value for production. It is decided (that is, to continue) (non-winning).

<Structure of data table related to special effects>
Next, with reference to FIGS. 34 and 35, the configuration of various data tables stored in the data storage area of the ROM cartridge substrate 86, particularly related to the special effect, will be described.

[Judgment value for special production lottery]
First, with reference to FIG. 34, the determination value for the special effect lottery used for the reserved lottery for the special effect in the present embodiment will be described.

In the pachi-slot machine 1 of the present embodiment, the specific internal state (mode) related to the ART function changes mainly as described with reference to FIGS. 28 to 30. The special effect is an effect executed to suggest a change in this mode, and a determination value for special effect lottery is predetermined in order to determine whether or not the change in the mode is the target of the special effect execution. Has been done.

As shown in FIG. 34, the determination value "0" determines that the current normal mode is the "precursor mode" and the number of precursor games is "1" or more in the "normal time".

In addition, the judgment value "1" indicates that the normal mode has shifted from "low probability 1" to "heaven preparation" to "heaven short" or higher as a result of the mode transition lottery (see FIG. 30) in "normal time". judge.

Further, the judgment value "2" indicates that the normal mode has shifted from "low probability 1" or "low probability 2" to "heaven preparation" as a result of the mode transition lottery (see FIG. 30) in the "normal time". judge.

Further, the determination value "3" determines that the normal mode has shifted to "heaven long" or higher as a result of the mode transition lottery (see FIG. 30) in the "normal time".

Further, the determination value "4" determines that the result of the mode transition lottery (see FIG. 30) in the "normal time" is another case.

The determination value "5" is set to "normal ART", in which the current ART mode is determined to be "additional precursor mode" (that is, ART stock or the number of ART games is added, but the addition is awaited. Mode) and the number of precursor games is "1" or more.

Further, the determination value "6" determines that the ART mode has shifted from "high accuracy preparation" or less to "high accuracy" or more as a result of the mode transition lottery (not shown) in "normal ART".

Further, the determination value "7" determines that the ART mode has shifted from "low accuracy" or less to "high accuracy preparation" as a result of the mode transition lottery (not shown) in "normal ART".

Further, the determination value "8" determines that the ART mode has shifted to "high accuracy" or higher as a result of the mode transition lottery (not shown) in the "normal ART".

Further, the determination value "9" determines that the result of the mode transition lottery (not shown) in the "normal ART" is another case.

Although the conditions defined by the above-mentioned determination values may overlap, the sub CPU 201 determines whether or not the conditions defined by the determination values are met in order from the top (that is, in the order of "0" to "9"). In order to make a judgment, when the conditions defined by the judgment values overlap, the judgment value having a smaller judgment value is selected.

[Normal special production reservation lottery table]
Next, with reference to FIG. 35, a lottery table used in the reserved lottery of the special effect will be described. FIG. 35 is a diagram showing an example of a normal special effect reservation lottery table when the probability denominator is “32768”. The normal special effect reservation lottery table is a table referred to at the time of the reservation lottery performed in S1194 of the special effect reservation process described later with reference to FIG. 121.

In the normal special effect reservation lottery table shown in FIG. 35, information on the lottery value is conceptually shown. "0" in the table means that the lottery value "0" is specified, and "extremely low" means that the lottery value is specified in the range of "1" to "99". To do. Further, "low" in the table means that the lottery value is defined in the range of "100" to "999", and "medium" means that the lottery value is in the range of "1000" to "9999". "High" means that the lottery value is specified in "10000" or more. Further, "all remaining" in the table means that the remaining value obtained by subtracting other lottery values from the probability denominator "32768" is defined as the lottery value. For example, if the lottery values such as "all remaining", "0", "0", and "0" are specified in the table, the lottery value of the "all remaining" is "32768".

Further, in the normal special effect reservation lottery table shown in FIG. 35, the special effect "none" corresponds to the special effect reservation parameter "0" described later, and the special effect "weak" corresponds to the special effect reservation parameter "1" described later. The special effect "medium" corresponds to the special effect reservation parameter "2" described later, and the special effect "strong" corresponds to the special effect reservation parameter "3" described later.

The special effect "none" indicates that the special effect is not reserved, and the special effect "weak" indicates that, for example, a light effect image is weakly wavy as a special effect. Yes, the special effect "medium" indicates that, for example, a light effect image is strongly wavy as a special effect, and the special effect "strong" is a special effect, for example, a light effect. This indicates that the effect of continuously waving the image is executed.

In the normal special production reservation lottery table shown in FIG. 35, the internal winning combination "MB medium bell" is synonymous with the above-mentioned "MB medium lip", and the internal winning combination "RT3 medium lip" is "F_RT3_lip A1". "F_RT3_lip C4", the internal winning combination "blue 7 fake" indicates "F_SP fake rip A" and "F_SP fake rip B", and the internal winning combination "blue 7" indicates "blue 7". It indicates "F_SP lip A" to "F_SP lip C".

In the normal special effect reservation lottery table shown in FIG. 35, the special effect reservation parameter “0” is based on the determination value (see FIG. 34), the internal winning combination, and the effect random value extracted on the sub-control circuit 200 side. "" To "3" is determined.

<Explanation of operation of main control circuit>
Next, with reference to FIGS. 36 to 112, the contents of various processes executed by the main CPU 101 of the main control circuit 90 by using the program will be described.

[Processing when power is turned on (reset interrupt)]
First, the power-on (reset interrupt) processing of the pachi-slot machine 1 performed under the control of the main CPU 101 will be described with reference to FIGS. 36 and 37. FIG. 36 is a flowchart showing the procedure at the time of power-on (reset interrupt), and FIGS. 37A to 37C are sources for executing the processes of S2, S7 and S8 and S13 in the flowchart, respectively. It is a figure which shows an example of a program. In the power-on (reset interrupt) processing shown in FIG. 36, when the power management circuit 93 detects that the supply of the power supply voltage to the microprocessor 91 has started, the reset signal is sent to the microprocessor 91. It is output to the "XSRST" terminal, and is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

First, the main CPU 101 determines whether or not the power supply monitoring port (power supply monitoring means) is in the ON state (S1).

When the main CPU 101 determines in S1 that the power supply monitoring port is in the ON state (when the determination in S1 is YES), the main CPU 101 repeats the process of S1. The state in which the power supply monitoring port is turned on here means a state in which the power supply voltage (DC + 5V) supplied to the main CPU 101 is not stable.

On the other hand, in S1, when the main CPU 101 determines that the power supply monitoring port is not in the ON state (when the determination in S1 is NO), the main CPU 101 performs an initialization process of the timer circuit 113 (PTC) (S2). In this process, the main CPU 101 initially sets the timer circuit 113. Specifically, the main CPU 101 sets the frequency division ratio in the timer prescaler register (not shown), sets the timer control register (not shown) to interrupt enable, etc., and sets the timer counter (not shown). Set the initial count value.

Next, the main CPU 101 performs initialization processing of the first serial communication circuit 114 (SCU1) between the main control circuit 90 and the sub-control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. Initialization processing is performed (S3). Next, the main CPU 101 performs an initialization process of the random number circuit 110 (RDG) (S4). Next, the main CPU 101 performs a write test of the main RAM 103 (S5).

Next, the main CPU 101 determines as a result of the write test whether or not the writing to the main RAM 103 is normally performed (S6).

In S6, when the main CPU 101 determines that the writing to the main RAM 103 has not been performed normally (when the determination in S6 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, in S6, when the main CPU 101 determines that the writing to the main RAM 103 has been normally performed (when the determination in S6 is YES), the main CPU 101 is in the state of the timer control register (not shown) of the timer circuit 113. (S7).

Next, the main CPU 101 determines whether or not the current state is the occurrence timing of the interrupt process based on the acquired state of the timer control register (S8). Specifically, the main CPU 101 determines whether or not 1.1172 ms has elapsed from the start of the timer count based on the acquired state of the timer control register.

In the present embodiment, when the timer time 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the count process of the CPU built-in timer is started. After that, the status of the timer circuit 113 can be acquired by reading the information of the timer control register (not shown). Then, in the present embodiment, a bit (discrimination bit) capable of discriminating (seeing) whether or not the current state is the occurrence timing of the interrupt process (whether or not it is the timer interrupt state) in the timer control register. ) Is provided.

Therefore, in the process of S7, the main CPU 101 reads the information of the timer control register (not shown), and in the process of S8, the main CPU 101 is in the ON / OFF state of the discrimination bit in the timer control register (not shown). By referring to "1" / "0"), it is determined whether or not the current state is the occurrence timing of the interrupt process. When 1.1172 ms has elapsed from the start of counting by the timer circuit 113 (if the count value of the timer circuit 113 is 0), the discrimination bit is turned on.

In S8, when the main CPU 101 determines that the current state is not the timing at which the interrupt process occurs (when the determination in S8 is NO), the main CPU 101 returns the process to the process of S7 and repeats the processes after S7.

On the other hand, in S8, when the main CPU 101 determines that the current state is the timing at which the interrupt process occurs (when the determination in S8 is YES), the main CPU 101 performs a thumb check process (out of regulation) (S9). .. In this process, the main CPU 101 performs a thumb check process of the main RAM 103, and this process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. Further, the program used in this thumb check process is stored in the non-standard area in the main ROM 102 (see FIG. 12B). The details of the thumb check process will be described later with reference to FIGS. 51 and 52 described later.

Further, in S8, when the main CPU 101 determines that the current state is the occurrence timing of the interrupt process (when the determination in S8 is YES), the main CPU 101 performs the interrupt process described later before the process in S9. The interrupt process (see FIG. 100 described later) is executed. Then, by this interrupt process, a non-operation command is transmitted from the main control circuit 90 (main control board 71) to the sub control circuit 200 (sub control board 72).

After the process of S9, the main CPU 101 determines whether or not the setting key type switch 54 is in the ON state (S10).

In S10, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when the determination in S10 is YES), the main CPU 101 performs the process of S15 described later. On the other hand, in S10, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (when the determination in S10 is NO), the main CPU 101 determines the thumb check based on the result of the thumb check process in S9. It is determined whether or not the result is normal (S11).

In S11, when the main CPU 101 determines that the thumb check determination result is not normal (when the determination in S11 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, in S11, when the main CPU 101 determines that the thumb check determination result is normal (when the determination in S11 is YES), the main CPU 101 performs the game return process (S12). In this process, the main CPU 101 performs a process of returning the game state to the state before the power failure detection. The details of the game return process will be described later with reference to FIG. 38 described later.

When the determination in S6 or S11 is NO, the main CPU 101 displays the character string "rr" indicating the occurrence of an error on the information display 6 (7-segment LED display) (S13). After that, the main CPU 101 repeats the WDT clearing process (S14).

Here, returning to the process of S10 again, if S10 is a YES determination, the main CPU 101 performs a setting change confirmation process (S15). In this process, the main CPU 101 mainly performs a setting change command generation / storage process at the start of the setting change. The details of the setting change confirmation process will be described later with reference to FIG. 40 described later.

Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets the address "at the time of RAM abnormality or at the start of setting change" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. Erase (clear) the information up to the final address of the RAM area. Then, after the processing of S16, the main CPU 101 starts the main processing described later (see FIG. 54 described later).

In the present embodiment, the power-on (reset interrupt) processing is performed as described above. Then, the processing of S2 during the power-on (reset interrupt) processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 37A.

In the source program of FIG. 37A, 10 MHz (supply clock is 20 MHz) is set as the CPU clock, 228 is set as the prescaler register set value, and 49 is set as the initial count value. As a result, 1.1172 ms (= 1 / (10 MHz / 288) × 49) is calculated as the timer time (execution cycle) of the interrupt process.

Further, the processes of S7 and S8 during the above-described power-on (reset interrupt) process are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 37B. Specifically, the process of acquiring the state of the timer control register in S7 is executed by the "LD" instruction in FIG. 37B, and the determination process in S8 is executed by the "JBIT" instruction in FIG. 37B. Then, the "LD" instruction in FIG. 37B and the "JBIT" instruction in FIG. 37B are repeatedly executed until 1.1172 ms elapses from the start of counting by the timer circuit 113, and 1.1172 ms elapses from the start of counting by the timer circuit 113. , The interrupt request signal is output from the timer circuit 113 to the main CPU 101 via the interrupt controller 112. The main CPU 101, triggered by the input of this interrupt request signal, starts the interrupt process having the first 1.1172 ms cycle after the power is restored.

Since the command related to the game operation is not set in the first 1.1172 ms cycle interrupt process immediately after the power is restored (after the initialization when the power is turned on), the main control circuit 90 to the sub control circuit 200 No operation command is sent. By permitting the interrupt process immediately after the power is restored in this way, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

In addition, the data stored in the L register, H register, E register, D register, and C register are set in the communication parameters 1 to 5 constituting the non-operation command transmitted in this communication operation, respectively, when the power is restored. Will be done. Therefore, in the present embodiment, the data set in the communication parameters 1 to 5 of the non-operation command transmitted in the first interrupt process after the power is restored is made different (undefined) each time the power is restored. Can be done. That is, the sum value (BCC) of the non-operation command transmitted in the interrupt process immediately after the power is restored (after the initialization when the power is turned on) can be made different for each power restoration. In this case, fraudulent acts such as goto can be suppressed.

Further, the processing (interrupt prohibition processing) of S13 during the power-on (reset interrupt) processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 37C. .. Then, control when displaying the error code "rr" on the 2-digit 7-segment LED in the information display 6 is executed by one source code "LDW HL, 100H * cZCHRAR + cBX_PAYSEG" as shown in FIG. 37C. Then, the output operation of the 7-segment common output data and the output operation of the 7-segment cathode output data to the 2-digit 7-segment LED are performed at the same time.

That is, in the pachi-slot machine 1 of the present embodiment, the 7-segment common output data and the 7-segment cathode output data are output at the same time when the 2-digit 7-segment LED is dynamically lit and controlled. In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED on the source program can be reduced, and the capacity of the source program (capacity used by the main ROM 102) can be reduced. Therefore, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to enhance the playability.

The "7-segment common output data" referred to here is LED drive data output to the common (common) terminal of the 7-segment LED when the 7-segment LED is dynamically controlled, and the "7-segment cathode output data" is , This is LED drive data output to each cathode terminal of the 7-segment LED when the 7-segment LED is dynamically lit and controlled.

[Game return processing]
Next, with reference to FIGS. 38 and 39, the game return process performed in S12 during the power-on (reset interrupt) process (see FIG. 36) will be described. Note that FIG. 38 is a flowchart showing the procedure of the game return process, and FIG. 39 is a diagram showing an example of a source program for executing the processes of S25 to S32 in the flowchart.

First, the main CPU 101 sets the stack pointer (SP) at the time of power failure (S21). Next, the main CPU 101 clears (offs) the on-edge data before the 10-interrupt processing of the input port and the currently set on-edge data (S22). Next, the main CPU 101 sets the backup data of the output port in the output port (S23). Next, the main CPU 101 reads the data of the input port and saves the data in the current data storage area of the input port and before the interrupt processing (S24).

Next, the main CPU 101 sets the address of the rotating cylinder control data storage area (S25). Next, the main CPU 101 sets the number of reels to be checked (“3” in this embodiment) (S26).

Next, the main CPU 101 acquires reel control management information (data related to fluctuation control of the display column when a power failure occurs) of a predetermined reel based on the address of the set rotation cylinder control data storage area (S27). The reel control management information (variation control management information in the display column) is information related to the control state (rotation status) of each reel, and is backed up and saved in the event of a power failure.

Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation status during reel acceleration, constant speed waiting, or constant speed (S28).

When the main CPU 101 determines in S28 that the condition of S28 is not satisfied (when the determination in S28 is NO), the main CPU 101 performs the process of S31 described later. On the other hand, in S28, when the main CPU 101 determines that the condition of S28 is satisfied (YES in S28), the main CPU 101 clears the spinning control data (reel control management information) (S29). By this process, after returning to the game, the rotation control of the reel is started from the acceleration process. Next, the main CPU 101 sets the reel operation timing value (execution start timing “1” of the rotation cylinder control data) (S30). When "1" is set in the reel operation timing, the excitation change timing is set in the reel control process (see S903 in FIG. 100 described later), so that the main CPU 101 accelerates the reel rotation control. Start from.

After the processing of S30 or when the determination in S28 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S31). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is "0" (S32).

In S32, when the main CPU 101 determines that the value of the number of reels after subtraction is not "0" (when the determination in S32 is NO), the main CPU 101 changes the reel to be checked and shifts the processing to the processing of S27. Return and repeat the processing after S27.

On the other hand, in S32, when the main CPU 101 determines that the value of the number of reels after subtraction is "0" (when the determination in S32 is YES), the main CPU 101 performs the RAM initialization process (S33). In this process, the main CPU 101 sets the address "at the time of power recovery" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the final address of the game RAM area is set from the start address. Delete (clear) the information up to the address.

Next, the main CPU 101 restores the data of all the registers saved at the time of power failure detection to all the registers (S34). Then, after the process of S34, the main CPU 101 ends the game return process and returns the process to the process at the time of power failure detection.

In this game return process, the main CPU 101 generates data for a game return command to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 47B described later) provided in the main RAM 103. The game return command that has been saved and saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100. May be good. In this case, the game return command may be configured to include each parameter that specifies that the game returns to the state before the power failure recovery.

In the present embodiment, the game return process is performed as described above. In the game return processing of the present embodiment, as described above, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the reel is rotating at the time of power failure, reel control management is performed at the time of power recovery. The processing necessary for starting the re-rotation of the reel by acquiring the information is also performed (see the processing of S25 to S32). Therefore, in the present embodiment, the reel rotation control can be stably performed even when the reel is recovered from the electric power failure during the rotation of the cylinder, and the player is not discomforted.

Further, the processes S25 to S32 during the game return process described above are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 39. As described above, the microprocessor 91 with a security function for a game machine used in the pachislot machine 1 of the present embodiment is provided with various instruction codes dedicated to the main CPU 101. For example, the "LDQ" instruction (predetermined read instruction) in FIG. 39 is one of the main CPU 101 dedicated instruction codes.

For example, when the source code "LDQ HL, k" is executed on the source program, the address specified by the contents of the Q register (stored data) and the 1-byte integer k (direct value) becomes the HL register. Loaded into. At this time, the content of the Q register becomes the address value on the upper side of the designated destination address, and the integer k (direct value) becomes the address value on the lower side of the designated destination address. Therefore, when the source code "LDQ HL, .LOW.wR1_CTRL" in FIG. 39 is executed, the contents of the Q register (the address value on the upper side of the address of the rotation control data storage area) and the integer value ". The address (address of the rotation control data storage area) specified by "LOW.wR1_CTRL" (address value on the lower side of the address of the rotation control data storage area) is loaded into the HL register. Note that ".LOW." Is not an actual instruction but a pseudo instruction. In this pseudo-instruction function, only the lower address of the address of the storage area specified after ".LOW." Is enabled. Further, the pseudo instruction is not an instruction stored in the actual ROM, but an instruction for reference by the conversion program (assembler) when converting the source file into a format for storing in the ROM.

As described above, in the present embodiment, by using the main CPU 101 dedicated instruction code that specifies the address using the Q register (extension register), the main ROM 102, the main RAM 103, and the memory map I / O can be set by the direct value. Can be accessed. In this case, the instruction code related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Setting change confirmation process]
Next, the setting change confirmation process performed in S15 during the power-on (reset interrupt) process (see FIG. 36) will be described with reference to FIGS. 40 and 41. 40 is a flowchart showing the procedure of the setting change confirmation process, FIG. 41A is a diagram showing an example of a source program for executing the processes of S44 to S47 in the flowchart, and FIG. 41B is a diagram showing an example of the source program. It is a figure which shows an example of the source program for executing the process of S57 in the flowchart.

First, the main CPU 101 performs an initialization process of the non-standard RAM area in the main RAM 103 (S41). Next, the main CPU 101 performs one interrupt wait process (S42). In this process, the main CPU 101 waits until the process of transmitting the non-operation command by the interrupt process to the sub-control circuit 200 is completed.

Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets the address "at the time of RAM abnormality or at the start of setting change" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. Erase (clear) the information up to the final address of the RAM area.

Next, the main CPU 101 determines whether or not the setting key type switch 54 is in the ON state (S44). The setting key (not shown) inserted into the setting key type switch 54 is an operation key for operating the setting (setting values 1 to 6) of the pachislot machine 1, and is set when the setting key is turned on. The key type switch 54 is turned on.

In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (when the determination in S44 is NO), the main CPU 101 ends the setting change confirmation process and turns on the power (reset interrupt). ) Move to the processing of S16 of the time processing (see FIG. 36). On the other hand, in S44, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when the determination in S44 is YES), the main CPU 101 performs a medal acceptance prohibition process (S45). By this process, the solenoid of the selector 66 (see FIG. 7) is not driven, and the inserted medals are ejected from the medal payout outlet 24 (see FIG. 2).

Next, the main CPU 101 sets the setting change start or setting confirmation start information (005H: first value) in the L register, and performs the generation and storage process of the setting change command (setting change / setting confirmation start) (S46). .. In this process, the main CPU 101 generates setting change command data (first command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process, and generates the command data. It is stored in the communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 42 described later. Further, the setting change command (setting change / setting confirmation start) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100. Will be sent to.

Next, the main CPU 101 sets the error count relay to the ON state (S47). Next, the main CPU 101 determines whether the setting change or the setting confirmation has been performed (S48).

In S48, when the main CPU 101 determines that the setting has not been changed (the setting has been confirmed) (when the determination in S48 is NO), the main CPU 101 performs the process of S55 described later.

On the other hand, in S48, when the main CPU 101 determines that the setting has been changed (the setting has not been confirmed) (when the determination in S48 is YES), the main CPU 101 updates the set value (S49). ). Next, the main CPU 101 performs a 7-segment display setting process of the set value (S50). By this process, the updated set value can be displayed on the 7-segment LED in the information display 6.

Next, the main CPU 101 determines whether or not the reset switch 76 is in the ON state (S51).

When the main CPU 101 determines in S51 that the reset switch 76 is in the ON state (when the determination in S51 is YES), the main CPU 101 returns the process to the process of S49 and repeats the processes after S49. On the other hand, in S51, when the main CPU 101 determines that the reset switch 76 is not in the ON state (when the determination in S51 is NO), the main CPU 101 determines whether or not the start switch 79 is in the ON state (S52). ..

When the main CPU 101 determines in S52 that the start switch 79 is not in the ON state (when the determination in S52 is NO), the main CPU 101 returns the process to the process in S51 and repeats the processes after S51. On the other hand, in S52, when the main CPU 101 determines that the start switch 79 is in the ON state (when the determination in S52 is YES), the main CPU 101 is set in the set value storage area (not shown) provided in the main RAM 103. Store the value (S53).

Next, the main CPU 101 determines whether or not the setting key type switch 54 is in the off state (S54).

In S54, when the main CPU 101 determines that the setting key type switch 54 is not in the off state (when the determination in S54 is NO), the main CPU 101 repeats the process of S54. On the other hand, in S54, when the main CPU 101 determines that the setting key type switch 54 is in the off state (when the determination in S54 is YES), the main CPU 101 performs the process of S55 described later.

When the determination in S48 is NO or the determination in S54 is YES, the main CPU 101 determines whether the setting change or the setting confirmation has been performed (S55).

In S55, when the main CPU 101 determines that the setting has not been changed (the setting has been confirmed) (when the determination in S55 is NO), the main CPU 101 performs the process of S57 described later. On the other hand, in S55, when the main CPU 101 determines that the setting has been changed (the setting has not been confirmed) (when the determination in S55 is YES), the main CPU 101 performs the RAM initialization process (S56). .. In this process, the main CPU 101 uses the address (the address next to the set value storage area) of the main RAM 103 shown in FIG. 12C at the end of the setting change, which is not shown, as the start address of the initialization start. It is set and the information from the start address to the final address of the game RAM area is erased (cleared).

After processing S56 or when S55 determines NO, the main CPU 101 sets the setting change end or setting confirmation end information (004H: second value) in the L register, and sets the setting change command (setting change / setting confirmation end). ) Is generated and stored (S57). In this process, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change process or the setting confirmation process, and generates the command data. It is stored in the communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 42 described later. Further, the setting change command (setting change / setting confirmation end) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100. Will be sent to. Then, after the processing of S57, the main CPU 101 ends the setting change confirmation processing, and shifts the processing to the processing of S16 of the power-on (reset interrupt) processing (see FIG. 36).

In the present embodiment, the setting change confirmation process is performed as described above. The processes S44 to S47 during the above-mentioned setting change confirmation process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 41A. Among them, for example, the state determination process of the setting key of S44 is executed by the source code "BITQ 7, (.LOW. (WIBUF + 4))" in FIG. 41A, and the error count relay of S47 is set to the ON state. The process is executed by the source code "SETQ 1, (.LOW.wECRRQ)" in FIG. 41A.

Both the "BITQ" instruction and the "SETQ" instruction are instruction codes dedicated to the main CPU 101 that specify addresses using the Q register (extension register).

When, for example, the source code "BITQ b, (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer value k (direct value: lower address value) are executed. If bit b of the memory at the address specified by) is checked and "1" is stored in the bit b, "0" is set in the zero flag (bit 6: see FIG. 11) of the flag register F. If "0" is stored in the bit b, "1" is set in the zero flag (predetermined bit area) of the flag register F. Therefore, when the source code "BITQ 7, (.LOW. (WIBUF + 4)" in FIG. 41A is executed, the stored data of the Q register and the address specified by the integer value ".LOW. (WIBUF + 4)" If bit 7 of the memory of is checked and "1" is stored in the bit 7, "0" is set in the zero flag of the flag register F, and if "0" is stored in the bit 7. , "1" is set to the zero flag of the flag register F.

Further, for example, when the source code "SETQ b, (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer value k (direct value: lower side) are executed. "1" is set in the memory bit b of the address specified by (address value). Therefore, when the source code "SETQ 1, (.LOW.wECRRQ)" in FIG. 41A is executed, the stored data of the Q register and the memory of the address specified by the integer value ".LOW.wECRRQ" "1" is set in bit 1.

That is, in the setting change confirmation process of the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extension register) as described above are used, and the direct value is obtained by using these main CPU 101 dedicated instruction codes. Then, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. In this case, the instruction code related to the address setting can be omitted, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to increase the free space of the main ROM 102 and to speed up the processing.

Further, the generation / storage process of the setting change command (initialization command) performed at the start of the setting change / setting confirmation of S46 during the setting change confirmation process described above is performed by the main CPU 101 executing the "CALLF" command in FIG. 41A. The generation / storage process of the setting change command (initialization command) performed at the end of the setting change / setting confirmation of S57 described above is performed by the main CPU 101 executing the "CALLF" command in FIG. 41B. The "CALLF" instruction is also an instruction code dedicated to the main CPU 101.

For example, when the source code "CALLF mn" is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is specified by the stack pointer (SP). It is saved in the memory, the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address specified by "mn". However, the "CALLF" instruction is a 2-byte instruction, and the jumpable address range is in the range of 0000H to 11FFH. Therefore, for example, when the source code "CALLF SB_PCIIT_00" in FIG. 41A is executed, the current value of the PC register is saved in the memory specified by the stack pointer (SP), and the stack pointer is updated by -2. , The address of "SB_PCIIT_00" is stored in the PC register, and the process jumps to the address specified by "SB_PCIIT_00".

In the present embodiment, an instruction code called a "CALL" instruction is also prepared as an instruction code of the same type as the "CALLF" instruction. Then, for example, when the source code "CALL mn" is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is changed as in the "CALLF" instruction. It is saved in the memory specified by the stack pointer (SP), the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address specified by "mn". However, the "CALL" instruction is a 3-byte instruction, and the jumpable address range is different from that of the "CALLF" instruction, and the jumpable address range is in the range of 0000H to FFFFH. Since the "CALLF" instruction is an instruction code having a smaller number of bytes than the "CALL" instruction, the capacity of the source program (the capacity used by the main ROM 102) can be reduced and the processing efficiency can be improved. be able to.

Further, in the setting change confirmation process of the present embodiment, as shown in FIGS. 41A and 41B, the jump destination address “SB_PCIT_00” specified by the “CALLF” instruction in S46 is the jump destination specified by the “CALLF” instruction in S57. It is the same as the address of. That is, in the present embodiment, the setting change command (initialization command) to be transmitted to the sub-control circuit 200 at the time of setting change (when the game machine is started), at the start of setting confirmation (during normal operation), and at the end of setting confirmation is generated and stored. The source programs for executing the above are the same, and the source programs for the setting change command generation and storage processing used in both the S46 and S57 processes are shared (modularized).

In this case, since it is not necessary to separately provide the source program for the setting change command generation and storage processing in both the S46 and S57 processes, the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. .. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Setting change command generation and storage processing]
Next, the setting change command generation / storage process performed in S46 and S57 during the setting change confirmation process (see FIG. 40) will be described with reference to FIGS. 42 and 43. Note that FIG. 42 is a flowchart showing the procedure of the setting change command generation / storage process, and FIG. 43 is a diagram showing an example of a source program for executing the setting change command generation / storage process.

First, the main CPU 101 sets the information of the set values (1 to 6) in the E register (S61). Next, the main CPU 101 sets the RT state information in the C register (S62). Next, the main CPU 101 sets the command type information (02H) of the setting change command in the A register (S63).

Next, the main CPU 101 performs a communication data storage process (S64). In this process, the main CPU 101 has the information set in each register in S61 to S63 and the information set in the D register in S46 or S57 (see FIG. 40) (setting change start / setting change end / setting status). Setting change command data is generated by using (setting confirmation start / setting confirmation end), and the generated command data is saved in the communication data storage area. The details of the communication data storage process will be described later with reference to FIG. 44 described later.

After the process of S64, the main CPU 101 ends the setting change command generation and storage process. When the setting change command generation and storage process performed in S46 during the setting change confirmation process (see FIG. 40) is terminated, the main CPU 101 performs the process after the process of S64 in the setting change confirmation process (see FIG. 40). Move to the process of S47. Further, when ending the setting change command generation and storage process performed in S57 during the setting change confirmation process (see FIG. 40), the main CPU 101 ends the setting change command generation and storage process after the process of S64, and also sets the settings. The change confirmation process (see FIG. 40) is also completed.

In the present embodiment, the setting change command generation / storage process is performed as described above. The setting change command generation / storage process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 43.

As described above, in the setting change command generation and storage process, the setting status is stored in the D register as communication parameter 4 immediately before the setting change command generation and storage process is executed, and the set value is set during the execution of the setting change command generation and storage process. Is stored in the E register as the communication parameter 3, and the RT information is stored in the C register as the communication parameter 5. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), the communication parameters 3 to 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side, and these New information is set in the communication parameters. On the other hand, the other communication parameters 1 and 2 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side, and are for communication parameters 1 and 2. Therefore, the values currently stored in the L register and the H register are set. Therefore, the values of the communication parameters 1 and 2 at the time of transmitting the setting change command (initialization command) are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Communication data storage process]
Next, with reference to FIGS. 44 and 45, for example, the communication data storage process performed in S64 during the setting change command generation and storage process (see FIG. 42) will be described. The communication data storage process is executed not only when the setting change command is generated but also when other commands are generated. FIG. 44 is a flowchart showing the procedure of the communication data storage process, and FIG. 45 is a diagram showing an example of a source program for executing the processes of S71 to S76 during the communication data storage process.

First, the main CPU 101 stores the data set in the A register as communication command type data in the communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register as the parameters 1 and 2 of the communication command in the communication data temporary storage area (predetermined storage area) in the main RAM 103 (S72). ..

Next, the main CPU 101 stores the data set in the D register and the E register as the parameters 3 and 4 of the communication command in the communication data temporary storage area in the main RAM 103 (S73). Next, the main CPU 101 stores the data set in the B register and the C register as the data of the parameter 5 of the communication command and the RT state, respectively, in the communication data temporary storage area in the main RAM 103 (S74).

Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in the communication data temporary storage area in the main RAM 103 (S76).

After the processing of S76, the main CPU 101 determines whether or not there is a free space in the communication data storage area in the main RAM 103 (S77). In this embodiment, a maximum of nine command data can be stored in the communication data storage area (see FIG. 47B described later).

When the main CPU 101 determines in S77 that there is no free space in the communication data storage area (when the determination in S77 is NO), the main CPU 101 ends the communication data storage process and, for example, sets change command generation and storage process (when the communication data storage area is NO). (See FIG. 42) also ends.

On the other hand, in S77, when the main CPU 101 determines that there is a vacancy in the communication data storage area (when the determination in S77 is YES), the main CPU 101 is stored in the communication data temporary storage area by the above-mentioned processes S71 to S76. The communication data is stored in the communication data storage area as communication command data (S78).

Next, the main CPU 101 performs the communication data pointer update process (S79). In this process, the main CPU 101 mainly updates the communication data pointer indicating the storage address of the communication data in the communication data storage area. The details of the communication data pointer update process will be described later with reference to FIG. 46 described later.

Then, after the process of S79, the main CPU 101 ends the communication data storage process and, for example, the setting change command generation and storage process (see FIG. 42).

In the present embodiment, the communication data storage process is performed as described above. The processes S71 to S76 during the above-mentioned communication data storage process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 45. Then, in this series of processing, the storage processing of the communication command type data, various communication parameters, the game state flag data, and the BCC data included in the command data is a Q register on the source program as shown in FIG. It is executed by using the "LDQ" instruction, which is an instruction code dedicated to the main CPU 101 that specifies an address using (extension register).

Specifically, by executing the source code "LDQ (.LOW. (WPDT_TMP + 0)), A", the type data of the communication command stored in the A register becomes 1 with the stored data (upper address value) in the Q register. It is stored in the communication data temporary storage area of the address specified by the integer value ".LOW. (WPDT_TMP + 0)" (lower address value) of the byte. Further, by executing the source code "LDQ (.LOW. (WPDT_TPP + 1)), HL", the communication parameter 1 stored in the L register is changed to the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TMP + 1)). The communication parameter 2 stored in the communication data temporary storage area of the address specified by "" and stored in the H register is stored in the communication data temporary storage area of the next address. Further, by executing the source code "LDQ (.LOW. (WPDT_TPP + 3)), DE", the communication parameter 3 stored in the E register is changed to the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TPP + 3)". The communication parameter 4 stored in the communication data temporary storage area of the address specified by "" and stored in the D register is stored in the communication data temporary storage area of the next address. Then, by executing the source code "LDQ (.LOW. (WPDT_TPP + 5)), BC", the communication parameter 5 stored in the C register is changed to the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TPP + 5)". The game state flag data stored in the communication data temporary storage area of the address specified by "" and stored in the B register is stored in the communication data temporary storage area of the next address.

Further, the BCC data which is the sum value of the command data set in the communication data storage process is calculated by executing a series of source codes "ADD (additional instruction code) A, H" to "ADD A, B", and A. Stored in a register. Then, by executing the source code "LDQ (.LOW. (WPDT_TPP + 7)), A", the BCC data stored in the A register becomes the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TPP + 7)". It is stored in the communication data temporary storage area of the address specified in.

As described above, in the present embodiment, when creating one packet (8 bytes) of communication data (command data), various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer). In such a command data creation method, the data stored in each register at the time of command generation is stored as it is in the communication data temporary storage area as various parameters of the command data. Therefore, when command data including unused parameters is created, the value of the unused parameters becomes an indefinite value each time it is created. In this case, even if there is command data of the same type and the values of the parameters used are the same, the sum value (BCC data) of the command data can be changed each time the command is created. Further, in the present embodiment, the calculation of the sum value, which is one of the error codes, is calculated by ADD (addition instruction code), but instead of the addition instruction code, SUB (subtraction instruction code) and XOR (exclusive OR). The same effect can be obtained by calculating the error code using the instruction code). Further, the same effect can be obtained by calculating the error code using the MUL (multiplication instruction code) or DIV (division instruction code), which is an instruction dedicated to the main CPU 101.

Therefore, in the present embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress fraudulent acts such as goto, and it is necessary to add unnecessary goto countermeasure processing. Therefore, it is possible to suppress the pressure on the program capacity of the main control circuit 90 due to the addition of the anti-goto processing.

[Communication data pointer update process]
Next, the communication data pointer update process performed in S79 during the communication data storage process (see FIG. 44) will be described with reference to FIGS. 46 and 47. Note that FIG. 46 is a flowchart showing the procedure of the communication data pointer update process, FIG. 47A is a diagram showing an example of a source program for executing the communication data pointer update process, and FIG. 47B is a diagram showing a communication data pointer update process. It is a figure which shows the structure of the communication data storage area which is actually set on the source program of an update process.

First, the main CPU 101 acquires the value of the currently set communication data pointer (S81).

Next, the main CPU 101 adds and updates the value of the communication data pointer by one packet (8 bytes) (S82). In this process, when the value of the updated communication data pointer is equal to or larger than the upper limit size of the communication data storage area (see FIG. 47B), the main CPU 101 sets the value of the updated communication data pointer to "0". , This invalidates all command data stored in the communication data storage area (makes it the same state as the discarded state).

In the present embodiment, the amount of data (1 packet) transmitted in one transmission operation is 8 bytes. That is, in the present embodiment, one command data can be transmitted by one transmission operation. Further, in the present embodiment, since a maximum of 9 command data can be stored in the communication data storage area (see FIG. 47B), the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). .. Therefore, in the present embodiment, the range of the communication data pointer is set to "0" to "71", and in the process of S82, the value of the communication data pointer after the update (when the communication data pointer is updated by +8) is "71 (when the communication data pointer is updated by +8). If the value exceeds "upper limit value)", set the updated communication data pointer value to "0" (return the communication data storage destination address to the start address) and store the communication data. Disable all command data stored in the area (make it the same as the discarded state). If the value of the communication data pointer is set to "0", the next time the command data is stored in the communication data storage area, it is stored from the start address of the communication data storage area, so it is stored before that. The command data will be overwritten with new command data. Therefore, in the present embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds "71 (upper limit value)".

Then, after the process of S82, the main CPU 101 ends the communication data pointer update process and also ends the communication data storage process (see FIG. 44).

In the present embodiment, the communication data pointer update process is performed as described above. Then, the communication data pointer update process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 47A. Among them, the update process of the communication data pointer in S82 is executed by the "ADD" instruction and the "ICPLD" instruction (predetermined update instruction) in FIG. 47A, and this "ICPLD" instruction is also dedicated to the main CPU 101. It is an instruction code.

For example, when the source code "ICPLD A, n" is executed on the source program, the contents (stored data) of the A register and the integer n are compared, and when the contents of the A register are less than the integer n, , "1" is added to the contents of the A register, and when the contents of the A register are an integer n or more, "0" is set in the A register.

Therefore, when the communication data pointer update process of S82 is executed, the source code "ADD A, 7" is first executed on the source program of FIG. 47A, and the contents of the A register (the communication data pointer before the update) are executed. "7" is added to the value), and the addition result is stored in the A register. Next, the source code "ICPLD A, 71" is executed, the contents of the A register (the value of the communication data pointer after adding 7) are compared with the integer "71", and the contents of the A register are less than the integer "71". If there is, "1" is added to the contents of the A register, and if the contents of the A register are an integer "71" or more, "0" is set in the A register. That is, in the process of S82, when the value of the communication data pointer is updated by +7, if the value of the updated communication data pointer exceeds the upper limit value "71", the process of clearing the communication data pointer to zero (communication). The process of returning the data storage address to the start address of the communication data storage area) is performed. On the other hand, if the updated communication data pointer value does not exceed the upper limit value "71", the communication data pointer value is totaled by adding "1" to the communication data pointer with the "ICPLD" instruction. Update +8.

As described above, in the present embodiment, in the communication data pointer update process, communication data is used by one "ICPLD" instruction code (an instruction code in which the upper limit determination instruction of the transmission buffer and the determination branch instruction are integrated). It is possible to collectively execute the pointer update (1 addition) process, the communication data pointer determination check process after the update, and the communication data pointer clear process. In this case, it is not necessary to provide an instruction code for executing each process separately. For example, the branch instruction code for determining whether or not the updated communication data pointer value exceeds the upper limit value "71" can be omitted.

Therefore, the capacity of the source program (the capacity used by the main ROM 102) can be reduced by using the "ICPLD" instruction code dedicated to the main CPU 101 in the communication data pointer update process or the like. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Processing at the time of power failure (external)]
Next, the power failure (external) processing of the pachi-slot machine 1 performed under the control of the main CPU 101 will be described with reference to FIG. 48. FIG. 48 is a flowchart showing a procedure of (external) processing at the time of power failure. In the power failure (external) process shown in FIG. 48, when the power supply management circuit 93 detects a decrease in the power supply voltage (power failure) supplied to the microprocessor 91, the power failure detection signal is transmitted to the microprocessor 91. Is output to the "XINT" terminal of the above, and is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

First, the main CPU 101 saves the data set in all the registers (S91). Next, the main CPU 101 reads the data set in the power failure detection port (S92).

Next, the main CPU 101 determines whether or not the power failure detection port is in the ON state (S93).

In S93, when the main CPU 101 determines that the power interruption detection port is not in the ON state (when the determination in S93 is NO), the main CPU 101 sets the interrupt processing permission (S94). Then, after the processing of S94, the main CPU 101 ends the (external) processing at the time of power failure. It should be noted that these processes performed when S93 is a NO determination correspond to the process of countermeasures against momentary power failure that occurs when the power management circuit 93 momentarily detects a power failure.

On the other hand, in S93, when the main CPU 101 determines that the power failure detection port is in the ON state (when the determination in S93 is YES), the main CPU 101 sets that the medal cannot be inserted and sets the stop of the hopper device 51. (S95).

Next, the main CPU 101 saves the currently set value of the stack pointer (SP) in the stack area of the game RAM area in the main RAM 103 (S96).

Next, the main CPU 101 performs a checksum generation process of the main RAM 103 (S97). This process is performed in the non-standard work area (see FIG. 12C) in the main RAM 103. Further, the program used in this checksum generation process is stored in the non-standard area in the main ROM 102 (see FIG. 12B). The details of the checksum generation process will be described later with reference to FIG. 49 described later.

Next, the main CPU 101 sets access prohibition to the main RAM 103 (S98). Then, after the processing of S98, the infinite loop processing is performed until the power supply is stopped (until the power supply voltage reaches a voltage at which the main CPU 101 cannot operate).

[Checksum generation process (non-standard)]
Next, the checksum generation process performed in S97 during the power failure (external) process (see FIG. 48) will be described with reference to FIGS. 49 and 50. Note that FIG. 49 is a flowchart showing the procedure of the checksum generation process, FIG. 50A is a diagram showing an example of a source program for executing the checksum generation process, and FIG. 50B is a checksum generation process. It is a figure which shows the state of the update operation of the stack pointer executed and the operation of reading data from a main RAM 103 to a register.

First, the main CPU 101 saves the current stack pointer (SP) value (the address in use of the stack area of the game RAM area) in the non-standard stack area of the non-standard RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (S102). Next, the main CPU 101 sets the address value (F0H) on the upper side of the RAM address (address of the non-standard stack area) in the Q register (S103). Next, the main CPU 101 sets the power failure occurrence flag (S104).

Next, the main CPU 101 sets the stack pointer with the calculation start address of the sum value in the game RAM area, and sets the sum calculation counter with the value obtained by dividing the number of bytes of the sum value calculation target storage area by "2". Set (S105). The sum calculation counter is a counter for determining the end trigger of the sum value calculation, and is provided in the main RAM 103. Then, when the sum calculation counter set in S105 becomes "0", the sum value calculation process of the game RAM area of the main RAM 103 is terminated.

Next, the main CPU 101 clears the HL register to 0 (sets the value “0”) (S106). By this process, the initial value "0" of the sum value is set.

Next, the main CPU 101 executes an instruction code (source code "POP DE" shown in FIG. 50A) called an "POP instruction" (specific instruction), and stores the main RAM 103 set in the stack pointer (SP). The data (stored value) of the area for 2 bytes is read from the address of the area to the DE register (S107).

When the "POP" instruction is executed, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the lower register of the pair register and specified by the stack pointer. The data (memory contents) stored in the 1-byte area of the address where the updated address is updated by 1 is loaded into the register on the upper side of the pair register. When the "POP" instruction is executed, an address update process for 2 bytes (a process of adding "2" to the address) is performed on the address set in the stack pointer (SP).

Therefore, in the processing of S107, the data (memory contents) stored at the address specified by the stack pointer is loaded into the E register and saved at the address specified by the stack pointer plus "1". The data (memory contents) is loaded into the D register.

FIG. 50B shows the operation of reading data into the DE register and the operation of updating the address set in the stack pointer when the “POP” instruction is executed. If the address set in the stack pointer (SP) is "F010h" at the start of calculation of the sum value, the data (memory contents) stored in the address "F010h" is loaded into the E register and the address. The data (memory contents) stored in "F011h" is loaded into the D register. Further, at this time, an update process of adding 2 to the address set in the stack pointer (SP) is performed, and the address set in the stack pointer (SP) is changed from "F010h" to "F012h". Then, when the "POP" instruction is executed again, the data (memory contents) stored in the address "F012h" is loaded into the E register, and the data (memory contents) stored in the address "F013h" is loaded. It is loaded into the D register. At this time, the address set in the stack pointer (SP) is updated, and the address set in the stack pointer (SP) is changed from "F012h" to "F014h". After that, every time the "POP" instruction is executed, the above-mentioned operation of reading data to the DE register and the operation of updating the address set in the stack ponter are repeated.

After the process of S107, the main CPU 101 performs a sum value calculation process (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S110).

In S110, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S110 is NO), the main CPU 101 returns the process to the process of S107 and repeats the processes after S107. That is, the processes of S107 to S110 are repeated until the sum value calculation process of the game RAM area of the main RAM 103 is completed.

On the other hand, in S110, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S110 is YES), the main CPU 101 sets the DE register in the non-standard RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-standard sum count value is set in the sum calculation counter (S111). The non-standard sum count value is the number of bytes in the non-standard storage area. Therefore, when the sum calculation counter set in S111 becomes "0", the sum value calculation process of the non-standard RAM area of the main RAM 103, that is, the sum value calculation process of the entire main RAM 103 is completed.

Next, the main CPU 101 reads the data (stored value) of one byte of the area from the address of the non-standard RAM area set in the DE register into the A register (S112).

Next, the main CPU 101 performs a sum value calculation process (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S115).

In S115, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S115 is NO), the main CPU 101 returns the processing to the processing in S112 and repeats the processing after S112. That is, the processes of S112 to S115 are repeated until the process of adding the sum value of the non-standard RAM area of the main RAM 103 to the sum value of the game RAM area is completed.

On the other hand, in S115, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S115 is YES), the main CPU 101 sets the value stored in the HL register when a power failure occurs. As the sum value of, it is stored in the sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) saved in the non-standard stack area in S101 in the stack pointer (S117). Then, after the processing of S117, the main CPU 101 ends the checksum generation processing, and shifts the processing to the processing of S98 at the time of power failure (external) processing (see FIG. 48).

In the present embodiment, the checksum generation process is performed as described above. Then, the checksum generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 50A. As described above, in the present embodiment, the checksum of the main RAM 103 when a power failure occurs is calculated by an addition formula. At this time, in the calculation of the sum value of the game RAM area, the addition process is performed in 2-byte units (see the source code "ADD HL, DE" in FIG. 50A), and in the non-standard RAM area, the addition process is performed in 1-byte units. (See the source code "ADDWB HL, A" in FIG. 50A).

[Sum check processing (non-standard)]
Next, the thumb check process performed in S9 during the power-on processing (see FIG. 36) will be described with reference to FIGS. 51 to 53. 51 and 52 are flowcharts showing the procedure of the thumb check process, and FIG. 53 is a diagram showing an example of a source program for executing the processes of S122 to S132 during the checksum check process.

First, the main CPU 101 saves the current stack pointer (SP) value in the non-standard stack area (S121). Next, the main CPU 101 sets the address of the sum value storage area in the stack pointer, and sets the value obtained by dividing the number of bytes of the sum value calculation target storage area by "2" in the sum calculation counter (S122). The sum calculation counter set here is a counter for determining the end trigger of the sum value calculation (sum value subtraction process), and is provided in the main RAM 103. Next, the main CPU 101 acquires a sum value (checksum) from the sum value storage area (S123). By this process, the checksum (initial value before subtraction) generated when the power failure occurs is stored in the HL register.

Next, the main CPU 101 executes the "POP" instruction and reads the data (stored value) of the area of 2 bytes from the address of the storage area of the main RAM 103 set in the stack pointer (SP) into the DE register (S124). .. At this time, by executing the "POP" instruction, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the E register, and the address specified by the stack pointer is used. The data (memory contents) stored in the 1-byte area of the updated address is loaded into the D register (see FIG. 50B). When the "POP" instruction is executed, an address update process for 2 bytes (a process of adding 2 addresses) is performed on the address set in the stack pointer (SP).

Next, the main CPU 101 performs a sum value calculation (subtraction) process (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (initial value of the sum value or the sum value after the previous subtraction process), and the subtraction is performed. Store the value as a sum value in the HL register.

Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S127).

In S127, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S127 is NO), the main CPU 101 returns the processing to the processing of S124, and repeats the processing after S124. That is, the processes of S124 to S127 are repeated until the subtraction process of the sum value is completed over the entire area of the game RAM area of the main RAM 103.

On the other hand, in S127, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S127 is YES), the main CPU 101 sets the DE register in the non-standard RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-standard sum count value is set in the sum calculation counter (S128). The non-standard sum count value is the number of bytes in the non-standard RAM area.

Next, the main CPU 101 reads the data (stored value) of one byte of the area from the address of the non-standard RAM area set in the DE register into the A register (S129).

Next, the main CPU 101 performs a sum value calculation (subtraction) process (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value as a sum value in the HL register.

Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S132).

In S132, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S132 is NO), the main CPU 101 returns the processing to the processing of S129, and repeats the processing after S129. That is, the processes of S129 to S132 are repeated until the subtraction process of the sum value is completed over the entire area of the non-standard RAM area of the main RAM 103.

On the other hand, in S132, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S132 is YES), the main CPU 101 sets "sum error" in the determination result of the thumb check process. (S133). Next, the main CPU 101 determines whether or not the calculated sum value is “0” (S134).

In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether or not the sum value is “0”. In the present embodiment, the sum value becomes "0" when the value of the sum calculation counter set in S128 becomes "0", that is, when the subtraction process of the sum value is completed over the entire area of the main RAM 103. If, the zero flag in the flag register F is set to "1", and if the sum value is not "0", the zero flag in the flag register F is set to "0". Therefore, if "1 (on state)" is set in the zero flag of the flag register F at the time of processing S134, the main CPU 101 determines that the sum value is "0".

In S134, when the main CPU 101 determines that the calculated sum value is not "0" (when the determination in S134 is NO), the main CPU 101 performs the process of S139 described later. On the other hand, in S134, when the main CPU 101 determines that the calculated sum value is "0" (when the determination in S134 is YES), the main CPU 101 sets "power failure" in the determination result (S135). ).

Next, the main CPU 101 acquires the power failure occurrence flag (S136). Next, the main CPU 101 determines whether or not the power failure generation flag is in the state without power failure (off state) (S137).

In S137, when the main CPU 101 determines that the power interruption occurrence flag is in the state of no power interruption (when the determination in S137 is YES), the main CPU 101 performs the process of S139 described later. On the other hand, in S137, when the main CPU 101 determines that the power interruption occurrence flag is not in the state without power interruption (when the determination in S137 is NO), the main CPU 101 sets "normal" in the determination result (S138).

After the processing of S138, if S134 is a NO determination or S137 is a YES determination, the main CPU 101 saves the determination result in the thumb check determination result and clears (offs) the power failure occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) saved in the non-standard stack area in S121 to the stack pointer (S140). Then, after the processing of S140, the main CPU 101 ends the thumb check processing, and shifts the processing to the processing of S10 of the power-on processing (see FIG. 36).

In the present embodiment, the sum check process is performed as described above. Then, the processes S122 to S132 during the above-mentioned checksum check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 53.

As described above, in the thumbchock determination process of the main RAM 103 in the present embodiment, first, the value of the checksum generated when the power failure occurs is sequentially subtracted from the data stored in the main RAM 103 when the power is restored. At this time, in the game RAM area, the subtraction process is performed in 2-byte units (see the source code "SUB HL, DE" in FIG. 53), and in the non-standard RAM area, the subtraction process is performed in 1-byte units (in FIG. 53). Source code "SUBWB HL, A") is performed. Next, it is determined whether or not an abnormality has occurred based on whether or not the final subtraction result is "0" (whether or not the zero flag is on). Then, when the subtraction result is "0" (when the zero flag is on), it is determined to be normal, and when the subtraction result is not "0" (when the zero flag is off), it is abnormal. It is judged.

That is, in the present embodiment, the checksum generation process when a power failure occurs is performed by an addition method, and the checksum determination process when the power is restored is performed by a subtractive method. Then, normal / abnormal determination is performed based on the final subtraction result of the checksum. When such a checksum generation process and determination process are performed, it is not necessary to generate a checksum again when the power is restored and to collate the checksum with the checksum when a power failure occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, it is possible to secure a free space corresponding to the omitted portion of the collation instruction code in the main ROM 102, and it is possible to improve the game playability by utilizing the increased free space. The "POP" instruction executed in the above-mentioned checksum generation process when a power failure occurs and the checksum determination process when the power is restored is a stack pointer (SP) operation-only instruction, and the source code ". In addition to "POP DE", there are source codes "POP HL", "POP AF" and the like.

[Main processing of pachislot under the control of the main CPU]
Next, with reference to FIG. 54, the main processing (main operation processing) of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described. Note that FIG. 54 is a flowchart (hereinafter referred to as a main flow) showing the procedure of the main process.

First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address "at the end of one game" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and from the start address, the game RAM area Delete (clear) the information up to the final address. The storage area in this range is, for example, a storage area such as an internal winning combination storage area and a display combination storage area, which requires data to be erased for each unit game (game).

Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this process, the main CPU 101 performs an input check process such as a medal sensor (not shown) and a start switch 79. The details of the medal reception / start check process will be described later with reference to FIG. 55 described later.

Next, the main CPU 101 performs a random number acquisition process (S203). In this process, the main CPU 101 uses a random number value for internal winning combination lottery (0 to 65535: a value of the random number register 0 of the random number circuit 110 that becomes a hard latch random number) and a random number value for production used in various ART-related lottery (0 to 65535). 0 to 65535: each value of the random number registers 1 to 3 of the random number circuit 110 to be a soft latch random number, 0 to 255: each value of the random number registers 4 to 7 of the random number circuit 110 to be a soft latch random number), etc. The extracted various random number values are stored in a random number value storage area (not shown) provided in the main RAM 103. The details of the random number acquisition process will be described later with reference to FIG. 63 described later.

Next, the main CPU 101 performs an internal lottery process (S204). In this process, the main CPU 101 performs an internal winning combination determination process by lottery based on the random number value (hard latch random number) extracted in S203. The details of the internal lottery process will be described later with reference to FIG. 64 described later.

Next, the main CPU 101 performs a symbol setting process (S205). In this process, the main CPU 101, for example, generates an internal winning combination from the hit request flag status (flag status information), expands the hit request flag data, and stores the hit request flag data in the hit request flag storage area. And so on. That is, the main CPU 101 performs a process of setting a combination of symbols that are permitted to be stopped and displayed on the effective line in the unit game this time, out of a plurality of predetermined combinations of symbols (see FIG. 18). ..

Although detailed control is omitted, when the bonus combination (BB) is already stored in the carry-over combination storage area (see FIG. 23) in the symbol setting process of S205, the main CPU 101 has the bonus combination (see FIG. 23). In this unit game, including BB), a combination of symbols that are allowed to be stopped and displayed on the valid line is set, and if the bonus combination (BB) is determined as the internal winning combination, the bonus The combination (BB) is stored in the carry-over combination storage area (see FIG. 23) as a carry-over combination. Further, in this case, a process of setting the RT4 state (RT4) as the RT state is performed.

Next, the main CPU 101 performs a start command generation / storage process (S206). In this process, the main CPU 101 generates data for a start command to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100. The start command is configured to include each parameter for specifying the internal winning combination and the like.

Next, the main CPU 101 performs the second interface board control process (S207). The second interface board control process is executed in the non-standard work area of the main RAM 103. The details of the second interface board control process will be described later with reference to FIG. 66 described later.

Next, the main CPU 101 performs a state-specific control process (S208). In this process, the main CPU 101 mainly performs a game start process (start process) according to a state in which the game is performed (for example, each state shown in FIG. 14). The details of the state-specific control processing will be described later with reference to FIG. 68 described later.

Next, the main CPU 101 performs a reel stop initial setting process (S209). In this process, the main CPU 101 refers to the reel stop initial setting table (not shown) and acquires the attraction priority table selection table number, the attraction priority table number, and the stop table number based on the internal winning combination and the game state. And the process of storing "3" in the stop button non-operation counter.

Next, the main CPU 101 performs a reel rotation start process (S210). In this process, the main CPU 101 requests the start of rotation of all reels. Then, when the start of rotation of all reels is requested, three stepping motors (not shown) are driven by an interrupt process (see FIG. 100 described later) executed at a constant cycle (1.1172 msec). Controlled, the rotation of the left reel 3L, the middle reel 3C and the right reel 3R is started. Each reel is then accelerated and controlled until its rotational speed reaches a constant speed, after which it is controlled to maintain that constant speed.

Next, the main CPU 101 performs a reel rotation start command generation / storage process (S211). In this process, the main CPU 101 generates data of a reel rotation start command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100. The reel rotation start command is configured to include a parameter indicating that the reel rotation start operation has been started.

Next, the main CPU 101 performs a pull-in priority storage process (S212). In this process, the main CPU 101 acquires the attraction priority data and stores it in the attraction priority data storage area. The details of the pull-in priority storage process will be described later with reference to FIG. 73 described later.

Next, the main CPU 101 performs a reel stop control process (S213). In this process, the main CPU 101 controls the rotation stop of the corresponding reel based on the timing at which the left stop button 17L, the middle stop button 17C, and the right stop button 17R are pressed and the internal winning combination. The details of the reel stop control process will be described later with reference to FIG. 81 described later.

Next, the main CPU 101 performs a winning search process (S214). In this process, the main CPU 101 stores the data in the symbol code storage area (see FIG. 27) in the winning operation flag storage area (see FIG. 22). Further, in this process, the main CPU 101 displayed the display combination on the effective line (that is, which combination of the plurality of predetermined symbol combinations shown in FIG. 18 was displayed on the effective line). ) Judge whether or not, and set the number of medals to be paid out based on the judgment result. The details of the winning search process will be described later with reference to FIG. 88 described later.

Next, the main CPU 101 performs an illegal hit check process (S215). In this process, the main CPU 101 synthesizes a hit request flag (internal winning combination) and a winning operation flag (display combination), and determines whether or not there is an illegal hit error based on the combination result. The details of the illegal hit check process will be described later with reference to FIG. 90 described later.

Next, the main CPU 101 performs a winning check / medal payout process (S216). In this process, the main CPU 101 performs a process of generating a winning operation command. Further, in this process, the main CPU 101 drives the hopper device 51 and updates the number of credits based on the number of payouts of the display combination determined in S214, and performs the medal payout process. The details of the winning check / medal payout process will be described later with reference to FIG. 92 described later.

Next, the main CPU 101 performs a bonus check process (S217). In this process, the main CPU 101 controls the operation and termination of the bonus state. The details of the bonus check process will be described later with reference to FIG. 96 described later.

Next, the main CPU 101 performs an RT check process (S218). In this process, the main CPU 101 performs RT state transition control based on the symbol combination stopped and displayed on the effective line. The details of the RT check process will be described later with reference to FIG. 97 described later.

Next, the main CPU 101 performs a state-based control process at the end of the game (S219). In this process, the main CPU 101 mainly performs a game end process (that is, a process after all stops) according to a state in which the game is performed (for example, each state shown in FIG. 14). The details of the control processing for each state at the end of the game will be described later with reference to FIG. 98 described later. Then, after the processing of S219 (after the end of one game), the main CPU 101 returns the processing to the processing of S201.

[Medal reception / start check processing]
Next, the medal acceptance / start check process performed in S202 in the main flow (see FIG. 54) will be described with reference to FIGS. 55 and 56. FIG. 55 is a flowchart showing the procedure of the medal acceptance / start check process, and FIG. 56 is a diagram showing an example of a source program for executing the processes of S231 to S233 during the medal acceptance / start check process. is there.

First, the main CPU 101 determines whether or not the value of the automatic insertion medal counter is "0" (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is "1" or more, the main CPU 101 determines that there is an automatic insertion request. Further, the automatic insertion medal counter is data for identifying whether or not the display combination related to the replay is established in the previous unit game. When the display combination related to the re-game is established, the number of medals inserted in the previous unit game is automatically inserted into the automatic insertion medal counter.

In S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" (when the determination in S221 is YES), the main CPU 101 performs the process of S225 described later.

On the other hand, in S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is not "0" (when the determination in S221 is NO), the main CPU 101 performs the medal insertion process (S222). In this process, the main CPU 101 performs a medal insertion command generation / storage process, an LED lighting control process for the number of medals inserted, and the like. The details of the medal insertion process will be described later with reference to FIG. 57 described later.

Next, the main CPU 101 subtracts 1 from the value of the automatic insertion medal counter (S223). Next, it is determined whether or not the value of the automatically inserted medal counter after subtraction is "0" (S224).

In S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is not "0" (when the determination in S224 is NO), the main CPU 101 returns the process to the process of S222 and repeats the processes after S222.

On the other hand, in S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" (when S224 determines YES), or when S221 determines YES, the main CPU 101 performs medal auxiliary storage. The storage switch check process is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals based on the on / off state of the medal auxiliary storage switch 75.

Next, the main CPU 101 performs a medal insertion state check process (S226). Next, the main CPU 101 determines whether or not the medal can be inserted based on the result of the medal insertion state check process (S227).

When the main CPU 101 determines in S227 that the medal cannot be inserted (when the determination in S227 is NO), the main CPU 101 performs the process of S231 described later.

On the other hand, when the main CPU 101 determines in S227 that the medal can be inserted (when the determination in S227 is YES), the main CPU 101 performs a medal insertion check process (S228). In this process, the main CPU 101 credits the medal, for example, based on the medal sensor input state, a process of determining whether or not the medal has passed normally, and when the number of medals inserted exceeds a specified number. Perform processing and so on. The details of the medal insertion check process will be described later with reference to FIG. 59 described later.

Next, the main CPU 101 determines whether or not the medal insertion or credit is possible based on the result of the medal insertion check process (S229).

When the main CPU 101 determines in S229 that the medal can be inserted or credited (when the determination in S229 is YES), the main CPU 101 performs the process of S231 described later. On the other hand, in S229, when the main CPU 101 determines that the medal cannot be inserted or credited (when the determination in S229 is NO), the main CPU 101 performs a medal acceptance prohibition process (S230). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medals are ejected from the medal payout outlet 24.

After the processing of S230, if S227 is a NO determination or S229 is a YES determination, the main CPU 101 determines whether or not the current number of inserted medals is the playable start number (S231). In this embodiment, the number of games that can be started is three (see FIG. 18).

In S231, when the main CPU 101 determines that the current number of inserted medals is the number of playable start numbers (when the determination in S231 is YES), the main CPU 101 performs the process of S234 described later. On the other hand, in S231, when the main CPU 101 determines that the current number of inserted medals is not the playable start number (when the determination in S231 is NO), the main CPU 101 determines whether or not there is a medal inserted (S232). ).

In S232, when the main CPU 101 determines that a medal has been inserted (when the determination in S232 is YES), the main CPU 101 returns the process to S226 and repeats the processes after S226. On the other hand, in S232, when the main CPU 101 determines that no medal has been inserted (NO in S232), the main CPU 101 performs the setting change confirmation process described with reference to FIG. 40 (S233). In this process, the main CPU 101 performs a setting change command generation / storage process at the start of setting confirmation.

After the processing of S233 or when the determination in S231 is YES, the main CPU 51 determines whether or not the start switch 79 is in the ON state (S234).

When the main CPU 101 determines in S234 that the start switch 79 is not in the ON state (when the determination in S234 is NO), the main CPU 101 returns the process to S226 and repeats the processes after S226.

On the other hand, in S234, when the main CPU 101 determines that the start switch 79 is in the ON state (when the determination in S234 is YES), the main CPU 101 performs a medal acceptance prohibition process (S235). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medals are ejected from the medal payout outlet 24. Then, after the processing of S235, the main CPU 101 ends the medal acceptance / start check processing, and shifts the processing to S203 of the main flow (see FIG. 54).

In the present embodiment, the medal acceptance / start check process is performed as described above. Then, the processes of S231 to S233 during the above-mentioned medal acceptance / start check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 56. Among them, in the process of S233, the process is jumped to the address "SB_WVSC_00" of the execution program of the setting change confirmation process by the "CALLF" instruction which is the instruction code dedicated to the main CPU 101, and the setting change confirmation described with reference to FIGS. 40 and 41. Perform processing.

Then, the process of S233 during the above-mentioned medal acceptance / start check process, that is, the setting change confirmation process, is executed regardless of the game state. Therefore, in the present embodiment, regardless of the game state, that is, even if the game state is a bonus state (special prize operation state), the set value and the hall menu (various history data (error, power failure history, etc.)) are displayed. It can be confirmed, and fraudulent acts such as goto can be suppressed.

[Medal insertion process]
Next, the medal insertion process performed in S222 during the medal acceptance / start check process (see FIG. 55) will be described with reference to FIGS. 57 and 58. Note that FIG. 57 is a flowchart showing the procedure of the medal insertion process, and FIG. 58 is a diagram showing an example of a source program for executing the medal insertion process.

First, the main CPU 101 adds "1" to the value of the medal counter (S241). The medal counter is a counter for counting the number of inserted medals, and is provided in the main RAM 103.

Next, the main CPU 101 performs a medal insertion command generation / storage process (S242). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 each time one medal is inserted. The medal insertion command is configured to include parameters for specifying the number of inserted medals and the like.

Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 7) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the number of inserted medals based on the number of inserted medals (value of the medal counter) (S244). In this process, for example, when the number of inserted medals is one, the LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated, and for example, when the number of inserted medals is three. LED lighting data for lighting all of the first to third LEDs for displaying the number of inserted medals is calculated. The method for calculating the LED lighting data will be described in detail later.

Next, the main CPU 101 uses the calculated LED lighting data to light the corresponding LED for displaying the number of inserted medals (S245). Then, after the processing of S245, the main CPU 101 ends the medal insertion processing, and shifts the processing to S223 of the medal acceptance / start check processing (see FIG. 55).

In the present embodiment, the medal insertion process is performed as described above. The medal insertion process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 58. Among them, in the process of S244, the LED lighting data for displaying the number of inserted medals is generated not by the loop process referring to the table but by the arithmetic process. This arithmetic processing is performed by sequentially executing the source codes "LD A, L" to "OR L" in the source program shown in FIG. 58 by the main CPU 101.

In this arithmetic processing, first, by executing the source code "LDA, L", the data of the number of inserted medals stored in the L register is stored in the A register. For example, when the number of inserted medals is 3, "00000011B" ("3" in decimal number) is stored in the A register. In the present embodiment, the 1-byte data is described as "***** B", but the last character "B" is "0" or "1" indicated before the character "B". Means that it is bit data.

Next, by executing the source code "ADD A, A", the data stored in the A register is added to the data stored in the A register, and the addition result is stored in the A register. For example, when the data stored in the A register before the execution of this "ADD" instruction is "00000011B" (when the number of inserted medals is 3), this "ADD" instruction causes the addition result. "00000011B" is stored in the A register.

Next, by executing the source code "DEC A", the data stored in the A register is subtracted by 1, and the subtraction result is stored in the A register. For example, if the data stored in the A register before the execution of the "DEC" instruction is "0000001110B", the subtraction result "000000101B" is stored in the A register by this "DEC" instruction. ..

Next, by executing the source code "OR L", a logical sum operation is performed between the data stored in the L register (the number of medals inserted) and the data stored in the A register, and the calculation result is stored in the A register. It is stored. For example, when the data stored in the A register is "000000101B" and the data stored in the L register is "00000011B" before the execution of this "OR" instruction (the number of medals inserted is three). In this case, the "OR" instruction stores "000000111B", which is the result of the OR operation of both data, in the A register. Then, the data stored in the A register by executing the "OR" command becomes the LED lighting data for displaying the number of inserted medals (data indicating the lighting state of the inserted medals LED).

For example, when the number of inserted medals is 3, as described above, the final calculation result "000000111B" is for displaying the number of inserted medals by the calculation process of the LED lighting data for displaying the number of inserted medals in S244. It becomes LED lighting data. Then, in the present embodiment, the “1/0” of bit 0 of the finally calculated LED lighting data is “on / off” of the output port to the LED (first LED) for displaying the number of inserted medals. The "1/0" of bit 1 corresponds to the "on / off" state of the output port to the LED (2nd LED) for displaying the number of inserted medals of the second piece, and the "1" of bit 2 corresponds to the state. "/ 0" corresponds to the "on / off" state of the output port to the LED (third LED) for displaying the number of inserted medals. Therefore, when the number of inserted medals is 3, as described above, "000000111B" is generated as the LED lighting data, so that all the output ports of the first to third LEDs for displaying the number of inserted medals are displayed. It is set to the on state, and all the first to third LEDs for displaying the number of inserted medals are turned on.

When the LED lighting data for displaying the number of inserted medals is generated by arithmetic processing as described above, the table data referred to when generating the LED lighting data for displaying the number of inserted medals is not required, so that the table area of the main ROM 102 It is possible to increase the free space of the LED and minimize the increase in the capacity of the program. That is, in the above-mentioned medal insertion process of the present embodiment, the process of displaying the medal insertion LED can be made more efficient, the free space of the main ROM 102 is secured (increased), and the increased free area is utilized. It becomes possible to enhance the playability.

[Medal insertion check process]
Next, the medal insertion check process performed in S228 during the medal acceptance / start check process (see FIG. 55) will be described with reference to FIGS. 59 and 60. Note that FIG. 59 is a flowchart showing the procedure of the medal insertion check process, and FIG. 60 is a diagram showing an example of a source program for executing the processes of S255 to S258 during the medal insertion check process.

First, the main CPU 101 determines whether or not the game is being replayed (S251).

When the main CPU 101 determines in S251 that the game is being replayed (when the determination in S251 is YES), the main CPU 101 ends the medal insertion check process and performs the medal acceptance / start check process (see FIG. 55). Move to S229.

On the other hand, in S251, when the main CPU 101 determines that the replay is not in progress (when the determination in S251 is NO), the main CPU 101 permits medal acceptance (S252). In this process, the solenoid of the selector 66 (see FIG. 4) is driven, and medals inserted from the medal insertion slot 24 are accepted. The accepted medals are counted and then guided to the hopper device 51.

Next, the main CPU 101 performs a bet button check process (S253). In this process, the main CPU 101 determines whether or not the bet button (MAX bet button 15a or 1-bet button 15b) has been operated based on the ON / OFF state of the BET switch 77. Next, the main CPU 101 determines whether or not the betting operation is completed based on the result of the betting button check processing in S253 (S254).

When the main CPU 101 determines in S254 that the betting operation has been completed (when the determination in S254 is YES), the main CPU 101 ends the medal insertion check process and performs the medal acceptance / start check process (see FIG. 55). Move to S229.

On the other hand, in S254, when the main CPU 101 determines that the betting operation has not been completed (when the determination in S254 is NO), the main CPU 101 determines that the medal sensor input state (game medium reception state) at the time of the current processing. Acquires the medal sensor input state at the time of the previous processing (S255). The medal sensor input state is information indicating the passing status of the medal received in the medal insertion slot 24 in the selector 66, and is the detection result of each medal sensor (not shown) provided at the entrance and exit of the selector 66. Is generated by.

In the present embodiment, the medal sensor input state is represented by 1 byte (8 bits) of data, and the upstream first medal sensor (not shown) provided at the exit of the selector 66 side by side in the medal passing direction. The detection result corresponds to the bit 0 information ("0" or "1"), and the detection result of the second medal sensor (not shown) on the downstream side corresponds to the bit 1 information ("0" or "1"). To do. When the passage of the medal is detected by the first medal sensor, "1" is set in bit 0, and when the passage of the medal is detected by the second medal sensor, "1" is set in bit 1. Will be done. Therefore, the medal sensor input state "0000000000B" indicates the state before or after passing the medal (at the time of passing), and the medal sensor input state "00000001B" indicates the state at the start of passing the medal, and the medal sensor input state "0000001B". "00000011B" indicates a state in which the medal is passing, and the medal sensor input state "00000010B" indicates a state immediately before the completion of passing the medal.

Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current processing has changed from the medal sensor input state at the time of the previous processing (S256).

In S256, when the main CPU 101 determines that the medal sensor input state at the time of the current processing has not changed from the medal sensor input state at the time of the previous processing (when the determination in S256 is NO), the main CPU 101 is described in S261 described later. Perform processing.

On the other hand, in S256, when the main CPU 101 determines that the medal sensor input state at the time of the current processing has changed from the medal sensor input state at the time of the previous processing (when the determination in S256 is YES), the main CPU 101 is at the time of the previous processing. Based on the medal sensor input state, a normal value (normal change value) of the medal sensor input state obtained at the time of the current processing is generated by arithmetic processing (S257).

In this process, when the medal sensor input state at the time of the previous process is "00000000000B" (when both the first and second medal sensors have not detected medals), it is regarded as a normal change value of the medal sensor input state. When "00000001B" (when the first medal sensor detects medals and the second medal sensor does not detect medals) is generated and the medal sensor input state at the time of the previous processing is "00000001B", the medal sensor "00000011B" (when both the first and second medal sensors are medal detection) is generated as a normal change value of the input state. Further, in this process, when the medal sensor input state at the time of the previous process is "00000011B", the normal change value of the medal sensor input state is "00000010B" (the first medal sensor has not detected a medal, and the second (When the medal sensor is medal detection) is generated, and when the medal sensor input state at the time of the previous processing is "00000010B", the normal change value of the medal sensor input state is "00000000000B" (first and second medals). If both sensors do not detect medals) is generated. The method of generating (calculating) the normal change value of the medal sensor input state will be described in detail later.

Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current processing is the same as the normal change value generated in S257 (S258). In this determination process, it is determined whether or not a medal retrograde error has occurred, and if the determination condition of S258 is not satisfied, the main CPU 101 determines that a medal retrograde error has occurred.

In S258, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the same as the normal change value generated in S257 (when the determination in S258 is NO), the main CPU 101 performs the processing of S262 described later. Do.

On the other hand, in S258, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is the same as the normal change value generated in S257 (when the determination in S258 is YES), the main CPU 101 is at the time of the current processing. It is determined whether or not the medal sensor input state of the above is the state at the time of passing the medal (“00000000B”) (S259). In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is the state at the time of passing the medal (when the determination in S259 is YES), the main CPU 101 performs the process of S263 described later.

In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the state at the time of passing the medal (when the determination in S259 is NO), the main CPU 101 sets the medal passing check timer (S260). The time set in the medal passage check timer in this process can be set to any time as long as it is possible to determine whether or not the medal has passed the selector 66. Further, the timer value set in this process may be changed according to, for example, the medal sensor input state at the time of the current process.

After the processing of S260 or when the determination of S256 is NO, the main CPU 101 indicates whether the medal sensor input state at the time of the current processing is the medal passing state (“000000011B”) and the medal passing check timer is stopped. (S261). In this determination process, it is determined whether or not a medal passing error (inserted medal passing time error) has occurred, and if the determination condition of S261 is satisfied, the main CPU 101 determines that a medal passing error has occurred.

When the main CPU 101 determines in S261 that the determination condition of S261 is not satisfied (when the determination in S261 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

On the other hand, in S261, when the main CPU 101 determines that the determination condition of S261 is satisfied (when S261 is a YES determination), or when S258 is a NO determination, that is, a medal passing error or a medal retrograde error has occurred. If it is determined, the main CPU 101 performs error processing (S262). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation and storage process. The details of error processing will be described later with reference to FIG. 61, which will be described later. Then, after the processing of S262, the main CPU 101 returns the processing to the processing of S253, and repeats the processing after S253.

Here, returning to the process of S259 again, if S259 is a YES determination, the main CPU 101 determines whether or not a specified number of medals (three in the present embodiment) have already been inserted (S263). ..

In S263, when the main CPU 101 determines that the specified number of medals have not been inserted (when the determination in S263 is NO), the main CPU 101 performs the medal insertion process described with reference to FIG. 57 (S264). Then, after the processing of S264, the main CPU 101 returns the processing to the processing of S253, and repeats the processing after S253.

On the other hand, in S263, when the main CPU 101 determines that a specified number of medals have already been inserted (when the determination in S263 is YES), the main CPU 101 adds "1" to the value of the credit counter (S265). ). Next, the main CPU 101 performs a medal insertion command generation / storage process (S266). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100.

Next, the main CPU 101 determines whether or not the number of credits of the medal is the upper limit value (50 in the present embodiment) based on the value of the credit counter (S267).

In S267, when the main CPU 101 determines that the number of credits for medals is not the upper limit value (when the determination in S267 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253. On the other hand, in S267, when the main CPU 101 determines that the number of credits of medals is the upper limit value (when the determination in S267 is YES), the main CPU 101 ends the medal insertion check process and performs the medal acceptance / start check process. Move to S229 of the process (see FIG. 55).

In the present embodiment, the medal insertion check process is performed as described above. Then, the processes of S255 to S258 during the above-mentioned medal insertion check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 60. Among them, the process of generating the normal change value of the medal sensor input state of S257 is performed by an arithmetic process, not by a process of referring to and acquiring the table. Specifically, the normal change value generation process is performed by the main CPU 101 executing the source codes "RLA" and "AND cBX_MDINSW" in the source program shown in FIG. 60 in this order.

The "RLA" instruction is an instruction code that shifts the 1-byte data stored in the A register to the left (in the direction from bit 0 to bit 7) once (by 1 bit). In the example shown in FIG. 60, the 1-byte data indicating the previous medal sensor input state stored in the A register by the source code “LDA, B” executed before the “RLA” instruction is the “RLA” instruction. Shifts to the left once. At this time, the bit data newly stored in bit 0 is determined based on the execution result of the source code "CP cBX_MDISW2" executed before the "RLA" instruction.

The "CP" instruction is an instruction code that executes a comparison operation. Further, "cBX_MDISW2" is 1 byte of data, and is "00000010B" in this embodiment. When the source code "CP cBX_MDISW2" is executed, 1-byte data indicating the previous medal sensor input state stored in the A register is compared with "cBX_MDISW2 (00000010B)".

Then, as a result of executing the source code "CP cBX_MDISW2", if the result that the 1-byte data indicating the previous medal sensor input state is less than "cBX_MDISW2 (00000010B)" is obtained, the carry flag of the flag register F is obtained. (See FIG. 11) is set to "1", and when the "RLA" instruction is executed, the carry flag "1" of the flag register F is stored in bit 0 of the A register. On the other hand, as a result of executing the source code "CP cBX_MDISW2", if the result that the 1-byte data indicating the previous medal sensor input state is "cBX_MDISW2 (00000010B)" or more is obtained, the carry flag of the flag register F is obtained. (See FIG. 11) is set to "0", and when the "RLA" instruction is executed, the carry flag "0" of the flag register F is stored in bit 0 of the A register.

Therefore, for example, if the 1-byte data indicating the previous medal sensor input state is "0000000000B (state before or after passing the medal (when passing))" (<"cBX_MDISW2"), the "RLA" command is issued. By execution, "00000001B" is generated, and if the 1-byte data indicating the previous medal sensor input state is "00000001B (state at the start of medal passage)" (<"cBX_MDISW2"), the "RLA" instruction is executed. Will generate "00000011B". On the other hand, for example, if the 1-byte data indicating the previous medal sensor input state is "000000111B (state during medal passing)" (> "cBX_MDISW2"), "00000011B" is generated by executing the "RLA" instruction. If the 1-byte data indicating the previous medal sensor input state is "00000010B (state immediately before the completion of medal passage)" (= "cBX_MDISW2"), "00000100B" is generated by executing the "RLA" command. To.

Next, when the source code "AND cBX_MDINSW" is executed, the 1-byte data (stored data in the A register) generated by executing the "RLA" instruction is logically ANDed with the 1-byte data "cBX_MDINSW", and the medal sensor. The normal change value of the input state is calculated. The 1-byte data "cBX_MDISW" is "00000011B" in this embodiment. Therefore, when the source code "AND cBX_MDINSW" is executed, only the data of bit 0 and bit 1 in the stored data of the A register is masked, and the other bit data becomes "0".

As a result, for example, if the 1-byte data indicating the previous medal sensor input state is "00000000000B (state before passing the medal)", the normal change value of the medal sensor input state is "00000001B (state at the start of passing the medal)". ) ”Is generated, and if the 1-byte data indicating the previous medal sensor input state is“ 00000001B (state at the start of medal passage) ”, the normal change value of the medal sensor input state is“ 000000111B (during medal passing). State) ”is generated. On the other hand, for example, if the 1-byte data indicating the previous medal sensor input state is "000000111B (state during medal passing)", the normal change value of the medal sensor input state is "00000010B (state immediately before the completion of medal passage)". Is generated, and if the 1-byte data indicating the previous medal sensor input state is "00000010B" (the state immediately before the completion of passing the medal), the normal change value of the medal sensor input state is "0000000000B (after passing the medal (passing)). Time) state) ”is generated.

As described above, by changing the detection process of the change mode of the medal sensor input state from the table reference process to the arithmetic process, the free space of the table storage area of the main ROM 102 can be increased and the capacity of the program can be increased. It can be minimized. Therefore, by adopting the above-mentioned method, it is possible to improve the efficiency of the detection process of the medal insertion sensor state, and it is possible to improve the playability by utilizing the increased free space in the main ROM 102.

[Error handling]
Next, with reference to FIGS. 61 and 62, for example, the error processing performed in S262 during the medal insertion check processing (see FIG. 59) will be described. FIG. 61 is a flowchart showing an error processing procedure, and FIG. 62 is a diagram showing an example of the configuration of an error table actually referred to on the error processing source program.

In the error table shown in FIG. 62, for each 1-byte data (for example, 1-byte data stored in the address “dERR_HE” in FIG. 62) indicating the on / off state of the port indicating the type of the error factor, Error display data (for example, 1-byte data stored in the addresses "dERR_HE + 1" and "dERR_HE + 2" in FIG. 62) is defined. This error display data is output to the 2-digit 7-segment LED (both for displaying the number of payouts and for displaying the error) included in the information display 6.

First, the main CPU 101 turns off the medal solenoid (S271). Specifically, the main CPU 101 stops driving the solenoid of the selector 66 (see FIG. 7). Next, the main CPU 101 saves the medal payout number display data (S272).

Next, the main CPU 101 performs an error table setting process (S273). By this process, the start address of the error table shown in FIG. 62 is set on the source program.

Next, the main CPU 101 acquires an error factor (S274). The error factor acquired in this process changes according to the process in which the error process currently being processed is read. As shown in FIG. 62, the error factors targeted in the present embodiment include "hopper empty error", "hopper jam error", "inserted medal passing count error", "inserted medal passing check error", and "" "Insert medal passage check error", "Insert medal passage time error", "Insert medal retrograde error", "Insert medal auxiliary storage full error", and "Illegal hit error" are specified. For example, when the error processing is read after the processing of S258 during the medal insertion check processing, the “inserted medal retrograde error (Cr)” in FIG. 62 is acquired as an error factor in this processing. Further, for example, when the error process is read after the process of S261 during the medal insertion check process, the "inserted medal passing time error (CE)" in FIG. 62 is acquired as an error factor in this process. ..

Next, the main CPU 101 acquires error display data from the error table and the error cause (S275). For example, when the error factor is "insertion medal retrograde error (Cr)", the error shown in FIG. 62 is used as the error display data to be output to the upper digit 7-segment LED among the 2-digit 7-segment LEDs in this process. The 1-byte data "001001110B" stored in the address "dERR_CR + 1" in the table is acquired, and the 1-byte data "00000101B" stored in the address "dERR_CR + 2" is used as the error display data to be output to the lower digit 7-segment LED. Is acquired. In this case, the two characters "Cr" are displayed as error information on the two-digit 7-segment LED.

Next, the main CPU 101 performs an error command (generation) generation and storage process (S276). In this process, the main CPU 101 generates data of an error command when an error occurs, which is transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. .. The error command when an error occurs stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100. The error command when an error occurs includes a parameter indicating that an error has occurred.

Next, the main CPU 101 performs a standby process for an interrupt time (1.1172 ms) (S277). Next, the main CPU 101 determines whether or not the error has been cleared (S278).

When the main CPU 101 determines in S278 that the error has not been cleared (when the determination in S278 is NO), the main CPU 101 returns the process to the process in S277 and repeats the processes after S277.

On the other hand, in S278, when the main CPU 101 determines that the error has been cleared (when the determination in S278 is YES), the main CPU 101 performs an error factor clearing process (S279). This process is performed in a non-standard work area of the main RAM 103. Next, the main CPU 101 performs a restoration process of the payout number display data of the medals saved in S272 (S280).

Next, the main CPU 101 performs an error command (release) generation and storage process (S281). In this process, the main CPU 101 generates data of an error command at the time of error cancellation to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. .. The error command at the time of canceling the error stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100. The error command at the time of error cancellation includes a parameter indicating error cancellation. Then, after the processing of S281, the main CPU 101 ends the error processing, and shifts the processing to, for example, S253 during the medal insertion check processing (see FIG. 59). In the error release, the generated error factor is released, and the error state is released by pressing the reset switch 76.

[Random number acquisition process]
Next, with reference to FIG. 63, the random number acquisition process performed in S203 in the main flow (see FIG. 54) will be described. Note that FIG. 63 is a flowchart showing the procedure of the random number acquisition process.

First, the main CPU 101 acquires a hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as a random number value for internal winning combination lottery, and uses a random number value storage area (not) in the main RAM 103. Save in (shown) (S291).

Next, the main CPU 101 uses soft latch random numbers in the random number registers 1 to 7 of the random number circuit (in this embodiment, 0 to 65535: random number values for effect used in the lottery process for executing the lock effect during MB, 0 to 255: ART-related. A soft latch random number acquisition register is set to generate (a random number value for effect used in the lottery process) (S292). Next, the main CPU 101 sets the acquisition number (for example, 7) of the soft latch random numbers (S293).

Next, the main CPU 101 collectively acquires the number of acquired soft latch random numbers, and stores the acquired number of soft latch random numbers in the random number value storage area (S294). At this time, the soft latch random number (effect random number value, 2-byte random number value) acquired from the random number register 1 of the random number circuit 110 is the hardware acquired from the random number register 0 of the random number circuit in the random number value storage area. It is stored in an area different from the area in which the latch random number (random number value for the internal winning combination lottery) is stored. Then, after the processing of S294, the main CPU 101 ends the random number acquisition processing and shifts the processing to S204 of the main flow (see FIG. 54). In this embodiment, a predetermined storage area of the main RAM 103 is allocated as a random number storage area in order to be able to store a plurality of 2-byte random numbers and 1-byte random numbers.

[Internal lottery processing]
Next, the internal lottery process performed in S204 in the main flow (see FIG. 54) will be described with reference to FIGS. 64 and 65. Note that FIG. 64 is a flowchart showing the procedure of the internal lottery process, FIG. 65A is a diagram showing an example of a source program for executing the processes of S302 to S305 during the internal lottery process, and FIG. 65B is a diagram. It is a figure which shows an example of the source program for executing the process of S308-S309 in the internal lottery process.

First, the main CPU 101 performs a set value / medal insertion number check process (S301). In this process, the main CPU 101 checks the set value (any of 1 to 6) of the current game and the number of inserted medals (3 in the present embodiment).

Next, the main CPU 101 sets the internal lottery table for general games and the number of lottery (67 times in this embodiment) (S302). In this process, the value (win request flag status) of the "winning number" in the internal lottery tables (RT0 to RT4) shown in FIGS. 16 and 17 is set in the C register, and the "judgment data" (not shown: address) is set. The value of (data for determining the reference destination of) is set in the A register.

Next, the main CPU 101 determines whether or not the RB is in operation (S303). That is, the main CPU 101 determines whether or not it is in the BB gaming state (BB is operating). When the main CPU 101 determines in S303 that the RB is not in operation (when the determination in S303 is NO), the main CPU 101 performs the process of S305 described later.

On the other hand, when it is determined in S303 that the main CPU 101 is operating the RB (when the determination in S303 is YES), the main CPU 101 is an internal lottery table for the middle of the RB (shown in FIGS. 16 and 17 in this embodiment). The table indicated by the "in BB" column in the internal lottery table) and the number of lottery (67 times in the present embodiment as in the general game) are set (S304). In this process, the internal lottery table and the number of lottery for general games set in S302 are overwritten with the internal lottery table and the number of lottery for RB. In the internal lottery table shown in FIGS. 16 and 17, for convenience of explanation, the internal lottery table for general games and the internal lottery table in RB have the same configuration, but in each game state, The configuration may be different so that only the necessary internal winning combinations are drawn.

After the processing of S304 or when the determination in S303 is NO, the main CPU 101 acquires the determination data of the lottery target combination from the set internal lottery table and updates the lottery table address (S305).

Next, the main CPU 101 determines whether or not the determination data is RT state-specific data (S306). In this process, the main CPU 101 determines whether or not the currently acquired lottery target combination is an internal winning combination whose lottery value changes according to the RT state. For example, the main CPU 101 determines whether or not the address defined in the currently acquired lottery target combination determination data is an address in the lottery value selection table (not shown) for each RT state.

For example, in the internal lottery table shown in FIGS. 16 and 17, the determination data associated with the internal winning combination “F_normal lip” is the internal winning combination “F_” in the RT state-specific lottery value selection table (not shown). Since the address of the "normal lip" is specified, the determination data associated with the internal winning combination "F_normal lip" corresponds to the data for each RT state. Therefore, when the currently acquired lottery target combination is the internal winning combination “F_normal lip”, the main CPU 101 determines that the determination data is the RT state-specific data in the processing of S306.

In S306, when the main CPU 101 determines that the determination data is not the RT state-specific data (when the determination in S306 is NO), the main CPU 101 performs the process of S308 described later. On the other hand, in S306, when the main CPU 101 determines that the determination data is the RT state-specific data (when the determination in S306 is YES), the main CPU 101 uses the RT state-specific lottery value selection table (not) based on the determination data. Selection data is acquired from (shown in the figure), and the acquired selection data is set in the determination data (S307).

After the processing of S307 or when the determination in S306 is NO, the main CPU 101 determines whether or not the determination data of the lottery target combination is the data for each setting (S308). In this process, the main CPU 101 determines whether or not the currently acquired lottery target combination is an internal winning combination whose lottery value changes according to the set value. For example, the main CPU 101 determines whether or not the address defined in the currently acquired lottery target combination determination data is an address in the internal lottery value table (not shown) for each setting.

For example, in the internal lottery table shown in FIGS. 16 and 17, when the internal winning combination “F_common bell” is specified so that the higher the set value, the higher the lottery value, the internal winning combination “F_common bell” is specified. The judgment data associated with "" corresponds to the internal winning combination "F_common bell" because the address of the internal winning combination "F_common bell" in the setting-specific lottery value selection table (not shown) is specified. The attached judgment data corresponds to the setting-specific data. Therefore, when the currently acquired lottery target combination is the internal winning combination “F_common bell”, the main CPU 101 determines that the determination data is the setting-specific data in the process of S308.

In S308, when the main CPU 101 determines that the determination data is not the setting-specific data (when the determination in S308 is NO), the main CPU 101 performs the process of S310 described later. On the other hand, in S308, when the main CPU 101 determines that the determination data is the data for each setting (when the determination in S308 is YES), the main CPU 101 adds the set value data (any of 0 to 5) to the determination data. Then, the added value is set in the determination data (S309). The set value data added to the determination data in this process is the data associated with the set value, but the set value data "0" to "5" are not the values of the set value itself, but are "0" to "5", respectively. It is the data corresponding to "setting 1" to "setting 6".

After the processing of S309 or when the determination in S308 is NO, the main CPU 101 calculates the address of the area in which the lottery value of the lottery target combination is stored based on the set determination data, and the lottery stored in the address. Get the value (S310).

For example, when the lottery target combination is an internal winning combination (for example, "F_black BAR") whose lottery value does not change depending on either the RT state or the set value, the main CPU 101 starts from the address indicated by the determination data. Acquire the lottery value "8".

Further, for example, when the lottery target combination is an internal winning combination (for example, "F_normal lip") whose lottery value varies depending on the RT state, the main CPU 101 is in the RT0 state from the address indicated by the determination data. If it is (RT0), the lottery value "8332" is acquired, if it is the RT4 state (RT4), the lottery value "18041" is acquired, and if it is another RT state (RT1 to RT3), it is acquired. Acquire the lottery value "0".

Further, for example, when the lottery target combination is an internal winning combination (for example, "F_common bell") whose lottery value changes depending on the RT state, the main CPU 101 sets a value from the address indicated by the determination data. The lottery value corresponding to "1" to "6" is acquired. At this time, the lottery value corresponding to the set value is acquired by adding the set value data to the determination data (processing in S309) and designating the obtained address.

Further, for example, when the lottery target combination is an internal winning combination whose lottery value varies depending on both the RT state and the set value, the main CPU 101 has an internal lottery value table for each RT state and an internal lottery value table for each setting. The lottery value is obtained with reference to both (see S306 to S309).

Next, the main CPU 101 acquires a random number value (any of 0 to 65535) for the internal winning combination lottery stored in the random number storage area (S311).

Next, the main CPU 101 performs a lottery execution process (S312). In this process, the main CPU 101 adds the random number value acquired in S311 to the lottery value acquired in S310, and sets the addition result as the lottery result (winning / non-winning of the lottery target combination). In this lottery execution process, when the sum of the lottery value and the random number value exceeds 65535 (overflow), it is determined that the lottery target combination has won (the lottery target combination has been determined as the internal winning combination). To.

Next, the main CPU 101 stores a value obtained by adding the lottery value to the random number value (random number value after the lottery execution) as a new random number value in the random number storage area (S313). Next, the main CPU 101 determines whether or not the lottery execution process has won (whether or not an overflow has occurred) (S314).

In S314, when the main CPU 101 determines that the winning combination has been won in the lottery execution process (when the determination in S314 is YES), the main CPU 101 refers to the internal lottery table and refers to the winning request flag status (corresponding to the winning internal winning combination). The value of the "winning number") is acquired (S315). For example, in the general game, if the winning combination is won in the lottery execution process when the lottery target combination is "F_normal lip", in the process of S315, "1" is acquired as the hit request flag status. Then, after the processing of S315, the main CPU 101 performs the processing of S319 described later.

On the other hand, in S314, when the main CPU 101 determines that the lottery has not been won in the lottery execution process (when the determination in S314 is NO), the main CPU 101 updates the lottery target combination to the next combination in the internal lottery table, and draws. The number of times is subtracted by 1 (S316). Next, the main CPU 101 determines whether or not the number of lottery after subtraction is "0" (S317).

In S317, when the main CPU 101 determines that the number of lottery after subtraction is not "0" (when the determination in S317 is NO), the main CPU 101 returns the process to the process of S305 and repeats the processes after S305.

On the other hand, in S317, when the main CPU 101 determines that the number of lottery after subtraction is "0" (when the determination in S317 is YES), that is, when the internal winning combination is "missing", the main CPU 101 determines. Set the loss status (S318). The "lost status" corresponds to the hit request flag status in which the winning number is "0". Then, after the processing of S318, the main CPU 101 performs the processing of S319 described later.

Next, the main CPU 101 determines whether or not the CB is in operation (S319). That is, the main CPU 101 determines whether or not it is in the MB gaming state (MB operating). When the main CPU 101 determines in S319 that the CB is not operating (when the determination in S319 is NO), the main CPU 101 ends the internal lottery process and shifts the process to S205 in the main flow (see FIG. 54).

On the other hand, in S319, when the main CPU 101 determines that the CB is in operation (when the determination in S319 is YES), the main CPU 101 sets all the small winning bits in the hit request flag storage area (internal winning combination storage area). The process of turning it on is performed (S320). That is, during the CB operation, the main CPU 101 performs a process of winning all the small winning combinations regardless of the result of the internal lottery process. Specifically, the main CPU 101 performs a process of storing "1" in the bits corresponding to NML01 (S_L1st miss A) to NML23 (S_chance 3) in the hit request flag storage area (internal winning combination storage area). .. Then, after the processing of S320, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 54).

In the present embodiment, the internal lottery process is performed as described above. The processes S302 to S305 during the internal lottery process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 65A. Among them, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 65A.

When, for example, the source code "LDIN ss, (HL)" is executed on the source program, the memory specified by the address set in the HL register (pair register) and the address obtained by adding "1" to the address. The contents (data) of are loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (2 addition). Therefore, when the source code "LDIN AC, (HL)" in FIG. 65A is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the AC register, and the address set in the HL register is updated by +2 (2 addition). In the determination data acquisition process of S305, as described above, the determination data is stored in the A register and the request flag status is stored in the C register by this "LDIN" instruction (predetermined read instruction). ..

As described above, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed by one instruction code (“LDIN” instruction). In this case, the instruction code related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, the processes of S308 and S309 during the internal lottery process described above are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 65B. Among them, in the addition processing of the set value data (any of 0 to 5) of S309, the main CPU 101 uses the source codes "MUL A, 6" and "ADDQ A, (.LOW.wWAVENUM)" in FIG. 65B. It is performed by executing in this order. Both the "MUL" instruction and the "ADDQ" instruction are instruction codes dedicated to the main CPU 101, and the "ADDQ" instruction is an instruction code dedicated to the main CPU 101 that specifies an address using a Q register (extension register).

When, for example, the source code "MUL A, n" is executed on the source program, the stored data in the A register is multiplied by the 1-byte integer n, and the multiplication result is stored in the A register. Therefore, in the source code "MUL A, 6" in FIG. 65B, the contents (stored data) of the A register are multiplied by a 1-byte integer 6, and the multiplication result is stored in the A register. This multiplication process is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, since the pachi-slot machine 1 of the present embodiment is provided with a dedicated calculation circuit (calculation circuit 107) for executing multiplication processing and division processing on the source program, the efficiency of multiplication processing and division processing should be improved. Can be done.

Further, for example, when the source code "ADDQ r, (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer k (direct value: lower address value) are executed. The stored data of the r register (A, B, C, D, E, H or L register) is added to the memory contents (stored data) of the address specified by), and the addition result is stored in the r register. To. Therefore, when the source code "ADDQ A, (.LOW.wWAVENUM)" in FIG. 65B is executed, the stored data of the Q register and the memory of the address specified by the 1-byte integer value ".LOW.wWAVENUM". The contents (stored data) of the A register are added to the contents (set value data) of, and the addition result is stored in the A register.

That is, in the example shown in FIG. 65B, in the addition processing of the set value in S309, the coefficient "6" is multiplied by the relative value for selecting the lottery table, and the set value data is added to the multiplied value to obtain the lottery target combination. The address of the lottery table in which the lottery value of is stored is calculated.

As described above, in the present embodiment, the main CPU 101 dedicated instruction code (“ADDQ” instruction) using the Q register (extension register) is used in the internal lottery process, and if this instruction code is used, the direct value is used. Therefore, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. Therefore, the instruction related to the address setting can be omitted on the source program of the internal lottery processing, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Second interface board control process (non-standard)]
Next, with reference to FIG. 66, the second interface board control process performed in S207 in the main flow (see FIG. 54) will be described. FIG. 66 is a flowchart showing the procedure of the second interface board control process. This process is performed in the non-standard work area (see FIG. 12C) in the main RAM 103. Further, the program used in the second interface board control process is stored in the non-standard area in the main ROM 102 (see FIG. 12B).

First, the main CPU 101 saves the address data of the stack area in the main RAM 103 set in the stack pointer (SP) (S361). Next, the main CPU 101 sets the address data of the non-standard stack area in the main RAM 103 in the stack pointer (SP) (S362).

Next, the main CPU 101 acquires navigation data (S363). Next, the main CPU 101 sets the navigation conversion table in the non-standard work area in the main RAM 103 (S364).

Next, the main CPU 101 refers to the navigation conversion table and acquires the push order number for the second interface (S365). Next, the main CPU 101 stores the acquired push order number for the second interface in the non-standard push order number storage area (not shown) provided in the non-standard work area (S366). Next, the main CPU 101 sets “0” to the value of the pressing position table selection counter provided in the non-standard work area (S367).

Next, the main CPU 101 determines whether or not the acquired navigation data is push order navigation (navigation data for push order small combination) (S368). In S368, when the main CPU 101 determines that the acquired navigation data is the push order navigation (when the determination in S368 is YES), the main CPU 101 performs the process of S372 described later.

On the other hand, in S368, when the main CPU 101 determines that the acquired navigation data is not the push-order navigation (when the determination in S368 is NO), the main CPU 101 determines that the acquired navigation data is the navigation data (10) for the BB1 stop operation. It is determined whether or not it is (S369).

In S369, when the main CPU 101 determines that the acquired navigation data is the navigation data for the BB1 stop operation (when the determination in S369 is YES), the main CPU 101 performs the process of S371 described later. On the other hand, in S369, when the main CPU 101 determines that the acquired navigation data is not the navigation data for the BB1 stop operation (when the determination in S369 is NO), the main CPU 101 sets the value of the pressing position table selection counter to "1". Is added (S370). In S370, the process of adding "1" to the value of the pressing position table selection counter is a process performed to acquire the pressing position of BB2 from the pressing position table (not shown).

After the processing of S370 or when the determination in S369 is YES, the main CPU 101 adds "1" to the value of the pressing position table selection counter (S371). In S371, the process of adding "1" to the value of the pressing position table selection counter is a process performed to acquire the pressing position of BB1 or BB2 from the pressing position table (not shown).

After the processing of S371 or when the determination in S368 is YES, the main CPU 101 selects the pressing position table (not shown) based on the value of the pressing position table selection counter (S372). Next, the main CPU 101 refers to the selected pressing position table and acquires pressing position data for three reels (left reel 3L, middle reel 3C, and right reel 3R) (S373). Next, the main CPU 101 stores the acquired pressing position data in the non-standard pressing position storage area (not shown) provided in the non-standard work area (S374). By the processing of S367 to S371, if the navigation data is the push order navigation, the value of the push position table selection counter becomes "0", and if the navigation data is the navigation data for the BB1 stop operation, the push position table selection counter The value is "1", and if the navigation data is the navigation data for the BB2 stop operation, the value of the pressing position table selection counter is "2". That is, the pressed position data is acquired based on the navigation data.

The processing of S369 and S371 is a processing when a plurality of "BB" as bonus combinations (for example, two of BB1 and BB2) are provided, and in the present embodiment, "BB" as a bonus combination. Since only one is provided (see FIG. 18), the processing of S369 and S371 becomes unnecessary. However, also in the present embodiment, a plurality of (for example, two or more) "BBs" as bonus combinations may be provided, and in this case, the processing of S369 and S371 or the same processing is performed. Then, the value of the pressing position table selection counter according to the type of the bonus combination may be selected.

Next, the main CPU 101 performs the second interface board output process (S375). The details of the second interface board output process will be described later with reference to FIG. 67 described later.

Next, the main CPU 101 performs restoration processing of all registers (S376). Next, the main CPU 101 sets the address data of the stack area saved in S361 in the stack pointer (SP) (S377). Then, after the processing of S377, the main CPU 101 ends the second interface board control processing, and shifts the processing to S208 of the main flow (see FIG. 54).

[Second interface board output processing]
Next, the second interface board output process performed in S375 during the second interface board control process (see FIG. 66) will be described with reference to FIG. 67. FIG. 67 is a flowchart showing the procedure of the second interface board output processing. The second interface board output process is performed in the non-standard work area of the main RAM 103.

First, the main CPU 101 determines whether or not the transmission operation is performed via the second interface serial line (second serial communication circuit 115: SCU2) (S381). When the main CPU 101 determines in S381 that the transmission operation is being performed via the serial line for the second interface (when the determination in S381 is YES), the main CPU 101 ends the second interface board output process. The process is transferred to S376 of the second interface board control process (see FIG. 66).

On the other hand, in S381, when the main CPU 101 determines that the transmission operation is not performed via the serial line for the second interface (when the determination in S381 is NO), the main CPU 101 is provided in the non-standard work area. The loop counter value is set to "3" (the number of reels), and the serial communication sum value is set to the initial value "1" (S382). Next, the main CPU 101 transmits transmission start data via the second interface serial line (second serial communication circuit 115: SCU2) (S383).

Next, the main CPU 101 refers to the non-standard pressing position storage area of the predetermined reel (rotary reel), and acquires the pressing position data of the predetermined reel (S384). Next, the main CPU 101 updates the reference non-standard pressing position storage area to that of the next target reel (rotary reel) (S385).

Next, the main CPU 101 acquires pulse number data corresponding to the pressing position data (symbol position) based on the pulse conversion data (not shown) and the acquired pressing position data (S386). The details of the correspondence between the pressing position data (symbol position) and the pulse number data will be omitted, but for example, the acquired pressing position data (symbol position) is "3" (symbol "blue 7" in the left reel 3L). ), "38" is acquired as pulse number data, and when the pressing position data (symbol position) is "10" (symbol "black BAR" in the left reel 3L), it is as pulse number data. "155" is acquired. Further, for example, when the acquired pressing position data (symbol position) is "12" (symbol "white 7" in the left reel 3L), "189" is acquired as pulse number data, and the pressing position data (symbol) is acquired. When the position) is "15" (the symbol "black BAR" in the left reel 3L), "239" is acquired as the pulse number data.

Next, the main CPU 101 transmits the acquired pulse number data via the second interface serial line (second serial communication circuit 115: SCU2) (S387). Next, the main CPU 101 adds the pulse number data to the serial communication sum value (S388). Next, the main CPU 101 subtracts 1 from the value of the loop counter (S389).

Next, the main CPU 101 determines whether or not the value of the loop counter is "0" (S390). In S390, when the main CPU 101 determines that the value of the loop counter is not "0" (when the determination in S390 is NO), the main CPU 101 changes the target reel to the next reel and returns the process to S384. The processing after S384 is repeated.

On the other hand, in S390, when the main CPU 101 determines that the value of the loop counter is "0" (when the determination in S390 is YES), the main CPU 101 sets the serial communication sum value to the serial line for the second interface (first). 2 Serial communication circuit 115: SCU2) for transmission (S391). Then, after the processing of S391, the main CPU 101 ends the second interface board output processing, and shifts the processing to S376 of the second interface board control processing (see FIG. 66).

[Control processing by state]
Next, with reference to FIG. 68, the state-specific control processing performed in S208 in the main flow (see FIG. 54) will be described. FIG. 68 is a flowchart showing the procedure of the state-specific control process.

First, the main CPU 101 determines whether or not the current game is in ART (see FIG. 14) (S401). In S401, when the main CPU 101 determines that the current game is not in ART (when the determination in S401 is NO), the main CPU 101 performs the process of S409 described later.

Although not shown in FIG. 68, when the main CPU 101 determines that the current game is in ART (when the determination in S401 is YES), the game is played according to the RT state, the internal winning combination, and the like. In order to notify the procedure of the stop operation that is advantageous to the player (see FIGS. 19 to 21), the navigation data indicating the procedure of the stop operation that is advantageous to the player is provided in the navigation data storage area of the main RAM 103 (see FIG. 102A described later). Performs the process of storing in.

On the other hand, in S401, when the main CPU 101 determines that the current game is in ART (when the determination in S401 is YES), the main CPU 101 determines whether or not the current game is in the double specialization zone (see FIG. 14). (S402). In S402, when the main CPU 101 determines that the current game is in the double specialization zone (when the determination in S402 is YES), the main CPU 101 performs the start processing in the double specialization zone (S403). The details of the start processing in the double specialization zone will be described later with reference to FIGS. 69 and 70 described later. Then, after the processing of S403, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 54).

On the other hand, in S402, when the main CPU 101 determines that the current game is not in the double specialization zone (when the determination in S402 is NO), the main CPU 101 is in the CP specialization zone during BB (see FIG. 14). It is determined whether or not it is (S404). In S404, when the main CPU 101 determines that the current game is in the CP special zone in BB (when the determination in S404 is YES), the main CPU 101 performs the process at the start in the CP special zone in BB (S405). ). In the process at the start of the CP specialization zone in the BB, for example, as described above, the CP acquisition lottery is performed. Then, after the processing of S405, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 54).

On the other hand, in S404, when the main CPU 101 determines that the current game is not in the CP specialization zone during BB (when the determination in S404 is NO), the main CPU 101 is in the continuous challenge of the current game (see FIG. 14). Whether or not it is determined (S406). In S406, when the main CPU 101 determines that the current game is in the continuous challenge (when the determination in S406 is YES), the main CPU 101 performs the start processing during the continuous challenge (S407). The details of the start-time processing during the continuous challenge will be described later with reference to FIG. 71 described later. Then, after the processing of S407, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 54).

On the other hand, in S406, when the main CPU 101 determines that the current game is not in the continuous challenge (when the determination in S406 is NO), the main CPU 101 performs the process at the start during normal ART (S408). In this normal ART start-time processing, for example, as described above, various lottery such as ART stock lottery and CP acquisition lottery are performed, and the ART game number counter is subtracted by "1" for each game, and the number of ART games. When the counter reaches "0", a continuous challenge is set from the next game. Then, after the processing of S408, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 54).

In S401, when the main CPU 101 determines that the current game is not in ART (when the determination in S401 is NO), the main CPU 101 determines whether or not the current game is in a promotion chance (see FIG. 14) (see FIG. 14). S409). In S409, when the main CPU 101 determines that the current game is in the promotion chance (YES in S409), the main CPU 101 performs the start processing during the promotion chance (S410). The details of the process at the start during the promotion chance will be described later with reference to FIG. 72 described later. Then, after the processing of S410, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 54).

On the other hand, in S409, when the main CPU 101 determines that the current game is not in the promotion chance (when the determination in S409 is NO), the main CPU 101 is in the history specialization zone during BB (see FIG. 14). Whether or not it is determined (S411). In S411, when the main CPU 101 determines that the current game is in the history specialization zone during BB (when the determination in S411 is YES), the main CPU 101 performs the process at the start of the history specialization zone during BB (S412). ). In this BB middle history special zone middle start processing, for example, as described above, ART lottery is performed based on the winning history of the internal winning combination. Then, after the processing of S412, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 54).

On the other hand, in S411, when the main CPU 101 determines that the current game is not in the history specialization zone during BB (when the determination in S411 is NO), the main CPU 101 is in the chance zone for the current game (see FIG. 14). Whether or not it is determined (S413). In S413, when the main CPU 101 determines that the current game is in the chance zone (when the determination in S413 is YES), the main CPU 101 performs the start processing in the chance zone (S414). In this chance zone start processing, for example, as described above, ART lottery is performed for 5 games with a higher probability than in the normal time. Then, after the processing of S414, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 54).

On the other hand, in S413, when the main CPU 101 determines that the current game is not in the chance zone (when the determination in S413 is NO), the main CPU 101 performs the normal middle start process (S415). In this normal middle start process, for example, as described above, various lottery such as ART lottery and CZ lottery are performed. Then, after the processing of S415, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 54).

[Processing at start during double specialization zone]
Next, with reference to FIGS. 69 and 70, the process at the start of the double specialization zone performed in S403 during the state-specific control process (see FIG. 68) will be described. 69 and 70 are flowcharts showing the procedure at the start of the double specialization zone.

First, the main CPU 101 determines whether or not it is the start of the double specialization zone (S421). That is, the main CPU 101 determines whether or not it is the first game that has shifted from another production game state to the double specialization zone. In S421, when the main CPU 101 determines that it is the start of the double specialization zone (when the determination in S421 is YES), the main CPU 101 performs a state lottery at the start of the double specialization zone (S422). Specifically, the main CPU 101 determines the internal state of the double specialization zone based on the double specialization zone start state lottery table (see FIG. 33A).

On the other hand, in S421, when the main CPU 101 determines that it is not the start of the double specialization zone (when the determination in S421 is NO), and after the processing of S422, whether or not the main CPU 101 wins the "RT3 lip A". (S423). In S423, when it is determined that the main CPU 101 has not won the "RT3 lip A" (when the determination in S423 is NO), the main CPU 101 performs the process of S427 described later.

On the other hand, in S423, when the main CPU 101 determines that the "RT3 lip A" has been won (when the determination in S423 is YES), the main CPU 101 performs a blue 7 fake notification lottery (S424). Specifically, the main CPU 101 determines whether or not to execute the blue 7 challenge effect based on the blue 7 fake lottery table (see FIG. 33C) in the double specialization zone.

Next, the main CPU 101 determines in S424 whether or not the blue 7 fake notification lottery has been won (S425). In S425, when the main CPU 101 determines that the blue 7 fake notification lottery has not been won (when the determination in S425 is NO), the main CPU 101 performs the process of S436 described later.

On the other hand, in S425, when the main CPU 101 determines that the blue 7 fake notification lottery has been won (when the determination in S425 is YES), the main CPU 101 performs a process of turning on the end prohibition flag (S426). By this process, the end lottery of the double specialization zone is not performed in the game. Then, after the processing of S426, the main CPU 101 performs the processing of S436 described later.

In S423 described above, when it is determined that the main CPU 101 has not won the "RT3 lip A" (when the determination in S423 is NO), the main CPU 101 determines whether or not the "RT3 lip C" has been won. (S427). In S427, when the main CPU 101 determines that the "RT3 lip C" has not been won (when the determination in S427 is NO), the main CPU 101 performs the process of S433 described later.

On the other hand, in S427, when the main CPU 101 determines that the "RT3 lip C" has been won (when the determination in S427 is YES), the main CPU 101 performs a process of turning on the end prohibition flag (S428). By this process, the end lottery of the double specialization zone is not performed in the game. Next, the main CPU 101 performs a process of adding "1" to the ART stock counter (S429). By this process, ART stock is added. Next, the main CPU 101 performs a blue 7 o'clock CP acquisition lottery (S430). Specifically, the main CPU 101 determines whether or not CP is acquired based on the blue 7 o'clock CP acquisition lottery table (see FIG. 33 (B)) in the double specialization zone.

Next, the main CPU 101 determines whether or not the blue 7 o'clock CP acquisition lottery has been won (S431). In S431, when the main CPU 101 determines that the blue 7 o'clock CP acquisition lottery has not been won (when the determination in S431 is NO), the main CPU 101 performs the process of S436 described later.

On the other hand, in S431, when the main CPU 101 determines that the blue 7 o'clock CP acquisition lottery has been won (when the determination in S431 is YES), the main CPU 101 performs a process of adding "1" to the CP counter (S432). By this process, CP is added. In this process, the value to be added to the CP counter may be determined by lottery. Then, after the processing of S432, the main CPU 101 performs the processing of S436 described later.

In S427 described above, when it is determined that the main CPU 101 has not won the "RT3 lip C" (when the determination in S427 is NO), the main CPU 101 performs a CP acquisition lottery in the double specialization zone (S433). Specifically, the main CPU 101 determines whether or not CP is acquired based on the CP acquisition lottery table (see FIG. 32) in the double specialization zone.

Next, the main CPU 101 determines whether or not the CP acquisition lottery in the double specialization zone has been won (S434). In S434, when it is determined that the main CPU 101 has not won the CP acquisition lottery in the double specialization zone (when the determination in S434 is NO), the main CPU 101 performs the process of S436 described later.

On the other hand, in S434, when the main CPU 101 determines that the CP acquisition lottery in the double specialization zone has been won (when the determination in S434 is YES), the main CPU 101 performs a process of adding "1" to the CP counter (S435). ). By this process, CP is added. In this process, the value to be added to the CP counter may be determined by lottery.

Next, the main CPU 101 determines whether or not the number of remaining games (guaranteed games) in the double specialization zone is greater than 0 (S436). That is, the main CPU 101 determines whether or not the number of guaranteed games is within the double specialization zone. In S436, when the main CPU 101 determines that the number of remaining games (guaranteed games) in the double specialization zone is a value greater than 0 (when the determination in S436 is YES), the main CPU 101 is in the double specialization zone. The number of remaining games (the number of guaranteed games) is subtracted by "1" (S437).

On the other hand, in S436, when the main CPU 101 determines that the number of remaining games (guaranteed games) in the double specialization zone is not a value larger than 0 (when the determination in S436 is NO), and after the processing of S437, the main CPU 101 Determines whether or not the number of remaining games (the number of guaranteed games) in the double specialization zone is 0 (S438). That is, the main CPU 101 determines whether or not the guaranteed number of games has been exhausted. In S438, when the main CPU 101 determines that the number of remaining games (guaranteed games) in the double specialization zone is not 0 (when the determination in S438 is NO), the main CPU 101 performs the process of S450 described later.

On the other hand, in S438, when the main CPU 101 determines that the number of remaining games (guaranteed games) in the double specialization zone is 0 (when the determination in S438 is YES), the main CPU 101 wins the "normal role". It is determined whether or not it has been done (S439). In S439, when the main CPU 101 determines that the "normal combination" has not been won (when the determination in S439 is NO), the main CPU 101 performs the process of S450 described later.

On the other hand, in S439, when the main CPU 101 determines that the "normal combination" has been won (when the determination in S439 is YES), the main CPU 101 determines whether or not the end prohibition flag is on (S440). When the main CPU 101 determines in S440 that the end prohibition flag is ON (when the determination in S440 is YES), the main CPU 101 performs the process of S450 described later.

On the other hand, when it is determined in S440 that the end prohibition flag is not on (when the determination in S440 is NO), the main CPU 101 performs a double specialization zone end lottery (S441). Specifically, the main CPU 101 determines whether or not to end the double special zone based on the double special zone end lottery table (see FIG. 33 (D)).

Next, the main CPU 101 determines whether or not the double specialization zone end lottery has been won (S442). In S442, when it is determined that the main CPU 101 has not won the double specialization zone end lottery (when the determination in S442 is NO), the main CPU 101 performs the process of S450 described later.

On the other hand, in S442, when it is determined that the main CPU 101 has won the double specialization zone end lottery (when the determination in S442 is YES), the main CPU 101 performs a process of ending the double specialization zone (S443).

Next, the main CPU 101 determines whether or not the state before the start (that is, the effect game state before the transition to the double specialization zone) is a promotion chance (S444). In S444, when the main CPU 101 determines that the pre-start state is a promotion chance (when the determination in S444 is YES), the main CPU 101 sets the promotion chance (S445) and performs the process of S449 described later. By this process, after the end of the double specialization zone, it returns to the promotion chance.

On the other hand, in S444, when the main CPU 101 determines that the pre-start state is not a promotion chance (NO in S444), the main CPU 101 determines whether or not the pre-start state is a continuous challenge (S446). .. In S446, when the main CPU 101 determines that the pre-start state is a continuous challenge (when the determination in S446 is YES), the main CPU 101 sets the continuous challenge (S447) and performs the process of S449 described later. By this process, after the end of the double specialization zone, it returns to the continuous challenge.

On the other hand, in S446, when the main CPU 101 determines that the pre-start state is not a continuous challenge (when the determination in S446 is NO), the main CPU 101 sets the normal ART (S448). By this process, after the end of the double specialization zone, the process shifts to the normal ART.

Next, the main CPU 101 initializes the pre-start state (S449), turns it off if the end prohibition flag is on in the game (S450), ends the process at the start in the double special zone, and mains the process. The process moves to S209 of the process (see FIG. 54).

[Processing at start during continuous challenge]
Next, with reference to FIG. 71, the process at the start of the continuous challenge performed in S407 during the state-specific control process (see FIG. 68) will be described. FIG. 71 is a flowchart showing the procedure at the start of the continuous challenge.

First, the main CPU 101 determines whether or not the "RT3 lip C" has been won (S461). In S461, when it is determined that the main CPU 101 has not won the "RT3 lip C" (when the determination in S461 is NO), the main CPU 101 performs the process of S467 described later.

On the other hand, in S461, when the main CPU 101 determines that the "RT3 lip C" has been won (when the determination in S461 is YES), the main CPU 101 performs a promotion chance special activation lottery (S462). Specifically, the main CPU 101 performs a special activation lottery as to whether or not to shift to a promotion chance, for example, with a probability of 1/256.

Next, the main CPU 101 determines whether or not the promotion chance special activation lottery has been won (S463). In S463, when the main CPU 101 determines that the promotion chance special activation lottery has not been won (when the determination in S463 is NO), the main CPU 101 performs the process of S467 described later.

On the other hand, in S463, when the main CPU 101 determines that the promotion chance special activation lottery has been won (when the determination in S463 is YES), the main CPU 101 sets the navigation data for establishing blue 7 (S464). By this process, information (pushing order) of the stop operation in which a specific symbol (in this case, the "blue 7" symbol) is lined up on a specific line is notified.

Next, the main CPU 101 turns on the promotion chance activation flag (S465). By this process, the next game is shifted to the promotion chance.

Next, the main CPU 101 reserves the promotion chance start lock effect (S466). By this process, at the start of the next game, a lock effect for notifying that the promotion chance starts is executed. Then, after the processing of S466, the processing at the start during the continuous challenge is ended, and the processing is transferred to S209 of the main processing (see FIG. 54).

In S461 described above, when it is determined that the main CPU 101 has not won the "RT3 lip C" (when S461 is a NO determination), and in S463 described above, the main CPU 101 has won the promotion chance special activation lottery. When it is determined that the case is not present (when the determination in S463 is NO), the main CPU 101 determines whether or not the "RT3 lip B" has been won (S467). In S467, when the main CPU 101 determines that the "RT3 lip B" has not been won (when the determination in S467 is NO), the main CPU 101 performs the process of S475 described later.

On the other hand, in S467, when the main CPU 101 determines that the "RT3 lip B" has been won (when the determination in S467 is YES), the main CPU 101 sets the navigation data for establishing blue 7 (S468). .. By this process, information (pushing order) of the stop operation in which a specific symbol (in this case, the "blue BAR" symbol) is lined up on a specific line is notified.

Next, the main CPU 101 performs a promotion chance activation lottery (S469). Specifically, for example, an activation lottery is performed to determine whether or not to shift to a promotion chance with a probability of 4/256.

Next, the main CPU 101 determines whether or not the promotion chance activation lottery has been won (S470). In S470, when the main CPU 101 determines that the promotion chance activation lottery has not been won (when the determination in S470 is NO), the main CPU 101 performs the process of S473 described later.

On the other hand, in S470, when the main CPU 101 determines that the promotion chance activation lottery has been won (when the determination in S470 is YES), the main CPU 101 turns on the promotion chance activation flag (S471). By this process, the next game is shifted to the promotion chance.

Next, the main CPU 101 reserves the promotion chance expectation lock effect (success) (S472). By this process, at the start of the next game, a common lock effect for expecting the promotion chance to start (for example, an effect in which the reel action of rotating each reel in the reverse direction is executed twice) is executed, and then promotion is performed. A fixed lock effect (for example, an effect in which a reel action for rotating each reel in the reverse direction is executed) is executed to notify that the chance starts. Then, after the processing of S472, the processing at the start during the continuous challenge is ended, and the processing is transferred to S209 of the main processing (see FIG. 54).

In S470 described above, when the main CPU 101 determines that the promotion chance activation lottery has not been won (when the determination in S470 is NO), the main CPU 101 performs a process of adding "50" to the ART game number counter (S473). ). By this process, after the end of the continuous challenge, it is possible to return to the normal ART in the set with the added number of ART games.

Next, the main CPU 101 reserves the promotion chance expectation lock effect (failure) (S474). By this process, at the start of the next game, the above-mentioned common lock effect is executed, but the final lock effect is not executed. Then, after the processing of S474, the processing at the start during the continuous challenge is ended, and the processing is transferred to S209 of the main processing (see FIG. 54).

In S467 described above, when it is determined that the main CPU 101 has not won the "RT3 lip B" (when the determination in S467 is NO), the main CPU 101 performs a CP acquisition lottery (S475). Specifically, the main CPU 101 performs a CP acquisition lottery based on the internal winning combination and the random value for production.

Next, the main CPU 101 determines whether or not the CP acquisition lottery has been won (S476). In S476, when the main CPU 101 determines that the CP acquisition lottery has been won (when the determination in S476 is YES), the main CPU 101 performs a process of adding "1" to the CP counter (S477). By this process, CP is added. In this process, the value to be added to the CP counter may be determined by lottery. Then, after the processing of S477, the processing at the start during the continuous challenge is ended, and the processing is transferred to S209 of the main processing (see FIG. 54).

On the other hand, in S476, when the main CPU 101 determines that the CP acquisition lottery has not been won (when the determination in S476 is NO), the main CPU 101 has "RT1 lip", "RT2 lip", "RT3 lip A", Alternatively, it is determined whether or not the "RT3 lip C" has been won or "missed" (S478). In S478, when the main CPU 101 determines that "RT1 lip", "RT2 lip", "RT3 lip A", or "RT3 lip C" is not a win or "missing" (when S478 is a NO determination), The main CPU 101 ends the process at the start during the continuous challenge, and shifts the process to S209 of the main process (see FIG. 54).

On the other hand, in S478, when the main CPU 101 determines that the "RT1 lip", "RT2 lip", "RT3 lip A", or "RT3 lip C" is a win or "missing" (S478 is a YES determination). Case), the main CPU 101 performs a process of subtracting "1" from the CP counter (S479). In this process, the value for subtracting the CP counter may be determined by lottery. Then, after the processing of S479, the processing at the start during the continuous challenge is ended, and the processing is transferred to S209 of the main processing (see FIG. 54).

[Processing at start during promotion chance]
Next, with reference to FIG. 72, the process at the start of the promotion chance to be performed in S410 during the state-based control process (see FIG. 68) will be described. FIG. 72 is a flowchart showing the procedure at the start of the promotion chance. Although not shown in FIG. 72, the main CPU 101 has a stop operation procedure (FIGS. 19 to 21) that is advantageous for the player according to the RT state, the internal winning combination, and the like even during the promotion chance. In order to notify (see), a process of storing the navigation data indicating the procedure of the stop operation advantageous to the player in the navigation data storage area of the main RAM 103 (see FIG. 102A described later) is performed.

First, the main CPU 101 performs a continuous guarantee lottery for promotion chances (S491). Specifically, the main CPU 101 determines that, for example, when the internal winning combination is a specific combination other than the fixed combination (for example, "F_strong bell"), the promotion chance is continued with a probability of 1/2. ..

Next, the main CPU 101 determines whether or not the lottery for continuous guarantee of promotion chance has been won (S492). In S492, when the main CPU 101 determines that the promotion chance continuation guarantee lottery has been won (when the determination in S492 is YES), the main CPU 101 performs the process of S495 described later.

On the other hand, in S492, when it is determined that the main CPU 101 has not won the promotion chance continuation guarantee lottery (when the determination in S492 is NO), the main CPU 101 performs the promotion chance continuation lottery (S493). Specifically, for example, when the main CPU 101 is the first game of the promotion chance, it decides to continue the promotion chance with a probability of 85/256, and when it is the second and subsequent games of the promotion chance, for example, Decide to continue the promotion chance with a probability of 128/256. In this process, it is possible to determine whether or not to continue the promotion chance for a plurality of consecutive games (for example, until the next game).

Next, the main CPU 101 determines whether or not the player has won the continuous lottery for the promotion chance (S494). In S494, when it is determined that the main CPU 101 has won the continuous lottery of the promotion chance (when the determination in S494 is YES), the main CPU 101 performs a process of adding "1" to the continuation number counter (S495). Then, after the processing of S495, the processing at the start during the promotion chance is terminated, and the processing is transferred to S209 of the main processing (see FIG. 54).

On the other hand, in S494, when the main CPU 101 determines that the promotion chance has not been won in the continuous lottery (when the determination in S494 is NO), the main CPU 101 adds the value corresponding to the continuation counter to the ART game number counter. , The process of clearing the continuation number counter is performed (S496). In this process, for example, if the continuation number counter is "0", the main CPU 101 sets the value of the ART game number counter to "111", and if the continuation number counter is "1", the value of the ART game number counter. Is set to "222". When the value of the ART game number counter is calculated by calculation (for example, the number of games played during the promotion chance is multiplied by the specified value "111"), it is set as the initial value of the continuation counter at the start of the promotion chance. "1" may be set.

Next, the main CPU 101 determines whether or not the pre-start state is a continuous challenge (S497). In S497, when the main CPU 101 determines that the pre-start state is a continuation challenge (when the determination in S497 is YES), the main CPU 101 sets the continuation challenge (S498) and initializes the pre-start state (S499). ). By this process, after the promotion chance ends, the player returns to the continuous challenge. Then, after the processing of S499, the processing at the start during the promotion chance is ended, and the processing is transferred to S209 of the main processing (see FIG. 54).

On the other hand, in S497, when the main CPU 101 determines that the pre-start state is not a continuous challenge (when the determination in S497 is NO), the main CPU 101 sets the normal ART (S500). By this process, after the promotion chance ends, the game shifts to the normal ART. Then, after the processing of S500, the processing at the start during the promotion chance is ended, and the processing is transferred to S209 of the main processing (see FIG. 54).

[Pull-in priority storage process]
Next, with reference to FIGS. 73 and 74, the pull-in priority storage process performed in S212 in the main flow (see FIG. 54) will be described. FIG. 73 is a flowchart showing the procedure of the pull-in priority storage process. Further, FIG. 74 is a diagram showing an example of a source program for executing the processes of S625 and S626 described later during the attraction priority storage process.

First, the main CPU 101 sets "3" to the number of search reels (S621). Next, the main CPU 101 performs a pull-in priority table selection process (S622). In this process, a pull-in priority table (not shown) is selected based on the internal winning combination and the operation stop button.

Next, the main CPU 101 performs a pull-in priority storage area selection process (S623). In this process, the pull-in priority data storage area of the reel to be searched is selected. Next, the main CPU 101 sets "20" as the number of symbol checks (number of times) (S624).

Next, the main CPU 101 performs a symbol code acquisition process (S625). In this process, the symbol code is acquired by referring to the winning operation flag storage area and the symbol code storage area corresponding to the number of symbol checks. The details of the symbol code acquisition process will be described later with reference to FIG. 75 described later.

Next, the main CPU 101 performs a logical product calculation process (S626). In this process, the main CPU 101 performs a process of generating the winning operation flag data. The details of the logical product calculation process will be described later with reference to FIG. 77 described later.

Next, the main CPU 101 performs a pull-in priority acquisition process (S627). In this process, the main CPU 101 has the bit set to "1" in the winning operation flag (display combination) storage area (see FIG. 22), and the bit is set to "1" in the hit request flag storage area. The attraction priority data is acquired by referring to the attraction priority table (not shown) for the winning combination. The details of the pull-in priority acquisition process will be described later with reference to FIGS. 78 and 79 described later.

Next, the main CPU 101 stores the acquired attraction priority data in the attraction priority data storage area (not shown) in the main RAM 103 (S628). At this time, the attraction priority data is stored in the attraction priority data storage area so that the value of each priority and the bit of the storage area correspond to each other.

The pull-in priority data storage area is provided with a priority data storage area for each type of main reel. In each attraction priority data storage area, the attraction priority data determined according to each symbol position "0" to "19" of the corresponding main reel is stored. In the present embodiment, by referring to this attraction priority data storage area, it is searched whether or not a more appropriate number of sliding pieces exists in addition to the number of sliding pieces determined based on the stop table.

The content of the priority pull-in data stored in the pull-in priority data storage area differs depending on the type of the pull-in priority table number in the pull-in priority table referred to when determining the pull-in priority data. Further, the pull-in priority data indicates that the larger the value, the higher the priority. By referring to the pull-in priority data, it is possible to relatively evaluate the priority among the symbols arranged on the peripheral surface of the main reel. That is, the symbol whose highest value is determined as the attraction priority data is the symbol with the highest priority. Therefore, it can be said that the pull-in priority data indicates the order between the symbols arranged on the peripheral surface of the main reel. If there are a plurality of symbols having the same value of the pull-in priority data, one symbol is determined according to the priority order defined by the priority order table.

Next, the main CPU 101 updates the pull-in priority storage area (S629). In this process, the main CPU 101 sets a pull-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts 1 from the number of symbol checks (S630). Next, the main CPU 101 determines whether or not the number of symbol checks is "0" (S631).

In S631, when the main CPU 101 determines that the number of symbol checks is not "0" (when the determination in S631 is NO), the main CPU 101 returns the process to the process of S625 and repeats the processes after S625. On the other hand, in S631, when the main CPU 101 determines that the number of symbol checks is "0" (when the determination in S631 is YES), the main CPU 101 performs a search target reel change process (S632).

Next, the main CPU 101 subtracts 1 from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is "0", that is, whether or not the above-mentioned series of processes has been performed on all the main reels (S634).

When the main CPU 101 determines in S634 that the number of search reels is not "0" (when the determination in S634 is NO), the main CPU 101 returns the process to the process of S622 and repeats the processes after S622. On the other hand, in S634, when the main CPU 101 determines that the number of search reels is "0" (when the determination in S634 is YES), the main CPU 101 ends the attraction priority storage process and performs the process in the main flow (FIG. FIG. (Refer to 54), move to S213.

In the present embodiment, the attraction priority storage process is performed as described above. The processing of S625 and S626 during the above-mentioned pull-in priority storage processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 74.

Among them, the logical product calculation process of S626 is performed by the main CPU 101 executing the source code "CALLF SB_DAND_00" in FIG. 74. The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_DAND_00" in FIG. 74 is executed, processing is performed at the address specified by "SB_DAND_00". The jump is made and the logical product calculation process is started.

[Design code acquisition process]
Next, the symbol code acquisition process performed in S625 during the attraction priority storage process (see FIG. 73) will be described with reference to FIGS. 75 and 76. FIG. 75 is a flowchart showing the procedure of the symbol code acquisition process, and FIG. 76 is a diagram showing an example of a source program for executing the symbol code acquisition process.

First, the main CPU 101 clears the winning operation flag storage area (S641). In this process, the main CPU 101 sets "0" in all the storage areas in the winning operation flag storage area (see FIG. 22). Next, the main CPU 101 sets the first reel symbol arrangement table (see FIG. 15) (S642).

Next, the main CPU 101 determines whether or not the first reel (left reel 3L) is stopped (S643).

In S643, when the main CPU 101 determines that the first reel (left reel 3L) is stopped (when the determination in S643 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, in S643, when the main CPU 101 determines that the first reel (left reel 3L) is not stopped (when the determination in S643 is NO), the main CPU 101 uses the second reel symbol arrangement table (see FIG. 15). Set (S644). In this process, the first reel symbol arrangement table set in the process of S642 is overwritten by the second reel symbol arrangement table.

Next, the main CPU 101 determines whether or not the second reel (middle reel 3C) is stopped (S645).

In S645, when the main CPU 101 determines that the second reel (middle reel 3C) is stopped (when the determination in S645 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, in S645, when the main CPU 101 determines that the second reel (middle reel 3C) is not stopped (when the determination in S645 is NO), the main CPU 101 uses the third reel symbol arrangement table (see FIG. 15). Set (S646). In this process, the second reel symbol arrangement table set in the process of S644 is overwritten by the third reel symbol arrangement table.

After the processing of S646, or when S643 or S645 is a YES determination, the main CPU 101 performs a symbol check process at the time of executing the stop operation on the reel to be stopped controlled, and corresponds to the symbol corresponding to the symbol acquired by the symbol check process. Acquire the winning operation table (not shown) (S647). The symbol-corresponding winning operation table (not shown) stores data indicating a winning operation flag (display combination) that can be stopped and displayed according to the stopped symbol. For example, when the first reel (left reel 3L) is stopped and the symbol located on the effective line during the stop operation is "replay" (see FIG. 18), "C_CL lip", "S_TT_XD lip", "C_" Acquires the start address of the symbol-corresponding winning operation table in which data indicating "special role", "S_CB 2", "S_weak chance", and "S_chance 3" is stored.

Next, the main CPU 101 sets the winning operation flag storage area (S648). Next, the main CPU 81 performs the compressed data storage process (S649). In this process, the main CPU 101 mainly performs a process of transferring (expanding) the winning operation flag data that can be won in the symbol-corresponding winning operation table to the corresponding storage area in the winning operation flag storage area.

After the processing of S649, the main CPU 101 sets the winning operation flag storage area updated by the compressed data storage processing, sets the symbol code storage area, and sets the data length of the winning operation flag storage area (7 bytes in this embodiment). Is set (S650). Then, after the processing of S650, the main CPU 101 ends the symbol code acquisition processing, and shifts the processing to S626 of the pull-in priority storage processing (see FIG. 73).

In the present embodiment, the symbol code acquisition process is performed as described above. The symbol code acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 76. Among them, the compressed data storage process of S649 is performed by the main CPU 101 executing the source code "CALLF SB_BTEP_00" in FIG. 76.

The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_BTEP_00" in FIG. 76 is executed, processing is performed at the address specified by "SB_BTEP_00". Jump and start the compressed data storage process. Then, in this compressed data storage process, as described above, the winning operation flag data (compressed data) stored in the symbol-corresponding winning operation flag table of each reel is expanded (copied) in the winning operation flag storage area.

In this embodiment, the data related to the winning is compressed / decompressed by the processing procedure described in S647 to S649 during the symbol code acquisition process described above, and the command code dedicated to the main CPU 101 described above is performed in the process. By using the above, it is possible to improve the efficiency of the compression / decompression processing of the data related to the winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

Further, in the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address "SB_BTEP_00" specified by the "CALLF" command is executed in the symbol setting process (see S205 of FIG. 54). In the compressed data storage process (not shown), it is configured to be the same as the jump destination address specified by the "CALLF" instruction. That is, in the present embodiment, the source program for executing the compressed data storage process performed in the symbol code acquisition process is the same as the source program for executing the compressed data storage process performed in the symbol setting process, and the compressed data storage is performed. The processing source program is shared (modularized). Therefore, it is not necessary to separately provide the source program for the compressed data storage process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Logical product operation processing]
Next, with reference to FIG. 77, for example, the logical product calculation process performed in S626 during the attraction priority storage process (see FIG. 73) will be described. FIG. 77 is a flowchart showing the procedure of the logical product calculation process. The logical product calculation process shown in FIG. 77 is performed not only in S626 in the attraction priority storage process (see FIG. 73) but also in S687 in the attraction priority acquisition process (see FIGS. 78 and 79 described later). Is also executed.

In the logical product calculation process executed in S626 during the attraction priority storage process (see FIG. 73), the two data to be logically producted are stored in the winning operation flag set in S650 during the above-mentioned symbol code acquisition process. The data of the area and the data of the symbol code storage area. The former data corresponds to the "logical product destination data" described later, and the latter data corresponds to the "logical product source data" described later. Further, in this case, the number of bytes "7" of the data length (7 bytes) set in S650 during the above-mentioned symbol code acquisition process corresponds to the "number of logical products" described later.

On the other hand, in the logical product operation process executed in S687 in the attraction priority acquisition process (see FIGS. 78 and 79 described later), the two data to be ANDed are the hit (retract) request flag storage area. Data and data of the winning operation flag storage area. The former data corresponds to the "logical product destination data" described later, and the latter data corresponds to the "logical product source data" described later. Further, in this case, the number of bytes "1" of the data length (1 byte) of the RT operation combination display flag described in FIG. 80B described later corresponds to the "logical product number" described later. The number of bytes "7", which is the data length of the hit request flag storage area and the winning operation flag storage area, may be made to correspond to the "logical product number" described later.

First, the main CPU 101 acquires the logical product source data (for example, the data of the symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation of the logical product source data and the logical product destination data (for example, data in the winning operation flag storage area), and saves the calculation result as the logical product destination data (S662).

Next, the main CPU 101 adds 1 to the address of the logical product source data to be acquired (S663). Next, the main CPU 101 adds 1 to the address of the logical product destination data to be referred to (S664).

Next, the main CPU 101 subtracts 1 from the number of logical products (S665). Next, the main CPU 101 determines whether or not the number of logical products is "0" (S666).

In S666, when the main CPU 101 determines that the number of logical products is not "0" (when the determination in S666 is NO), the main CPU 101 returns the process to the process of S661 and repeats the processes after S661. On the other hand, in S666, when the main CPU 101 determines that the number of logical products is "0" (when the determination in S666 is YES), the main CPU 101 ends the logical product calculation process and stores the process, for example, in the pull-in priority order. The process moves to S627 of the process (see FIG. 73).

[Pull-in priority acquisition process]
Next, the attraction priority acquisition process performed in S627 during the attraction priority storage process (see FIG. 73) will be described with reference to FIGS. 78 to 80. 78 and 79 are flowcharts showing the procedure of the attraction priority acquisition process. FIG. 80A is a diagram showing an example of a source program for executing the process of S680 to S683 described later during the attraction priority acquisition process, and FIG. 80B shows the process of S686 described later during the attraction priority acquisition process. It is a figure which shows an example of the source program for execution.

First, the main CPU 101 determines whether or not it is time to check the right reel 3R (specific display column) (S671).

When the main CPU 101 determines in S671 that it is not the time to check the right reel 3R (when the determination in S671 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S671, when the main CPU 101 determines that it is the time to check the right reel 3R (when the determination in S671 is YES), the main CPU 101 "ANY combination" in the symbol combination (winning combination) related to the internal winning combination. It is determined whether or not (a combination of predetermined symbols) is included (S672). The "ANY combination" here means a combination in which the winning is confirmed regardless of at least the stop symbol of the right reel 3R (at least the winning combination in which the stop symbol of the right reel 3R is an arbitrary symbol).

In S672, when the main CPU 101 determines that the symbol combination related to the internal winning combination does not include the "ANY combination" (when the determination in S672 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S672, when the main CPU 101 determines that the symbol combination related to the internal winning combination includes the "ANY combination" (when the determination in S672 is YES), the main CPU 101 determines that the "ANY combination" in the winning operation flag storage area. The storage area corresponding to the "combination" is masked (S673). Specifically, the main CPU 101 sets "1" in the bit corresponding to the "ANY combination" in the winning operation flag storage area.

After the processing of S673, or when S671 or S672 is determined to be NO, the main CPU 101 sets the address of the winning operation flag storage area (see FIG. 22) by adding "1" to the address of the last storage area. Is set, stop prohibition data is set, and the winning operation flag data length (data length of the winning operation flag storage area: 7 bytes in this embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons for which a stop operation is detected. Further, the operation state of the stop button is acquired by referring to the operation stop button storage area (see FIG. 25).

Next, the main CPU 101 subtracts (updates -1) the address of the set winning operation flag storage area by 1 (S676). Next, the main CPU 101 generates hit request flag data from the set winning operation flag storage area and the corresponding hit request flag storage area (see FIG. 22), and based on the generated hit request flag data. Generate a prohibited winning operating position (S677).

Next, the main CPU 101 determines whether or not the stop operation position is the prohibited winning operation position (S678).

In S678, when the main CPU 101 determines that the stop operation position is not the prohibited winning operation position (when the determination in S678 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, in S678, when the main CPU 101 determines that the stop operation position is the prohibited winning operation position (when the determination in S678 is YES), the value of the stop button operation counter of the main CPU 101 is the value of the third stop. Whether or not it is determined (S679).

In S679, when the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop (when the determination in S679 is YES), the main CPU 101 performs the process of S705 described later. On the other hand, in S679, when the main CPU 101 determines that the value of the stop button operation counter is not the value of the third stop (when the determination in S679 is NO), the value of the stop button operation counter of the main CPU 101 is the second stop. It is determined whether or not it is a value (S680).

In S680, when the main CPU 101 determines that the value of the stop button operation counter is not the value of the second stop (when the determination in S680 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, in S680, when the main CPU 101 determines that the value of the stop button operation counter is the value of the second stop (when the determination in S680 is YES), whether or not the main CPU 101 is after the right reel 3R is stopped. (S681).

In S681, when the main CPU 101 determines that the right reel 3R has been stopped (YES in S681), the main CPU 101 performs the process of S684 described later. On the other hand, in S681, when the main CPU 101 determines that the right reel 3R has not been stopped (when the determination in S681 is NO), the main CPU 101 has a flag that the hit request flag may be interfered with by "ANY combination". It is determined whether or not (whether or not "ANY role" is not included in the symbol combination (winning combination) related to the internal winning combination) (S682).

In S682, when the main CPU 101 determines that the hit request flag is not a flag that may be interfered with by the "ANY combination" (when the determination in S682 is YES), the main CPU 101 performs the process of S684 described later. On the other hand, in S682, when the main CPU 101 determines that the hit request flag is a flag that may be interfered with by the "ANY combination" (when the determination in S682 is NO), the main CPU 101 currently checks "ANY". It is determined whether or not it is time to check the hit request flag including the "combination" (S683).

In S683, when the main CPU 101 determines that the current check is the time to check the hit request flag including the "ANY combination" (when the determination in S683 is YES), the main CPU 101 performs the process of S705 described later.

On the other hand, in S683, when the main CPU 101 determines that the current check is not the time to check the hit request flag including "ANY combination" (when S683 is NO determination), when S678 or S680 is NO determination, or S681. Alternatively, when the determination in S682 is YES, the main CPU 101 subtracts 1 from the winning operation flag data length (S684). Next, the main CPU 101 determines whether or not the winning operation flag data length is “0” (S685).

In S685, when the main CPU 101 determines that the winning operation flag data length is not "0" (when the determination in S685 is NO), the main CPU 101 returns the processing to the processing of S676 and repeats the processing after S676.

On the other hand, in S685, when the main CPU 101 determines that the winning operation flag data length is "0" (when the determination in S685 is YES), the main CPU 101 performs a stop control pull-in request flag setting process (S686). .. This process is performed by sequentially executing each process specified in the source program of FIG. 80B by the main CPU 101. Therefore, in this process, the AND operation process described with reference to FIG. 77 is performed. In the logical product operation process executed in the process of S686, as described above, the data of the hit (pull-in) request flag storage area is set in the "logical product destination data", and the data of the winning operation flag storage area is set. It is set in the "logical product source data", and the number of bytes "1" of the data length (1 byte) of the RT operation combination display flag is set in the "logical product count". The RT operation combination display flag is a storage area in which the symbol combination related to the RT transition is defined in the winning operation flag storage area, and in the present embodiment, only the storage area 7 is provided as shown in FIG. As described above, the number of bytes “7”, which is the data length (7 bytes) of the hit request flag storage area and the winning operation flag storage area, may be set in the “logical product number”.

Next, the main CPU 101 refers to the pull-in priority table address storage area (not shown) to acquire the pull-in priority table (not shown) (S687).

Next, the main CPU 101 determines whether or not the data in the pull-in priority table stored at the currently set address is the end code (000H) (S688).

In S688, when the main CPU 101 determines that the data in the pull-in priority table stored at the currently set address is the end code (when the determination in S688 is YES), the main CPU 101 uses S705, which will be described later. Perform the processing of. On the other hand, in S688, when the main CPU 101 determines that the data in the pull-in priority table stored at the currently set address is not the end code (when the determination in S688 is NO), the main CPU 101 operates the winning operation. The flag storage area is set (S689).

Next, the main CPU 101 acquires the attraction priority data from the attraction priority table based on the currently set address (S690). Next, the main CPU 101 sets the block counter of the pull-in priority table (S691). In the present embodiment, in this process, the main CPU 101 sets "2" to the value of the block counter in the pull-in priority table.

Next, the main CPU 101 sets the number of checks of the attraction priority table, and adds 1 (+1 update) to the address of the attraction priority table to be referred to (S692). In the present embodiment, in this process, the main CPU 101 sets "8" as an example in the number of checks of the pull-in priority table. The number of checks in the pull-in priority table can be arbitrarily set according to the number of bits of the check data defined in the pull-in priority table.

Next, the main CPU 101 acquires check data based on the updated address of the pull-in priority table, and extracts check bits from the check data (S693).

Next, the main CPU 101 determines whether or not the value of the extracted check bit is “1” (S694).

In S694, when the main CPU 101 determines that the value of the extracted check bit is not "1" (when the determination in S694 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, in S694, when the main CPU 101 determines that the value of the extracted check bit is "1" (when the determination in S694 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referred to. (+1 update), and based on the updated address, the determination data is acquired from the pull-in priority table (S695).

Next, the main CPU 101 determines whether or not the currently acquired winning operation flag data is the determination target based on the determination data acquired in S695 (S696). In this process, the main CPU 101 compares the currently acquired winning operation flag data with the determination data, determines whether or not the former corresponds to the latter, and the former corresponds to the latter. In that case, it is determined that the currently acquired winning operation flag data is the determination target.

In S696, when the main CPU 101 determines that the winning operation flag data is not the determination target (when the determination in S696 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, in S696, when the main CPU 101 determines that the winning operation flag data is the determination target (when the determination in S696 is YES), the main CPU 101 updates the attraction priority data (S697). In this process, the main CPU 101 updates (overwrites) the currently set attraction priority data with the attraction priority data associated with the determination data acquired in S697.

Next, the main CPU 101 updates the check data (S698). In this process, the main CPU 101 shifts the check data by one bit to the right (direction from bit 7 to bit 0). In this process, "0" is set in bit 7 of the check data after the shift.

After the processing of S698, or when S694 or S696 is determined to be NO, the main CPU 101 determines whether or not there is a bit to be checked (a bit in which "1" is set) in the check data (S699).

In S699, when the main CPU 101 determines that there is no bit to be checked in the check data (when the determination in S699 is NO), the main CPU 101 performs the process of S702 described later. On the other hand, in S699, when the main CPU 101 determines that the check data has a bit to be checked (when the determination in S699 is YES), the main CPU 101 adds 1 to the address of the winning operation flag storage area to be checked (+1 update). ), And the number of checks is subtracted by 1 (S700).

Next, the main CPU 101 determines whether or not the number of checks is "0" (S701). When the main CPU 101 determines in S701 that the number of checks is not "0" (when the determination in S701 is NO), the main CPU 101 returns the process to the process of S698 and repeats the processes after S698.

On the other hand, in S701, when the main CPU 101 determines that the number of checks is "0" (when the determination in S701 is YES), the main CPU 101 sets the number of checks to the address of the winning operation flag storage area currently referred to. The initial value "8" is added to update the address of the winning operation flag storage area, and the value of the block counter is subtracted by 1 (S702). Next, the main CPU 101 determines whether or not the value of the block counter is "0" (S703).

When the main CPU 101 determines in S703 that the value of the block counter is not "0" (when the determination in S703 is NO), the main CPU 101 returns the process to the process of S692 and repeats the processes after S692.

On the other hand, in S703, when the main CPU 101 determines that the value of the block counter is "0" (when the determination in S703 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referred to (+1 update). ) (S704). Then, after the processing of S704, the main CPU 101 returns the processing to the processing of S688, and repeats the processing after S688.

Here, returning to the processing of S679, S683 or S688 again, if S679, S683 or S688 is a YES determination, the main CPU 101 uses the attraction order data set at this time as the final attraction priority data. Set (S705). If S679 or S683 is YES, the main CPU 101 sets "0 (00H)" as the final pull-in priority data. In this case, since the end code is assigned to the attraction priority data "0 (00H)", no attraction data (stop prohibition) is set. Then, after the processing of S705, the main CPU 101 ends the attraction priority acquisition process, and shifts the process to S628 of the attraction priority storage process (see FIG. 73).

In the present embodiment, the attraction priority acquisition process is performed as described above. The pull-in priority handling process of the “ANY combination” of S680 to S683 during the above-mentioned pull-in priority acquisition process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 80A. Be told. Among them, for example, the determination process of S683 is executed by a "JCP" instruction (predetermined determination instruction) on the source program. The "JCP" instruction is an instruction that executes an operation equivalent to a comparison instruction, and is an instruction code dedicated to the main CPU 101.

For example, when the source code "JCP cc, A, n, e" is executed on the source program, the contents (stored data) of the A register are compared with the integer n, and the comparison result is the condition of cc. If so, the process is jumped to the address specified by e. In the "cc condition" of the "JCP" instruction, one of the carry flag state and the zero flag state in the flag register F is specified (see FIG. 11). For example, if "C" is specified for cc, the condition of cc means that the carry flag is "1" (on state), and if "NC" is specified for cc, the condition of cc. Means that the carry flag is "0" (off state). Further, for example, if "Z" is specified for cc, the condition of cc means that the zero flag is "1" (on state), and if "NZ" is specified for cc, the condition of cc is The condition means that the zero flag is "0" (off state).

As shown in FIG. 80A, when the "JCP" instruction is used on the source program of the pull-in priority correspondence process of the "ANY role", the instruction related to the address setting can be omitted (the instruction related to the address setting is separately provided). Therefore, it is possible to increase the processing efficiency of the pull-in priority handling process of the "ANY combination" and reduce the capacity of the source program (the capacity used by the main ROM 102).

Further, the stop control pull-in request flag setting process of S686 during the pull-in priority acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 80B. In the stop control pull-in request flag setting process of S686, as shown in FIG. 80B, the "LDQ" instruction and the "CALLF" that specify the address using the Q register (extension register), which is the instruction code dedicated to the main CPU 101. The instruction is used.

Therefore, by using the "LDQ" instruction using the Q register (extension register) in the stop control pull-in request flag setting process of S686, the main ROM 102, the main RAM 103, and the memory map I / O are accessed by direct values. can do. In this case, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced. Further, the "CALLF" instruction is a 2-byte instruction code as described above. Therefore, by using these main CPU 101 dedicated instruction codes in the stop control pull-in request flag setting process, the processing efficiency can be improved and the limited capacity of the main RAM 103 can be effectively utilized. ..

Further, in the present embodiment, in the stop control pull-in request flag setting process of S686 during the priority pull-in order acquisition process, the jump destination logical product operation address “SB_DAND_00” specified by the “CALLF” instruction is the above-mentioned FIG. 73. It is the same as the jump destination address specified by the "CALLF" instruction in the logical product operation processing of S626 during the attraction priority storage processing described in (see FIG. 74). That is, in the present embodiment, the source program for executing the AND operation processing performed in the stop control pull-in request flag setting process of S686 during the priority pull-in order acquisition process is the logic performed in S626 during the pull-in priority storage process. It is the same as the source program for executing the AND operation process, and the source program for the AND operation process is shared (modularized) in both the S686 and S626 processes. In this case, in both the S686 and S626 processes, it is not necessary to separately provide the source program for the logical product operation process, so that the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

As described above, in the various processes during the priority attraction order acquisition process of the present embodiment, the various instruction codes dedicated to the main CPU 101 described above are appropriately used to improve the efficiency of the corresponding processes and reduce the capacity of the source program. doing. As a result, in the present embodiment, it is possible to improve the efficiency of the program processing speed of the main control circuit 90 and reduce the capacity, and it is possible to improve the playability by utilizing the free area corresponding to the reduced capacity. It becomes.

[Reel stop control process]
Next, the reel stop control process performed in S213 in the main flow (see FIG. 54) will be described with reference to FIGS. 81 to 83. Note that FIG. 81 is a flowchart showing the procedure of the reel stop control process. FIG. 82 is a diagram showing an example of a source program for executing the processes of S711 to S716 described later during the reel stop control process, and FIG. 83 is a diagram showing the process of S726 described later during the reel stop control process. It is a figure which shows an example of the source program for this.

First, the main CPU 101 performs a reel stop enable signal OFF process (S711). In this process, the main CPU 101 mainly performs the port output process of the reel stop enable signal OFF data. Further, this process is performed using the non-standard work area of the main RAM 103. The details of the reel stop enable signal OFF process will be described later with reference to FIG. 84 described later.

Next, the main CPU 101 determines whether or not the rotation speeds of all the reels have reached a predetermined constant speed (whether or not the speed has reached a "constant speed") (S712). In S712, when the main CPU 101 determines that the rotation speeds of all reels are not "constant speed" (when the determination in S712 is NO), the main CPU 101 repeats the process of S712.

On the other hand, in S712, when the main CPU 101 determines that the rotation speeds of all the reels have reached "constant speed" (when the determination in S712 is YES), the main CPU 101 performs a reel stop enable signal ON process (S713). In this process, the main CPU 101 mainly performs the port output process of the reel stop enable signal ON data. Further, this process is performed using the non-standard work area of the main RAM 103. The details of the reel stop enable signal ON processing will be described later with reference to FIG. 85 described later.

Next, the main CPU 101 determines whether or not a valid stop button has been pressed (S714).

When the main CPU 101 determines in S714 that the valid stop button has not been pressed (when the determination in S714 is NO), the main CPU 101 returns the process to the process of S713 and repeats the processes after S713. On the other hand, in S714, when the main CPU 101 determines that a valid stop button has been pressed (when the determination in S714 is YES), the main CPU 101 updates the operation stop button storage area (see FIG. 25), and the stop button is not yet pressed. The value of the operation counter is subtracted by 1 (S715).

Next, the main CPU 101 determines the search target reel from the operation stop button (S716). Further, in this process, the address (start address) set process of the reel control data storage area in which the reel control management information of the search target reel is stored is also performed (source code "LDQ IX, wR1_CTRL- (wR2_CTRL)" in FIG. 82. -WR1_CTRL) ").

Next, the main CPU 101 performs a reel stop enable signal OFF process (S717). Similar to S711, this process is performed using the non-standard work area of the main RAM 103. The details of the reel stop enable signal OFF process will be described later with reference to FIG. 84 described later. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

Next, the main CPU 101 performs a reel stop selection process (S719). Although detailed description is omitted, in this process, the main CPU 101 performs a process of selecting the number of sliding pieces.

Next, the main CPU 101 determines a scheduled stop position based on the stop start position and the number of sliding pieces determined in S719, and stores the determined stop scheduled position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding pieces to the stop start position, and sets the addition result as the stop scheduled position.

Next, the main CPU 101 executes the symbol code storage process (S721). In this process, the symbol code corresponding to the scheduled stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether or not the reel to be controlled is the reel of the final stop (third stop) (S722). In this process, the main CPU 101 determines whether or not the reel to be controlled is the reel of the final stop (third stop) based on the value of the stop button non-operation counter, and the value of the stop button non-operation counter is set. When it is "0", it is determined that the reel to be controlled is the reel of the final stop.

In S722, when the main CPU 101 determines that the reel to be controlled is not the reel of the final stop (when the determination in S722 is NO), the main CPU 101 performs the control change process (S723). In this process, the stop information group used for stopping the reel is updated when the reel is at a specific stop position. Next, the main CPU 101 performs the pull-in priority storage process described with reference to FIG. 73 (S724).

Next, the main CPU 101 performs a stop interval remaining time standby process (S725). In this process, the main CPU 101 performs a standby process until a preset predetermined reel stop interval time elapses. Then, after the processing of S725, the main CPU 101 returns the processing to the processing of S711, and repeats the processing after S711.

Here, returning to the process of S722 again, when the main CPU 101 determines in S722 that the reel to be controlled is the reel of the final stop (when the determination in S722 is YES), the main CPU 101 excites all the reels. Determines whether or not is in the stopped state (S726). In S726, when the main CPU 101 determines that the excitation of all reels is not in the stopped state (when the determination in S726 is NO), the main CPU 101 repeats the process of S726.

On the other hand, in S726, when the main CPU 101 determines that the excitation of all reels is in the stopped state (when the determination in S726 is YES), the main CPU 101 keeps the stop button operated for the third stop in the ON state. It is determined whether or not (the stop button is not released) (S727). In S727, when the main CPU 101 determines that the stop button operated by the third stop operation remains in the ON state (when the determination in S727 is YES), the main CPU 101 repeats the process of S727. On the other hand, in S727, when the main CPU 101 determines that the stop button operated by the third stop operation is not in the ON state (when the determination in S727 is NO), the main CPU 101 ends the reel stop control process and performs the process. Move to S214 of the main flow (see FIG. 54).

In the present embodiment, the reel stop control process is performed as described above. The processes S711 to S716 during the reel stop control process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 82. As shown in FIG. 82, in the source program of the reel stop control process of the present embodiment, an instruction code dedicated to the main CPU 101, for example, an "LDQ" instruction for specifying an address using a Q register (extension register) or "LDQ" instruction " The "CALLF" instruction is used.

Therefore, by using such a main CPU 101 dedicated instruction code in the reel stop control process, the capacity of the source program of the reel control process can be reduced and the processing efficiency of the reel stop control process can be improved. it can. That is, in the present embodiment, it is possible to improve the efficiency of the program processing speed and reduce the capacity of the main control circuit 90, and utilize the free area of the main ROM 102 increased according to the reduced capacity for playability. Can be increased.

Further, the determination process of S726 during the reel stop control process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 83. As shown in FIG. 83, this process is executed by using the "LDQ" instruction and the "ORQ" instruction (predetermined OR operation instruction) on the source code.

The "ORQ" instruction is an instruction code that performs a logical sum operation, and is an instruction code dedicated to the main CPU 101 that specifies an address using a Q register (extension register). Then, for example, when the source code "ORQ (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer k (direct value: lower address value) are used. A logical sum operation is performed between the contents of the memory (stored data) at the specified address and the contents (stored data) of the A register, and the calculation result is stored in the A register.

Therefore, in the determination process of S726 during the reel stop control process, when the source code "LDQ A, (.LOW.wR1_TIM)" in FIG. 83 is first executed, the stored data of the Q register and the integer value " The contents of the memory (excitation timer value of the first reel) at the address specified by ".LOW.wR1_TIM" are loaded into the A register. In the present embodiment, the address of the area in the main RAM 103 where the excitation timer value of the first reel is stored is "F032h". Then, in the determination process of S726 described above, the upper address value "F0h" of the address "wR1_TIM (F032h)" is set in the Q register in advance when the LDQ instruction is executed, and the lower side is set to the k value (direct value). The address value (".LOW.wR2_TIM" = 32h) is substituted.

Next, when the source code "ORQ (.LOW.wR2_TIM)" in FIG. 83 is executed, the address "wR2_TIM (wR2_TIM) of the area in which the stored data (F0h) of the Q register and the excitation timer value of the second reel are stored. The logical sum operation of the memory contents (excitation timer value of the second reel) of the address specified by the lower address value (3Dh) of "F03Dh)" and the contents of the A register (excitation timer value of the first reel) is performed. The calculation result (combined result of the excitation timer value of the first reel and the excitation timer value of the second reel) is stored in the A register. Next, when the source code "ORQ (.LOW.wR3_TIM)" in FIG. 83 is executed, the address "wR3_TIM" of the area in which the stored data (F0h) of the Q register and the excitation timer value of the third reel are stored is executed. The contents of the memory (excitation timer value of the third reel) of the address specified by the lower address value (48h) of "F048h)" and the contents of the A register (excitation timer value of the first reel and the excitation timer of the second reel). A logical sum operation with the value (combination result with the value) is performed, and the operation result (combination result of the excitation timer values of the first to third reels) is stored in the A register.

As described above, in the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extension register) are used in the check process of the stopped state of the reel (rotary cylinder). Therefore, by using these main CPU 101 dedicated instruction codes, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values, and the instruction related to the address setting is omitted on the source program. Therefore, the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

As described above, in the various processes during the reel stop control process of the present embodiment, the various instruction codes dedicated to the main CPU 101 described above are appropriately used to improve the efficiency of the corresponding processes and reduce the capacity of the source program. ing. As a result, in the present embodiment, it is possible to improve the efficiency of the program processing speed of the main control circuit 90 and reduce the capacity, and it is possible to improve the playability by utilizing the free area corresponding to the reduced capacity. It becomes.

[Reel stoptable signal OFF processing]
Next, the reel stop enable signal OFF process performed in S711 or S717 during the reel stop control process (see FIG. 81) will be described with reference to FIG. 84. Note that FIG. 84 is a flowchart showing a procedure for turning off the reel stop enable signal.

First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S731). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S732).

Next, the main CPU 101 saves the data set in all the registers (S733). Next, the main CPU 101 performs a reel stop enable signal OFF data setting process (S734).

Next, the main CPU 101 performs non-standard port output processing (S735). In this process, the main CPU 101 generates and outputs OFF output data (output off mode data), which will be described later, based on the reel stop enable signal OFF data. This process is performed using the non-standard work area of the main RAM 103. The details of the non-standard port output processing will be described later with reference to FIG. 86 described later.

Next, the main CPU 101 restores the data of all the registers saved in S733 (S736). Next, the main CPU 101 sets the address of the stack area saved in S731 in the stack pointer (SP) (S737).

Then, after the processing of S737, the main CPU 101 ends the reel stop enable signal OFF processing. At this time, if the executed reel stop enable signal OFF process is the process of S711 in the reel stop control process (see FIG. 81), the main CPU 101 shifts the process to the process of S712 in the reel stop control process. On the other hand, when the executed reel stop enable signal OFF process is the process of S717 in the reel stop control process (see FIG. 81), the main CPU 101 shifts the process to the process of S718 in the reel stop control process.

[Reel stoptable signal ON processing]
Next, with reference to FIG. 85, the reel stop enable signal ON process performed in S713 during the reel stop control process (see FIG. 81) will be described. FIG. 85 is a flowchart showing the procedure of the reel stop enable signal ON processing.

First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S741). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S742).

Next, the main CPU 101 saves the data set in all the registers (S743). Next, the main CPU 101 refers to the operation stop button storage area (see FIG. 25) and acquires the stop button state (S744). Next, the main CPU 101 performs a reel stop enable signal ON data setting process (S745).

Next, the main CPU 101 performs non-standard port output processing (S746). In this process, the main CPU 101 generates and outputs ON output data (output on mode data) described later based on the reel stop enable signal ON data. This process is performed using the non-standard work area of the main RAM 103. The details of the non-standard port output processing will be described later with reference to FIG. 86 described later.

Next, the main CPU 101 restores the data of all the registers saved in S743 (S747). Next, the main CPU 101 sets the address of the stack area saved in S741 in the stack pointer (SP) (S748). Then, after the processing of S748, the main CPU 101 ends the reel stop enable signal ON processing, and shifts the processing to the processing of S714 in the reel stop control processing (see FIG. 81).

[Non-standard port output processing]
Next, with reference to FIGS. 86 and 87, the non-standard port output process performed in S735 during the reel stoptable signal OFF process (see FIG. 84) and S746 during the reel stoptable signal ON process (see FIG. 85). explain. Note that FIG. 86 is a flowchart showing the procedure of non-standard port output processing. Further, FIG. 87 is a diagram showing an example of a source program for executing the non-standard port output process.

First, the main CPU 101 determines whether or not the port output setting is the ON output mode (S751). In this process, the main CPU 101 determines that the port output setting is the ON output mode when the reel stop enable signal ON data is set, and when the reel stop enable signal OFF data is set, the main CPU 101 determines. , Judge that the port output setting is not ON output mode.

In S751, when the main CPU 101 determines that the port output setting is the ON output mode (when the determination in S751 is YES), the main CPU 101 performs the process of S753 described later. On the other hand, in S751, when the main CPU 101 determines that the port output setting is not the ON output mode (when the determination in S751 is NO), the main CPU 101 performs an OFF output data (output off mode data) generation process (S752). ). In this process, among the ports (bits) that are currently in the output on state, the port (bit) that you want to turn off is turned off, and the port (bit) that is currently in the output off state is turned off. OFF output data for maintaining the state is generated.

After the processing of S752 or when the determination in S751 is NO, the main CPU 101 performs an ON output data (output on mode data) generation process (S753). In this process, among the ports (bits) that are currently in the output off state, the port (bit) that you want to turn on is turned on, and the port (bit) that is currently in the output on state is turned on. ON output data for maintaining the state is generated. Next, the main CPU 101 outputs the generated output data from the designated port (S754).

Then, after the processing of S754, the main CPU 101 ends the non-standard port output processing. At this time, if the executed non-standard port output process is the process of S735 during the reel stop enable signal OFF process (see FIG. 84), the main CPU 101 processes the process of S736 during the reel stop enable signal OFF process. Move to. On the other hand, when the executed non-standard port output process is the process of S746 during the reel stop enable signal ON process (see FIG. 85), the main CPU 101 changes the process to the process of S747 during the reel stop enable signal ON process. Transfer.

In this embodiment, the non-standard port output process is performed as described above. Then, the above-mentioned non-standard port output processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 87.

Among them, in the OFF output data generation process of S752 during the above-mentioned non-standard port output process, the source codes "XOR (HL)" and "AND (HL)" in FIG. 87 are executed in this order. Will be done. Further, the process of generating the ON output data of S753 during the above-mentioned non-standard port output process is performed by executing the source code "OR (HL)" in FIG. 87.

By performing such output data generation processing on the source program, the OFF output data generated in S752 is generated even if the ON output data generation processing of S753 is performed after the OFF output data generation processing of S752. Does not change.

For example, the port output setting is the OFF output mode, and the output data indicating the non-standard port that you want to turn off in this process is "00010111" ("1" is the bit that you want to turn off), and the non-standard port is currently When the output data (backup data) output to is "0100011" ("1" is the bit currently on), the data of bit 0, bit 1 and bit 5 of the backup data is changed from "1" to "1". OFF output data for setting to "0" is generated. In this case, first, when the source code "XOR (HL)" in FIG. 87 is executed, an exclusive OR operation is performed between the output data "00010111" and the backup data "0101011", and the operation result is " 01000100 ”is obtained. Next, when the source code "AND (HL)" in FIG. 87 is executed, a logical product operation of the calculation result "010000100" and the backup data "0101001" is performed, and the calculation result "01000000" is used as OFF output data. Will be generated.

After that, when the ON output data generation process of S753 (source code “OR (HL)” in FIG. 87) is executed, the calculation result “01000000” (OFF output data) is turned on by this process. A logical sum operation is performed with the output data "00000000000" indicating the non-standard port to be desired (since the port output setting is the OFF output mode, "0" is set for each bit of the output data), and the calculation result is “01000000” is obtained, and the OFF output data does not change. Qualitatively, when the port output setting is the OFF output mode, in the ON output data generation process of S753, the output for keeping the port (bit) that is in the output ON state in the OFF output data in the ON state. Since the data is generated, the OFF output data generated in S752 does not change even if the ON output data generation process of S753 is performed after the OFF output data generation process of S752.

[Prize search process]
Next, the winning search process performed in S214 in the main flow (see FIG. 54) will be described with reference to FIGS. 88 and 89. Note that FIG. 88 is a flowchart showing the procedure of the winning search process. Further, FIG. 89 is a diagram showing an example of a source program for executing the winning search process.

First, the main CPU 101 transfers and stores the data of each storage area stored in the symbol code storage area (see FIG. 27) to the corresponding storage area of the winning operation flag storage area (see FIG. 22) (S761). .. Then, at the end of this process, the last address of the winning operation flag storage area is set in the DE register.

Next, the main CPU 101 sets the address of the payout number data table (not shown) in the HL register (S762). Next, the main CPU 101 sets the number of payout number tables as the initial value of the winning search counter, and sets the initial value in the B register (S763).

Next, the main CPU 101 data on the number of medals to be paid out (in this embodiment, any one of 14, 13, 9, 7, 3, and 1) based on the address set in the HL register. Is set in the C register, the determination target data is set in the A register, and "2" is added (+2 update) to the address set in the HL register (S764).

Next, the main CPU 101 extracts the value of the determination bit from the data of the number of medals to be paid out set in the C register (S765). This determination bit is information indicating whether or not the block is the determination target block of the winning search. Next, the main CPU 101 determines whether or not the block is a determination target block based on the value of the extracted determination bit (S766). In this process, the main CPU 101 determines that the block is a determination target block when the value of the extracted determination bit is "1".

In S766, when the main CPU 101 determines that the block is not the determination target block (when the determination in S766 is NO), the main CPU 101 performs the process of S768 described later. On the other hand, in S766, when the main CPU 101 determines that the block is the determination target block (when the determination in S766 is YES), the main CPU 101 subtracts 1 from the address of the winning operation flag storage area set in the DE register (-). 1 update) (S767).

After the processing of S767 or when the determination in S766 is NO, the main CPU 101 extracts the data of the storage area specified by the address of the winning operation flag storage area set in the DE register as the determination data (S768).

Next, the main CPU 101 determines whether or not the determination result is a prize based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, if the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a prize.

In S769, when the main CPU 101 determines that the result of the determination is not a prize (when the determination in S769 is NO), the main CPU 101 performs the process of S776 described later. On the other hand, in S769, when the main CPU 101 determines that the determination result is a winning result (when the determination in S769 is YES), the main CPU 101 has three current games (a game in which the number of medals bet is three). ) (S770).

In S770, when the main CPU 101 determines that the current game is a three-card game (when the determination in S770 is YES), the main CPU 101 performs the process of S772 described later. On the other hand, in S770, when the main CPU 101 determines that the current game is not a three-card game (when the determination in S770 is NO), the main CPU 101 pays out a two-card game (a game in which the number of medals bet is two). The number of sheets (2 sheets) is set in the C register (S771). In this embodiment, since the number of cards that can be started is 3 (see FIG. 18), the processing of S770 is always a YES determination.

After the processing of S771 or when the determination in S770 is YES, the main CPU 101 updates the number of payouts (S772). Specifically, the main CPU 101 adds the number of medals to be paid out set in the C register to the current value of the winning number counter, and sets the added value to the number of payouts.

Next, the main CPU 101 determines whether or not the value of the number of payouts is less than the maximum number of payouts "14" (S773).

In S773, when the main CPU 101 determines that the value of the number of payouts is less than the maximum number of payouts "14" (when the determination in S773 is YES), the main CPU 101 performs the process of S775 described later. On the other hand, in S773, when the main CPU 101 determines that the value of the number of payouts is not less than the maximum number of payouts "14" (when the determination in S773 is NO), the main CPU 101 sets the maximum number of payouts "14" to the number of payouts. (S774).

After the processing of S774 or when the determination in S773 is YES, the main CPU 101 stores the payout number in the winning number counter (S775).

After the processing of S775 or when the determination in S769 is NO, the main CPU 101 determines whether or not there is another prize (S776). In S776, when the main CPU 101 determines that there is another prize (when the determination in S776 is YES), the main CPU 101 returns the process to the process of S769 and repeats the processes after S769.

On the other hand, in S7776, when the main CPU 101 determines that there is no other prize (when the determination in S776 is NO), the main CPU 101 subtracts 1 (updates -1) the value of the prize search counter (S777). In addition, as in the present embodiment, when there is only one effective line, since a plurality of small winning combinations are not duplicated and won a prize, the processing of S776 is always a NO determination.

Next, the main CPU 101 determines whether or not the value of the winning search counter is "0" (S778).

In S778, when the main CPU 101 determines that the value of the winning search counter is not "0" (when the determination in S778 is NO), the main CPU 101 returns the processing to the processing of S764 and repeats the processing after S764. On the other hand, in S778, when the main CPU 101 determines that the value of the winning search counter is "0" (when the determination in S778 is YES), the main CPU 101 ends the winning search process and performs the process in the main flow (FIG. FIG. 54) Move to the process of S215.

In the present embodiment, the winning search process is performed as described above. Then, the above-mentioned winning search process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 89. Among them, the set processing of the payout number of S764 and the determination target data is performed by the main CPU 101 executing the source code “LDIN AC, (HL)”.

When, for example, the source code "LDIN ss, (HL)" is executed on the source program, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( The data) is loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (2 addition). Therefore, when the source code "LDIN AC, (HL)" in FIG. 89 is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( The number of payouts and the data to be determined) are loaded into the AC register, and the address set in the HL register is updated by +2 (2 additions). In the process of S764, by this "LDIN" instruction, the data of the number of payouts is stored in the A register, the determination target data is stored in the C register, and the address set in the HL register is updated by +2.

As described above, in the winning search process of the present embodiment, both the data load process and the address update process can be performed by one "LDIN" command. In this case, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, the acquisition process of the value of the medal counter referred to in the determination process of S770 during the above-mentioned winning search process, the acquisition process of the value of the winning number counter referred to in the processing of S772, and the winning number counter performed in the processing of S775. As shown in FIG. 89, all the save (update) processes are executed by the "LDQ" instruction (instruction code dedicated to the main CPU 101) that specifies the address using the Q register (extension register). Therefore, in the winning search process of the present embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by the direct value by using the "LDQ" instruction, so that the address on the source program. The instruction related to the setting can be omitted (it is not necessary to separately provide the instruction related to the address setting), and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, as shown in FIG. 89, the determination process of S769 during the winning search process described above is executed by the "JSLAA" instruction (predetermined determination instruction) on the source program. The "JSLAA" instruction is an instruction that executes an operation equivalent to a left shift (SLA) instruction.

For example, when the source code "JSLAA cc, e" is executed on the source program, if the condition of cc is satisfied, the process is jumped to the address specified by e. The state of the carry flag in the flag register F is specified in the "cc condition" specified by the "JSLAA" instruction. For example, if "C" is specified for cc, the condition of cc means that the carry flag is "1" (on state), and if "NC" is specified for cc, the condition of cc. Means that the carry flag is "0" (off state). Therefore, in the source code "JSLAA NC, MN_CKLN_06" in FIG. 89, if the carry flag is "0" (off state), the process jumps to the address specified by "MN_CKLN_06".

Further, the determination processing of S770 and S773 during the winning search processing described above is executed by the "JCP" instruction on the source program as shown in FIG. 89. As described above, the "JCP" instruction is an instruction that executes an operation equivalent to a comparison instruction, and is an instruction code dedicated to the main CPU 101.

Therefore, when the above-mentioned "JSLAA" command and "JCP" command are used on the source program of the winning search process, the command related to the address setting can be omitted (it is necessary to separately provide the command related to the address setting). The capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Illegal hit check processing]
Next, the illegal hit check process performed in S215 in the main flow (see FIG. 54) will be described with reference to FIGS. 90 and 91. Note that FIG. 90 is a flowchart showing the procedure of the illegal hit check process. Further, FIG. 91 is a diagram showing an example of a source program for executing the illegal hit check process. The illegal hit is a left reel 3L, a middle reel 3C, and a right reel 3R based on the internal winning combination that is drawn by the internal lottery process (see FIG. 64) and stored in the hit request flag storage area by the symbol setting process. It is a term indicating that a combination of symbols that cannot be established in (that is, a combination of symbols that is not permitted to be stopped and displayed) is stopped on the effective line (symbol combination is not established).

First, the main CPU 101 sets the address of the winning operation flag storage area (see FIG. 22) (S781). Next, the main CPU 101 sets the size of the winning operation flag storage area (the number of bytes, “7” in the present embodiment) to the value of the check counter (S782).

Next, the main CPU 101 is based on the address of the winning operation flag storage area currently set, and the internal winning combination stored in the storage area in the hit request flag storage area (internal winning combination storage area) corresponding to the address. Data (hit request flag data) is acquired (S783). Next, the main CPU 101 synthesizes the winning combination data (winning operation flag data) stored at the address of the currently set winning operation flag storage area and the internal winning combination data (winning request flag data) ( S784).

In this synthesis process, the main CPU 101 first obtains the exclusive OR of the winning combination data (winning operation flag data) and the internal winning combination data (winning request flag data) (source program shown in FIG. 91). Source code inside "XOR (HL)"). Next, the main CPU 101 obtains the logical product of the calculated exclusive-OR calculation result and the winning combination data (winning operation flag data) (source code “AND (HL)” in the source program shown in FIG. 91. ), The calculation result of the logical product is used as the synthesis result. If no illegal hit error has occurred, the value of this synthesis result is "0".

Next, the main CPU 101 determines whether or not an illegal hit error has occurred based on the result of the synthesis process of S784 (S785).

In S785, when the main CPU 101 determines that an illegal hit error has not occurred (NO in S785), the main CPU 101 updates the address of the winning operation flag storage area to be referred to by +1 (S786). Next, the main CPU 101 subtracts 1 from the value of the check counter (S787). Next, the main CPU 101 determines whether or not the value of the check counter is "0" (S788).

In S788, when the main CPU 101 determines that the value of the check counter is not "0" (when the determination in S788 is NO), the main CPU 101 returns the process to the process of S783 and repeats the processes after S783. On the other hand, in S788, when the main CPU 101 determines that the value of the check counter is "0" (when the determination in S788 is YES), the main CPU 101 ends the illegal hit check process and performs the process in the main flow (FIG. FIG. 54) Move to the process of S216 in.

Here, returning to the processing of S785 again, when the main CPU 101 determines in S785 that an illegal hit error has occurred (when the determination in S785 is YES), the main CPU 101 performs the error processing described with reference to FIG. (S789). By this processing, the two-character "EE" indicating the occurrence of an illegal hit error is displayed as error information on the two-digit 7-segment LED (both for displaying the number of payouts and for displaying the error) included in the information display 6. Error display data is output. The state in which the illegal hit error occurs (error state) is released by pressing the reset switch 76 (see FIG. 7).

Next, the main CPU 101 clears the value of the winning number counter and the data of the hit request flag storage area (S790). Then, after the processing of S790, the main CPU 101 ends the illegal hit check processing, and shifts the processing to the processing of S216 in the main flow (see FIG. 54).

In the present embodiment, the illegal hit check process is performed as described above. Then, the above-mentioned illegal hit check process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 91.

In the present embodiment, as shown in FIG. 22, the configuration of the winning operation flag storage area (display combination storage area) is the same as that of the hit request flag storage area (internal winning combination storage area), so that the winning operation flag The winning request flag storage area and the winning operation flag storage area arranged in the main RAM 103 at the time of combining the combination of the storage area combination and the internal winning combination can have the same configuration. Therefore, the calculation result of S784 in the illegal hit check process of the present embodiment (the result of synthesizing the data of the winning combination and the data of the internal winning combination) is the data of the winning combination and the internal on the source program as described above. It is obtained by simply ANDing the winning combination data (executed with the "AND" instruction). As a result, in the present embodiment, the illegal hit check process can be made more efficient and simplified, the free space of the main control program can be secured (increased), and the increased free space can be used for playability. It becomes possible to increase.

[Prize check / medal payout process]
Next, the winning check / medal payout process performed in S216 in the main flow (see FIG. 54) will be described with reference to FIGS. 92 and 93. Note that FIG. 92 is a flowchart showing the procedure of winning check / medal payout processing. Further, FIG. 93 is a diagram showing an example of a source program for executing the processes of S804 to S808 described later during the winning check / medal payout process.

First, the main CPU 101 performs a winning operation command generation process (S801). In this process, the main CPU 101 generates type data and various communication parameters included in the winning operation command transmitted to the sub-control circuit 200. The winning operation command is configured to include a parameter for specifying a winning operation flag (display combination) and the like.

Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 44 (S802). By this process, the winning operation command data is stored in the communication data storage area (see FIG. 47B) provided in the main RAM 103. The winning operation command is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100.

Next, the main CPU 101 determines whether or not the value of the winning number counter is "0" (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is "0" (when the determination in S803 is YES), the main CPU 101 ends the winning check / medal payout process, and performs the process in the main flow (when the winning check / medal payout process is completed). (See FIG. 54), the process proceeds to S217.

On the other hand, in S803, when the main CPU 101 determines that the value of the winning number counter is not "0" (when the determination in S803 is NO), the main CPU 101 has the maximum number of medals credited (stored). In the embodiment, it is determined whether or not the number is 50 or more (S804).

In S804, when the main CPU 101 determines that the number of credits for medals is not equal to or greater than the upper limit (when the determination in S804 is NO), the main CPU 101 adds "1" to the value of the credit counter (updates +1). S805). The added value of the credit counter is displayed by a 2-digit 7-segment LED (not shown) for displaying the number of stored sheets included in the information display 6. Next, the main CPU 101 performs a medal payout number check process (S806). The details of the medal payout number check process will be described later with reference to FIG. 94 described later.

Next, the main CPU 101 determines whether or not the payout of medals has been completed (S807). In S807, when the main CPU 101 determines that the medal payout has been completed (when the determination in S807 is YES), the main CPU 101 ends the winning check / medal payout process, and the process is in the main flow (see FIG. 54). Move to the processing of S217.

On the other hand, in S807, when the main CPU 101 determines that the payout of medals has not been completed (when the determination in S807 is NO), the main CPU 101 performs a payout interval standby process (S808). In this process, the main CPU 101 waits until the preset medal payout interval time (60.33 msec in this embodiment: 54 cycles of the interrupt process (1.1172 msec cycle) described later in FIG. 100) elapses. Wait. Then, after the processing of S808, the main CPU 101 returns the processing to the processing of S803, and repeats the processing after S803.

Here, returning to the process of S804 again, when the main CPU 101 determines in S804 that the number of credits for medals is equal to or greater than the upper limit (50) (when the determination in S804 is YES), the main CPU 101 determines. The medal payout process is performed (S809). By this process, one medal is paid out. Then, after the processing of S809, the main CPU 101 ends the winning check / medal payout processing, and shifts the processing to the processing of S217 in the main flow (see FIG. 54).

In the present embodiment, the winning check and the medal payout process are performed as described above. The processes S804 to S808 during the winning check / medal payout process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 93.

In the present embodiment, when the payout operation is continued after the credit counter is updated (+1), the main CPU 101 performs a wait (payout interval wait) process for 60.33 ms in the process of S808, but this process is performed. , On the source program, the main CPU 101 is realized by executing the source codes "LD BC, cTM_PAYC" and "RST SB_W1BC_00" in this order. In this way, in the winning check / medal payout process, if a wait (waiting for payout interval) of 60.33 ms is performed when the payout operation is continued after updating the credit counter (+1), useless waiting time is reduced. It is possible to reduce the mental burden on the player.

[Check process for paying out medals]
Next, the medal payout number check process performed in S806 during the winning check / medal payout process (see FIG. 92) will be described with reference to FIGS. 94 and 95. Note that FIG. 94 is a flowchart showing the procedure of the medal payout number check process. Further, FIG. 95A is a diagram showing an example of a source program for executing the processes of S811 to S814 described later during the medal payout number check process, and FIG. 95B shows S816 and S816 described later during the medal payout number check process. It is a figure which shows an example of the source program for executing the process of S817.

First, the main CPU 101 adds (+1 update) to the value of the medal OUT counter (S811). The medal OUT counter is a counter for counting the number of times the medal is paid out. Next, the main CPU 101 adds (+1 update) to the value of the payout number counter (S812). The payout number counter is a counter for counting the payout number of medals.

Next, the main CPU 101 performs a payout number 7SEG display process (S813). In this process, the main CPU 101 performs a control process of displaying the value of the payout number counter by a 2-digit 7-segment LED (not shown) for displaying the payout number included in the information display 6.

Next, the main CPU 101 performs an update process of the winning combination end number counter (S814). The winning combination end number counter is a counter for counting the remaining number of medals to be paid out corresponding to the winning combination. In this process, the main CPU 101 compares the value of the combination end number counter with the lower limit value “0”, and if the value of the combination end number counter is larger than the lower limit value “0”, the combination end number counter. The value of the counter is subtracted by 1 (updated by -1), and when the value of the winning combination end number counter is equal to or less than the lower limit value "0", the value of the winning combination ending number counter is held at "0".

Next, the main CPU 101 subtracts (updates -1) the value of the winning number counter by 1 (S815).

Next, the main CPU 101 performs a credit information command generation process (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command transmitted to the sub-control circuit 200. The credit information command is configured to include a parameter for specifying the number of credits for medals.

Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 44 (S817). By this process, the credit information command data is stored in the communication data storage area (see FIG. 47B) provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 100. Then, after the processing of S817, the main CPU 101 ends the medal payout number check process, and shifts the process to the process of S807 during the winning check / medal payout process (see FIG. 92).

In the present embodiment, the medal payout number check process is performed as described above. The processes of S811 to S814 during the above-mentioned medal payout number check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 95A. Among them, the update process of the winning combination end number counter in S814 is executed by the "DCPLD" instruction (predetermined update instruction) in FIG. 95A. The "DCPLD" instruction is an instruction code dedicated to the main CPU 101.

For example, when the source code "DCPLD (HL), n" is executed on the source program, the memory contents (stored data) of the address specified by the HL register are compared with the integer n, and the memory contents are changed. If it is larger than the integer n, the contents of the memory are subtracted by 1, and if the contents of the memory are not more than the integer n, the integer n is stored in the memory at the address specified by the HL register. Therefore, when the source code "DCPLD (HL), 0" in FIG. 95A is executed, the memory contents (value of the winning combination end number counter) and the integer 0 (lower limit value) of the address specified by the HL register are executed. If the memory content (value of the winning combination end number counter) is greater than an integer 0, the memory content is subtracted by 1, and if the memory content is an integer 0 or less, the memory content is subtracted. "0" is set in (value of the number counter for the end of the winning combination). That is, if the value of the current combination end number counter is larger than "0", the combination end number counter is updated, and if the current combination end number counter value is "0" or less. , The process of holding the value of the winning combination end number counter at "0" is performed.

As described above, in the process of S814 during the medal payout number check process, one "DCPLD" command (a command in which the lower limit judgment command of the number management counter and the judgment branch command are integrated) is used to complete the number of consecutive combinations. Both the counter update (subtraction) process and the process of holding the value of the continuous end number counter at "0" can be executed. In this case, it is not necessary to provide an instruction code for executing both processes separately. For example, the determination branch instruction code for determining whether or not the value of the continuous end number counter is "0" can be omitted. Therefore, in the medal payout number check process of the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, and the free space can be secured (increased) in the main ROM 102, resulting in an increase. It is possible to improve the playability by utilizing the free space.

Further, the processes of S816 and S817 during the above-mentioned medal payout number check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 95B.

Among them, in the process of S816, as shown in FIG. 95B, the value of the payout counter is set in the communication parameter 1 of the credit information command via the L register, and the credit is set in the communication parameter 5 via the C register. The value of the counter is set. However, the other communication parameters 2 to 4 constituting the credit information command are set with values (indefinite values) currently stored in the H register, the E register, and the D register, respectively. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Bonus check process]
Next, with reference to FIG. 96, the bonus check process performed in S217 in the main flow (see FIG. 54) will be described. Note that FIG. 96 is a flowchart showing the procedure of the bonus check process.

First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S821). That is, the main CPU 101 determines whether or not the current gaming state is the BB gaming state or the MB gaming state. In S821, when the main CPU 101 determines that the current gaming state is not the bonus state (when the determination in S821 is NO), the main CPU 101 performs the process of S826 described later.

On the other hand, in S821, when the main CPU 101 determines that the current gaming state is the bonus state (when the determination in S821 is YES), the main CPU 101 is for counting the number of medals that can be paid out during the bonus state. The number of medals paid out in the winning check / medal payout process is subtracted from the value of the bonus payout number counter (S822).

Next, the main CPU 101 determines whether or not the value of the payout number counter during the bonus is less than "0" (S823). In S823, when the main CPU 101 determines that the value of the payout number counter during the bonus is not less than "0" (when the determination in S823 is NO), the main CPU 101 is in the RB game if the current game state is the BB game state. The state (RB operating) is maintained, and if the current gaming state is the MB gaming state, a process of maintaining the CB gaming state (CB operating) is performed (S824). Specifically, in the game state flag storage area (see FIG. 24), when "1" is stored in bit 0 (BB game state), "1" is always set in bit 1 (RB game state). When "1" is stored in bit 2 (MB game state), "1" is always stored in bit 3 (CB game state). As a result, the BB game state (BB operation) is always controlled during the RB game state (RB operation), and the MB game state (MB operation) is always controlled during the CB game state (CB operation). To. Then, after the processing of S824, the bonus check processing is terminated, and the processing is transferred to the processing of S218 in the main flow (see FIG. 54).

On the other hand, in S823, when the main CPU 101 determines that the value of the payout number counter during the bonus is less than "0" (when the determination in S823 is YES), the main CPU 101 performs the bonus end processing (S825). In this process, the main CPU 101 clears various information in the bonus state (for example, at the end of the BB game state, the BB game state flag and the RB game state flag are turned off ("0" is cleared), and the MB At the end of the game state, the MB game state flag and the CB game state flag are turned off (clear "0"), and at the end of the BB game state, all the RT state flags are set to the off state. (That is, the RT state is set to the RT0 state). Then, after the processing of S825, the bonus check processing is terminated, and the processing is transferred to the processing of S218 in the main flow (see FIG. 54).

Here, returning to the process of S821 again, when S821 is a NO determination, the main CPU 101 determines whether or not BB or MB is established (S826). That is, the main CPU 101 determines whether or not the symbol combination of BB or MB (the symbol combination of "C_BB" or "C_MB") is displayed in the current game. In S826, when the main CPU 101 determines that BB or MB has not been established (when the determination in S826 is NO), the main CPU 101 ends the bonus check process and performs the process in S218 in the main flow (see FIG. 54). Move on to the processing of.

On the other hand, in S826, when the main CPU 101 determines that BB or MB has been established (when the determination in S826 is YES), the main CPU 101 sets "144" to the value of the bonus payout number counter (S827). Next, the main CPU 101 determines whether or not the MB is established (S828). In S828, when the main CPU 101 determines that the MB is not established (that is, the BB is established) (when the determination in S828 is NO), the main CPU 101 performs the process of S830 described later.

On the other hand, in S828, when the main CPU 101 determines that the MB is established (that is, the BB is not established) (when the determination in S828 is YES), the main CPU 101 sets the value of the bonus payout number counter to "13". "(S829). That is, the main CPU 101 overwrites the value of the bonus payout number counter from "144" to "13". As a result, in the present embodiment, the BB game state (during BB) ends when more than "144" medals are paid out, and the MB game state (during MB) has more than "13" medals. It is set to end when there is a payout of. The value of the payout number counter during the bonus shows an example of the present embodiment, and this value can be appropriately changed and set.

Next, the main CPU 101 performs a bonus start processing (S830). In this process, the main CPU 101 sets, for example, a bonus state to the game state of the next game (for example, at the start of the BB game state, the BB game state flag and the RB game state flag are turned on (“1” is set). Set), and if it is the start of the MB game state, perform various processes necessary for starting the operation of the bonus such as turning on the MB game state flag and the CB game state flag (setting “1”). Then, after the processing of S830, the main CPU 101 ends the bonus check processing and shifts the processing to the processing of S218 in the main flow (see FIG. 54).

[RT check processing]
Next, the RT check process performed in S218 in the main flow (see FIG. 54) will be described with reference to FIG. 97. Note that FIG. 97 is a flowchart showing the procedure of the RT check process.

First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S841). That is, the main CPU 101 determines whether or not the current gaming state is the BB gaming state or the MB gaming state. In S841, when the main CPU 101 determines that the current gaming state is the bonus state (when the determination in S841 is YES), the main CPU 101 ends the RT check process and is performing the process in the main flow (see FIG. 54). The process of S219 is performed.

On the other hand, in S841, when the main CPU 101 determines that the current gaming state is not the bonus state (when the determination in S841 is NO), the main CPU 101 determines whether or not the RT state is the RT4 state (S842). .. In S842, when the main CPU 101 determines that the RT state is the RT4 state (when the determination in S842 is YES), the main CPU 101 ends the RT check process, and S219 in the main flow (see FIG. 54) of the process. Move to the processing of.

On the other hand, in S842, when the main CPU 101 determines that the RT state is not the RT4 state (when the determination in S842 is NO), the main CPU 101 determines whether or not the symbol combination of "bell spilled eyes" is displayed (). S843). That is, the main CPU 101 determines whether or not any of the symbol combinations of "S_RT1 transition A", "S_RT1 transition B", and "S_RT1 transition C" is displayed on the valid line. In S843, when the main CPU 101 determines that the symbol combination of "bell spilled eyes" is displayed (when the determination in S843 is YES), the main CPU 101 performs the process of S845 described later.

On the other hand, in S843, when the main CPU 101 determines that the symbol combination of "bell spilled eyes" is not displayed (when the determination in S843 is NO), the main CPU 101 displays the symbol combination of "RT1 transition lip". It is determined whether or not it is (S844). That is, the main CPU 101 determines whether or not any combination of the symbols of "S_RT1 lip A" and "S_RT1 lip B" is displayed on the valid line. In S844, when the main CPU 101 determines that the symbol combination of "RT1 transition lip" is not displayed (when the determination in S844 is NO), the main CPU 101 performs the process of S846 described later.

In S843, when the main CPU 101 determines that the symbol combination of "bell spilled eyes" is displayed (when the determination in S843 is YES), and in S844, the main CPU 101 displays the symbol combination of "RT1 transition lip". When it is determined that the combination has been performed (when the determination in S844 is YES), the main CPU 101 sets the RT1 state flag to the ON state (S845). By this process, when the RT state is another RT state, the RT state shifts to the RT1 state. Then, after the processing of S845, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 54).

Here, returning to the process of S844 again, when S844 is NO-determined, the main CPU 101 determines whether or not the combination of the symbols of "RT2 transition lip" is displayed (S846). That is, the main CPU 101 determines whether or not the combination of the symbols of "C_RT2 lip" is displayed on the effective line. In S846, when the main CPU 101 determines that the symbol combination of "RT2 transition lip" is not displayed (when the determination in S846 is NO), the main CPU 101 performs the process of S848 described later.

On the other hand, in S846, when the main CPU 101 determines that the symbol combination of "RT2 transition lip" is displayed (when the determination in S846 is YES), the main CPU 101 sets the RT2 state flag to the ON state (S847). By this process, when the RT state is another RT state, the RT state shifts to the RT2 state. Then, after the processing of S847, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 54).

Here, returning to the process of S846 again, when the determination in S846 is NO, the main CPU 101 determines whether or not the combination of the symbols of the "RT3 transition lip" is displayed (S848). That is, the main CPU 101 determines whether or not any combination of symbols of "S_RT3 lip", "C_SP_CL lip", "C_SP_XU lip" and "C_SP_XD lip" is displayed on the valid line. In S848, when the main CPU 101 determines that the symbol combination of "RT3 transition lip" is not displayed (when the determination in S846 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (FIG. 54). (See) Move to the process of S219 in.

On the other hand, in S848, when the main CPU 101 determines that the symbol combination of "RT3 transition lip" is displayed (when the determination in S848 is YES), the main CPU 101 sets the RT3 state flag to the ON state (S849). By this process, when the RT state is another RT state, the RT state shifts to the RT3 state. Then, after the processing of S849, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 54).

[Control processing by state at the end of the game]
Next, with reference to FIG. 98, the state-based control process at the end of the game performed in S219 in the main flow (see FIG. 54) will be described. Note that FIG. 98 is a flowchart showing the procedure of the control process for each state at the end of the game.

First, the main CPU 101 determines whether or not the current game is in ART (see FIG. 14) (S861). In S861, when the main CPU 101 determines that the current game is not in ART (when the determination in S861 is NO), the main CPU 101 performs the process of S865 described later.

On the other hand, in S861, when the main CPU 101 determines that the current game is in ART (when the determination in S861 is YES), the main CPU 101 determines whether or not the current game is in a continuous challenge (see FIG. 14). Determine (S862). In S862, when the main CPU 101 determines that the current game is in the continuous challenge (when the determination in S862 is YES), the main CPU 101 performs the processing at the end of the continuous challenge (S863). The details of the processing at the end of the continuous challenge will be described later with reference to FIG. 99 described later. Then, after the processing of S863, the main CPU 101 ends the state-based control processing at the end of the game, and shifts the processing to S201 of the main flow (see FIG. 54).

On the other hand, in S862, when the main CPU 101 determines that the current game is not in the continuous challenge (when the determination in S862 is NO), the main CPU 101 performs other state-based control processing at the end of the game during ART (S864). In addition to this, in the control process according to the state at the end of the game during ART, for example, when there is a prize (operation) of BB, a process of shifting to the CP special zone during BB from the next game is performed. Then, after the processing of S864, the main CPU 101 ends the state-based control processing at the end of the game, and shifts the processing to S201 of the main flow (see FIG. 54).

Here, returning to the process of S861 again, when S861 determines NO, the main CPU 101 performs other normal middle game end state-specific control processes (S865). In the other control process according to the state at the end of the normal game, for example, when there is a prize (operation) of the BB, a process of shifting to the BB history special zone from the next game is performed. Then, after the processing of S865, the main CPU 101 ends the state-based control processing at the end of the game, and shifts the processing to S201 of the main flow (see FIG. 54).

[Processing at the end of continuous challenge]
Next, with reference to FIG. 99, the process at the end of the continuous challenge performed in S863 during the control process for each state at the end of the game (see FIG. 98) will be described. Note that FIG. 99 is a flowchart showing the procedure at the end of the continuous challenge.

First, the main CPU 101 determines whether or not the promotion chance activation flag is on (S871). In S871, when the main CPU 101 determines that the promotion chance activation flag is not on (when the determination in S871 is NO), the main CPU 101 performs the process of S874 described later.

On the other hand, in S871, when the main CPU 101 determines that the promotion chance activation flag is on (when the determination in S871 is YES), the main CPU 101 sets the promotion chance (S872). That is, the main CPU 101 controls the transition from the next unit game to the promotion chance. Next, the main CPU 101 sets a continuous challenge as the pre-start state (S873). That is, the main CPU 101 stores information for performing control to shift to the continuous challenge again when the transferred promotion chance ends. Then, after the processing of S873, the main CPU 101 ends the processing at the end of the continuous challenge, and shifts the processing to S201 of the main flow (see FIG. 54).

Here, returning to the process of S871 again, when the determination in S871 is NO, the main CPU 101 determines whether or not the CP has become 0 (S874). That is, the main CPU 101 determines whether or not all the acquired CPs have been consumed in the continuous challenge. In S874, when the main CPU 101 determines that the CP is not 0 (when the determination in S874 is NO), the main CPU 101 ends the processing at the end of the continuous challenge and performs the processing in the main flow (see FIG. 54). Move to S201.

On the other hand, in S874, when the main CPU 101 determines that the CP has become 0 (when the determination in S874 is YES), the main CPU 101 determines whether or not the ART game number counter is 0 (S875). That is, the main CPU 101 determines whether or not the number of ART games has been added in the continuous challenge. In S875, when the main CPU 101 determines that the ART game number counter is not 0 (when the determination in S875 is NO), the main CPU 101 performs the process of S878 described later.

On the other hand, in S875, when the main CPU 101 determines that the ART game number counter is 0 (when the determination in S875 is YES), the main CPU 101 determines whether or not the ART stock counter is 0 (S876). .. That is, the main CPU 101 determines whether or not there is ART stock. In S876, when the main CPU 101 determines that the ART stock counter is not 0 (when the determination in S876 is NO), the main CPU 101 performs a process of subtracting "1" from the ART stock counter (S877).

Next, the main CPU 101 performs the ART transition initial setting process (S878). In this ART transition processing setting process, if the number of ART games is added in the continuous challenge, the process of returning to the normal ART of the set with the number of ART games is performed, and the number of ART games is added in the continuous challenge. If not, the process of starting the next set of normal ART is performed. In this case, the promotion lottery for the promotion chance can be performed in this process. Then, after the processing of S878, the main CPU 101 ends the processing at the end of the continuous challenge, and shifts the processing to S201 of the main flow (see FIG. 54).

On the other hand, in S876, when the main CPU 101 determines that the ART stock counter is 0 (when the determination in S876 is YES), the main CPU 101 performs a normal transition initial setting process (S879). In this normal transition initial setting process, the game state is shifted at the normal time, a lottery is performed at the end of ART in the normal mode, and a determined normal mode is set. Then, after the processing of S879, the main CPU 101 ends the processing at the end of the continuous challenge, and shifts the processing to S201 of the main flow (see FIG. 54).

[Interrupt processing controlled by the main CPU (1.1172 msec)]
Next, with reference to FIG. 100, the interrupt processing performed by the main CPU 101 at a cycle of 1.1172 msec will be described. Note that FIG. 100 is a flowchart showing the procedure of the interrupt process. The interrupt process repeatedly executed at a cycle of 1.1172 msec is generated based on the output timing of the timeout signal of the timer circuit 113 set in the initialization process of the timer circuit 113 (PTC) (see S2 in FIG. 36). This is a process executed when the interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

First, the main CPU 101 performs a register save process (S901). Next, the main CPU 101 performs an input port check process (S902). In this process, signals input from various switches such as a stop switch are checked.

Next, the main CPU 101 performs a reel control process (S903). In this process, the main CPU 101 starts rotating the left reel 3L, the middle reel 3C, and the right reel 3R when all the reels are requested to start rotating, and then each reel rotates at a constant speed. It drives and controls three stepping motors. When the number of sliding pieces is determined, the main CPU 101 updates the symbol counter of the corresponding reel by the number of sliding pieces. Then, the main CPU 101 waits for the updated symbol counter to match the value corresponding to the scheduled stop position (the symbol at the scheduled stop position reaches the area on the effective line of the display window) of the corresponding reel. The corresponding stepping motor is driven and controlled so that the rotation is decelerated and stopped.

Next, the main CPU 101 performs a communication data transmission process (S904). In this process, various commands stored in the communication data storage area are mainly transmitted to the sub-control circuit 200 via the first serial communication circuit 114 (see FIG. 9) of the main control circuit 90. After transmitting a command to the sub-control circuit 200, the main CPU 101 subtracts and updates the communication data pointer by one packet (not shown), and clears the transmitted command data in the communication data storage area. When a plurality of command data are stored in the communication data storage area, the command data is transmitted to the sub-control circuit 200 in the order of the oldest stored command data. Further, when the command data is not stored in the communication data storage area, that is, when the value of the communication data pointer is "0", a non-operation command is generated and transmitted to the sub-control circuit 200. Next, the main CPU 101 performs a insertion medal passage check process (S905). In this process, the main CPU 101 checks whether or not the inserted medal has passed the selector 66 based on the detection result (medal sensor input state) of the medal sensor (not shown). Next, the main CPU 101 performs the WDT restart process (S906).

Next, the main CPU 101 performs a 7-segment LED drive process (S907). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display 6, and displays, for example, the number of medals to be paid out, the number of credits, and the stop button pressing order data. The details of the 7-segment LED drive process will be described later with reference to FIG. 101 described later.

Next, the main CPU 101 performs a timer update process (S908). In this process, the main CPU 101 performs a count (subtraction) process of various set timers. The details of the timer update process will be described later with reference to FIG. 106 described later.

Next, the main CPU 101 performs an error detection process (S909). Next, the main CPU 101 performs a door open / close check process (S910). In the door open / close check process, the main CPU 101 checks the open / closed state of the front door 2b (see FIG. 2) by checking the on (door closed) / off (door open) state of the door open / close monitoring switch 67.

Next, the main CPU 101 performs a test firing test signal control process (S911). In this process, a control process is performed when various test signals are output to the testing machine via the second interface boat or the like. Further, this process is executed using the non-standard work area (see FIG. 12C) of the main RAM 103. In the present embodiment, this process is also performed at a time other than the test firing test (after the pachislot machine 1 is installed in the game store), but at this time, the main control board 71 passes through the second interface boat or the like. Since it is not connected to the testing machine, various test signals are generated but not output. The details of the test firing test signal control process will be described later with reference to FIG. 108 described later.

Next, the main CPU 101 performs a register reset process (S912). Then, after the processing of S912, the main CPU 101 ends the interrupt processing.

[7-segment LED drive processing]
Next, the 7-segment LED drive process performed in S907 during the interrupt process (see FIG. 100) will be described with reference to FIGS. 101 and 102. Note that FIG. 101 is a flowchart showing the procedure of the 7-segment LED drive process. Further, FIG. 102A is a diagram showing an example of a source program for executing the processes of S923 to S925 described later during the 7-segment LED drive process, and FIG. 102B is a diagram showing S931 to be described later during the 7-segment LED drive process. It is a figure which shows an example of the source program for executing the process of S936.

First, the main CPU 101 adds (+1 update) to the value of the interrupt counter (S921). Next, the main CPU 101 determines whether or not the value of the interrupt counter is an odd number (S922).

When the main CPU 101 determines in S922 that the value of the interrupt counter is not an odd number (when the determination in S922 is NO), the main CPU 101 ends the 7-segment LED drive process and interrupts the process (see FIG. 100). ) Moves to the processing of S908. That is, in the present embodiment, the 7-segment LED drive process is performed every two interruption cycles. In the present embodiment, an example of executing the 7-segment LED drive process when the value of the interrupt counter is even has been described, but the present invention is not limited to this, and the 7-segment LED drive process is not limited to this when the value of the interrupt counter is odd. The LED drive process may be executed, or the execution timing of the 7-segment LED drive process may be determined by using the quotient or the remainder when the value of the interrupt counter is divided by an arbitrary integer.

On the other hand, in S922, when the main CPU 101 determines that the value of the interrupt counter is an odd number (when the determination in S922 is YES), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets the address of the push order display data storage area for storing the push order display data output to each cathode of the 7-segment LED (S924).

Next, the main CPU 101 performs a 7-segment display data generation process (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 103 described later.

Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets the address of the credit display data storage area for storing the credit display data output to each cathode of the 7-segment LED (S927).

Next, the main CPU 101 performs a 7-segment display data generation process (S928). In this process, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 103 described later.

Next, the main CPU 101 sets the address of the 7-segment common counter storage area for storing the value of the 7-segment common counter described later (S929). Next, the main CPU 101 adds (+1 update) to the value of the 7-segment common counter (S930). In this process, when the updated 7-segment common counter value becomes "8", the main CPU 101 sets the 7-segment common counter value to "0". In the present embodiment, since the 7-segment LED is dynamically controlled, the value of the 7-segment common counter is updated every 8 times.

Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and addresses the target cathode data storage area (push order display data storage area or target storage area in the credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This process is performed in order to temporarily turn off the 7-segment LED to eliminate the influence of the afterimage.

Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). Then, after the processing of S936, the main CPU 101 ends the 7-segment LED drive processing, and shifts the processing to the processing of S908 in the interrupt processing (see FIG. 100).

In the present embodiment, the 7-segment LED drive process is performed as described above. The processes S923 to S925 during the 7-segment LED drive process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 102A. Further, the processes of S931 to S936 during the above-mentioned 7-segment LED drive process are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 102B.

Among them, the output processing of each 7-segment output data of S936 is executed by one source code "LD (cPA_SEGCOM), BC" as shown in FIG. 102B. Therefore, in the 7-segment LED drive process of the present embodiment, the 7-segment common output (selection) data and the 7-segment cathode output data are output at the same time when the 2-digit 7-segment LED is dynamically lit and controlled. That is, in the dynamic lighting control of the 7-segment LED when performing push order navigation on the instruction monitor, and the 7-segment common output (7-segment common output) in the dynamic lighting control of the 7-segment LED when displaying credit information with the 2-digit 7-segment LED. (Selection) data and 7-segment cathode output data are output at the same time.

In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, it becomes possible to improve the playability. Further, in the present embodiment, an example in which a 7-segment drive circuit (not shown) that performs a 7-segment LED drive process is configured by a cathode common circuit and controlled by the cathode has been described, but the present invention is not limited to this, and 7 The seg drive circuit may be composed of an anode common circuit, and the 7-segment LED may be controlled by the anode.

Further, as shown in FIG. 102A, the Q register (extension register) is used for both the acquisition process of the navigation data of S923 and the address set process of the push display data storage area of S924 during the 7-segment LED drive process described above. It is executed by the "LDQ" instruction (instruction code dedicated to the main CPU 101) that specifies the address. Therefore, in the 7-segment LED drive process of the present embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by the direct value by using the "LDQ" instruction, so that the source program can be used. , The instruction related to the address setting can be omitted (it is not necessary to separately provide the instruction related to the address setting), and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[7-segment display data generation process]
Next, the 7-segment display data generation process performed in S925 and S928 in the 7-segment LED drive process (see FIG. 101) will be described with reference to FIGS. 103 to 105. Note that FIG. 103 is a flowchart showing the procedure of the 7-segment display data generation process. FIG. 104 is a diagram showing an example of a source program for executing the 7-segment display data generation process. Further, FIG. 105 is a diagram showing an example of the configuration of the 7-segment cathode table that is actually referred to on the source program of the 7-segment display data generation process.

The "display data" described later generated in the 7-segment display data generation process performed in S925 during the 7-segment LED drive process (see FIG. 101) corresponds to the push-order display data, and the 7-segment LED drive process (FIG. 101). The "display data" described later generated in the 7-segment display data generation process performed in S928 in (see 101) corresponds to the credit display data.

First, the main CPU 101 divides the display data set in the cathode data storage area by "10", acquires the quotient value of the division result as the display data of the upper digit of the 2-digit 7-segment LED, and divides the data. The remaining value of the result is acquired as the display data of the lower digit (S941). Next, the main CPU 101 determines whether or not to display the upper digit based on the acquired display data of the upper digit (S942).

In S942, when the main CPU 101 determines that the upper digit display is to be performed (when the determination in S942 is YES), the main CPU 101 performs the process of S944 described later. On the other hand, in S942, when the main CPU 101 determines that the upper digit is not displayed (when the determination in S942 is NO), the main CPU 101 sets no display of the upper digit (S943).

After the processing of S943 or when the determination in S942 is YES, the main CPU 101 refers to the 7-segment cathode table (see FIG. 163) and acquires the display data of the upper digit (S944). Next, the main CPU 101 saves the acquired high-order digit display data in the high-order digit display data storage area (not shown) (S945).

Next, the main CPU 101 refers to the 7-segment cathode table (see FIG. 105) and acquires the display data of the lower digits (S946). Next, the main CPU 101 saves the acquired low-order digit display data in the low-order digit display data storage area (not shown) (S947).

Then, after the processing of S947, the main CPU 101 ends the 7-segment display data generation processing. At this time, if the executed 7-segment display data generation process is the process of S925 during the 7-segment LED drive process (see FIG. 101), the main CPU 101 changes the process to the process of S926 during the 7-segment LED drive process. Transfer. On the other hand, when the executed 7-segment display data generation process is the process of S928 in the 7-segment LED drive process (see FIG. 101), the main CPU 101 shifts the process to the process of S929 in the 7-segment LED drive process. ..

In the present embodiment, the 7-segment display data generation process is performed as described above. The 7-segment display data generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 104.

[Timer update process]
Next, the timer update process performed in S908 during the interrupt process (see FIG. 100) will be described with reference to FIGS. 106 and 107. Note that FIG. 106 is a flowchart showing the procedure of the timer update process. Further, FIG. 107 is a diagram showing an example of a source program for executing the processes of S951 to S954 described later during the timer update process.

First, the main CPU 101 sets the update start address of the 2-byte timer storage area (not shown) in the HL register, and sets the number of 2-byte timers in the B register (S951).

Next, the main CPU 101 compares the 2-byte timer value with its lower limit value "0", and if the 2-byte timer value is larger than the lower limit value "0", subtracts 1 from the 2-byte timer value (updates -1). If the 2-byte timer value is equal to or less than the lower limit value "0", the 2-byte timer value is held at "0" (S952). Further, in the process of S952, the main CPU 101 subtracts 2 (-2 updates) the update start address of the 2-byte timer storage area set in the HL register.

Next, the main CPU 101 subtracts (updates -1) the number of 2-byte timers set in the B register by 1 (S953). Next, the main CPU 101 determines whether or not the number of 2-byte timers set in the B register is "0" (S954).

In S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is not "0" (when the determination in S954 is NO), the main CPU 101 returns the processing to the processing of S952, and after S952. Repeat the process.

On the other hand, in S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is "0" (when the determination in S954 is YES), the main CPU 101 stores the 1-byte timer in the HL register. The update start address of is set, and the number of 1-byte timers is set in the B register (S955).

Next, the main CPU 101 compares the 1-byte timer value with its lower limit value "0", and if the 1-byte timer value is larger than the lower limit value "0", the 1-byte timer value is subtracted by 1 (-1 update). When the 1-byte timer value is equal to or less than the lower limit value "0", the 1-byte timer value is held at "0" (S956). Further, in the process of S956, the main CPU 101 subtracts 1 (-1 update) the update start address of the 1-byte timer storage area set in the HL register.

Next, the main CPU 101 subtracts (updates -1) the number of 1-byte timers set in the B register by 1 (S957). Next, the main CPU 101 determines whether or not the number of 1-byte timers set in the B register is "0" (S958).

In S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is not "0" (when the determination in S958 is NO), the main CPU 101 returns the processing to the processing of S956, and after S956. Repeat the process.

On the other hand, in S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is "0" (when the determination in S958 is YES), the main CPU 101 performs an electromagnetic counter control process (S959). ). In this process, an output control process is performed when a signal indicating IN / OUT of the medal is output to the external centralized terminal plate 47. Then, after the processing of S959, the main CPU 101 ends the timer update processing, and shifts the processing to the processing of S909 in the interrupt processing (see FIG. 100).

In the present embodiment, the timer update process is performed as described above. The processes S951 to S954 (two-byte timer update process) during the timer update process described above are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 107.

Among them, the process of S952 (update process of the 2-byte timer) is executed by the "DCPWLD" instruction (predetermined update instruction) in FIG. 107. The "DCPWLD" instruction is an instruction code dedicated to the main CPU 101.

When, for example, the source code "DCPWLD (HL), n" is executed on the source program, the contents (stored data) of the memory for 2 bytes from the address specified in the HL register are compared with the integer n. When the contents of the memory for 2 bytes are larger than the integer n, the contents of the memory for 2 bytes are subtracted by 1, and when the contents of the memory for 2 bytes are not more than the integer n, it is specified by the HL register. The integer n is stored in the memory for 2 bytes from the address.

Therefore, in the source code "DCPWLD (HL), 0" in FIG. 107, the contents of the memory for 2 bytes (2-byte timer value) and the integer "0" (lower limit value) from the address specified by the HL register are used. When the contents of the memory for 2 bytes are larger than the integer "0", the contents of the memory for 2 bytes are subtracted by 1, and the contents of the memory for 2 bytes are equal to or less than the integer "0". Is set to "0" in the contents of the memory for 2 bytes. That is, if the current 2-byte timer value is larger than "0", the 2-byte timer is updated, and if the current 2-byte timer value is "0" or less, the 2-byte timer value is "0". Is held in.

As described above, in the timer update process of the present embodiment, both the timer value update (subtraction) process and the timer value holding process are executed by the "DCPWLD" instruction code dedicated to the main CPU 101. can do. In this case, it is not necessary to provide an instruction code for executing both processes separately. Further, the judgment branch instruction code for determining whether or not the timer value is "0" can be omitted. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, it becomes possible to improve the playability. In the present embodiment, an example in which the "DCPWLD" instruction is used only in the update process of the 2-byte timer has been described, but the present invention is not limited to this, and the "DCWPLD" instruction is also used in the update process of the 1-byte timer. You may use it.

[Test firing test signal control processing (non-standard)]
Next, with reference to FIG. 108, the test firing test signal control process performed in S911 during the interrupt process (see FIG. 100) will be described. Note that FIG. 108 is a flowchart showing the procedure of the test firing test signal control process.

First, the main CPU 101 saves the address of the stack area of the main RAM 103 (S961). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S962). Next, the main CPU 101 saves the data of all the registers (S963).

Next, the main CPU 101 performs a rotating cylinder braking signal generation process (S964). In this process, the main CPU 101 generates and outputs a rotation control signal (drive signal) for each reel, which is output to the testing machine via the second interface boat or the like. The details of the rotating cylinder braking signal generation process will be described later with reference to FIG. 109 described later.

Next, the main CPU 101 performs a special prize signal control process (S965). In this process, the main CPU 101 performs an output process of a bonus (special prize) ON / OFF signal (test signal) output to the testing machine. The details of the prize signal control process will be described later with reference to FIG. 110 described later.

Next, the main CPU 101 performs the condition device signal control process (S966). In this process, the main CPU 101 performs a control signal output process corresponding to the state of the condition device signal control flag. The details of the condition device signal control process will be described later with reference to FIGS. 111 and 112 described later.

Next, the main CPU 101 performs a restoration process of the data of all the registers saved in the process of S963 (S967). Next, the main CPU 101 sets the address of the stack area saved in the process of S961 in the stack pointer (SP) (S968). Then, after the processing of S968, the main CPU 101 ends the test firing test signal control processing, and shifts the processing to the processing of S912 in the interrupt processing (see FIG. 100).

[Rotating cylinder braking signal generation processing]
Next, with reference to FIG. 109, the rotating cylinder braking signal generation process performed in S964 during the test firing test signal control process (see FIG. 108) will be described. Note that FIG. 109 is a flowchart showing the procedure of the rotating cylinder braking signal generation processing.

First, the main CPU 101 sets a rotation cylinder control data storage area (not shown) in the non-standard work area (S971). Next, the main CPU 101 sets the number of reels to "3" and clears the rotation cylinder control signal and its generation state (1 byte data) (S972).

Next, the main CPU 101 determines whether or not the rotating cylinder control data is “less than stopped” data (S973). The "less than stopped" rotation control data here is rotation control data other than rotation control data for stopping the reel, that is, rotation control data for rotationally driving the reel (acceleration). It is one of the states of preparation, acceleration, constant speed waiting, constant speed, and waiting for stop start position).

In S973, when the main CPU 101 determines that the rotation control data is "less than stopped" data (when the determination in S973 is YES), the main CPU 101 performs the process of S975 described later. On the other hand, in S973, when the main CPU 101 determines that the rotation control data is not "less than stopped" data (when the determination in S973 is NO), the main CPU 101 determines that the rotation control data is "statically indeterminate hold control end". It is determined whether or not the data is (S974). The rotating cylinder control data of "statically indeterminate hold control end" here is rotation cylinder control data indicating a state in which all phases of the reel are stopped.

In S974, when the main CPU 101 determines that the rotation control data is the data of "statically indeterminate hold control end" (when the determination in S974 is YES), the main CPU 101 performs the process of S976 described later. On the other hand, in S974, when the main CPU 101 determines that the rotation control data is not the data of "statically indeterminate hold control end" (when the determination in S974 is NO), or when the determination in S973 is YES, the main CPU 101 determines. Bit 3 of the rotation control signal generation state (1 byte data) is turned on (“1”) (S975).

After the processing of S975 or when the determination in S974 is NO, the main CPU 101 shifts the data of each bit in the generated state by one bit to the right (in the direction from bit 7 to bit 0) (S976). Next, the main CPU 101 updates the address of the rotating cylinder control data storage area to the address of the next reel to be controlled (S977).

Next, the main CPU 101 subtracts 1 from the number of reels (S978). Next, the main CPU 101 determines whether or not the number of reels is "0" (S979).

When the main CPU 101 determines in S979 that the number of reels is not "0" (when the determination in S979 is NO), the main CPU 101 returns the process to the process of S973 and repeats the processes after S973.

On the other hand, in S979, when the main CPU 101 determines that the number of reels is "0" (when the determination in S979 is YES), the main CPU 101 outputs the data in the generated state via the rotating cylinder braking signal output port. Output to the first interface board 301 (see FIG. 7) (S980). Then, after the processing of S980, the main CPU 101 ends the rotation cylinder braking signal generation processing, and shifts the processing to the processing of S965 in the test firing test signal control processing (see FIG. 108).

[Special prize signal control processing]
Next, with reference to FIG. 110, the special prize signal control process performed in S965 during the test firing test signal control process (see FIG. 108) will be described. Note that FIG. 110 is a flowchart showing the procedure of the special prize signal control process.

First, the main CPU 101 acquires the game state flag by referring to the game state flag storage area (see FIG. 24) (S991). Next, the main CPU 101 determines whether or not the gaming state is the RB gaming state (S992).

In S992, when the main CPU 101 determines that the gaming state is the RB gaming state (when the determination in S992 is YES), the main CPU 101 sends an ON signal from the RB medium signal port for the test signal to the first interface for the test machine. Output to board 301 (see FIG. 7) (S993). On the other hand, in S992, when the main CPU 101 determines that the gaming state is not the RB gaming state (when the determination in S992 is NO), the main CPU 101 sends an OFF signal from the RB medium signal port for the test signal to the first test machine. Output to the interface board 301 (see FIG. 7) (S994).

After the processing of S993 or S994, the main CPU 101 refers to the game state flag storage area (see FIG. 24) and determines whether or not the game state is the BB game state (S995).

In S995, when the main CPU 101 determines that the gaming state is the BB gaming state (when the determination in S995 is YES), the main CPU 101 sends an ON signal from the BB medium signal port for the test signal to the first interface for the test machine. Output to board 301 (see FIG. 7) (S996). On the other hand, in S995, when the main CPU 101 determines that the gaming state is not the BB gaming state (when the determination in S995 is NO), the main CPU 101 sends an OFF signal from the BB medium signal port for the test signal to the first test machine. Output to the interface board 301 (see FIG. 7) (S997).

Then, after the processing of S996 or S997, the main CPU 101 ends the special prize signal control processing, and shifts the processing to the processing of S966 in the test firing test signal control processing (see FIG. 108).

In this embodiment, since the CB gaming state and the MB gaming state are further provided (see FIG. 24), the same processing as described above may be performed in the RB gaming state and the MB gaming state. ..

Specifically, after the processing of S998, when the main CPU 101 determines whether or not the gaming state is the CB gaming state, and the main CPU 101 determines that the gaming state is the CB gaming state, the test signal is used. While the ON signal is output from the CB medium signal port to the first interface board 301 for the test machine (see FIG. 7), when it is determined that the gaming state is not the CB gaming state, the OFF signal is output from the CB medium signal port for the test signal. The output may be made to the first interface board 301 for the testing machine (see FIG. 7).

Further, after the processing, the main CPU 101 determines whether or not the gaming state is the MB gaming state, and when the main CPU 101 determines that the gaming state is the MB gaming state, the MB signal port for the test signal. While outputting the ON signal to the first interface board 301 for the tester (see FIG. 7), when it is determined that the gaming state is not the MB gaming state, the OFF signal is output from the MB medium signal port for the test signal to the tester. 1 Output to the interface board 301 (see FIG. 7) may be performed.

However, in the present embodiment, since the MB game state lasts only two games at the maximum (see FIG. 96), in the case of being configured in this way, the CB game state and the MB game state are provided. Even if there is, the ON signal or the OFF signal may not be output from the signal port for the test signal to the first interface board 301 for the tester (see FIG. 7).

Further, in the present embodiment, since the RB game state and the BB game state and the CB game state and the MB game state are configured not to operate at the same time, whether or not the CB game state is operating. When outputting a signal indicating whether or not, an ON signal or an OFF signal is output using the RB medium signal port as a signal port for the test signal, and a signal indicating whether or not the MB game state is operating is output. In this case, the ON signal or the OFF signal may be output by using the BB medium signal port as the signal port for the test signal.

[Condition device signal control processing]
Next, the condition device signal control process performed in S966 during the test firing test signal control process (see FIG. 108) will be described with reference to FIGS. 111 and 112. 11 and 112 are flowcharts showing the procedure of the condition device signal control process.

First, the main CPU 101 determines whether or not the condition device signal control flag is in the initial state (S1001). In S1001, when the main CPU 101 determines that the condition device signal control flag is in the initial state (when the determination in S1001 is YES), the main CPU 101 ends the condition device signal control process and performs the process as a test firing test signal control process. The process proceeds to S967 (see FIG. 108).

On the other hand, in S1001, when the main CPU 101 determines that the condition device signal control flag is not in the initial state (when the determination in S1001 is NO), the main CPU 101 sets the condition device signal control flag to the ON state of the replay state identification signal. It is determined whether or not it is indicated (S1002).

In S1002, when the main CPU 101 determines that the condition device signal control flag indicates the ON state of the replay state identification signal (when the determination in S1002 is YES), the main CPU 101 serves the condition device signal control state. The ON state of the physical condition device signal is set (S1003). Next, the main CPU 101 outputs the RT state information from the condition devices 1 to 6 signal ports to the first interface board 301 for the testing machine (see FIG. 7) (S1004). Then, after the processing of S1004, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 108).

On the other hand, in S1002, when the main CPU 101 determines that the condition device signal control flag does not indicate the ON state of the replay state identification signal (when the determination in S1002 is NO), the condition device signal control flag is set in the main CPU 101. It is determined whether or not the re-game state identification signal indicates an off state (S1005).

In S1005, when the main CPU 101 determines that the condition device signal control flag indicates the off state of the replay state identification signal (when the determination in S1005 is YES), the main CPU 101 uses the condition devices 1 to 8 signal ports. Outputs the OFF signal from the first interface board 301 for the testing machine (see FIG. 7) (S1006). Then, after the processing of S1006, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 108).

On the other hand, in S1005, when the main CPU 101 determines that the condition device signal control flag does not indicate the off state of the replay state identification signal (when the determination in S1005 is NO), the main CPU 101 has the condition device signal control state. It is determined whether or not the accessory condition device signal is on (S1007).

In S1007, when the main CPU 101 determines that the condition device signal control state is the ON state of the accessory condition device signal (when the determination in S1007 is YES), the main CPU 101 wins a special prize from the condition devices 1 to 8 signal ports. The number information is output to the first interface board 301 for the testing machine (see FIG. 7), and at this time, the ON signal is output from the condition device 8 signal port to the first interface board 301 for the testing machine (see FIG. 7) (see FIG. 7). S1008). Next, the main CPU 101 sets a predetermined waiting time (24.58 ms in this embodiment) in the condition device signal output waiting timer (S1009). Next, the main CPU 101 sets the condition device signal control state to the state of waiting for the condition device signal output (S1010). Then, after the processing of S1010, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 108).

On the other hand, in S1007, when the main CPU 101 determines that the condition device signal control state is not the ON state of the accessory condition device signal (when the determination in S1007 is NO), the main CPU 101 has the condition device signal control state as the condition device signal. It is determined whether or not the output is waiting (S1011).

In S1011, when the main CPU 101 determines that the condition device signal control state is the state of waiting for the condition device signal output (when the determination of YES in S1011), the value of the condition device signal output wait timer of the main CPU 101 is "0". It is determined whether or not it is (S1012).

In S1012, when the main CPU 101 determines that the value of the condition device signal output waiting timer is not "0" (when the determination in S1012 is NO), the main CPU 101 ends the condition device signal control process and tests the process. The process shifts to the process of S967 in the signal control process (see FIG. 108). On the other hand, in S1012, when the main CPU 101 determines that the value of the condition device signal output waiting timer is "0" (when the determination in S1012 is YES), the main CPU 101 is in the condition device signal control state. The on state of the signal or the off state of the condition device signal is set (S1013). Then, after the processing of S1013, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 108).

Here, returning to the processing of S1011 again, when the main CPU 101 determines in S1011 that the condition device signal control state is not the state of waiting for the condition device signal output (when the determination in S1011 is NO), the main CPU 101 determines the condition. It is determined whether or not the device signal control state is the on state of the small combination condition device signal (S1014).

In S1014, when the main CPU 101 determines that the condition device signal control state is the on state of the small combination condition device signal (when the determination in S1014 is YES), the main CPU 101 has a small combination from the condition devices 1 to 8 signal ports. The information of the winning number (for example, the winning number predetermined as including the small winning combination among the winning numbers (see FIGS. 16 and 17)) is output to the first interface board 301 for the testing machine (see FIG. 7). At this time, the ON signal is output from the condition device 7 signal port to the first interface board 301 for the testing machine (see FIG. 7) (S1015). Next, a predetermined waiting time (24.58 ms in this embodiment) is set in the condition device signal output waiting timer (S1016). Next, the main CPU 101 sets the condition device signal control state to the state of waiting for the condition device signal output (S1017). Then, after the processing of S1017, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 108).

On the other hand, in S1014, when the main CPU 101 determines that the condition device signal control state is not the ON state of the small winning combination condition device signal (when the determination in S1014 is NO), the main CPU 101 is turned off from the condition devices 1 to 8 signal ports. The signal is output to the first interface board 301 for the testing machine (see FIG. 7) (S1018). Then, after the processing of S1018, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 108).

<Explanation of operation of sub-control circuit>
Next, with reference to FIGS. 113 to 122, the contents of various processes executed by the sub CPU 201 of the sub control circuit 200 by using the program will be described.

[Power-on processing of sub CPU]
First, the power-on process of the sub CPU 201 will be described with reference to FIG. 113. Note that FIG. 113 is a flowchart showing the procedure of the power-on process.

First, when the power of the sub CPU 201 is turned on, the sub CPU initial setting process is executed (S1101). In this process, for example, the initialization process of the sub CPU 201, the initialization process of the connected device (IC (Integrated Circuit), LSI (Large-scale Integration), etc.), the initialization process of the memory (DRAM), the OS (Operating System) Initialization processing and the like are performed.

Next, the sub CPU 201 makes a request to start the accessory control task as a request to start the sub task (S1102). The term "role" as used herein means an effect device that produces an effect by a physical operation, and when the effect device is also provided in the present embodiment and the effect using the effect device can be executed, this is used. The operation of the effect device is controlled by the accessory control task. The accessory control task is executed, for example, in the power-on processing of the sub CPU, when the accessory control task request is generated from the OS in response to the activation request of the accessory control task by the sub CPU 201.

Next, the sub CPU 201 makes a request to start the lamp control task described above (S1103). Next, the sub CPU 201 makes a request to activate the sound control task described above (S1104).

Next, the sub CPU 201 makes a request to start the main board communication task described above (S1105). The main board communication task is executed, for example, in the power-on processing of the sub CPU, when the main board communication task request is generated from the OS in response to the start request of the main board communication task by the sub CPU 201. The details of the main board communication task will be described later with reference to FIG. 115 described later.

Next, the sub CPU 201 makes a request to start the animation task described above (S1106). The animation task is executed, for example, in the power-on processing of the sub CPU, when an animation task request is generated from the OS in response to a request for starting the animation task by the sub CPU 201. Further, the animation task is repeated in a cycle of 33 msec including, for example, a processing time in order to control the image display operation of the display device 11 (projector mechanism 211) and / or the sub display device 18.
I will control it.

Next, the sub CPU 201 performs a backup recovery process (S1107). In this process, the sub CPU 201 uses various game data (game state data, number of ART games, number of ART stocks, CP, etc.) stored in SRAM (static RAM) and various history data for work DARM (dynamic). Copy to RAM). By this process, the effect content in the pachislot machine 1 can be restored to the state before the power failure. Then, after the process of S1107, the sub CPU 201 ends the power-on process.

[Sub CPU interrupt interrupt processing]
Next, the power interruption interrupt processing of the sub CPU 201 will be described with reference to FIG. 114. This process is, for example, an interrupt process that is executed when an abnormality such as a power failure occurs. Note that FIG. 114 is a flowchart showing the procedure of the power interruption interrupt processing.

When a power failure (decrease in power supply voltage) occurs, the sub CPU 201 performs a backup creation process (S1111). In this process, the sub CPU 201 copies various data to be held from the DRAM to the SRAM when the power failure is detected. That is, the sub CPU 201 performs the reverse process of the backup recovery process (S1107 during the power-on process) described above. By this process, even if the data is destroyed, the correct data is saved as backup data.

[Main board communication task]
Next, the main board communication task executed by the sub CPU 201 will be described with reference to FIG. 115. Note that FIG. 115 is a flowchart showing the procedure of the main board communication task.

First, the sub CPU 201 performs a reception check of the command transmitted from the main control circuit 90 and acquires the command registration data (S1121). Next, the sub CPU 201 extracts the type of the received command (S1122). In this embodiment, the command data is composed of 8 bytes of data, and the first byte of data indicates the type of command.

Next, the sub CPU 201 determines whether or not the command type is a specified type (S1123).

In the present embodiment, the command type is associated with any of a plurality of predetermined types of codes, and when the game is operating normally, the command type is one of the prescribed codes. Become. Therefore, in the process of S1123, if the type of the received command is any of the codes within the specified code, the sub CPU 201 determines that the command type is valid (specified type). On the other hand, if the command type is a non-standard code, the sub CPU 201 determines that some abnormality (including cheating) has occurred during the game, and determines that the command type is invalid.

In S1123, when the sub CPU 201 determines that the command type is not the specified type (NO in S1123), the sub CPU 201 returns the process to S1121 and repeats the processes after S1121. On the other hand, in S1123, when the sub CPU 201 determines that the command type is the specified type (YES in S1123), the sub CPU 201 stores a message in the message queue based on the received command (when the sub CPU 201 determines that the command type is YES). S1124). The message queue is a mechanism for exchanging information between processes. Then, after the processing of S1124, the sub CPU 201 returns the processing to S1121 and repeats the processing after S1121.

Although not shown, the sub CPU 101 takes out the message (that is, the information included in each parameter of the received command) in the message queue (that is, each of the received commands). Acquires the information contained in the parameters), and executes the processing (processing at the time of receiving various commands) according to the command type and the content of the command. For example, the processes of FIGS. 116 and 118 to 122 described later show an example of the command reception processing.

[Sub-side navigation control processing]
Next, the sub-side navigation control process will be described with reference to FIG. 116. Note that FIG. 116 is a flowchart showing the procedure of the sub-side navigation control process.

First, the sub CPU 201 determines whether or not the navigation data has been acquired (S1131). The sub CPU 201 acquires the navigation data determined by the main control board 71 from the start command data received from the main control board 71. Therefore, in the process of S1131, the sub CPU 201 determines whether or not the navigation data is included in the received start command data.

In the present embodiment, the determined navigation data is included in the start command data, but the mode of transmitting the navigation data is not limited to this. For example, the main CPU 101 generates and stores specific state command data including at least navigation data only in a specific state (for example, during ART) in which navigation data needs to be transmitted, and the sub CPU 201 generates and stores the specific state command data of the specific state command data. It may be determined whether or not the navigation data is included in the data.

In S1131, when the sub CPU 201 determines that the navigation data has been acquired (when the determination in S1131 is YES), the sub CPU 201 sets the sub-side navigation data according to the navigation data (S1132). For example, when the sub CPU 201 acquires the navigation data "4", the navigation data for notifying the push order "left, middle, right" is set as the sub side navigation data by this process. As a result, the content of the stop operation can be notified on both the main side and the sub side. Then, after the processing of S1132, the sub CPU 201 ends the sub-side navigation control processing.

On the other hand, in S1131, when it is determined that the sub CPU 201 has not acquired the navigation data (when the determination in S1101 is NO), the sub CPU 201 determines whether or not navigation (notification of stop operation) is necessary. (S1133). When the sub CPU 201 determines in S1133 that navigation is not necessary (NO in S1133), the sub CPU 201 ends the sub-side navigation control process.

On the other hand, in S1133, when the sub CPU 201 determines that navigation is necessary (when the determination in S1133 is YES), the sub CPU 201 sets the sub-side navigation data according to various lottery results (S1134). For example, when the sub CPU 201 is in the ART gaming state and an internal winning combination that is not a push order combination is determined, in order to enhance the effect, the sub CPU 201 independently provides effect data for notifying the content of the stop operation. Can be decided. Then, after the processing of S1134, the sub CPU 201 ends the sub-side navigation control processing.

[Player registration process]
Next, the player registration process will be described with reference to FIG. 117. Note that FIG. 117 is a flowchart showing the procedure of the player registration process.

First, the sub CPU 201 determines whether or not the registration operation has been accepted (S1141). For example, when the operation of the registration button 222b is accepted on the menu screen 222 (see FIG. 5B) of the sub display device 18, and the predetermined operation is accepted on the registration screen (not shown) displayed in that case, the sub CPU 201 performs the registration operation. Is determined to have been accepted.

When the sub CPU 201 determines in S1141 that the registration operation has been accepted (when the determination in S1141 is YES), the sub CPU 201 sets the player registration state (S1142). In the situation where the player registration state is set, the sub CPU 201 of the sub display device 18 can display the game information screens 223, 224, 225 (see FIGS. 5C to 5E) on the sub display device 18. Control the display screen. Then, after the process of S1142, the sub CPU 201 ends the player registration process.

On the other hand, in S1141, when it is determined that the sub CPU 201 has not accepted the registration operation (when the determination in S1141 is NO), the sub CPU 201 determines whether or not the registration deletion operation has been accepted (S1143). For example, when a specific operation is accepted on the registration screen of the sub display device 18, the sub CPU 201 determines that the registration deletion operation has been accepted.

When the sub CPU 201 determines in S1143 that the registration deletion operation is not accepted (NO in S1113), the sub CPU 201 ends the player registration process.

On the other hand, in S1143, when it is determined that the sub CPU 201 has accepted the registration deletion operation (when the determination in S1143 is YES), the sub CPU 201 clears the player registration state (S1144). In the situation where the player registration state is cleared, the sub CPU 201 makes it impossible to display the game information screens 223, 224, 225 (see FIGS. 5C to 5E) on the sub display device 18. Control the display screen of. Then, after the process of S1144, the sub CPU 201 ends the player registration process.

[History management process]
Next, the history management process will be described with reference to FIG. 118. Note that FIG. 118 is a flowchart showing the procedure of the history management process.

First, the sub CPU 201 acquires the game result from various command data received from the main control board 71 (S1151). For example, in this process, the sub CPU 201 can grasp the type of the winning combination determined as the internal winning combination from the start command data. Further, for example, in this process, the sub CPU 201 can grasp the symbol combination displayed from the winning operation command data (that is, the presence or absence of winning of the winning combination determined as the internal winning combination). Further, for example, in this process, the sub CPU 201 can grasp the current gaming state and the transition status of the gaming state from the start command data and the like.

Next, the sub CPU 201 performs a game history update process based on the acquired game result (S1152). By this process, the sub CPU 201 is based on the game results acquired from various command data, for example, the number of games (number of games), the number of bonuses, the number of ARTs, the number of CZs, the number of CZ successes, the number of promotion chances, and the special zone ( It is possible to manage various game histories such as the number of times (CP special zone and double special zone in BB), the number of wins for each role, and the probability of winning. Then, after the process of S1152, the sub CPU 201 ends the history management process.

[Direction decision processing]
Next, the effect determination process will be described with reference to FIG. 119. Note that FIG. 119 is a flowchart showing the procedure of the effect determination process. It should be noted that this effect determination process shows an example of the command reception process when the start command data transmitted from the main control board 71 is received.

First, the sub CPU 201 acquires information on each parameter from the received command and updates the game information (S1161). For example, the sub CPU 201 compares the information on the current gaming state with the information on the gaming state one game before, and if there is a change in the gaming state, stores the game information to that effect. Further, for example, the sub CPU 201 compares the information of the current mode with the information of the mode one game before, and if there is a change in the mode, stores the game information to that effect.

Next, the sub CPU 201 determines whether or not the current gaming state is in the promotion chance (S1162). In S1162, when the sub CPU 201 determines that the current gaming state is in the promotion chance (YES in S1162), the sub CPU 201 performs the effect determination process during the promotion chance (S1163). In this process, the sub CPU 201 performs a process of determining the content of the effect during the promotion chance. The details of the effect determination process during the promotion chance will be described later with reference to FIG. 120 described later. Then, after the process of S1163, the sub CPU 201 ends the effect determination process.

On the other hand, in S1162, when the sub CPU 201 determines that the current gaming state is not in the promotion chance (when the determination in S1162 is NO), the sub CPU 201 determines whether or not the current gaming state is in ART. (S1164). In S1164, when the sub CPU 201 determines that the current gaming state is in ART (when the determination in S1164 is YES), the sub CPU 201 is in the effect state during ART (various effect game states (zones), various internal states). Etc.) and the game information such as the internal winning combination, the production pattern during ART is determined (S1165). Then, after the processing of S1165, the processing of S1167 described later is performed.

On the other hand, in S1164, when the sub CPU 201 determines that the current gaming state is not in ART (when the determination in S1164 is NO), the sub CPU 201 is in a non-ART effect state (various effect game states (zones), various types). The normal production pattern is determined according to the game information such as the internal state) and the internal winning combination (S1166).

Next, the sub CPU 201 determines whether or not the determined effect pattern is an effect pattern for which special effects are prohibited (S1167). Here, since the special effect is executed when all the reels 3L, 3C, 3R are stopped, the predetermined effect pattern is such that all the reels 3L, 3C, 3R are stopped. When a specific effect is sometimes executed, the effect pattern is an effect pattern prohibiting the special effect in which the special effect and the effect timing compete with each other. That is, the sub CPU 201 determines in this process whether or not the determined effect pattern is such an effect pattern.

In S1167, when the sub CPU 201 determines that the determined effect pattern is an effect pattern for which special effects are prohibited (when the determination in S1167 is YES), the sub CPU 201 ends the effect determination process.

On the other hand, in S1167, when the sub CPU 201 determines that the determined effect pattern is not the effect pattern for which the special effect is prohibited (when the determination in S1167 is NO), the sub CPU 201 performs the special effect reservation process (S1168). In this process, the sub CPU 201 performs a process of determining whether or not to reserve the special effect according to the determination value for the special effect lottery. The details of the special effect reservation process will be described later with reference to FIG. 121 described later. Then, after the process of S1168, the sub CPU 201 ends the effect determination process.

[Direction decision processing during promotion chance]
Next, with reference to FIG. 120, the effect determination process during the promotion chance performed in S1163 of the effect determination process (see FIG. 119) will be described. Note that FIG. 120 is a flowchart showing the procedure of the effect determination process during the promotion chance.

First, the sub CPU 201 determines whether or not the continuation number counter is 0 (S1171). That is, the sub CPU 201 determines whether or not it is the first game in the promotion chance. In S1171, when the sub CPU 201 determines that the continuation number counter is not 0 (when the determination in S1171 is NO), the sub CPU 201 performs the process of S1175 described later.

On the other hand, in S1171, when the sub CPU 201 determines that the continuation number counter is 0 (when the determination in S1171 is YES), the sub CPU 201 determines whether or not the next game is successful in continuation (S1172). That is, the sub CPU 201 determines whether or not the result of the continuous lottery (or the continuous guarantee lottery) by the main CPU 101 is the winning.

In S1172, when the sub CPU 201 determines that the next game is not successful in continuation (when the determination in S1172 is NO), the sub CPU 201 determines an effect pattern for displaying (no resurrection pattern) according to the number of continuations (S1173). ). By this process, for example, after the start of the second game, it is notified that the promotion chance ends in the first game and the number of ART games is fixed at "111". Then, after the process of S1173, the sub CPU 201 ends the effect determination process during the promotion chance.

On the other hand, in S1172, when the sub CPU 201 determines that the next game is a success of continuation (when the determination of YES in S1172), the sub CPU 201 displays a display according to the number of continuations or a next continuous confirmation display (no resurrection pattern). The effect pattern to be performed is determined (S1174). By this processing, for example, in the case of displaying according to the number of continuations, it is notified that the promotion chance continues after the start of the second game, and the number of ART games has been added up to "222". Further, for example, when the next continuous confirmation display (no revival pattern) is performed (that is, when the continuation is successful up to the third game), the promotion chance continues after the start of the second game, and the number of ART games Is notified that the number has been added up to "222", and at the end of the second game, the number of ART games exceeds "222" (for example, "223"), so that the third game is also displayed. You will be informed that your promotion chances will continue. Then, after the process of S1174, the sub CPU 201 ends the effect determination process during the promotion chance.

In S1171 described above, when the sub CPU 201 determines that the continuation number counter is not 0 (when the determination in S1171 is NO), the sub CPU 201 determines whether or not the game is continuous success (S1175). In S1175, when the sub CPU 201 determines that the game is not successful in continuation (when the determination in S1175 is NO), the sub CPU 201 determines an effect pattern for displaying the number of acquired ART games (S1176). By this process, for example, at the end of the game (or after the start of the next game), it is notified that the promotion chance ends in the game and the number of ART games is determined by the number of games corresponding to the game. .. Then, after the process of S1176, the sub CPU 201 ends the effect determination process during the promotion chance.

On the other hand, in S1175, when the sub CPU 201 determines that the game is continuous success (when the determination in S1175 is YES), the sub CPU 201 determines whether or not the next game is continuous success (S1177). In S1177, when the sub CPU 201 determines that the next game is not successful in continuation (when the determination in S1177 is NO), the sub CPU 201 determines an effect pattern for displaying (with a resurrection pattern) according to the number of continuations (S1178). ). By this processing, for example, after the start of the next game, the promotion chance continues, and it is notified that the number of ART games has been added to the number of games corresponding to the next game. Further, for example, at the end of the game (or after the start of the next game), after it is once notified that the promotion chance ends in the game and the number of ART games is determined by the number of games corresponding to the game. , The revival effect is performed, and after the start of the next game, the promotion chance continues, and it is notified that the number of ART games has been added to the number of games corresponding to the next game. This notification mode corresponds to the resurrection pattern. Then, after the process of S1178, the sub CPU 201 ends the effect determination process during the promotion chance.

On the other hand, in S1177, when the sub CPU 201 determines that the next game is a success of continuation (when the determination of YES in S1177), the sub CPU 201 is whether or not the continuation confirmation display (next continuation confirmation display) is performed in the previous game. (S1179). In S1179, when the sub CPU 201 determines that the continuation confirmation display (next continuation confirmation display) has not been performed in the previous game (when the determination in S1179 is NO), the sub CPU 201 displays according to the number of continuations, or the next time. The effect pattern for performing the continuous confirmation display (with the resurrection pattern) is determined (S1180). Then, after the process of S1180, the sub CPU 201 ends the effect determination process during the promotion chance.

On the other hand, in S1179, when the sub CPU 201 determines that the continuation confirmation display (next continuation confirmation display) has been performed in the previous game (when the determination in S1179 is YES), the sub CPU 201 displays according to the number of continuations, or the next time. A production pattern for performing continuous confirmation display (no revival pattern) is determined (S1181). Then, after the process of S1181, the sub CPU 201 ends the effect determination process during the promotion chance.

That is, when the continuation confirmation display (next continuation confirmation display) is performed in the previous game, the sub CPU 201 selects the effect pattern so that the resurrection pattern cannot be selected in the game, and the continuation confirmation is performed in the previous game. If the display (next continuous confirmation display) is not performed, the effect pattern is selected so that the resurrection pattern can be selected in the game. As a result, it is possible to match the effect contents of the effect to be executed.

[Special production reservation processing]
Next, with reference to FIG. 121, the special effect reservation process performed in S1168 of the effect determination process (see FIG. 119) will be described. Note that FIG. 121 is a flowchart showing the procedure of the special effect reservation process.

First, the sub CPU 201 determines whether or not a mode transition has occurred in the game (S1191). In S1191, when the sub CPU 201 determines that the mode transition has occurred in the game (when the determination in S1191 is YES), the sub CPU 201 clears the special effect reservation parameter to 0 (S1192). That is, when the execution of the special effect is reserved, the sub CPU 201 performs a process of temporarily canceling the reserved special effect if a mode shift occurs before the special effect is executed.

After the processing of S1192 and in S1191, when the sub CPU 201 determines that the mode transition has not occurred in the game (when the determination in S1191 is NO), the sub CPU 201 has a special effect reservation parameter of "1" or more. It is determined whether or not there is (S1193). That is, the sub CPU 201 determines whether or not the execution of the special effect is reserved. In S1193, when the sub CPU 201 determines that the special effect reservation parameter is "1" or more (when the determination in S1193 is YES), the sub CPU 201 performs the process of S1196 described later.

On the other hand, in S1193, when the sub CPU 201 determines that the special effect reservation parameter is not "1" or more (when the determination in S1193 is NO), the sub CPU 201 sets the determination value for the special effect lottery (see FIG. 34). Then, a reservation lottery for the special effect is performed based on the determination value and the internal winning combination, and the lottery result is set as the special effect reservation parameter (S1194). For example, the sub CPU 201 determines the special effect reservation parameter in the normal time based on the normal time special effect reservation lottery table (see FIG. 35).

Next, the sub CPU 201 determines whether or not the special effect reservation parameter is "1" or more (S1195). In S1195, when the sub CPU 201 determines that the special effect reservation parameter is not "1" or more (when the determination in S1195 is NO), the sub CPU 201 ends the special effect reservation process.

On the other hand, in S1195, when the sub CPU 201 determines that the special effect reservation parameter is "1" or more (when the determination in S1195 is YES), and in S1193 described above, the sub CPU 201 determines that the special effect reservation parameter is "1". (When it is determined that S1193 is YES), the sub CPU 201 determines whether or not the "normal lip" has been won (S1196). The "normal lip" here does not mean only "F_normal lip", but includes a replay combination (for example, RT1 lip, RT2 lip, and RT3 lip) that can be normally established in a non-ART gaming state. Means. Alternatively, it means that it is a replay combination (see FIGS. 19 to 21) in which a combination of symbols of "S_TL lip" can be derived in a non-ART gaming state.

In S1196, when the sub CPU 201 determines that the "normal lip" has not been won (when the determination in S1196 is NO), the sub CPU 201 ends the special effect reservation process.

On the other hand, in S1196, when the sub CPU 201 determines that the "normal lip" has been won (when the determination in S1196 is YES), the sub CPU 201 turns on the special effect execution flag (S1197) and ends the special effect reservation process. To do. In S1196, when the sub CPU 201 determines that the "normal lip" has been won (when the determination in S1196 is YES), the sub CPU 201 further determines whether the determined effect pattern is an effect pattern for which special effects are prohibited. When it is determined whether or not the effect pattern is the effect pattern for which the special effect is prohibited, the special effect execution flag may not be turned on.

[Special production execution process]
Next, the special effect execution process will be described with reference to FIG. 121. Note that FIG. 121 is a flowchart showing the procedure of the special effect execution process. It should be noted that this special effect execution process shows an example of a command reception process when the winning operation command data transmitted from the main control board 71 is received.

First, the sub CPU 201 determines whether or not the special effect execution flag is on (S1201). When the sub CPU 201 determines in S1201 that the special effect execution flag is not on (when the determination in S1201 is NO), the sub CPU 201 ends the special effect execution process.

On the other hand, in S1201, when the sub CPU 201 determines that the special effect execution flag is ON (when the determination in S1201 is YES), the sub CPU 201 executes a special effect according to the value of the special effect reservation parameter (S1202). ).

Next, the sub CPU 201 turns off the special effect execution flag (S1203), clears the special effect reservation parameter to 0 (S1204), and ends the special effect execution process.

As described above, the pachi-slot machine 1 of the present embodiment has a plurality of specific internal states (for example, normal mode), and when there is a change in the specific internal state, a predetermined effect (for example, special effect) is executed. It is configured so that a predetermined effect is executed when a predetermined execution condition is satisfied after the reservation is made.

For example, when there are a plurality of lottery states having different transition probabilities to an advantageous state (for example, during ART) as a plurality of specific internal states, the lottery state becomes an advantageous lottery state, or an advantageous state. If there is a precursory state in which the transition of is awaited, it is reserved to execute a predetermined effect when the precursory state is reached.

Then, when a predetermined display result (for example, a combination of symbols of "S_TL lip") is derived (that is, a predetermined internal winning combination (for example, "normal lip") is established), a predetermined effect is executed. It is configured to be. That is, every time a predetermined display result is derived, the player can expect whether or not the predetermined effect is executed, and the unit game in which the specific internal state is changed and the predetermined effect are executed. It is configured so that it can be different from the unit game to be played. Therefore, when there are a plurality of specific internal states, the suggestions of the specific internal states can be varied.

[Example of production display during promotion chance]
Next, an example of the effect display during the promotion chance will be described with reference to FIGS. 123 to 125. FIG. 123 is a diagram showing a display example of pattern 1 as an example of the effect display during the promotion chance, and FIG. 124 is a diagram showing a display example of pattern 2 as an example of the effect display during the promotion chance. FIG. 125 is a diagram showing a display example of pattern 3 as an example of the effect display during the promotion chance.

(Pattern 1)
FIG. 123 shows an example of the effect display in the pattern (pattern 1) in which the promotion chance ends in the first game (first game).

First, when the promotion chance start lock effect or the promotion chance expectation lock effect (success) is being executed, the sub CPU 201 displays that the promotion chance has been started and displays 50 games of the initial ART games (1G). Locked at the start of the eyes).

Next, in the sub CPU 201, the promotion chance start lock effect or the promotion chance expectation lock effect (success) ends, the first game (first game) starts, and the first game (first game) ends. It is displayed that the number of ART games has been added to 111 games at an arbitrary timing until the game is played (start of 1G to stop of 1G).

Next, in the sub CPU 201, the second game (second game) starts, the promotion chance ends at any timing after the start of the second game (second game), and the number of ART games is 111 games. Display the confirmation (from the start of the 2G to the start of the 2G). It should be noted that it may be at the end of the first game (first game) that the promotion chance ends and the fact that the number of ART games is confirmed in 111 games is displayed.

As described above, in the pattern 1, the display (without the resurrection pattern) according to the number of continuations is performed (see FIG. 120).

(Pattern 2)
FIG. 124 shows an example of the effect display in the pattern (pattern 2) in which the promotion chance ends in the third game (third game).

First, when the promotion chance start lock effect or the promotion chance expectation lock effect (success) is being executed, the sub CPU 201 displays that the promotion chance has been started and displays 50 games of the initial ART games (1G). Locked at the start of the eyes). Since this display is the same as that in FIG. 123, the illustration is omitted in FIG. 124.

Next, in the sub CPU 201, the promotion chance start lock effect or the promotion chance expectation lock effect (success) ends, the first game (first game) starts, and the first game (first game) ends. It is displayed that the number of ART games has been added to 111 games at an arbitrary timing until the game is played (start of 1G to stop of 1G).

At this time, in pattern 2, it is determined that the promotion chance continues until the third game (third game).

Next, the sub CPU 201 indicates that the number of ART games has been added to the 223 games at an arbitrary timing from the start of the second game (second game) to the end of the second game (second game). Is displayed (2G start to 2G stop). Here, in the present embodiment, the number of ART games is increased to 223 games because the number of ART games is added with a certain rule of 111 games, 222 games, 333 games, and so on in the promotion chance. The display to the effect that it has been added is an irregular display.

This anomalous display informs that the promotion chance continues until the third game (third game). That is, by displaying the number of ART games "223" that exceeds the number of ART games "222" that is originally added, the number of ART games that are added exceeds "222" (that is, the promotion chance is the third time). (Third game) is continued until the game (third game) is continued, and at least the number of ART games "333" can be obtained). In this pattern 2, as an example of the above-mentioned irregular display, "223" exceeding the number of ART games "222" is displayed, but the present invention is not limited to this, and for example, "223" to "332". Any value can be displayed within the range of. That is, in the case of performing the above-mentioned irregular display, the number of ART games that can be added when the promotion chance continues until the second game (second game) is exceeded, and the promotion chance is the third game (third game). Any value can be displayed as long as it is less than the number of ART games that can be added when continuing up to). Further, this value may be determined by lottery.

At this time, if it is determined in pattern 2 that the promotion chance continues until the fourth game (fourth game), the promotion chance continues until the fourth game (fourth game). A relatively large value may be displayed as compared to the case where it has not been decided to do so. Alternatively, a relatively large value may be easily determined by lottery.

Next, the sub CPU 201 indicates that the number of ART games has been added to the 333 games at an arbitrary timing from the start of the third game (third game) to the end of the third game (third game). Is displayed (3G start to 3G stop).

Next, in the sub CPU 201, the fourth game (fourth game) starts, the promotion chance ends at any timing after the start of the fourth game (fourth game), and the number of ART games is 333 games. Display that it has been confirmed (from the start of the 4th G to after the start of the 4G). It should be noted that the promotion chance ends and the fact that the number of ART games has been confirmed in 333 games may be displayed at the end of the third game (third game).

In this way, in pattern 2, the display according to the number of continuations (without the resurrection pattern) is performed (in this case, the display according to the number of continuations (with the resurrection pattern) may be performed), and then the next time. The continuation confirmation display is performed, then the display according to the number of continuations (no revival pattern) is performed, and then the number of acquired ART games is displayed (see FIG. 120).

(Pattern 3)
FIG. 125 shows an example of the effect display in the pattern (pattern 3) in which the promotion chance ends in the second game (second game).

First, when the promotion chance start lock effect or the promotion chance expectation lock effect (success) is being executed, the sub CPU 201 displays that the promotion chance has been started and displays 50 games of the initial ART games (1G). Locked at the start of the eyes). Since this display is the same as that in FIG. 123, the illustration is omitted in FIG. 125.

Next, in the sub CPU 201, the promotion chance start lock effect or the promotion chance expectation lock effect (success) ends, the first game (first game) starts, and the first game (first game) ends. It is displayed that the number of ART games has been added to 111 games at an arbitrary timing until the game is played (start of 1G to stop of 1G).

Next, in the sub CPU 201, the second game (second game) starts, the promotion chance ends at any timing after the start of the second game (second game), and the number of ART games is 111 games. The confirmation is displayed once (from the start of the 2G to the start of the 2G). However, at any time until the end of the second game (second game) (for example, when the second game is completely stopped), the promotion chance actually continues, and the number of ART games is added to 222 games. Is displayed (when the 2nd G is completely stopped to the 2nd G is completely stopped).

Next, in the sub CPU 201, the third game (third game) starts, the promotion chance ends at any timing after the third game (third game) starts, and the number of ART games is 222 games. Display that it has been confirmed (from the start of the 3G to the start of the 3G).

In this way, in pattern 3, display according to the number of continuations (without a resurrection pattern) is performed (in this case, display according to the number of continuations (with a resurrection pattern) may be performed), and then continuation. The display according to the number of times (with a resurrection pattern) is performed, and then the number of acquired ART games is displayed (see FIG. 120).

As described above, the pachislot machine 1 of the present embodiment has a specific state (for example, promotion chance) in which the gaming period in the advantageous state (for example, during ART) is extended, and in this specific state, each time the game continues. It is configured to extend the playing period in an advantageous state. In addition, it is configured so that it can be determined in advance whether or not to continue a plurality of consecutive games in a specific state. Therefore, it is possible to make the game playability related to the continuation of the advantageous state various, and it is possible to improve the interest of the game.

Further, in the pachi-slot machine 1 of the present embodiment, in the current game in the specific state, the game in the specific state is continued until the next game, and the game in the specific state is continued until the next game. It is configured so that the effect to be executed in the next game can be different depending on the case where is determined.

For example, if it is not decided to continue the game in the specific state until the next game, in the next game, as the first effect, the advantage extended based on the continuation of the specific state until the game. If it is decided to continue the game in the specific state until the next game while notifying the game period of the state, in the next game, as the second effect, the specific state continues until the game. It is configured to notify the game period exceeding the game period in the advantageous state to be extended based on.

With such a configuration, it is possible to definitively notify that the specific state continues, that is, the gaming period in the advantageous state is further extended, and it is possible to further improve the interest of the game. In addition, while specifically notifying the game period of the advantageous state to be added, it is notified that the specific state will continue due to the contradiction of the mode, so that the interest of the game can be further improved.

[Numerical fluctuation display control]
Next, with reference to FIG. 126, the numerical fluctuation display control in the pachi-slot machine 1 of the present embodiment will be described. FIG. 126A shows an example of the specified time in the numerical fluctuation display, and FIG. 126B shows an example of the numerical fluctuation display control when the number of ART games is added in the ART gaming state. FIG. 126C is shown. Is an example of numerical fluctuation display control when the pachi-slot machine 1 is disconnected due to a power failure and then the power is restored and the pachi-slot machine 1 returns to the state before the power failure in the ART game state.

In the pachi-slot machine 1 of the present embodiment, when various numerical values displayed on the display device 11 (and / or the sub-display device 18) are changed during the game, the values before the change are sequentially changed within a specified time range, and finally. It is possible to execute a numerical fluctuation display (for example, a count-up display or a count-down display) that displays the numerical value after the fluctuation.

Then, as shown in FIG. 126A, the specified time for which the numerical fluctuation display is performed is specified according to the corresponding item (numerical value subject to fluctuation).

For example, when ART stock is added in the special zone (CP special zone in BB, double special zone) (the number of ART stocks in the special zone), the specified time is not specified, so the numerical value fluctuation is displayed. Is not performed, and the numerical display of the number of ART stocks is promptly switched to the numerical display after the change.

Also, for example, when CP is added (subtracted) (CP counter), when CP is added in the special zone (CP special zone in BB, double special zone) (the number of CP acquired in the special zone). ) Specifies a specified time "200 ms", and the numerical display is sequentially counted up (or counted down) within the specified time range, and then switched to the changed numerical display. ..

Further, for example, when the number of ART games is added (subtracted) (the number of ART remaining games), the number of remaining games (guaranteed games) in the double specialized zone in the specialized zone (double specialized zone) is added (subtracted). In the case of (the number of remaining games in the special zone), the specified time "500 ms" is specified, and the numerical display is sequentially counted up (or counted down) within the specified time range, and then fluctuates. It is designed to switch to the numerical display later. In the "number of remaining ART games", when the normal ART starts (that is, at the start of one set), the initial number of ART games (or the number of ART games given in the continuous challenge) is displayed numerically. Includes cases to do. In addition, the "number of remaining games in the special zone" includes a case where the number of guaranteed games is displayed numerically when the double special zone starts.

Further, for example, when the number of transitions from the non-ART gaming state to the ART gaming state is added (the number of first hits of ART) and the number of transitions to the normal ART is added (the number of ARTs), the specified time "1000 ms". Is specified, and the numerical display is sequentially counted up (or counted down) within the specified time range, and then switched to the numerical display after the fluctuation.

Here, as shown in FIG. 126B, when the current number of ART games is "40" and "remaining 40 games" is displayed in the ART game state, the number of ART games "10" is added. If this is the case, control is performed to sequentially change the numerical display of "40 games remaining" within the specified time "500 ms", and then display the number of ART games "50" after the change. Display the "50 games remaining".

On the other hand, as shown in FIG. 126C, in the ART gaming state, when the pachislot machine 1 is disconnected due to a power failure and then the power is restored and the pachislot machine 1 returns to the state before the power failure, "0 games remaining" is displayed as an initial display. After that, when the recovery process is completed, the "remaining 50 games" that display the current number of ART games "50" are displayed promptly. That is, in this case, control is not performed so that the numerical display displaying "remaining 0 games" is sequentially changed and displayed as "remaining 50 games".

In this case, the trigger for switching the initial display "0 games remaining" to "50 games remaining" may be, for example, a specific command (for example, the game return command described above) transmitted from the main control circuit 90. ..

Further, the initial display "0 games remaining" may not be displayed until the recovery process is completed or the above-mentioned specific command is transmitted from the main control circuit 90.

Further, the value (initial value) displayed in the initial display is not limited to "0" and can be any value. For example, the initial ART game number of "50" may be displayed, or a value (for example, "9999") that the player can clearly recognize as the initial display may be displayed.

It should be noted that the corresponding item (numerical value subject to fluctuation) in FIG. 126A is merely an example, and the specified time is also specified for the other applicable item (numerical value subject to fluctuation), and the numerical fluctuation display control is performed. It may be done.

For example, even when the cumulative number of medals acquired in the ART game state (the number of medals acquired during ART) is added (subtracted), a predetermined specified time may be specified and numerical fluctuation display control may be performed. .. In this case, different specified times may be set according to the number of medals paid out (that is, depending on the display combination).

Further, the “number of medals won during ART” may be controlled to change numerically even when the replay combination is established. Here, the replay combination does not pay out medals (see FIG. 18), but in reality, it has an equivalent relationship to the case where, for example, three medals are paid out. Therefore, when the replay combination is established, a numerical variation display is performed in which three "number of medals acquired during ART" are added at the end of the game, and at the start of the next game (for example, at the start operation), "acquisition of medals during ART" is performed. A numerical variation display in which the "number" is subtracted by 3 may be performed.

On the other hand, when the replay combination is established, the "number of medals won during ART" is not changed at the end of the game, and the "number of medals won during ART" is also set at the start of the next game (for example, at the start operation). It can also be kept unchanged.

In the present embodiment, any of these methods can be adopted. Further, in the present embodiment, for the normal replay combination (for example, RT3 rip) in the ART game state, the numerical fluctuation display of the "number of medals won during ART" is not displayed, and a specific replay combination (for example, "RT3 lip") is not displayed. For (F_SP Lip A) to "F_SP Lip C", etc.), it is possible not to display the numerical fluctuation of "the number of medals won during ART".

Regarding the "number of medals won during ART", when the method of displaying numerical fluctuations is adopted when the replay combination is established, the normal "medals during ART" is the same as in the case of "number of remaining ART games". If it is the display fluctuation timing of "Number of medals won", the numerical fluctuation display is performed, and if it is the display fluctuation timing of "Number of medals won during ART" at the time of recovery from power failure, the numerical fluctuation display is not performed. Can be configured in.

As described above, in the pachislot machine 1 of the present embodiment, when a predetermined numerical value (for example, the value of the ART game number counter) fluctuates, the predetermined numerical value is usually displayed before the fluctuating predetermined numerical value is displayed. It is configured so that the effect is enhanced by displaying the fluctuation over a predetermined period, but when the game machine returns to the state before the power failure after the power failure occurs, the fluctuation display is not performed. , It is configured to display a predetermined (ie, current) numerical value after the change.

For example, when a predetermined numerical value corresponds to the remaining gaming period of a specific gaming state (for example, during ART), and the remaining gaming period fluctuates, usually, the remaining gaming period is set to the predetermined period (for example, during ART). For example, after the fluctuation is displayed for 500 ms), the remaining game period after the fluctuation is displayed, but when the game machine returns to the state before the power failure after the power failure occurs, the fluctuation display is performed. Instead, it is configured to display the remaining (ie, current) playing period after the change.

That is, when the power is restored, the control for returning to the gameable state is prioritized over the control for enhancing the effect of the effect. Therefore, when the power is restored, the production content can be appropriately restored.

Further, in the pachi-slot machine 1 of the present embodiment, the control circuit (display control means) side that controls the effect in conjunction with returning to the game-enabled state on the control circuit (game control means) side that controls the progress of the game. However, it is configured so that it can be returned to a playable state. At that time, the display of the predetermined numerical value is configured to switch from the initial value to the current numerical value. Therefore, with a simple configuration, it is possible to notify that the game machine returns to the playable state, and it is possible to more appropriately restore the effect content when the power failure is restored.

Up to this point, the gaming machine according to the present embodiment has been described. Then, from the present embodiment, as an example, at least the following technical ideas (that is, the invention according to the present embodiment) can be grasped. However, these technical ideas are not limited to those described in the present embodiment, and various modifications and modifications can be made. Further, a plurality of technical ideas (including a part thereof, that is, including a part of the configuration of the invention according to the present embodiment) can be combined into another technical idea, or a certain technical idea can be obtained. A part of the idea can be used as another technical idea. Further, in a certain technical idea, a technical idea described subordinately can be an independent technical idea, or can be subordinated in another technical idea.

In the present embodiment, a pachi-slot machine is described as an example of a gaming machine, but this is not intended to limit the invention according to the present embodiment. For example, all the inventions according to the present embodiment have a configuration peculiar to pachislot such as a configuration related to reel control when a stop operation is performed and a configuration related to setting change and confirmation described in the present embodiment. It can also be applied to a game machine called "pachinko". For example, checksum generation and determination processing, various processing using the main CPU 101 dedicated instruction code (address specification processing using the Q register, soft timer update processing, 7-segment LED drive processing, communication data generation and storage processing, etc. ), Various processes using the non-standard ROM area and the non-standard RAM area are also suitable for pachinko.

That is, the invention according to the present embodiment performs an internal lottery (determination of hit or not) based on the fact that a predetermined fluctuation start condition is satisfied (for example, the game ball has passed through the starting region). Variable display is started (identification information is variablely displayed), and variable display is stopped (identification information is stopped and displayed) based on the fact that a predetermined variable end condition is satisfied (for example, the variable time has ended). , Pachinko capable of shifting to a special gaming state (hit gaming state) based on the derivation of a predetermined display result, pachinko provided with a game control means for controlling the progress of these games, and an effect display. The effect display means for controlling the effect display means and the effect display control means for controlling the effect display means are provided, and the effect display means is provided with variable display and stop display of the decorative pattern according to the variable display, and other effect display is performed. It can be applied to pachinko.

Similarly, a slot machine that uses a game ball as a game medium, an enclosed game machine that encloses the game medium and electronically adds game value, and a management frame that can be used and managed by a plurality of manufacturers are used. , It can be applied to other game machines such as a game machine called a management type game machine which can mount a game board in the management frame.

Further, for example, the various counters and various timers managed by the control of the main CPU 101 or the sub CPU 201 shown in the present embodiment have their management modes as long as they do not deviate from the gist of the invention according to the present embodiment. It can be changed as appropriate. For example, various counters and various timers managed by "addition" may be managed by "subtraction", and various counters and various timers managed by "subtraction" may be managed by "addition". It may be managed by. In this case, for example, the determination of whether or not it is "more than or equal to" should be read as the determination of whether or not it is "less than or equal to", and the determination of whether or not it is "more than" is "less than or equal to". The determination of whether or not the value has reached a predetermined value shall be read as the determination of whether or not the value has reached "0".

Further, for example, various data such as various counters, various flags, and various timers shown under the control of the main CPU 101 shown in the present embodiment do not deviate from the gist of the invention according to the present embodiment. , The various data managed by the control of the sub CPU 201 may be managed by the control of the sub CPU 201, and various data managed by the control of the sub CPU 201 shall be managed by the control of the main CPU 101 within a range not deviating from the gist of the invention according to the present embodiment. May be.

Further, for example, the internal control states such as various gaming states managed by the control of the main CPU 101 and various production gaming states shown in the present embodiment do not deviate from the gist of the invention according to the present embodiment. In the above, the states related to various effects managed by the control of the sub CPU 201 may be managed by the control of the main CPU 101 within the range not deviating from the gist of the invention according to the present embodiment. It may be done.

[Rock production during MB]
In the pachislot machine 1 of the present embodiment, in a gaming state different from the special gaming state (for example, MB gaming state), a specific combination (for example, "F_black BAR") that triggers the operation of the advantageous state (for example, during ART) The winning probability and the execution probability of a specific lock effect that triggers the operation of the advantageous state in the special gaming state are configured to be the same probability (for example, 8/65536). That is, regardless of which gaming state the gaming state is, the activation trigger of the advantageous state can be obtained with a certain probability. Therefore, it is possible to improve the interest of the game.

Further, in the pachi-slot machine 1 of the present embodiment, when a specific lock effect is executed in a special gaming state (for example, MB gaming state), a combination of symbols related to a specific combination (for example, "C_black BAR") The combination of symbols) is configured to temporarily stop. That is, if the combination of symbols related to the specific combination is displayed regardless of which game state the game state is, the player can be made aware that the operation trigger of the advantageous state has been established. ing. Therefore, for example, in the special game state, even if there are restrictions on the determination of the internal winning combination and the stop control of the reel, the player can easily feel that the operation trigger of the advantageous state has been established. , Further, the interest of the game can be improved.

In addition, in this embodiment, the privilege given when a specific combination is won and when a specific lock effect is executed is explained as a trigger for operation in an advantageous state. The benefits granted are not limited to other benefits. For example, a specific right (for example, CP) may be granted, or a player's mobile terminal that enables the display device 11 and / or the sub-display device 18 to obtain a privilege image (or another privilege). A two-dimensional code that can be read by) may be displayed.

Further, in the present embodiment, it is assumed that a specific lock effect can be executed only in a special gaming state (for example, MB gaming state), but the present invention is not limited to this, and for example, it is also specified in the following cases. It may be possible that the lock effect of is executed.

For example, if at least one of the plurality of reels is provided with another special gaming state (for example, a CB gaming state) in which the maximum number of sliding pieces is reduced from four symbols to one symbol, the other Similarly, in the special gaming state of the above, a specific lock effect may be executed.

Further, for example, for all of a plurality of reels, the maximum number of sliding pieces is four symbols, but when a specific winning combination is won, it becomes a specific winning combination in relation to another internal winning combination (for example, BB). Similarly, a specific lock effect may be executed even in a gaming state (for example, the RT4 state in the present embodiment; see FIG. 20) in which the combination of the symbols cannot be displayed or is difficult to be displayed. In this case, the specific lock effect is executed when a specific combination (for example, "F_black BAR") is won without drawing a lot for whether or not the specific lock effect is executed. You can also do it.

Further, for example, when a specific combination is configured as a replay combination, the specific lock effect cannot be executed in a gaming state (for example, RT1 state to RT3 state) in which the specific combination as the replay combination can be won. In a gaming state (for example, RT0 state and RT4 state) in which a specific combination cannot be won, a specific lock effect may be executed.

Further, for example, when a specific combination is configured as a bonus combination, a specific lock effect cannot be executed in a gaming state (for example, RT0 state to RT3 state) in which the specific combination as the bonus combination can be won. In a gaming state (for example, RT4 state) in which a specific combination cannot be won, a specific lock effect may be executed.

Further, for example, if a specific winning combination can be won with a predetermined number of inserted medals (for example, 3), but cannot be won with a specific number of inserted medals (for example, 2), a predetermined number of medals are inserted. In the game, a specific lock effect may not be executed, and in a game in which a specific number of inserted medals are inserted, a specific lock effect may be executed.

Further, for example, it is easy to display a combination of symbols related to a specific combination with a predetermined number of inserted sheets (for example, 3 sheets), but it is difficult to display with a specific number of inserted sheets (for example, 2 sheets). In some cases, a specific lock effect cannot be executed in a game in which a predetermined number of inserted medals are inserted, and a specific lock effect can be executed in a game in which a specific number of inserted medals are inserted. It may be.

That is, according to this technical idea, a specific lock effect can be executed in a unit game (or game state) in which a specific combination can be won or a combination of symbols related to the specific combination can be displayed (or easily displayed). On the other hand, in a unit game (or game state) in which a specific role cannot be won or a combination of symbols related to the specific role cannot be displayed (or is difficult to display), a specific lock effect can be executed. By doing so, it includes all forms in which the unfair feeling related to the granting of benefits can be eliminated between the gaming states. That is, it can be applied to all cases where a predetermined privilege is not (or is difficult to be) granted due to a lottery constraint or a stop control constraint.

[Continued Challenge]
In the pachi-slot machine 1 of the present embodiment, the advantageous state (for example, during ART) is configured to include the first advantageous state (for example, normal ART) and the second advantageous state (for example, continuous challenge). In the second advantageous state, it is possible to grant a plurality of specific rights (for example, CP) for performing an additional lottery (determination of whether or not to extend the game period) for the number of games in the first advantageous state. ing.

In addition, when a specific right is granted when the first advantageous state ends, the process shifts to the second advantageous state, and in the second advantageous state, the specific right is consumed to obtain the first advantageous state. When an additional lottery for the number of games (decision on whether to extend the game period) is performed and the additional lottery is won (when it is decided to extend the game period), the first advantageous state is continued. It is configured to be able to.

Then, when a plurality of specific rights are acquired, the specific rights are not wasted, and all of them are added to the number of games in the first advantageous state (decision as to whether or not to extend the game period). ) Is configured to be used. Therefore, in the second advantageous state, not only is it decided whether or not to continue the advantageous state, but also it is possible to create the possibility that a large number of games are added at one time. The sex can be varied and the interest of the game can be improved.

In the present embodiment, the second advantageous state is also an advantageous state (ART gaming state), and information on the stop operation advantageous to the player can be notified. Therefore, the specific right has a substantially advantageous state. It also acts as an extension. That is, since the second advantageous state continues until all the specific rights are consumed, it is possible to extend the second advantageous state itself as the number of the specific rights acquired increases. Therefore, it is possible to make the game playability related to the continuation of the advantageous state various.

Further, in the present embodiment, in the second advantageous state, it is assumed that a predetermined effect for the specific number of acquired rights is performed, and the display result in the game in which the predetermined effect is performed (as a premise thereof). Whether or not the game period of the first advantageous state is extended is determined based on the internal lottery result) (see FIG. 71), but whether or not the game period of the first advantageous state is extended. Is not limited to this.

For example, the specific number of rights acquired is set to be the game period in the second advantageous state (that is, the number of continuous games), and in the second advantageous state, the number of the specific rights acquired is the internal winning combination (that is, the number of continuous games). And / or based on the display result), it may be determined (lottery) whether or not the game period of the first advantageous state is extended. Further, regardless of the internal winning combination (and / or the display result), it may be determined (lottery) whether or not the gaming period in the first advantageous state is extended with a certain probability. In this case, if the game period in the first advantageous state is not extended even after a predetermined number of lottery, relief measures are provided such as increasing the probability that the game period in the first advantageous state will be extended. You may do so.

Further, for example, in the second advantageous state, information on at least a part of the stop operation is not notified, and when the internal winning combination is the push order combination, the stop operation is performed in the push order that is advantageous to the player. When performed, if the internal winning combination is not the pushing order, the game period in the first advantageous state is extended when the stop operation is performed in the pushing order that matches the pushing order determined by the lottery. May be determined. Alternatively, when a specific internal winning combination is determined, which allows the display of any of a plurality of specific symbols arbitrarily arranged so that they cannot be aimed at the same time on the symbol arrangement of a specific reel. When the stop operation is performed at the timing when the symbol can be displayed (that is, when this specific internal winning combination can be established), it is determined that the game period in the first advantageous state is extended. It may be done.

Further, for example, it may be determined (lottery) whether or not the gaming period in the first advantageous state is extended by consuming the acquired specific rights at a time. In this case, the greater the number of specific rights acquired, the higher the probability of deciding that the playing period in the first advantageous state will be extended. Further, in this case, the second advantageous state may not be defined as the gaming state, and such a lottery may be performed when the first advantageous state ends.

Further, for example, when the specific number of rights acquired is a predetermined number (for example, 10) or more, it may be decided to extend the game period in the first advantageous state without fail. .. In this case, the specific number of rights acquired may be all consumed, or the specific number of rights to be consumed by lottery may be determined.

Further, in the present embodiment, basically, when the first advantageous state ends, the transition to the second advantageous state is performed, but the transition timing (transition opportunity) of the second advantageous state is not limited to this. ..

For example, in the first advantageous state (or another advantageous state), the transition to the second advantageous state may be performed based on the establishment of a predetermined transition opportunity. This predetermined transition opportunity corresponds to, for example, the second advantageous state when the first advantageous state (or another advantageous state) and the second advantageous state are configured to play games in different RT states. It may be assumed that the state has shifted to the RT state. The transition to the RT state corresponding to the second advantageous state is performed when the predetermined push order combination is won, the stop operation is performed in an appropriate push order, and the predetermined combination of symbols is displayed. In the case, in the first advantageous state (or other advantageous state), whether to notify the information of the stop operation for displaying the combination of the predetermined symbols (that is, to shift to the second advantageous state) by lottery. It may be decided.

Further, for example, the predetermined transition trigger may be a lottery for shifting to the second advantageous state simply in the first advantageous state (or another advantageous state), and the lottery may be won. In this case, when it is decided to shift to the second advantageous state, the transition to the second advantageous state may be performed immediately, or the transition to the second advantageous state may be made via a predetermined precursor state. You may. Further, this predetermined precursor state may be up to the winning of the above-mentioned predetermined push order combination.

Further, for example, in the advantageous state, the specific number of rights acquired is not clearly shown to the player, and when the first advantageous state ends, the fact that the advantageous state has ended is displayed, and the game is once in the normal gaming state. After displaying, if a specific right has been acquired in the advantageous state, the second game is via a specific precursor state (or from the next game in which the first advantageous state is displayed). The transition to an advantageous state may be made. Further, the actual gaming state may be changed and controlled in the order of the first advantageous state (“normal ART”), the normal gaming state (“normal time”), and the second advantageous state (“continuation challenge”). In addition, this specific precursor state may be up to the winning of the above-mentioned predetermined push order combination. In this case, even after the advantageous state ends (or after the advantageous state ends is displayed), the possibility of shifting to the second advantageous state can remain, so that the game It is possible to maintain the expectation of the player, and it is possible to prevent the player from stopping the game and reducing the operating rate of the game machine.

Further, in the present embodiment, the target whose game period can be extended in the second advantageous state is the game period in the first advantageous state, but the target whose game period can be extended in the second advantageous state is not limited to this. ..

For example, in the second advantageous state, it is decided whether or not to extend the playing period of another advantageous state (for example, "promotion chance", "double specialization zone", or "continuation challenge" itself). You may. Also, for example, when the second advantageous state (“continuation challenge”) can be transferred from any of the other advantageous states (for example, “promotion chance”, “double specialization zone”, and “normal ART”). In the second advantageous state, it may be determined whether or not to extend the gaming period of the advantageous state (pre-start state) before the transition.

That is, this technical idea makes it possible to grant a specific right in an advantageous state, and consumes the granted specific right at a predetermined time of the advantageous state (for example, when the advantageous state ends). By deciding whether or not to extend the game period, it includes all forms that can improve the interest regarding the continuation of the advantageous state.

Further, in pachinko (the above-mentioned enclosed game machine or managed game machine may be used; the same applies hereinafter), as an advantageous state, for example, when it is determined whether or not to hit, the hit is relatively high. High probability state (probability change state) where the probability of being determined is high, a movable member (for example, electric) for assisting (that is, supporting) the game ball to easily pass (win) a specific starting area. Electric support state (high) that increases the operation probability (opening probability) of (called chew etc.) or increases the probability that the operation pattern (opening pattern) becomes a more advantageous operation pattern (opening pattern) than usual. By making it easier for the time (variable time) until the variable display stops (base state) to be shortened than usual, a time-saving state in which more games can be played in a short time, and the game ball passes through a specific area ( When the hit is confirmed by winning a V), a movable member is provided so as to make it difficult or easy for the game ball to pass through the specific area, and this movable member is used as the game ball to the specific area. A gaming state in which the operation probability (opening probability) of operating so as to facilitate passage is increased, or the probability that the operation pattern (opening pattern) becomes a more advantageous operation pattern (opening pattern) than usual is increased. Other favorable conditions can be adopted.

Then, for example, when a limiter is provided for the number of consecutive hits in the high probability state (probability change state) described above, the number of consecutive hits is subtracted or initialized (0) based on a specific right. It may be possible to extend the advantageous state by performing the process of clearing).

In pachinko, a specific right can be given as specific control data when it is detected that the game ball has passed (winning) through the various areas or other areas described above, and this detection can be given. The lottery is performed based on the lottery, and based on the result of the lottery, it can be given as specific control data.

Further, in pachinko, the selection of the above-mentioned opening of the movable member (or an advantageous opening pattern) may be a specific right, or the right to variably display the identification information (for example, also referred to as hold information or hold ball). To be) may be a specific right.

Further, in pachinko, a predetermined member capable of physically retaining (holding) a game ball rolling in a game area at a predetermined position is provided, and the game ball retained (held) by the predetermined member is retained (held). ) Is released, and whether or not the gaming period in the advantageous state is extended may be determined depending on whether or not the gaming ball passes through a specific area. As a result, it is possible to improve the interest peculiar to pachinko, which is to enjoy the movement of the rolling game ball, and to improve the interest regarding the continuation of the advantageous state.

[Priority digestion of CP]
In the pachi-slot machine 1 of the present embodiment, the advantageous state (for example, during ART) is configured to include the first advantageous state (for example, normal ART) and the second advantageous state (for example, continuous challenge). Perform a first right to continue the first advantageous state (for example, ART stock), and an additional lottery (decision as to whether or not to extend the game period) for the number of games in the first advantageous state in the second advantageous state. A second right (eg, CP) for is grantable.

Then, when the first advantageous state ends, if both the first right and the second right are granted, the control is configured to give priority to the transition to the second advantageous state. Has been done. That is, the second right is preferentially digested over the first right.

In this case, in the second advantageous state, when the second right is consumed and an additional lottery (decision as to whether or not to extend the game period) is performed for the number of games in the first advantageous state, and the additional lottery is won ( If it is decided to extend the game period), the first advantageous state can be continued without consuming the first right, and if the additional lottery is not won (the game period can be extended). Even if it is not decided), the first right can be consumed to continue the first advantageous state. Therefore, it is possible to make the game playability various while ensuring a sense of security regarding the continuation of the advantageous state, and it is possible to improve the interest of the game.

Further, even if the state shifts to the second advantageous state when the first advantageous state ends, the first advantageous state continues due to the consumption of the second right or the consumption of the first right. Since the possibility can be left, the expectation for the continuation of the advantageous state can be maintained.

It is possible to acquire a plurality of second rights in an advantageous state, and when a plurality of second rights are acquired, the second rights are not wasted and all of them are acquired. It is configured to be used for an additional lottery (determination of whether or not to extend the game period) in the number of games in the first advantageous state. Therefore, in the second advantageous state, not only is it decided whether or not to continue the advantageous state, but it is also possible to create the possibility that a large number of games are added at one time, so that the game playability is more diverse. It is possible to improve the interest of the game.

In the present embodiment, when the consumption of the second right is prioritized over the consumption of the first right and the game period in the first advantageous state is extended by the acquired second right, the first It was supposed that the first advantageous state would be continued without consuming the right, but this is the mode of extension of the game period of the advantageous state when the consumption of the second right is prioritized over the consumption of the first right. Not limited to.

For example, even if the gaming period in the first advantageous state is extended by the consumption of the second right, the gaming period in the first advantageous state is further extended by consuming the first right, and this second advantageous state is extended. In the state, a larger number of games may be added (a longer game period is extended).

Specifically, when the game period extended in the second advantageous state is less than the predetermined game period, and if the first right is granted, the first right is also consumed and the predetermined game period is consumed. The game period may be extended beyond the game period. For example, if the predetermined game period is 50 games, which is the basic game period of one set, the game period of 30 games is extended based on the second right in the second advantageous state. At the end of the second advantage state, based on the first right (that is, consuming one ART stock), the playing period of 50 games is extended, and the playing period of 80 games is extended as a whole. It is possible that the player is informed of this fact.

In this case, the predetermined game period can be set as a game period different from the basic game period of one set. For example, when the predetermined game period is 100 games, and the game period of 50 games is extended based on the second right in the second advantageous state, when the second advantageous state ends. In addition, based on the first right (that is, consuming one ART stock), the playing period of 50 games has been extended, and the playing period of 100 games as a whole has been extended, and the second advantageous state is the second. If the playing period of 100 games is extended based on the right of 2, it is assumed that the playing period of 100 games is extended without consuming the first right, and the second advantageous state is set. If the game period is not extended based on the right of 2, the game period of 100 games may be extended based on the first right (that is, consuming 2 ART stocks).

Further, in this case, the first right and the second right acquired are not specified in the advantageous state, and the lottery result based on the second right is not specified in the second advantageous state. , When transitioning (returning) from the second advantageous state to the first advantageous state, it is not specified which right is consumed, and simply 100 games (or 50 games or more in the other example described above). ) Is added (extended) to the player. By doing so, it is possible to make it difficult to understand what kind of rights have been consumed and shifted (returned) to the first advantageous state, so that the playability regarding the continuation of the advantageous state can be made more diverse. Can be done.

The predetermined game period described above is not limited to the above-mentioned example, and can be set arbitrarily. For example, the average winning probability of the first right (eg, ART stock), the average winning probability of the second right (eg, CP), or the first right and the second winning rate per one time in the first advantageous state. The reciprocal of the average winning probability of the right may be set as a predetermined game period. In this way, in the first advantageous state of transition (return) from the second advantageous state, the player expects that at least one of them will be able to acquire the first right and / or the second right. Can be given to, and the interest of the game can be improved.

Further, in the second advantageous state, if it is determined that the gaming period exceeding the above-mentioned predetermined gaming period is extended, all of them are not displayed when shifting (returning) to the first advantageous state. A part of the game period is displayed, and the remaining game period is displayed at an arbitrary timing during the first advantageous state (for example, when it is displayed that the first advantageous state ends). May be good. That is, the timing at which the extended gaming period is displayed to the player in the second advantageous state can be arbitrarily set.

As described above, when a certain limiter is set for the continuation of the advantageous section that is advantageous to the player, and the second advantageous state is entered just before the end of the advantageous section. , In the second advantageous state, the extension of the game period that exceeds the limit may not be performed, or even if the extension of the game period that exceeds the limit is performed, the limit is exceeded. It may not be displayed that the game period has been extended.

Further, in the present embodiment, when the above-mentioned predetermined gaming period is extended in the second advantageous state, a signal indicating that fact is transmitted via the external centralized terminal plate 47 to an external gaming device (for example,). , Data display, game media rental device, hall management device, etc.). As a result, it is possible to appropriately recognize that the advantageous state has continued even in the external gaming device.

That is, this technical idea makes it possible to grant a first right to decide to extend the advantageous state and a second right to decide whether or not to extend the advantageous state in the advantageous state, which is advantageous. Continuation of the advantageous state by deciding whether to extend the gaming period of the advantageous state based on the first right and the second right at a predetermined time of the state (for example, when the advantageous state ends). It includes all forms that can improve the interest in.

[Promotion chance]
The pachislot machine 1 of the present embodiment has a specific state (for example, promotion chance) in which the game period in the advantageous state (for example, during ART) is extended, and in this specific state, the game in the advantageous state each time the game continues. It is configured to extend the period. In addition, it is configured so that it can be determined in advance whether or not to continue a plurality of consecutive games in a specific state. Therefore, it is possible to make the game playability related to the continuation of the advantageous state various, and it is possible to improve the interest of the game.

Further, in the pachi-slot machine 1 of the present embodiment, in the current game in the specific state, the game in the specific state is continued until the next game, and the game in the specific state is continued until the next game. It is configured so that the effect to be executed in the next game can be different depending on the case where is determined.

For example, if it is not decided to continue the game in the specific state until the next game, in the next game, as the first effect, the advantage extended based on the continuation of the specific state until the game. If it is decided to continue the game in the specific state until the next game while notifying the game period of the state, in the next game, as the second effect, the specific state continues until the game. It is configured to notify the game period exceeding the game period in the advantageous state to be extended based on.

With such a configuration, it is possible to definitively notify that the specific state continues, that is, the gaming period in the advantageous state is further extended, and it is possible to further improve the interest of the game. In addition, while specifically notifying the game period of the advantageous state to be added, it is notified that the specific state will continue due to the contradiction of the mode, so that the interest of the game can be further improved.

In the present embodiment, the specific state describes a mode in which the game period in the advantageous state is extended each time the game in the specific state continues, but the benefit is obtained by continuing the game in the specific state. The mode to be given is not limited to this.

For example, it is possible to shift from a normal gaming state (for example, during non-ART) to a specific state, and a predetermined number of points (specific numerical value) is given each time the game continues in the specific state, and the number of points given is predetermined. When the number of points is reached (or determined by lottery) (when a predetermined achievement condition is satisfied), the privilege of shifting to an advantageous state may be given. In this case, it is sufficient that the effect pattern (see FIGS. 72 and 123 to 125) corresponding to the number of points to be given can be determined.

Further, in this case, in the specific state, there is a predetermined number of points (or determined by lottery), and each time the game continues in the specific state, a predetermined number of points (specific numerical value) is obtained from this number of points. When the number of points becomes 0 (when a predetermined achievement condition is satisfied), the privilege of shifting to an advantageous state may be given.

Further, in these cases, the number of games in the advantageous state may be added (the game period in the advantageous state is extended) when a predetermined achievement condition is satisfied in the specific state shifted from the advantageous state.

In addition, as in the above example, when a specific numerical value is decremented each time the game continues in a specific state and the effect is performed accordingly, for example, in the specific state, a battle effect between the ally character and the enemy character is performed. Is performed, the hit points of the enemy character (predetermined achievement conditions) are displayed, and when the game continues, the ally character attacks and the damage (specific) according to the attack is performed. A display is made to reduce the numerical value) from the hit points. At this time, if it is decided that the specific state will continue until the next game, the value corresponding to the damage larger than the damage corresponding to the normal attack will be reduced from the hit points in the next game (display ( Next time, the continuous confirmation display) may be performed. As a result, as in the present embodiment, it is possible to notify that the specific state continues until the next game, and by giving variation to the change in the numerical display, it is possible to prevent the production from becoming monotonous. Can be done.

It should be noted that whether or not the predetermined achievement condition is satisfied may be determined in advance before the specific state starts or when the specific state starts. In addition, it may be determined in advance whether or not a predetermined achievement condition is satisfied, and if so, at what timing (for example, what game in a specific state) the predetermined achievement condition is satisfied. In this case, depending on the timing at which the predetermined achievement condition is satisfied, either the display according to the number of continuations or the next continuation confirmation display may be displayed.

Further, in pachinko, for example, a jackpot game state in which the number of rounds is 5 (first specific state), a jackpot game state in which the number of rounds is 10 (second specific state), and a number of rounds is 15 rounds. When the jackpot game state (third specific state) is provided, at the start of the fifth round (or during the execution of the fifth round) and at the start of the tenth round (or execution of the tenth round). In the middle), when it is possible to perform an effect (rank-up effect) on whether or not the jackpot game state continues, in the fifth round of the second specific state, the rank-up as the second effect As an effect, the next continuous confirmation display may be performed by displaying the number of rounds "6", or in the 10th round of the third specific state, as a rank-up effect as the second effect, a round. By displaying the number "11", the next continuous confirmation display may be performed. In other cases, the actual number of rounds may be displayed so that the display according to the number of continuations (first effect) is performed.

That is, this technical idea becomes advantageous to the player each time the game in the specific state continues in the specific state, and it is possible to determine in advance how long the game in the specific state will continue until a predetermined time. In addition, it includes all forms that can improve the interest of the game by changing the production to be performed according to the decision.

[Special production]
The pachislot machine 1 of the present embodiment has a plurality of specific internal states (for example, normal mode), and when there is a change in the specific internal state, it is reserved to execute a predetermined effect (for example, a special effect). Then, when a predetermined execution condition is satisfied, a predetermined effect is executed.

For example, when there are a plurality of lottery states having different transition probabilities to an advantageous state (for example, during ART) as a plurality of specific internal states, the lottery state becomes an advantageous lottery state, or an advantageous state. If there is a precursory state in which the transition of is awaited, it is reserved to execute a predetermined effect when the precursory state is reached.

Then, when a predetermined display result (for example, a combination of symbols of "S_TL lip") is derived (that is, a predetermined internal winning combination (for example, "normal lip") is established), a predetermined effect is executed. It is configured to be. That is, every time a predetermined display result is derived, the player can expect whether or not the predetermined effect is executed, and the unit game in which the specific internal state is changed and the predetermined effect are executed. It is configured so that it can be different from the unit game to be played. Therefore, when there are a plurality of specific internal states, the suggestions of the specific internal states can be varied.

As described in the present embodiment, the probability that a predetermined display result (for example, a combination of symbols of "S_TL lip") can be derived (see FIGS. 16 to 21), that is, a predetermined execution condition is satisfied. The probability is higher than the probability that the normal mode shifts to the advantageous mode (see FIG. 29), that is, the probability that the lottery state becomes the advantageous lottery state. As a result, the frequency of games in which a specific internal state can be suggested can be increased, and the expectation of the player can be maintained.

Further, in the present embodiment, the mode in which the predetermined execution condition is satisfied by deriving the predetermined display result is described, but the mode in which the predetermined execution condition is satisfied is not limited to this.

For example, a special effect execution lottery may be performed based on the game state or the internal winning combination, and when the special effect execution lottery is won, a predetermined execution condition may be satisfied. Further, for example, when a display result other than the predetermined display result described in the present embodiment (for example, a combination of symbols of "S_TL lip") is derived, the predetermined execution condition may be satisfied.

Further, for example, when a specific operation is performed on the touch sensor 19, a predetermined execution condition may be satisfied. Further, for example, an operation button (not shown) for effect may be separately provided, and a predetermined execution condition may be satisfied when a specific operation is performed on the operation button. Further, for example, when a specific operation is performed on the start lever 16 or the stop buttons 17L, 17C, 17R, a predetermined execution condition may be satisfied. Further, in these cases, it is urged to perform a specific operation, and whether or not to perform a specific instruction effect indicating the procedure of the specific operation is determined based on the judgment value for the special effect and the value of the special effect reservation parameter. When a lottery is performed, a specific instruction effect is executed based on the lottery result, and a specific operation is performed, a predetermined execution condition may be satisfied.

That is, this technical idea has a plurality of specific internal states, makes it possible to perform a predetermined effect suggesting the specific internal state, determines whether or not the predetermined effect can be executed, and determines whether or not the predetermined effect can be performed. By making a decision as to whether or not to execute the effect, all the forms in which the suggestion of the specific internal state can be varied are included.

[Numerical fluctuation display control]
In the pachislot machine 1 of the present embodiment, when a predetermined numerical value (for example, a value of an ART game number counter) fluctuates, the predetermined numerical value fluctuates over a predetermined period before the fluctuating predetermined numerical value is displayed. It is configured so that the effect of the effect is enhanced by displaying it, but when the game machine returns to the state before the power failure after the power failure occurs, the change is not displayed and the change is performed after the change. It is configured to display a given (ie, current) number.

For example, when a predetermined numerical value corresponds to the remaining gaming period of a specific gaming state (for example, during ART), and the remaining gaming period fluctuates, usually, the remaining gaming period is set to the predetermined period (for example, during ART). For example, after the fluctuation is displayed for 500 ms), the remaining game period after the fluctuation is displayed, but when the game machine returns to the state before the power failure after the power failure occurs, the fluctuation display is performed. Instead, it is configured to display the remaining (ie, current) playing period after the change.

That is, when the power is restored, the control for returning to the gameable state is prioritized over the control for enhancing the effect of the effect. Therefore, when the power is restored, the production content can be appropriately restored.

In conjunction with returning to the game-enabled state on the control circuit (game control means) that controls the progress of the game, the control circuit (display control means) that controls the effect may also return to the game-enabled state. It is configured so that it can be done. At that time, the display of the predetermined numerical value is configured to switch from the initial value to the current numerical value. Therefore, with a simple configuration, it is possible to notify that the game machine returns to the playable state, and it is possible to more appropriately restore the effect content when the power failure is restored.

As described in the present embodiment, the predetermined numerical value can be applied to any numerical value as long as it is a numerical value related to the game. However, it is desirable that the predetermined numerical value is a numerical value related to the game, and in particular, a numerical value necessary for the progress of the game.

Further, in the present embodiment, a mode in which a specific numerical fluctuation display is not performed when returning to the state before the power interruption after the power failure occurs in the game machine is described, but the specific numerical fluctuation display is described. The mode in which the above is not performed is not limited to this.

For example, even when the gaming machine returns to a game-playable state after the setting is changed or the setting is confirmed, the specific numerical fluctuation display may not be performed. In particular, in the setting confirmation scene, it is necessary to promptly return to the state before the setting confirmation after the setting confirmation is completed. Therefore, in this way, the production content can be appropriately restored at the time of setting confirmation. Is thought to be possible.

That is, this technical idea includes all forms in which the production content can be appropriately restored in a situation where control for returning to a playable state is prioritized.

[Game history display function]
In the pachi-slot machine 1 of the present embodiment, a sub-display device 18 is provided separately from the display device 11 (projector mechanism 211 and display unit 212), and the sub-display device 18 displays various information useful to the player. For example, as shown in FIGS. 5A to 5E, a top screen 221 showing the outline game history, a menu screen 222 capable of performing various operations on the pachislot machine 1, and a game information screen 223, 224, 225 showing the detailed game history are sub-display devices. It can be displayed at 18.

Further, the pachi-slot machine 1 of the present embodiment has a function of enabling registration of a player who plays a game via a sub-display device 18, and a function of providing a unique service to the registered player. For example, in the present embodiment, when the registration of the player is not accepted, the game information screens 223, 224, and 225 showing the detailed game history cannot be displayed on the sub display device 18, but the registration of the player is performed. When accepting, the game information screens 223, 224, and 225 showing the detailed game history can be displayed on the sub display device 201. Since making it possible to confirm a more detailed game history leads to an improvement in the convenience of the player, in the present embodiment, the convenience can be improved when the registration of the player is accepted.

Further, in the pachi-slot machine 1 of the present embodiment, the sub-display device 18 is provided separately from the display device 11 that performs the effect. The sub display device 18 is controlled by the sub control board 72 (sub CPU 201) via the liquid crystal relay board 87. Further, the display unit 212 constituting the display device 11 is controlled by the sub control board 72 (sub CPU 201) via the accessory relay board (not shown). Therefore, in the present embodiment, the sub-display device 18 can be controlled separately from the display device 11. Specifically, the display screen of the sub-display device 18 can be switched even during the game (that is, during the execution of the effect by the display device 11). Therefore, even during the game, the player can acquire various information by switching the display of the sub-display device 18 without disturbing the effect executed by the display device 11.

Further, in the display device 11 of the pachi-slot machine 1 of the present embodiment, a flat image display is used by switching a plurality of screen mechanisms (display unit 212) for displaying an image by irradiating the irradiation light from the projector mechanism 211. When performing an effect, an effect using an image display having a sense of depth (three-dimensional effect), and an effect using a curved image display, the effect can be significantly enhanced. However, such an information display form is not suitable for displaying information unrelated to the production such as a game history during the production. Therefore, in the pachi-slot machine 1 of the present embodiment, information unrelated to the effect can be displayed on the sub-display device 18 provided separately from the display device 11, so that the effect of the effect is not impaired and the game is played. Various information such as history can be displayed appropriately.

By the way, in a general pachislot machine, a medal insertion slot 14 is provided on the right side of the pedestal portion 13 when viewed from the player side, and bet buttons 15a and 15b and a start lever 16 are provided on the left side of the pedestal portion 13. Therefore, normally, when advancing the game, the player operates the operation unit on the right side or the left side (side) of the pedestal portion 13.

On the other hand, in the pachi-slot machine 1 of the present embodiment, the sub display device 18 is provided on the side (left side) of the surface that stands substantially vertically from the pedestal portion 13, and the sub display device 18 is provided on the screen of the sub display device 18. A touch sensor 19 for switching the display screen of is provided. Therefore, in the present embodiment, the sub-display device 18 and the input device (touch sensor 19) for controlling the display are provided at the place where the player's hand is located during the game, so that the player's operability Can be improved. In particular, when the sub display device 18 with the touch sensor 19 is provided on the surface of the pedestal portion 13 that stands upright from the horizontal plane as in the present embodiment, the player puts his / her hand on the pedestal portion 13. However, the sub display device 18 can be operated. In this case, not only the operability of the player is improved, but also the fatigue of the player due to the operation can be reduced, and as a result, the operating rate can be expected to be improved.

[Non-standard ROM area and non-standard RAM area]
In the pachi-slot machine 1 of the present embodiment, as shown in FIG. 12B, various programs and various types used for various processes (various processes that do not affect the playability) that are not directly related to the playability of the game performed by the player. The data (table) is stored in the main ROM 102 in a non-standard ROM area arranged at an address different from the game ROM area.

In such a configuration of the main ROM 102, programs and data unnecessary for the game itself actually played by the player are arranged in a ROM area (non-standard ROM area) where programs and the like cannot be arranged under the conventional rules. can do. Therefore, in the present embodiment, it is possible to avoid pressure on the capacity of the game ROM area in the main ROM 102 of the main control board 71, and to enhance the expandability of the program and the table in the main ROM 102.

[Processing when power is turned on (reset interrupt)]
In the power-on (reset interrupt) processing of the pachi-slot machine 1 of the present embodiment, as shown in FIG. 36, the first 1.1172 ms cycle interrupt processing is performed immediately after the power is restored (before the thumb check) (S7 and S8). ), A non-operation command is transmitted from the main control circuit 90 to the sub control circuit 200. By permitting the interrupt process immediately after the power is restored in this way, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

Further, the communication parameters 1 to 5 constituting the non-operation command transmitted immediately after the power is restored are set with the data stored in the L register, the H register, the E register, the D register and the C register, respectively, when the power is restored. Will be done. Therefore, in the present embodiment, the sum value (BCC) of the non-operation command transmitted in the interrupt process immediately after the power is restored can be made different every time the power is restored, and fraudulent acts such as goto can be suppressed. it can.

Further, the control for displaying the error code "rr" on the 2-digit 7-segment LED in the information display 6 performed in the processing of S13 during the power-on (reset interrupt) processing is one "LDW". It is executed by an instruction (predetermined read instruction), and the output operation of the 7-segment common output (selection) data to the 2-digit 7-segment LED and the output operation of the 7-segment cathode output data are simultaneously performed (see FIG. 37C). That is, in the pachi-slot machine 1 of the present embodiment, when the 2-digit 7-segment LED is dynamically lit and controlled in the power-on (reset interrupt) processing, the 7-segment common output (selection) data and the 7-segment cathode output data are displayed. It is output at the same time.

In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, the playability can be enhanced.

[Game return processing]
In the game return processing of the pachislot machine 1 of the present embodiment, as shown in FIG. 38, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the reel is rotating at the time of power failure, When the power is restored, the reel control management information is acquired and the processing necessary for starting the reel rotation is also performed (see S25 to S32). Therefore, in the present embodiment, it is possible to stably control the re-rotation of the reel even when recovering from the electric power failure during the rotation of the reel, and the player is not discomforted.

Further, as described above, the pachi-slot machine 1 of the present embodiment includes a microprocessor 91 with a security function for a game machine. The microprocessor 91 is provided with various instruction codes (instruction codes dedicated to the main CPU 101) specific to the microprocessor 91 that can be specified on the source program, and the instruction codes dedicated to the main CPU 101 are used in various processes. This makes it possible to improve processing efficiency and reduce program capacity.

For example, in the game return process, as shown in FIG. 38, the "LDQ" instruction, which is one of the instruction codes dedicated to the main CPU 101, is used on the source program. The "LDQ" instruction is an instruction code that specifies an address using a Q register (extension register), and as described above, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed with direct values. In this case, the instruction code related to the address setting can be omitted, and the capacity of the source program for the game return processing (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Setting change confirmation process]
In the setting change confirmation process of the pachi-slot machine 1 of the present embodiment, as shown in FIG. 41A, the "BITQ" instruction and the "SETQ" instruction (predetermined instruction), which are instruction codes dedicated to the main CPU 101, are used on the source program. .. Both the "BITQ" instruction and the "SETQ" instruction are instruction codes for specifying an address using a Q register (extension register), and when these instruction codes are used, as described above, the main RAM 103 is a direct value. And memory map I / O can be accessed. In this case, the instruction code related to the address setting can be omitted, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to increase the free space of the main ROM 102 and to speed up the processing.

Further, the generation and storage processing of the setting change command (initialization command) performed at the time of setting change / setting confirmation start of S46 and at the end of setting change / setting confirmation of S57 during the setting change confirmation processing is as shown in FIGS. 41A and 41B. In addition, it is executed by the "CALLF" command, which is a command code dedicated to the main CPU 101, on the source program. The jump destination address specified by the "CALLF" instruction in S46 is the same as the jump destination address specified by the "CALLF" instruction in S57. That is, in the present embodiment, the setting change command (initialization command) to be transmitted to the sub-control circuit 200 at the time of setting change (when the game machine is started), at the start of setting confirmation (during normal operation), and at the end of setting confirmation is generated and stored. The source programs for executing the above are the same as each other, and the source programs are shared (modularized) in both the processes of S46 and S57.

In this case, in both the S46 and S57 processes, it is not necessary to separately provide the source program for the generation and storage process of the setting change command, so that the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. it can. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Setting change command generation and storage processing]
In the setting change command generation / storage process of the pachi-slot machine 1 of the present embodiment, as shown in FIG. 42, the set value is stored in the E register as the communication parameter 3, and the RT information is stored in the C register as the communication parameter 5. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), the communication parameters 3 and 5 are the communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side, and these New information is set in the communication parameters. On the other hand, the other communication parameters 1, 2 and 4 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side, and are communication parameters 1, 2 and 4. For and 4, the values currently stored in the L register, H register, and D register are set. Therefore, the values of the communication parameters 1, 2 and 4 at the time of transmitting the setting change command (initialization command) are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Communication data storage process]
In the communication data storage process of the pachislot 1 of the present embodiment, as shown in FIG. 44, the data stored in the A register is set as the type data of the communication command, and the L register, the H register, the E register, the D register and the C register are set. The data stored in the registers are set as communication parameters 1 to 5 of the communication command, respectively, and the data stored in the B register is set as the game state flag data of the communication command. That is, in the present embodiment, when creating one packet (8 bytes) of communication data (command data), various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer).

In this case, when command data including unused parameters is created, the value of the unused parameters becomes an undefined value each time it is created. That is, in the command data including unused parameters, even if there is command data of the same type and the values of the used parameters are the same, the sum value (BCC data) of the command data can be changed for each command creation. .. Therefore, in the present embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress fraudulent acts such as goto, and it is necessary to add unnecessary goto countermeasure processing. Therefore, it is possible to suppress the pressure on the program capacity of the main control circuit 90 due to the addition of the anti-goto processing.

[Communication data pointer update process]
In the communication data pointer update process of the pachislot machine 1 of the present embodiment, as shown in FIG. 47A, the "ICPLD" instruction, which is an instruction code dedicated to the main CPU 101, is used on the source program.

In the communication data pointer update process, the "ICPLD" instruction is an instruction code in which the upper limit determination instruction of the transmission buffer and the determination branch instruction are integrated, so that an instruction code for executing each instruction process separately is used. There is no need to provide it. Therefore, by using the "ICPLD" instruction, the capacity of the source program for the communication data pointer update process (the capacity used by the main ROM 102) can be reduced. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Checksum generation process and checksum check process]
In the pachislot machine 1 of the present embodiment, in the checksum generation process (non-standard) performed at the time of power failure, the checksum is calculated by sequentially adding the data of the main RAM 103 as shown in FIG. 49. On the other hand, in the thumb check process (non-standard) performed when the power is turned on (when the power is restored), the value of the checksum generated when the power is cut off is stored in the main RAM 103 when the power is restored, as shown in FIG. The data is sequentially subtracted, and the presence or absence of an abnormality is determined based on whether or not the final subtraction result is "0". That is, in the present embodiment, the checksum generation process when a power failure occurs is performed by an addition method, and the checksum determination process when the power is restored is performed by a subtractive method.

When such a checksum generation process and determination process are adopted, it is not necessary to generate a checksum again when the power is restored and collate the checksum with the checksum when a power failure occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, in the main ROM 102, it is possible to secure (increase) the free space corresponding to the omitted part of the collation instruction code, and it is possible to utilize the increased free space to improve the playability. Become.

[Medal reception / start check processing]
In the medal acceptance / start check process of the pachislot machine 1 of the present embodiment, as shown in FIG. 55, the setting change confirmation process (process of S233) is performed, and this process is executed regardless of the gaming state. Therefore, in the present embodiment, even if the game state is a bonus state (special prize operating state), the set value and the hall menu (various history data (error, power failure history, etc.)) can be confirmed, and the game can be checked. It is possible to suppress cheating.

[Medal insertion process]
In the medal insertion process of the pachislot machine 1 of the present embodiment, as shown in FIG. 57, in the process of S244, the LED lighting data for displaying the number of inserted medals is generated by arithmetic processing instead of loop processing with reference to the table. .. Specifically, a series of source codes "LD A, L" to "OR L" in the source program shown in FIG. 58 are sequentially executed to generate LED lighting data for displaying the number of inserted medals.

When the LED lighting data for displaying the number of inserted medals is generated by arithmetic processing, the free space of the table area of the main ROM 102 can be increased, and the increase in the capacity of the program can be minimized. That is, in the medal insertion process of the present embodiment, the process of displaying the medal insertion LED can be made more efficient, the free space of the main ROM 102 is secured (increased), and the increased free area is utilized to improve the playability. Can be enhanced.

[Medal insertion check process]
In the medal insertion check process (see FIG. 59) of the pachislot machine 1 of the present embodiment, the process of generating the normal change value of the medal sensor input state of S257 is performed by an arithmetic process, not a process of acquiring by referring to the table. Specifically, the medal sensor input state normal change value is calculated by sequentially executing the source codes "RLA" and "AND cBX_MDINSW" in the source program shown in FIG.

By changing the detection process of the change mode of the medal sensor input state from the table reference process to the arithmetic process, the free space of the table storage area of the main ROM 102 can be increased and the increase in the program capacity can be minimized. it can. Therefore, by adopting the above-mentioned processing method, it is possible to improve the efficiency of the detection processing of the change mode of the medal insertion sensor state, and to utilize the increased free space in the main ROM 102 to improve the playability. it can.

[Internal lottery processing]
In the internal lottery process of the pachi-slot machine 1 of the present embodiment (see FIG. 64), the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 65A. By executing this "LDIN" instruction, in the processing of S305, the determination data is stored in the A register, and the request flag status is stored in the C register. Further, by executing the "LDIN" instruction, the address set in the HL register is updated by +2 (addition of 2).

That is, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed by one instruction code (“LDIN” instruction). In this case, the instruction code related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the addition processing of the set value data (any of 0 to 5) of S309 of the internal lottery processing, the main CPU 101 uses the source codes “MUL A, 6” and “ADDQ A, (.LOW.wWAVENUM” in FIG. 65B. ) ”Is executed in this order.

The "MUL" instruction is an instruction code for multiplication processing dedicated to the main CPU 101, and the execution of this instruction is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, since the pachi-slot machine 1 of the present embodiment is provided with a dedicated calculation circuit (calculation circuit 107) for executing multiplication processing and division processing on the source program, the efficiency of multiplication processing and division processing should be improved. Can be done.

The "ADDQ" instruction (predetermined addition instruction) is an instruction code dedicated to the main CPU 101, and is an instruction code for specifying an address using a Q register (extension register). Then, by using this "ADDQ" instruction, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by the direct value. Therefore, by using the "ADDQ" instruction, the instruction related to the address setting can be omitted on the source program of the internal lottery processing, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. Can be done. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Design code acquisition process]
In the symbol code acquisition process (see FIG. 75) of the pachislot machine 1 of the present embodiment, the data related to the winning is compressed / decompressed by the processing procedure described in S647 to S649, and the main CPU 101 dedicated command in the processing is performed. By using a code (such as a "CALLF" command), it is possible to improve the efficiency of the data compression / decompression processing related to the winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

Further, in the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address specified by the "CALLF" instruction is compressed executed in the symbol setting process (see S205 of FIG. 54). In the data storage process (not shown), it is the same as the jump destination address specified by the "CALLF" instruction. That is, in the present embodiment, the source program for executing the compressed data storage process is shared (modularized) in both the symbol code acquisition process and the symbol setting process. In this case, since it is not necessary to separately provide the source program for the compressed data storage process in each process, the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Pull-in priority acquisition process]
In the pull-in priority order acquisition process of the pachi-slot machine 1 of the present embodiment (see FIGS. 78 and 79), the determination process of S683 during the pull-in priority correspondence process of the “ANY combination” is performed by the main CPU 101 dedicated instruction code on the source program. It is executed by a certain "JCP" instruction (comparison instruction) (see FIG. 80A).

When the "JCP" command is used on the source program of the "ANY role" pull-in priority processing, the command related to the address setting can be omitted as described above, so the "ANY role" pull-in priority support The processing efficiency of the processing can be increased, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced.

Further, in the stop control pull-in request flag setting process of S686 during the pull-in priority acquisition process, as shown in FIG. 80B, the Q register (extension register), which is an instruction code dedicated to the main CPU 101, is used on the source program. The "LDQ" instruction and the "CALLF" instruction for specifying an address are used.

Therefore, in the stop control pull-in request flag setting process of S686, by using the "LDQ" instruction, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (use of the main ROM 102). Capacity) can be reduced. Further, the "CALLF" instruction is a 2-byte instruction code as described above. Therefore, by using these main CPU 101 dedicated instruction codes in the stop control pull-in request flag setting process, the processing efficiency can be improved and the limited capacity of the main RAM 103 can be effectively utilized. ..

Further, in the present embodiment, in the stop control pull-in request flag setting process of S686 during the priority pull-in order acquisition process, the address of the jump destination logical product operation process specified by the "CALLF" instruction is the pull-in priority order storage process ( It is the same as the jump destination address specified by the "CALLF" instruction in the logical product operation processing of S626 in (see FIG. 73) (see FIG. 74). That is, in the present embodiment, the source program for executing the logical product calculation process is shared (modularized) in both the priority attraction order acquisition process and the attraction priority order storage process.

In this case, since it is not necessary to separately provide the source program for the logical product operation processing in both the priority attraction order acquisition process and the attraction priority order storage process, the capacity of the source program (the capacity used by the main ROM 102) is increased accordingly. Can be reduced. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Reel stop control process]
In the reel stop control process (see FIG. 81) of the pachi-slot machine 1 of the present embodiment, in the processes of S711 to S715, as shown in FIG. 82, the address is specified by using the Q register (extension register) on the source program. The "LDQ" instruction and the "CALLF" instruction are used.

Therefore, in the present embodiment, by using these main CPU 101 dedicated instruction codes, the capacity of the source program of the reel control processing can be reduced, and the processing efficiency of the reel stop control processing can be improved. That is, in the present embodiment, it is possible to improve the efficiency of the program processing speed and reduce the capacity of the main control circuit 90, and utilize the free area of the main ROM 102 that has increased according to the reduced capacity to improve the playability. Can be enhanced.

Further, in the determination process of S726 during the reel stop control process (check process of the stop state of the reel (rotary cylinder)), as shown in FIG. 83, the “LDQ” instruction and the “ORQ” instruction (Q) are displayed on the source program. A main CPU 101 dedicated instruction code) that specifies an address using a register (extension register) is used.

Therefore, in the present embodiment, the instruction related to the address setting can be omitted on the source program of the reel stop control process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. .. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Prize search process]
In the winning search process (see FIG. 88) of the pachi-slot machine 1 of the present embodiment, in the set process of the number of payouts and the determination target data in S764, as shown in FIG.

Therefore, in the winning search process of the present embodiment, both the data load process and the address update process can be performed by one "LDIN" command. In this case, the instruction related to the address setting can be omitted on the source program of the winning search process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, the acquisition process of the value of the medal counter referred to in the determination process of S770 during the winning search process, the acquisition process of the value of the winning number counter referred to in the processing of S772, and the saving of the winning number counter performed in the processing of S775 ( In each of the update) processes, as shown in FIG. 89, the "LDQ" instruction for specifying the address using the Q register (extension register) is used. Therefore, in the winning search process of the present embodiment, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the determination process of S769 during the winning search process, as shown in FIG. 89, the "JSLAA" instruction is used on the source program, and in the determination process of S770 and S773, the "JCP" instruction is used. When the "JSLAA" command and the "JCP" command are used on the source program of the winning search process, the command related to the address setting can be omitted as described above, and the capacity of the source program (main ROM 102) can be omitted accordingly. (Capacity used) can be reduced. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Illegal hit check processing]
In the present embodiment, as shown in FIG. 22, the configuration of the winning operation flag storage area (display combination storage area) is the same as that of the hit request flag storage area (internal winning combination storage area). Therefore, in the arithmetic processing of S784 in the illegal hit check processing of the present embodiment, the data of the winning combination and the data of the internal winning combination are simply logically producted (by the "AND" instruction) on the source program (see FIG. 91). You can get the result of combining the winning combination data and the internal winning combination data just by executing).

Therefore, in the present embodiment, the illegal hit check process can be made more efficient and simplified, and as a result, the free space of the main control program can be secured, and the free space can be used to enhance the playability. be able to.

[Prize check / medal payout process]
In the winning check / medal payout process (see FIG. 92) of the pachislot machine 1 of the present embodiment, when the payout operation is continued after the credit counter is updated (+1), the wait (payout interval) of 60.33 ms in the process of S808 Wait) Processing is performed. In this case, unnecessary waiting time can be reduced, and the mental burden on the player can be reduced.

[Check process for paying out medals]
In the update process of the winning combination end number counter of S814 during the medal payout number check process (see FIG. 94) of the pachislot machine 1 of the present embodiment, as shown in FIG. 95A, the instruction code dedicated to the main CPU 101 is used on the source program. The "DCPLD" instruction is used.

In the process of S814, the "DCPLD" instruction is an instruction code in which the lower limit determination instruction of the number management counter and the determination branch instruction are integrated, so that the update (subtraction) process of the combination end number counter and the consecutive end number Both processes of holding the counter value at "0" can be executed. In this case, it is not necessary to provide an instruction code for executing both processes separately. Therefore, in the medal payout number check process of the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, and the free space can be secured (increased) in the main ROM 102, resulting in an increase. It is possible to improve the playability by utilizing the free space.

Further, in the process of S816 during the medal payout number check process, as shown in FIG. 95B, the value of the payout counter is set in the communication parameter 1 of the credit information command, and the value of the credit counter is set in the communication parameter 5. Will be done. However, the other communication parameters 2 to 4 (unused parameters) constituting the credit information command are set to the values stored in the H register, the E register, and the D register at present. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[7-segment LED drive processing]
As shown in FIG. 102B, the output processing of the 7-segment common output (selection) data and the 7-segment cathode output data performed in S936 during the 7-segment LED drive processing (see FIG. 101) of the pachislot machine 1 of the present embodiment is one source. It is executed by the code "LD (cPA_SEGCOM), BC". That is, in the present embodiment, in the 7-segment LED drive process, the 7-segment common output data and the 7-segment cathode output data are output at the same time when the 2-digit 7-segment LED is dynamically lit. This output control is also performed when the push order display data is displayed on the instruction monitor in the information display 6.

In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED can be reduced on the source program of the 7-segment LED drive process. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, the playability can be enhanced.

[Timer update process]
In the process of S952 (update process of the 2-byte timer) in the timer update process (see FIG. 106) of the pachi-slot machine 1 of the present embodiment, as shown in FIG. 107, the main CPU 101 dedicated instruction code is added to the source program. The "DCPWLD" command is used.

When the "DCPWLD" instruction is executed in the timer update process, both the update (subtraction) process of the timer value (2-byte timer value) and the process of holding the timer value at "0" are executed as described above. Can be done. In this case, it is not necessary to provide an instruction code for executing both processes separately. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, the playability can be enhanced.

<Supplementary note (summary of the invention according to the present embodiment)>
[Game machine of the first invention]
In a conventional game machine, for at least one reel, the maximum number of movements of symbols (hereinafter referred to as "number of sliding pieces") until the symbols stop when a stop operation is performed is set as the first number of symbols (hereinafter, "number of sliding pieces"). For example, instead of reducing the number of second symbols (for example, one symbol) less than the number of first symbols (for example, four symbols), all small winning combinations are won regardless of the result of the lottery process. It is known that a specific special gaming state (MB gaming state) to be processed can be activated (see, for example, Japanese Patent Application Laid-Open No. 2007-117497).

By the way, in such a game machine, for example, in the case of adopting that a specific small winning combination is determined as an internal winning combination as an operation trigger of ART which is an advantageous state for the above-mentioned player, the above-mentioned During a specific special gaming state, the trigger for the operation of ART cannot be obtained or it becomes difficult to obtain it, so that the interest of the specific special gaming state, which should be originally advantageous for the player, is reduced. There was a problem of doing it.

The first invention has been made to solve the above-mentioned problems, and by making it possible to obtain an operation trigger of an advantageous state as in other gaming states even during a specific special gaming state. It is an object of the present invention to provide a game machine capable of improving the interest of the game.

The gaming machine of the first invention is
A gaming machine (for example, pachislot machine 1) that variablely displays a plurality of symbols in a plurality of display columns.
An internal winning combination determining means for determining an internal winning combination (for example, an internal lottery process by the main CPU 101),
When the start operation is performed by the player, the symbol variation start control means (for example, the reel rotation start process by the main CPU 101) that starts the symbol variation display, and
When the stop operation is performed by the player, the symbol variation stop control means (for example, the reel stop control process by the main CPU 101) that stops the symbol variation display based on the internal winning combination determined by the internal winning combination determining means. When,
When the symbol variation display is stopped by the symbol variation stop control means and a special symbol combination (for example, a combination of symbols of "C_MB") is displayed, the control is performed in a special gaming state (for example, MB gaming state). Special game state control means (for example, bonus check processing by the main CPU 101),
When a predetermined condition is satisfied, the advantageous state control means (for example, the main CPU 101) that controls the advantageous state (for example, during ART) that is advantageous for the player, and
In the special game state, a lock effect determining means (for example, main CPU 101) for determining whether or not to execute a specific lock effect (for example, a lock effect during MB) is provided.
In the special gaming state, when the stop operation is performed by the player, the symbol variation stop control means sets the maximum number of movement amounts of the symbols for at least one display row (for example, the reel 3R). It is a gaming state in which the number of symbols of 1 (for example, 4 symbols) is reduced to the number of 2nd symbols (for example, 1 symbol) less than the number of the first symbols.
The predetermined condition is that a specific combination (for example, "F_black BAR") is determined as an internal winning combination by the internal winning combination determining means in a gaming state different from the special gaming state, and the special gaming state. In the above, the lock effect determination means determines that the specific lock effect is to be executed.
In a game state different from the special gaming state, the probability that the specific combination is determined as the internal winning combination by the internal winning combination determining means, and in the special gaming state, the specific locking effect is performed by the locking effect determining means. It is characterized in that the probability that it is decided to execute is the same probability.

In the gaming machine of the first invention, a specific combination (for example, "F_black BAR") that triggers an operation of an advantageous state (for example, during ART) in a gaming state different from the special gaming state (for example, MB gaming state). The winning probability of the above and the execution probability of the specific lock effect that triggers the operation of the advantageous state in the special gaming state are configured to be the same probability (for example, 8/65536). That is, regardless of which gaming state the gaming state is, the activation trigger of the advantageous state can be obtained with a certain probability. Therefore, it is possible to improve the interest of the game.

Further, the gaming machine of the first invention is
The specific combination is an internal winning combination that allows the display of a specific combination of symbols (for example, a combination of symbols of "C_black BAR") when the internal winning combination is determined by the internal winning combination determining means. Yes,
The specific lock effect is characterized in that the game operation of the player is invalidated for a predetermined period of time, and the combination of the specific symbols is temporarily stopped within the predetermined period.

Further, in the gaming machine of the first invention, when a specific lock effect is executed in the special gaming state, a combination of symbols related to the specific combination (for example, a combination of symbols of "C_black BAR") is provisionally. It is configured to stop. That is, if the combination of symbols related to the specific combination is displayed regardless of which game state the game state is, the player can be made aware that the operation trigger of the advantageous state has been established. ing. Therefore, regardless of the determination of the internal winning combination in the special game state and the restriction of the reel stop control, the player can easily feel that the operation trigger of the advantageous state has been established, and the interest of the game is further improved. Can be made to.

[Game machine of the second to fourth inventions]
In a conventional game machine, during the operation of ART, the number of sets of ART (for example, the operation of ART with 50 games as one set, or the continuation of ART is given for each unit game) based on the internal winning combination. It is known that an additional lottery (right) is executed, the additional lottery is won, and the number of sets of ART is added to enable the continuation of ART (for example, Japanese Patent Application Laid-Open No. 2013-17520). See publication).

However, in such a game machine, whether or not ART, which is an advantageous state favorable to the player described above, continues is determined simply by whether or not the additional lottery is won, and therefore, the game related to the continuation of ART. There was a problem that the sex became monotonous.

The second to fourth inventions have been made in order to solve the above-mentioned problems, and improve the interest of the game by making the playability related to the continuation of the advantageous state advantageous to the player various. The purpose is to provide a game machine that can play.

(Game machine of the second invention)
The gaming machine of the second invention
A gaming machine (for example, pachislot machine 1) provided with advantageous state control means (for example, main CPU 101) that controls an advantageous state (for example, during ART) that is advantageous for the player when a predetermined condition is satisfied.
The advantageous state includes a first advantageous state (for example, normal ART) and a second advantageous state (for example, continuous challenge).
The advantageous state control means is
Right-giving means for determining whether or not to grant a specific right (for example, CP) that enables the determination of whether or not to extend the gaming period of the first advantageous state in the second advantageous state. (For example, main CPU 101)
When the first advantageous state ends
If the specific right is not granted, the advantageous state is terminated.
When the specific right is granted, it is possible to play the game in the second advantageous state, and it is decided to extend the game period of the first advantageous state in the second advantageous state. It is possible to play the game in the first advantageous state during the extended game period.
The rights granting means can grant a plurality of the specific rights in the advantageous state.
When a plurality of the specific rights are granted, all the specific rights are given even if it has already been decided to extend the gaming period of the first advantageous state in the second advantageous state. It is decided whether or not to extend the gaming period in the first advantageous state until the rights are consumed, and when all the specific rights are consumed, it is decided to extend in the second advantageous state. It is characterized in that the game period of the first advantageous state is added up and the game period of the first advantageous state is extended.

In the gaming machine of the second invention, the advantageous state (for example, during ART) is configured to include the first advantageous state (for example, normal ART) and the second advantageous state (for example, continuous challenge), and in the advantageous state, , It is possible to grant a plurality of specific rights (for example, CP) for performing an additional lottery (determination of whether or not to extend the game period) for the number of games in the first advantageous state in the second advantageous state. Has been done.

In addition, when a specific right is granted when the first advantageous state ends, the process shifts to the second advantageous state, and in the second advantageous state, the specific right is consumed to obtain the first advantageous state. When an additional lottery for the number of games (decision on whether to extend the game period) is performed and the additional lottery is won (when it is decided to extend the game period), the first advantageous state is continued. It is configured to be able to.

Then, when a plurality of specific rights are acquired, the specific rights are not wasted, and all of them are added to the number of games in the first advantageous state (decision as to whether or not to extend the game period). ) Is configured to be used. Therefore, in the second advantageous state, not only is it decided whether or not to continue the advantageous state, but also it is possible to create the possibility that a large number of games are added at one time. The sex can be varied and the interest of the game can be improved.

(Game machine of the third invention)
The gaming machine of the third invention is
A gaming machine (for example, pachislot machine 1) provided with advantageous state control means (for example, main CPU 101) that controls an advantageous state (for example, during ART) that is advantageous for the player when a predetermined condition is satisfied.
The advantageous state includes a first advantageous state (for example, normal ART) and a second advantageous state (for example, continuous challenge).
The advantageous state control means is
With a first right granting means (for example, main CPU 101) that determines whether or not to grant a first right (for example, ART stock) that enables the game to be played in the first advantageous state for a predetermined game period. ,
A second determination of whether or not to grant a second right (eg, CP) that allows the determination of whether or not to extend the gaming period of the first advantageous state in the second advantageous state is made. Including rights granting means (eg, main CPU 101)
When the game of the predetermined game period is performed in the first advantageous state,
If neither the first right nor the second right has been granted, the advantageous state is terminated.
When the first right is granted, it is possible to play the game again in the first advantageous state for the predetermined game period.
When the second right is granted, it is decided to enable the game to be played in the second advantageous state and to extend the game period of the first advantageous state in the second advantageous state. In that case, it is possible to play the game in the first advantageous state during the extended game period.
When both the first right and the second right are granted, the control is characterized in that the game is prioritized in the second advantageous state.

In the gaming machine of the third invention, the advantageous state (for example, during ART) is configured to include the first advantageous state (for example, normal ART) and the second advantageous state (for example, continuous challenge), and in the advantageous state, , The first right to continue the first advantageous state (for example, ART stock), and the additional lottery of the number of games of the first advantageous state in the second advantageous state (decision of whether to extend the game period). A second right to do (eg, CP) is configured to be grantable.

Then, when the first advantageous state ends, if both the first right and the second right are granted, the control is configured to give priority to the transition to the second advantageous state. Has been done. That is, the second right is preferentially digested over the first right.

In this case, in the second advantageous state, when the second right is consumed and an additional lottery (decision as to whether or not to extend the game period) is performed for the number of games in the first advantageous state, and the additional lottery is won ( If it is decided to extend the game period), the first advantageous state can be continued without consuming the first right, and if the additional lottery is not won (the game period can be extended). Even if it is not decided), the first right can be consumed to continue the first advantageous state. Therefore, it is possible to make the game playability various while ensuring a sense of security regarding the continuation of the advantageous state, and it is possible to improve the interest of the game.

Further, even if the state shifts to the second advantageous state when the first advantageous state ends, the first advantageous state continues due to the consumption of the second right or the consumption of the first right. Since the possibility can be left, the expectation for the continuation of the advantageous state can be maintained.

Further, the gaming machine of the third invention is
The second right granting means can grant a plurality of the second rights in the advantageous state.
It is characterized in that, in the second advantageous state, it is determined whether or not to extend the game period of the first advantageous state by the number of the second rights granted.

Further, the gaming machine of the third invention is
In the second advantageous state, even if it has already been decided to extend the gaming period of the first advantageous state, the first advantageous state remains until all the second rights are consumed. It is decided whether or not to extend the game period, and when all the second rights are consumed, the game period of the first advantageous state determined to be extended in the second advantageous state is added up. The game period of the first advantageous state is extended.

Further, in the gaming machine of the third invention, it is possible to acquire a plurality of second rights in an advantageous state, and when a plurality of second rights are acquired, the second right is acquired. The rights are not wasted, and all of them are provided for an additional lottery (decision on whether to extend the game period) for the number of games in the first advantageous state. Therefore, in the second advantageous state, not only is it decided whether or not to continue the advantageous state, but it is also possible to create the possibility that a large number of games are added at one time, so that the game playability is more diverse. It is possible to improve the interest of the game.

(Game machine of the fourth invention)
The gaming machine of the fourth invention is
When a predetermined condition is satisfied, the advantageous state control means (for example, the main CPU 101) that controls the advantageous state (for example, during ART) that is advantageous for the player, and
A gaming machine (eg, pachislot machine 1) including a specific state control means (for example, main CPU 101) that controls a specific state (for example, promotion chance) in which the gaming period of the advantageous state is extended when a specific condition is satisfied. ) And
The specific state is a state in which the game period of the advantageous state is extended based on the continuation of the game in the specific state.
The specific state control means is characterized in that it is possible to determine in advance whether or not to continue a plurality of consecutive games in the specific state.

The gaming machine of the fourth invention has a specific state (for example, promotion chance) in which the gaming period in the advantageous state (for example, during ART) is extended, and in this specific state, the advantageous state is set each time the game continues. It is configured to extend the game period. In addition, it is configured so that it can be determined in advance whether or not to continue a plurality of consecutive games in a specific state. Therefore, it is possible to make the game playability related to the continuation of the advantageous state various, and it is possible to improve the interest of the game.

Further, the gaming machine of the fourth invention is
An effect executing means (for example, a display device 11) for executing an effect,
An effect control means (for example, sub CPU 201) for controlling the effect execution means is provided.
The effect control means
In a predetermined game (for example, the first game) in the specific state, if it is determined to continue the specific state until the next game (for example, the second game) of the predetermined game, the predetermined game In the game following the game of, it is possible to cause the effect executing means to execute the first effect (for example, display of "222").
In the predetermined game in the specific state, if it is determined to continue the specific state until the next game (for example, the third game) following the predetermined game, the next of the predetermined game. The game is characterized in that it is possible for the effect executing means to execute a second effect (for example, display of "223") different from the first effect.

Further, the gaming machine of the fourth invention is
The specific state control means is
In the predetermined game in the specific state, the game period in the advantageous state is extended to the first game period (for example, 111 games).
In the next game of the predetermined game in the specific state, the game period in the advantageous state is extended to a second game period (for example, 222 games) which is longer than the first game period.
In the next game after the predetermined game in the specific state, the game period in the advantageous state can be extended to a third game period (for example, 333 games) which is longer than the second game period. Yes,
The first effect is an effect of notifying the second game period.
The second effect is an effect of notifying a game period exceeding the second game period.

Further, in the gaming machine of the fourth invention, in the current game in the specific state, the game in the specific state is continued until the next game, and the game in the specific state is continued until the next game. It is configured so that the effect to be executed in the next game can be different depending on the case where it is decided.

For example, if it is not decided to continue the game in the specific state until the next game, in the next game, as the first effect, the advantage extended based on the continuation of the specific state until the game. If it is decided to continue the game in the specific state until the next game while notifying the game period of the state, in the next game, as the second effect, the specific state continues until the game. It is configured to notify the game period exceeding the game period in the advantageous state to be extended based on.

With such a configuration, it is possible to definitively notify that the specific state continues, that is, the gaming period in the advantageous state is further extended, and it is possible to further improve the interest of the game. In addition, while specifically notifying the game period of the advantageous state to be added, it is notified that the specific state will continue due to the contradiction of the mode, so that the interest of the game can be further improved.

[Game machine of the fifth invention]
It is known that a conventional gaming machine has a plurality of specific internal states (for example, modes) and makes it possible to suggest the current specific internal state depending on the effect mode (for example, JP-A-2005-287880). See publication).

However, in such a game machine, since it is only determined by the production lottery whether or not to suggest the specific internal state as described above, there is a problem that the suggestion of the specific internal state becomes monotonous. there were.

The fifth invention has been made to solve the above-mentioned problems, and in a gaming machine having a plurality of specific internal states, various suggestions for the specific internal states are made to improve the interest of the game. The purpose is to provide a game machine that can be used.

The gaming machine of the fifth invention is
Profit-giving means (for example, main CPU 101) capable of performing variable display and giving profit based on the derived display result, and
A specific internal state control means (for example, main CPU 101) that has a plurality of specific internal states (for example, a normal mode) and controls transition between the plurality of specific internal states.
An effect executing means (for example, a display device 11) for executing an effect,
An effect control means (for example, sub CPU 201) for controlling the effect execution means is provided.
The effect executing means can execute a predetermined effect (for example, a special effect) suggesting that the result of the transition control by the specific internal state control means has become a predetermined result.
When the effect control means reserves to execute the predetermined effect when the result of the transition control by the specific internal state control means is the predetermined result, and then the predetermined execution condition is satisfied. It is characterized in that the effect executing means executes the predetermined effect.

Further, the gaming machine of the fifth invention is
When a predetermined condition is satisfied, an advantageous state control means (for example, main CPU 101) for controlling the advantageous state (for example, during ART) for the player is further provided.
The plurality of specific internal states include a plurality of lottery states having different probabilities that the predetermined conditions are satisfied.
The predetermined result is controlled by the specific internal state control means from a lottery state in which the probability that the predetermined condition is satisfied is relatively low to a lottery state in which the probability that the predetermined condition is satisfied is relatively high. Including that was decided
The predetermined execution condition is characterized in that a predetermined display result (for example, a combination of symbols of "S_TL lip") is derived.

Further, the gaming machine of the fifth invention is
The plurality of specific internal states further include a precursory state in which the predetermined condition is satisfied but the transition to the advantageous state is awaited.
The predetermined result is further characterized in that the specific internal state control means determines that the transition control from any one of the plurality of lottery states to the precursor state is determined.

The gaming machine of the fifth invention has a plurality of specific internal states (for example, a normal mode), and when there is a change in the specific internal state, a predetermined effect (for example, a special effect) is executed. It is configured so that a predetermined effect is executed when a predetermined execution condition is satisfied after making a reservation.

For example, when there are a plurality of lottery states having different transition probabilities to an advantageous state (for example, during ART) as a plurality of specific internal states, the lottery state becomes an advantageous lottery state, or an advantageous state. If there is a precursory state in which the transition of is awaited, it is reserved to execute a predetermined effect when the precursory state is reached.

Then, when a predetermined display result (for example, a combination of symbols of "S_TL lip") is derived (that is, a predetermined internal winning combination (for example, "normal lip") is established), a predetermined effect is executed. It is configured to be. That is, every time a predetermined display result is derived, the player can expect whether or not the predetermined effect is executed, and the unit game in which the specific internal state is changed and the predetermined effect are executed. It is configured so that it can be different from the unit game to be played. Therefore, when there are a plurality of specific internal states, the suggestions of the specific internal states can be varied.

[Game machine of the sixth invention]
In a conventional game machine, in the event of a power failure (that is, in the event of a power failure), a control circuit that maintains power supply using a backup battery and controls the effect enables processing according to the power failure state. Are known (see, for example, Japanese Patent Application Laid-Open No. 2010-172408).

According to such a game machine, it is considered that the effect content at the time of power failure can be restored at the time of power recovery (that is, at the time of power failure recovery).

However, in such a game machine, if the production content to be restored at the time of power restoration is enormous, the time required for restoration will be long. As a result, there is a possibility that the control circuit side that controls the progress of the game has returned to the game-enabled state, but the control circuit side that controls the effect cannot yet restore the effect content. There was a problem.

Such a problem is particularly serious in a game machine having the above-mentioned AT and ART functions. This is because the player suffers a significant disadvantage if he / she tries to play the game before the navigation function is properly exerted. Therefore, it is considered that there is room for further improvement in the method of restoring the production contents at the time of power restoration.

The sixth invention has been made to solve the above-mentioned problems, and an object of the sixth invention is to provide a game machine capable of appropriately restoring the effect content at the time of recovery from power failure.

The gaming machine of the sixth invention is
An information display means (for example, a display device 11) that displays information about the game, and
In a gaming machine provided with a display control means (for example, a sub-control circuit 200) for controlling the display content of the information display means.
The information display means can display predetermined information corresponding to a predetermined numerical value (for example, a value of an ART game number counter).
The display control means
When the predetermined numerical value fluctuates based on the progress of the game, a specific numerical fluctuation display (for example,, for example,) prior to displaying the predetermined information corresponding to the predetermined numerical value after the fluctuation on the information display means. It is possible to display specific information, which is a count-up display or a count-down display), on the information display means for a predetermined time (for example, 500 ms).
When a restoration process (for example, a backup restoration process by the sub CPU 201) for returning to the state before the power interruption is performed after the power failure occurs in the game machine, the specific information is displayed on the information display means. It is characterized in that the information display means displays the predetermined information corresponding to the current predetermined numerical value.

Further, the gaming machine of the sixth invention is
The game machine further includes a specific game state control means (for example, main CPU 101) that controls a specific game state (for example, during ART) when a predetermined condition is satisfied.
When the predetermined condition is satisfied, the specific game state control means can control the specific game state for a predetermined game period (for example, during 50 games).
The predetermined numerical value corresponds to the remaining gaming period of the specific gaming state.
The display control means
When the remaining gaming period of the specific gaming state fluctuates in the specific gaming state, the information display means displays the predetermined information corresponding to the remaining gaming period of the specific gaming state after the fluctuation. Therefore, it is possible to display the specific information that fluctuates and displays the remaining game period of the specific gaming state on the information display means as the specific numerical fluctuation display.
When the return process is performed in the game machine, the information display means displays the predetermined information corresponding to the remaining game period of the current specific game state without displaying the specific information on the information display means. It is characterized by displaying in.

In the gaming machine of the sixth invention, when a predetermined numerical value (for example, a value of an ART game number counter) fluctuates, the predetermined numerical value is usually displayed for a predetermined period before the fluctuating predetermined numerical value is displayed. It is configured so that the effect of the effect is enhanced by displaying the fluctuation, but if the game machine returns to the state before the power failure after the power failure occurs, the fluctuation display is not performed after the fluctuation. It is configured to display a given (ie, current) number of.

For example, when a predetermined numerical value corresponds to the remaining gaming period of a specific gaming state (for example, during ART), and the remaining gaming period fluctuates, usually, the remaining gaming period is set to the predetermined period (for example, during ART). For example, after the fluctuation is displayed for 500 ms), the remaining game period after the fluctuation is displayed, but when the game machine returns to the state before the power failure after the power failure occurs, the fluctuation display is performed. Instead, it is configured to display the remaining (ie, current) playing period after the change.

That is, when the power is restored, the control for returning to the gameable state is prioritized over the control for enhancing the effect of the effect. Therefore, when the power is restored, the production content can be appropriately restored.

Further, the gaming machine of the sixth invention is
The game machine further includes a game control means (for example, a main control circuit 90) that controls the progress of the game.
The game control means includes command transmission means (for example, communication data transmission processing by the main CPU 101) for transmitting a command to the display control means in one direction.
The command transmitting means transmits a specific command to the display control means when returning to the state before the power failure after the power failure occurs in the game machine.
When the return process is performed, the display control means causes the information display means to display initial information corresponding to an initial value (for example, 0) of the predetermined numerical value until the specific command is received. It is characterized by that.

Further, in the game machine of the sixth invention, the control circuit (display control means) that controls the effect in conjunction with returning to the game-enabled state on the control circuit (game control means) that controls the progress of the game. It is configured so that the player can return to the playable state. At that time, the display of the predetermined numerical value is configured to switch from the initial value to the current numerical value. Therefore, with a simple configuration, it is possible to notify that the game machine returns to the playable state, and it is possible to more appropriately restore the effect content when the power failure is restored.

[Game machine of the seventh invention]
In conventional game machines, there are known game machines that obtain a checksum of data stored in a RAM at the time of power failure and perform a checksum determination process at the time of power recovery (for example, Japanese Patent Application Laid-Open No. 2009-011375 (see). In the gaming machine of JP-A-2009-011375, in the checksum determination process at the time of power restoration, an error notification is performed when the checksum obtained at the time of power restoration does not match the checksum obtained at the time of power failure.

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been compressed due to the complexity of the game playability, and there is a demand for reducing the capacity of processing programs and tables other than the game playability managed by the main control circuit.

The seventh invention has been made to solve the above problems, and an object of the seventh invention is to reduce the capacity of processing programs, tables, etc. other than playability managed by the main control circuit to perform main control. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM of the circuit and enhancing the game playability by utilizing the free space of the ROM corresponding to the increased capacity.

In order to solve the above problems, the seventh invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A power supply means for supplying a power supply voltage (for example, a power supply board 53b and a switching regulator 94) and
When the power supply voltage exceeds a predetermined starting voltage value (for example, 10V), the starting means for outputting the starting signal to the arithmetic processing means (for example, the output processing of the reset signal of the power management circuit 93).
Output of a power failure detection signal of the power management circuit 93 (for example, output of a power failure detection signal) that outputs a power failure signal to the arithmetic processing means when the power supply voltage falls below a predetermined power failure voltage value (for example, 10.5 V). Processing), and equipped with
The arithmetic processing means
A flag register (for example, flag register F) that stores data corresponding to the result of arithmetic processing, and
When the power failure means outputs the power failure signal, all the information stored in the predetermined storage area (for example, the game RAM area) in the second storage means is cumulatively added to calculate the sum value. Sum value calculation means (for example, checksum generation processing),
A sum value that sequentially subtracts information stored in the predetermined storage area from the sum value generated by the sum value calculating means when the latest power failure occurs when the activation means outputs the activation signal. Subtraction means (for example, S122 to S131 during the thumb check process) and
When the subtraction process by the checksum value subtracting means is completed for all the information stored in the predetermined storage area, the subtraction result set in the predetermined bit area (for example, zero flag) in the flag register is set. A gaming machine comprising: a sum value determining means (for example, S134 during a thumb check process) for determining the presence or absence of an abnormality based on the corresponding data.

Further, in the gaming machine of the seventh invention, the sum value calculating means continuously executes a specific instruction (for example, a POP instruction) when adding information stored in the predetermined storage area. 2 bytes of information stored in the above are acquired and added, and the information of the read start address of the information is updated by 2 bytes.
The sum value subtracting means continuously stores the sum value by executing the specific instruction when subtracting the information stored in the predetermined storage area from the sum value generated when the power failure occurs. In addition to acquiring and subtracting bytes of information, the information of the read start address of the information may be updated by 2 bytes.

Further, in the gaming machine of the seventh invention, the arithmetic processing means has a stack pointer capable of setting the address of the predetermined storage area of the second storage means.
Even if the specific instruction executed when the sum value calculating means adds the information stored in the predetermined storage area is a dedicated instruction (for example, a POP instruction) for operating the stack pointer. Good.

According to the gaming machine of the seventh invention, the capacity of processing programs and tables other than game playability is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the ROM corresponding to the increased capacity is increased. It is possible to improve the playability by using the free area of.

[Game machine of the eighth to eleventh invention]
In a conventional game machine, a game machine equipped with a main control device that processes numerical data by using a stack pointer as an operation command has been proposed (see, for example, Japanese Patent Application Laid-Open No. 2005-237737).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The eighth to eleventh inventions have been made to solve the above problems, and an object of the eighth to eleventh inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM of the main control circuit and enhancing the game playability by utilizing the free space of the ROM corresponding to the increased capacity.

In order to solve the above problems, the eighth invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
A dedicated register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means by the stored data. ) And,
The arithmetic processing means executes a predetermined instruction (for example, "BITQ" instruction, "SETQ" instruction, "LDQ" instruction, etc.) capable of designating an address in the second storage means by using the expansion register. A game machine characterized by being possible.

Further, in the gaming machine of the eighth invention, a part of the address that can be specified by the expansion register may be a higher-level address value that constitutes the address.

Further, in order to solve the above problems, the ninth invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling the stop operation of the display column by the stop control means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
A dedicated register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means by the stored data. ) And,
The arithmetic processing means
In the process of checking the stopped state of the display column,
The predetermined read instruction (for example, the "LDQ" instruction) that can specify the address in the second storage means is executed by using the expansion register, and the predetermined read instruction stored in the second storage means is executed. Read the information indicating the variable display status of the display column,
Next, a predetermined OR operation instruction (for example, an "ORQ" instruction) capable of designating an address in the second storage means is executed using the expansion register, and the instruction is stored in the second storage means. The information indicating the state of the variable display of the other display column is read, and the logical sum operation is performed between the information and the information indicating the state of the variable display of the predetermined display column.
After that, the execution of the predetermined OR operation instruction is repeated, and the OR operation of the result of the OR operation and the information indicating the variable display state of each of the remaining display columns is repeated, and the OR is performed on all the display columns. A gaming machine characterized in that it is determined whether or not all display columns are in a stopped state based on the result of an OR operation obtained when the operation is completed.

Further, in the gaming machine of the ninth invention, a part of the address that can be specified by the expansion register may be an upper address value constituting the address.

Further, in order to solve the above problems, the tenth invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling the determination operation of the internal winning combination by the internal winning combination determining means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
A dedicated register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means by the stored data. ) And,
For the internal winning combination determined by the internal winning combination determining means, the winning probability changes according to the set value for adjusting the expected value for determining the internal winning combination related to the privilege grant. Is provided,
The arithmetic processing means
In the process of determining the internal winning combination,
By executing a predetermined addition instruction (for example, "ADDQ" instruction) capable of specifying an address in the second storage means using the expansion register, the setting of the internal winning combination according to the setting to be the lottery target. The current set value is added to the start address of the area where the lottery value for each value is stored, and the address where the lottery value of the internal winning combination for each setting associated with the current set value is stored is specified. A game machine characterized by acquiring the lottery value.

Further, in the gaming machine of the tenth invention, a part of the address that can be specified by the expansion register may be an upper address value constituting the address.

Further, in order to solve the above problems, the eleventh invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When the variable display of the plurality of display columns is stopped by the stop control means, a symbol corresponding to the internal winning combination related to the payout of the game medium is placed on the determination line set across the plurality of display columns. A privilege grant determination means (for example, a winning search process) for determining whether or not the combination of
An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the determination operation by the privilege grant determination means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
It has a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means.
The arithmetic processing means
In the process of determining whether or not the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line.
The game that can be given when a predetermined read command (for example, "LDIN" command) is executed and a combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line. The feature is that the data of the number of payouts of the medium and the judgment data corresponding to the data of the number of payouts indicating the type of the combination of the symbols corresponding to the internal winning combination related to the payout of the game medium are simultaneously acquired. A game machine to play.

Further, in the gaming machine of the eleventh invention, the arithmetic processing means is
In the process of determining whether or not the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line.
The inside related to the payout of the game medium by executing a predetermined judgment command (for example, "JSLAA" command) that can execute the judgment command, the process jump destination address designation command, and the process jump operation command with one command. It may be determined whether or not the combination of symbols corresponding to the winning combination is stopped and displayed.

According to the gaming machines of the eighth to eleventh inventions, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the increase is performed. It is possible to improve the playability by using the free area of the ROM corresponding to the capacity.

[Game machines of the twelfth and thirteenth inventions]
In a conventional game machine, when an abnormality occurs in the data stored in the RAM of the main control unit, it is controlled to the RAM abnormality error state, the progress of the game is disabled, and the setting change mode is entered. When a set value is newly selected / set based on a setting change operation, a game machine has been proposed that releases the disabled state of the progress of the game and makes the progress of the game possible (for example, Japanese Patent Application Laid-Open No. 2007-209810 (see).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The twelfth and thirteenth inventions have been made to solve the above problems, and the object of the twelfth and thirteenth inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM of the main control circuit and enhancing the game playability by utilizing the free space of the ROM corresponding to the increased capacity.

In order to solve the above problems, the twelfth invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
A data transmission means for transmitting command data related to the game operation (for example, S904 (communication data transmission process) during interrupt processing) and
Setting change confirmation means (for example, setting change confirmation processing) that can execute the setting value change processing and the setting value confirmation processing for adjusting the expected value for which the internal winning combination related to the privilege grant is determined,
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a setting value change operation or confirmation operation by the setting change confirmation means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
At the start of the set value change process or the set value confirmation process, the start command generation means for generating the first command data (for example, S43 during the setting change confirmation process) and
At the end of the set value change process or the set value confirmation process, the command generation means at the end of generating the second command data (for example, S57 during the setting change confirmation process) is provided.
The first command data generation process executed by the start command generation means and the second command data generation process executed by the end command generation means are shared. A featured game machine.

Further, in the gaming machine of the twelfth invention, the arithmetic processing means has a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means.
The arithmetic processing means
When generating the first command data, a first value (for example, "005H") is set in a predetermined register (for example, L register) of the general-purpose register, and the generation process is executed.
When generating the second command data, a second value (for example, "004H") may be set in a predetermined register of the general-purpose register to execute the generation process.

Further, in order to solve the above problems, the thirteenth invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
A data transmission means for transmitting command data related to the game operation (for example, S904 (communication data transmission process) during interrupt processing) and
Communication data generation means for creating the command data (for example, setting change command generation / storage process and communication data storage process)
Setting change confirmation means (for example, setting change confirmation processing) that can execute the setting value change processing and the setting value confirmation processing for adjusting the expected value for which the internal winning combination related to the privilege grant is determined,
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a command data generation operation by the communication data generation means and a setting value change operation or confirmation operation by the setting change confirmation means.
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
At the start of the set value change process or the set value confirmation process, the start command generation means for generating the start command data (for example, S43 during the setting change confirmation process) and
At the end of the set value change process or the set value confirmation process, it has an end command generation means (for example, S57 during the setting change confirmation process) that generates end command data.
The start-time command data generation process executed by the start-time command generation means and the end-time command data generation process executed by the end-time command generation means are shared.
The arithmetic processing means has a plurality of general-purpose registers in which a plurality of types of data are stored when the arithmetic processing is executed by the arithmetic processing means.
The arithmetic processing means
In the command data generation process
The communication parameter used among the plurality of types of communication parameters constituting the command data is set in the corresponding general-purpose register among the plurality of general-purpose registers.
The used communication parameters set in the general-purpose register are stored in a predetermined storage area (for example, a communication data temporary storage area) in the second storage means.
When there is an unused communication parameter among the plurality of types of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter at the time of generating the command data is used as the communication parameter. Store in the storage area of
A gaming machine characterized in that a sum value of the command data is generated based on the data stored in the general-purpose register associated with a communication parameter.

Further, in the game machine of the thirteenth invention, in the command data generation process, the value stored in the general-purpose register associated with the communication parameter is added to the value stored in the accumulator of the general-purpose register. Therefore, the sum value of the command data may be generated, and the generated sum value may be stored in the predetermined storage area.

According to the gaming machines of the twelfth and thirteenth inventions, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free space of the ROM of the main control circuit, and the ROM corresponding to the increased capacity is used. The free space can be used to improve playability.

[Game machines of the 14th and 15th inventions]
In a conventional game machine, a game machine that transmits a command from a game control board (main control circuit) to an effect control board (sub control circuit) is known (see, for example, Japanese Patent Application Laid-Open No. 2002-360766).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The 14th and 15th inventions have been made to solve the above problems, and an object of the 14th and 15th inventions is to reduce the capacity of a processing program, a table, etc. managed by a main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM of the main control circuit and enhancing the game playability by utilizing the free space of the ROM corresponding to the increased capacity.

In order to solve the above problems, the fourteenth invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A data transmission means for transmitting communication data related to the game operation (for example, S904 (communication data transmission process) during interrupt processing) and
Communication data generation and storage means (for example, communication data storage processing and communication) that creates the communication data and stores the generated communication data in a communication data storage area provided in a predetermined address range in the second storage means. Data pointer update process)
The communication data generation / storage means
When the communication data is sequentially stored in the communication data storage area from the storage area of the start address of the predetermined address range toward the storage area of the last address, an update instruction, an upper limit determination instruction, and a determination branch instruction are issued. By executing a predetermined update instruction (for example, "ICPLD" instruction) that can be executed by one instruction, the current value of the communication data pointer, which is a parameter related to address specification in the communication data storage area, and the last address. When the current upper limit value of the communication data pointer is compared with the upper limit value of the communication data pointer corresponding to, the communication data pointer is additionally updated, and the current communication data pointer is the upper limit value. If the above is the case, the gaming machine is characterized in that the communication data pointer is changed to the lower limit value of the communication data pointer corresponding to the start address.

Further, in the gaming machine of the fourteenth invention, the communication data generation / storage means stores the communication data pointer in the communication data storage area when the communication data pointer is changed to the lower limit value of the communication data pointer corresponding to the start address. The communication data may be invalidated.

Further, in order to solve the above problems, the fifteenth invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
In the counting process (for example, the medal payout number check process) of the value of predetermined data related to the progress of the game operation,
When updating the value of the predetermined data, the current update instruction (for example, "DCPLD" instruction) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction is executed. The value of the predetermined data is compared with the lower limit of the value of the predetermined data, and if the current value of the predetermined data is larger than the lower limit of the value of the predetermined data, the value of the predetermined data Is subtracted and updated, and if the current value of the predetermined data is equal to or less than the lower limit of the value of the predetermined data, the value of the predetermined data is held at the lower limit.

Further, in the gaming machine of the fifteenth invention, the predetermined data may be the number of payouts of the gaming medium.

According to the gaming machines of the 14th and 15th inventions, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the increase is performed. It is possible to improve the playability by using the free area of the ROM corresponding to the capacity.

[Game machine of the 16th invention]
In conventional game machines, game machines controlled by timer subtraction processing by software are known (see, for example, Japanese Patent Application Laid-Open No. 2004-041261).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The sixteenth invention has been made to solve the above problems, and an object of the sixteenth invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the ROM of the main control circuit. The purpose of the present invention is to provide a gaming machine capable of increasing the free space and using the free area of the ROM corresponding to the increased capacity to improve the game playability.

In order to solve the above problems, the sixteenth invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
In the timer value counting process of the soft timer (for example, timer update process)
By executing a predetermined update instruction (for example, "DCPWLD" instruction) that can execute an update instruction, a lower limit determination instruction, and a determination branch instruction with one instruction, the current timer value of the soft timer and the lower limit of the timer value are executed. While comparing with the value, if the current timer value of the soft timer is larger than the lower limit value, the timer value of the soft timer is subtracted and updated, and if the current timer value of the soft timer is equal to or less than the lower limit value. , A gaming machine characterized in that the timer value of the soft timer is held at the lower limit value.

In the gaming machine of the sixteenth invention, the soft timer may be a 2-byte soft timer.

Further, in the gaming machine of the 16th invention, the arithmetic processing means has a fixed cycle processing means (for example, an interrupt process repeatedly executed at a cycle of 1.1172 msec) that performs processing at a fixed cycle.
The timer value counting process by the soft timer is executed by the fixed cycle processing means.
The elapsed time of the soft timer may be determined based on the cycle in which the constant cycle processing means performs processing and the timer value.

Further, in the gaming machine of the sixteenth invention, the processing by the fixed cycle processing means is executed based on the interrupt signal generated by the timer function (for example, the timer circuit 113) built in the arithmetic processing means. It may be.

According to the gaming machine of the sixteenth invention, the capacity of the processing program and the table managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the increased capacity is increased. It is possible to provide a gaming machine capable of enhancing game playability by utilizing the free area of the ROM of the above.

[Game machines of the 17th and 18th inventions]
In a conventional game machine, a game machine that displays an internal lottery result with a 7-segment LED under the control of a main control circuit is known (see, for example, Japanese Patent Application Laid-Open No. 2008-237337).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The 17th and 18th inventions have been made to solve the above problems, and an object of the 17th and 18th inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM of the main control circuit and enhancing the game playability by utilizing the free space of the ROM corresponding to the increased capacity.

In order to solve the above problems, the seventeenth invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
Multiple 7-segment LEDs that broadcast specific information about the game,
A 7-segment LED driving means for driving the plurality of 7-segment LEDs (for example, a 7-segment LED driving process) and
An LED drive control means that controls the drive operation of the plurality of 7-segment LEDs by the 7-segment LED drive means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The LED drive control means
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read instruction (for example, "LDW" instruction) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A game machine characterized by doing.

Further, in the gaming machine of the seventeenth invention, the arithmetic processing means has a fixed cycle processing means (for example, an interrupt process repeatedly executed at a cycle of 1.1172 msec) that performs processing at a fixed cycle.
The fixed-cycle processing means counts the number of times the processing is executed by the fixed-cycle processing means.
When the counted value is an even number, the control process by the LED drive control means may be executed.

Further, in order to solve the above problems, the eighteenth invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
An instruction display (for example, an instruction monitor) including a plurality of 7-segment LEDs for notifying information regarding a stop operation of the variable display of the plurality of display columns, and
A 7-segment LED driving means for driving the plurality of 7-segment LEDs (for example, a 7-segment LED driving process) and
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling the driving operation of the plurality of 7-segment LEDs by the 7-segment LED driving means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read instruction (for example, "LDW" instruction) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A game machine characterized by doing.

Further, in the gaming machine of the eighteenth invention, the arithmetic processing means is
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and the stored data has an expansion register (for example, a Q register) capable of designating a part of an address in the second storage means.
The arithmetic processing means in the second storage means by executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means using the expansion register. The address of the stop operation instruction information storage area (for example, the navigation data storage area) that is arranged in and stores the information related to the stop operation of the variation display of the plurality of display columns is specified, and the variation display of the plurality of display columns is displayed. Information about the stop operation may be stored in the stop operation instruction information storage area.

According to the gaming machines of the 17th and 18th inventions, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the increase is performed. It is possible to improve the playability by using the free area of the ROM corresponding to the capacity.

[Game machine of the nineteenth invention]
In conventional game machines, a game machine in which a game control board (main control board) controls a reel unit is known (see, for example, Japanese Patent Application Laid-Open No. 2012-034914).

By the way, in the rotation control of the reel (rotating cylinder), the lack of stability of the rotation operation of the reel causes discomfort to the player (especially a skilled person), and there is a possibility that the discomfort may reduce the interest of the game. There is. In this case, the game store may be disadvantaged and the sales of the game machine itself may be affected.

The nineteenth invention has been made to solve the above-mentioned problems, and an object of the nineteenth invention is to suppress a lack of stability in the rotation operation of the reel so as not to give a player discomfort. It is to provide a game machine that can be played.

In order to solve the above problems, the nineteenth invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A setting switch (for example, a setting key type switch 54) for initializing a predetermined area of the second storage means is provided.
The arithmetic processing means
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When the power is restored, the input state of the input port and the output state of the output port at the time of power failure are set, and if the display column is fluctuating at the time of power failure, it is stored in the second storage means. A game return in which the fluctuation control management information (for example, reel control management information) of the display row when a power failure occurs is cleared, and information instructing the fluctuation start of the display row is set in the fluctuation control management information of the display row. A gaming machine characterized by having means (for example, game return processing).

Further, in the gaming machine of the nineteenth invention, the arithmetic processing means is
When the setting switch is in the off state, the process by the game return means is executed, and the process is executed.
When the setting switch is in the ON state, a predetermined area of the second storage means may be initialized without executing the process by the game return means.

According to the gaming machine of the nineteenth invention, it is possible to suppress the lack of stability of the reel rotation operation (variation display operation of the display row) so as not to give the player discomfort.

[Game machine of the twentieth invention]
In conventional game machines, game machines capable of displaying set values (1 to 6) by operating a setting change switch are known (for example, JP-A-2008-245704 and JP-A-2013-042870). See publication).

By the way, conventionally, a gaming machine in which a set value cannot be confirmed is the mainstream while a game is being played in a gaming state advantageous to the player, such as during a bonus game or an ART game. In such a game machine, if a bonus game or an ART game is started immediately after a fraudulent act called "goto", the fraudulent act cannot be confirmed, which may give a disadvantage to the game store. is there.

The twentieth invention has been made to solve the above-mentioned problems, and an object of the twentieth invention is a set value even while a game is being played in a gaming state which is advantageous to the player. It is to provide a game machine capable of confirming information such as, etc., and deterring fraudulent acts such as goto.

In order to solve the above problems, the twentieth invention provides a gaming machine having the following configuration.

A setting switch located in a predetermined position inside the game machine body,
Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) in which information necessary for executing the calculation process by the calculation processing means is stored, and
Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
Based on the internal winning combination determined by the internal winning combination determining means, an advantageous gaming means (for example, a bonus game described later) that executes a gaming state advantageous to the player, and
A setting change confirmation means (for example, S233 during medal reception / start check processing) that can change or confirm a setting value related to the probability that an internal winning combination is determined according to the operation of the setting switch,
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
It is equipped with a game start determination means (for example, medal reception / start check processing) for determining whether or not the game can be started.
The setting change confirmation means can change the setting value related to the probability that the internal winning combination is determined according to the operation of the setting switch when the power is turned on.
When it is determined by the game start determination means that the game can be started and the setting switch is operated, the setting change confirmation of the setting value related to the probability that the internal winning combination is determined regardless of the game state is confirmed. A gaming machine characterized in that it can be confirmed by processing by means.

Further, in the gaming machine of the twentieth invention, when the power is turned on to the gaming machine while the setting switch is operated, the setting change confirmation means initially initializes a predetermined storage area of the second storage means. At the same time, the set value may be changed and the changed set value may be stored in the second storage means.

According to the game machine of the twentieth invention, information such as a set value is confirmed even during a game in a game state advantageous to the player, such as during a bonus game or an ART game. It is possible to deter fraudulent acts such as goto.

[Game machines of the 21st and 22nd inventions]
In the conventional game machine, a game machine provided with a display device for displaying the number of inserted medals is known (see, for example, JP-A-1999-1978983).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The 21st and 22nd inventions have been made to solve the above problems, and the object of the 21st and 22nd inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM of the main control circuit and enhancing the game playability by utilizing the free space of the ROM corresponding to the increased capacity.

In order to solve the above problems, the 21st invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
A game medium detecting means (for example, a medal sensor) that detects a reception state (for example, a medal sensor input state) of the game medium, and
Whether or not the current change mode of the reception state of the game medium detected by the game medium detection means is normal is determined by arithmetic processing based on the reception state of the game medium detected in the previous process. A game machine including a game medium reception state determination means (for example, S255 to S258 during medal insertion check processing).

In the game machine of the twenty-first invention, the game medium reception state determining means logically logically sets a normal value of the reception state of the game medium that can be detected in the current process based on the reception state of the game medium detected in the previous process. It may be calculated by an operation, and the normal value may be compared with the current reception state of the game medium to determine whether or not the change mode of the reception state of the game medium is normal.

Further, in the game machine of the 21st invention, the game medium reception state determination means determines whether or not the change mode of the reception state of the game medium is normal by using 2 bits in the 1-byte information. You may.

In order to solve the above problems, the 22nd invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
Display means (for example, first LED to third LED) that notifies information indicating the number of input of the game medium in a display mode corresponding to the number of input of the game medium.
An arithmetic processing means (for example, main CPU 101, medal insertion processing) that performs arithmetic processing for controlling the notification operation by the display means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
It is characterized in that lighting control data for notifying information indicating the number of input of the game medium in a display mode corresponding to the number of input of the game medium is generated by a logical operation process based on the number of input of the game medium. A game machine to play.

Further, in the game machine of the 22nd invention, in the logical operation process, the lighting control data of the game medium may be generated from 3-bit data of information in 1 byte.

According to the gaming machines of the 21st and 22nd inventions, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free space of the ROM of the main control circuit, and the ROM of the increased capacity is used. The free space can be used to improve playability.

[Game machines of the 23rd and 24th inventions]
In a conventional game machine, a game machine in which a main board (main control board) and a sub board (sub control board) are connected by communication and a command is transmitted from the main board to the sub board is known (for example, a patent). See No. 5725590).

By the way, conventionally, the communication between the main control board that controls the game and the sub-control board that controls the effect is one-way communication from the main control board to the sub-control board, and when the power is turned on. There is a large gap between the startup time of the main control board and that of the sub control board. Therefore, the communication connection between the main control board and the sub control board at the time of turning on the power may become unstable.

The 23rd and 24th inventions have been made to solve the above problems, and an object of the 23rd and 24th inventions is a main control board (main control means) and a sub control board (main control means) at the time of power-on. It is to provide a game machine capable of stable operation of communication between sub-control means).

In order to solve the above problems, the 23rd invention provides a gaming machine having the following configuration.

A main control means (for example, a main control circuit 90) for transmitting communication data related to a game operation is provided.
The main control means
During the control process by the main control means, the interrupt process is executed at a predetermined cycle, and when the interrupt process is executed, if there is no communication data related to the game operation, the interrupt process execution means (for example,) that transmits a non-operation command. , Interrupt processing),
It has a power recovery processing execution means (for example, power-on processing) that executes a predetermined power recovery processing when the power is restored.
After the power restoration process is started, the power restoration processing executing means waits until the interrupt processing execution means can execute the interrupt processing (for example, S7 and S8 during the power-on processing). Do,
The interrupt processing execution means is a gaming machine characterized in that the interrupt processing is executed and the non-operation command is transmitted to the sub control means at the end of the standby by the power recovery processing execution means.

Further, in the gaming machine of the 23rd invention, the main control means is
A timer circuit (for example, timer circuit 113) that measures the predetermined cycle, and
It has an interrupt circuit (for example, an interrupt controller 112) that generates an interrupt signal for executing the interrupt process based on the timeout signal of the timer circuit.
The power recovery processing execution means
After setting the initial setting for generating the timeout signal in the timer circuit at the predetermined cycle, a process of waiting until the interrupt process can be executed by the interrupt process executing means is performed.
The end of the standby may be determined based on the presence or absence of the occurrence of the timeout signal in the timer circuit.

Further, in order to solve the above problems, the 24th invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
Communication data generation means for creating command data related to game operations (for example, setting change command generation / storage process and communication data storage process),
During the control process by the arithmetic processing means, the interrupt processing is executed at a predetermined cycle, and when the interrupt processing is executed, if there is no command data related to the game operation, the interrupt processing execution means (for example,) that transmits a non-operation command. , Interrupt processing),
Power recovery processing execution means (for example, power-on processing) that executes a predetermined power recovery processing when the power is restored,
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
After the power restoration process is started, the power restoration processing executing means waits until the interrupt processing execution means can execute the interrupt processing (for example, S7 and S8 during the power-on processing). Do,
The interrupt processing execution means executes the interrupt processing and transmits the no-operation command at the end of the standby by the power recovery processing execution means.
The arithmetic processing means
It has a plurality of general-purpose registers in which a plurality of types of data are stored when the arithmetic processing is executed by the arithmetic processing means.
The command data is composed of a command type, a plurality of communication parameters, and a sum value.
The plurality of communication parameters are each assigned to the plurality of general-purpose registers.
The communication data generation means is
After setting the communication parameter in the general-purpose register assigned to the communication parameter according to the command type of the command data, the communication parameter set in the general-purpose register is stored in a predetermined storage in the second storage means. Store in an area (for example, communication data temporary storage area)
Even if there is a communication parameter that is not used based on the command type of the command data among the plurality of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter is used as the communication parameter. Stored in the predetermined storage area as
A gaming machine characterized in that a sum value of the command data is generated based on the command type and the data stored in the general-purpose register assigned to the communication parameter.

Further, the gaming machine of the twenty-fourth invention includes a power supply monitoring means (for example, a power supply monitoring port) for monitoring the state of the power supply voltage.
The arithmetic processing means
If the power supply voltage state is not stable, wait until the power supply voltage state stabilizes.
After initializing the timer circuit, serial communication circuit, and random number circuit of the arithmetic processing means on the condition that the state of the power supply voltage is stable, the predetermined area of the second storage means is used. 2 Check if the storage means are normal and check
The no-operation command may be transmitted on condition that the second storage means is normal.

According to the gaming machines of the 23rd and 24th inventions, it is possible to stably operate the communication between the main control board and the sub control board when the power is turned on.

[Game machines of the 25th and 26th inventions]
In a conventional game machine, the stop control of the variable display of the reel symbol is performed based on the internal winning combination and the stop operation of the player, the winning judgment is made by the combination of the symbols, and the hopper (medal payout device) is based on the result of the winning judgment. ) Is controlled to control the payout of medals (see, for example, Japanese Patent Application Laid-Open No. 2008-119498).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The 25th and 26th inventions have been made to solve the above problems, and the purpose of the 25th and 26th inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM of the main control circuit and enhancing the game playability by utilizing the free space of the ROM corresponding to the increased capacity.

In order to solve the above problems, the 25th invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling the stop operation of the display column by the stop control means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
An expansion register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means and a part of an address in the second storage means can be specified by the stored data.
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of specifying an address in the second storage means using the expansion register, the detection result of the stop operation by the stop operation detection means can be obtained. The stop operation detection result acquisition means to be acquired (for example, S714 during the reel stop control process) and
When a player's stop operation with respect to a predetermined display row is detected by the stop operation detecting means, by executing the predetermined read command, the player is arranged in the second storage means and the predetermined display row is displayed. A stop control data storage area setting means for designating the address of the stop control data storage area for storing the stop control data of the variation display (for example, the source code "LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)" in FIG. 139) and A game machine characterized by having.

Further, in the gaming machine of the 25th invention, a part of the address that can be specified by the expansion register may be an upper address value constituting the address.

Further, in order to solve the above problems, the 26th invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, the combination of a plurality of types of symbols corresponding to the plurality of types of internal winning combinations is set across the plurality of display columns. Priority stop symbol determination means (for example, pull-in priority acquisition process) for determining a combination of symbols to be preferentially stopped and displayed on the determined determination line,
An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the stop operation of the display column by the stop control means and the determination operation of the combination of symbols to be stopped and displayed by the priority stop symbol determination means.
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
An expansion register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means and a part of an address in the second storage means can be specified by the stored data.
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of specifying an address in the second storage means using the expansion register, the detection result of the stop operation by the stop operation detection means can be obtained. The stop operation detection result acquisition means to be acquired (for example, S714 during the reel stop control process) and
When the player's stop operation with respect to the predetermined display row is detected by the stop operation detecting means, by executing the predetermined read command, the player is arranged in the second storage means and the predetermined display row is displayed. A stop control data storage area setting means for designating the address of the stop control data storage area for storing the stop control data of the variation display (for example, the source code "LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)" in FIG. 139) and
In the process of preferentially determining the combination of symbols to be stopped and displayed on the determination line by the priority stop symbol determining means, one comparison determination instruction, a process jump destination address designation instruction, and a process jump operation instruction. By executing a predetermined determination command (for example, "JCP" instruction) that can be executed by the command, a specific display column (for example, "JCP" command) currently being determined is combined with the combination of symbols corresponding to the internal winning combination to be determined. , Right reel 3R), it is determined whether or not a predetermined combination of symbols (for example, "ANY" combination) in which the stop symbol on the determination line is arbitrary is included, and the internal winning combination to be determined is used. When it is determined that the combination of the corresponding symbols includes the combination of the predetermined symbols, the optional combination handling processing means for prohibiting the stop display of the combination of the symbols corresponding to the internal winning combination to be determined (for example, A gaming machine characterized by having S683) during the attraction priority acquisition process.

Further, in the gaming machine of the 26th invention, a part of the address that can be specified by the expansion register may be an upper address value constituting the address.

According to the gaming machines of the 25th and 26th inventions, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free space of the ROM of the main control circuit, and the ROM of the increased capacity is used. The free space can be used to improve playability.

[Game machine of the 27th to 29th inventions]
In the conventional game machine, there is known a game machine that controls the stop of a symbol by using a pull-in priority table at the time of stop control of a symbol (see, for example, Japanese Patent Application Laid-Open No. 2007-175450).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The 27th to 29th inventions have been made to solve the above problems, and an object of the 27th to 29th inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM of the main control circuit and enhancing the game playability by utilizing the free space of the ROM corresponding to the increased capacity.

In order to solve the above problems, the 27th invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, the combination of a plurality of types of symbols corresponding to the plurality of types of internal winning combinations is set across the plurality of display columns. Priority stop symbol determination means (for example, pull-in priority acquisition process) for determining a combination of symbols to be preferentially stopped and displayed on the determined determination line,
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling an operation of determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
It has an extension register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means and a part of an address in the second storage means can be specified by the stored data. ,
In the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means.
The arithmetic processing means
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means using the expansion register, the second storage means is arranged and inside the second storage means. The winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) that specifies the address of the winning flag data storage area (for example, the winning request flag storage area) that stores the winning flag data corresponding to the winning combination, and
A winning flag data storage area (for example,) for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line by executing the predetermined reading command (for example, The winning flag storage area specifying means (for example, S686 during the attraction priority acquisition process) that specifies the address of the winning operation flag storage area), and
A gaming machine characterized by having a logical product calculation means (for example, S686 during a pull-in priority acquisition process) that performs a logical product calculation of the winning flag data and the corresponding winning flag data.

Further, in the gaming machine of the 27th invention, in the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, the combination of symbols corresponding to the internal winning combination to be determined is used. When a predetermined combination of symbols (for example, "ANY" combination) in which the stop symbol on the determination line in the specific display column (for example, the right reel 3R) currently being determined is arbitrary is included,
The arithmetic processing means includes an address designation process of the winning flag data storage area by the winning flag storage area designating means, an address designation process of the winning flag data storage area by the winning flag storage area designating means, and a logical product operation. The logical product operation processing by the means may not be executed.

Further, in order to solve the above problems, the 28th invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, the combination of a plurality of types of symbols corresponding to the plurality of types of internal winning combinations is set across the plurality of display columns. Priority stop symbol determination means (for example, pull-in priority acquisition process) for determining a combination of symbols to be preferentially stopped and displayed on the determined determination line,
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling an operation of determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means by the stored data. ) And,
In the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means.
The arithmetic processing means
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means using the expansion register, the second storage means is arranged and inside the second storage means. The winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) that specifies the address of the winning flag data storage area (for example, the winning request flag storage area) that stores the winning flag data corresponding to the winning combination, and
A winning flag data storage area (for example,) for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line by executing the predetermined reading command (for example, The winning flag storage area specifying means (for example, S686 during the attraction priority acquisition process) that specifies the address of the winning operation flag storage area), and
A logical product calculation means (for example, S686 during the attraction priority acquisition process) that performs a logical product operation of the winning flag data and the corresponding winning flag data, and
Priority data table acquisition means (for example, pull-in priority) for acquiring a data table that defines the priority of the combination of symbols to be stopped and displayed among the combinations of the plurality of types of symbols by executing the predetermined read command. A gaming machine characterized by having S687) during acquisition processing.

Further, in the game machine of the 28th invention, in the process of determining the combination of the symbols to be preferentially stopped and displayed by the priority stop symbol determining means, the combination of the symbols corresponding to the internal winning combination to be determined is used. When a predetermined combination of symbols (for example, "ANY" combination) in which the stop symbol on the determination line in the specific display column (for example, the right reel 3R) currently being determined is arbitrary is included,
The arithmetic processing means includes an address designation process of the winning flag data storage area by the winning flag storage area designating means, an address designation process of the winning flag data storage area by the winning flag storage area designating means, and a logical product operation. The logical product operation processing by the means may not be executed.

Further, in order to solve the above problems, the 29th invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
Error detection means (for example, illegal hit check processing) that determines whether or not an illegal hit error has occurred, and
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a determination operation by the error detecting means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
It has an extension register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means and a part of an address in the second storage means can be specified by the stored data. ,
In the process of determining whether or not an illegal hit error has occurred by the error detecting means,
The arithmetic processing means
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means using the expansion register, the second storage means is arranged and the plurality. Winning flag that specifies the address of the winning flag data storage area (for example, the winning operation flag storage area) that stores the winning flag data corresponding to the combination of symbols that are stopped and displayed on the judgment line set across the display column of Storage area designation means (for example, S781 during illegal hit check processing) and
A logical product calculation means (for example, S784 during illegal hit check processing) that performs a logical product operation of the winning flag data stored in the winning flag data storage area and the winning flag data indicating the corresponding internal winning combination. When,
It has an error determining means (for example, S785 during the illegal hit check process) for determining whether or not an illegal hit error has occurred based on the calculation result by the AND calculation means.
A gaming machine characterized in that the configuration of the winning flag data storage area (for example, the winning request flag storage area) in which the winning flag data is stored is the same as the configuration of the winning flag data storage area.

Further, in the gaming machine of the 29th invention, a part of the address that can be specified by the expansion register may be a higher-level address value that constitutes the address.

Further, in the gaming machine of the 29th invention, the arithmetic processing means has an error processing means for performing error processing when it is determined by the error detecting means that there is an illegal hit error.
The error processing means may visually notify the illegal hit error and stop the game until the illegal hit error is cleared.

According to the gaming machines of the 27th to 29th inventions, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free space of the ROM of the main control circuit, and the ROM of the increased capacity is used. The free space can be used to improve playability.

[Game machine of the thirtieth invention]
In conventional game machines, game machines that transmit command data from a game control board (main control board) to an effect control board (sub control board) are known (for example, Japanese Patent Application Laid-Open No. 2013-027655 and Japanese Patent Application Laid-Open No. 2014). -033751 (see).

By the way, in recent years, with the diversification of playability, there is a tendency that the processing related to playability increases in the effect control by the sub-control circuit. As a result, a fraudulent act called "goto" that falsifies the communication data transmitted from the main control circuit to the sub control circuit has occurred, causing damage to the amusement store. On the other hand, conventionally, as proposed in, for example, Japanese Patent Application Laid-Open No. 2014-033751 and the like, measures have been taken to prevent the transmission data from being lumped in the main control circuit. However, the addition of such anti-goto processing causes a problem that the program capacity of the main control circuit is compressed.

The thirtieth invention has been made to solve the above-mentioned problems, and an object of the thirtieth invention is to deter fraudulent acts and prevent fraud without performing fraud prevention processing on transmitted data. The purpose of the present invention is to provide a game machine capable of eliminating the pressure on the program capacity of the main control circuit due to processing.

In order to solve the above problems, the thirtieth invention provides a gaming machine having the following configuration.

A data transmission means (for example, a main control circuit 90) for transmitting communication data related to the game operation, and
A communication data generation means for creating the communication data (for example, communication data storage processing) and
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a communication data generation operation by the communication data generation means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
It has a plurality of general-purpose registers in which a plurality of types of data are stored when the arithmetic processing is executed by the arithmetic processing means.
The arithmetic processing means
In the communication data generation process by the communication data generation means
A plurality of types of communication parameters constituting the communication data are assigned to the plurality of general-purpose registers, respectively.
Among the plurality of types of communication parameters constituting the communication data, the communication parameter is set in the corresponding general-purpose register among the plurality of general-purpose registers based on the type of the communication data.
The communication parameters set in the general-purpose register are stored in a predetermined storage area (communication data temporary storage area) in the second storage means.
Among the plurality of types of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter when the communication data is generated is stored as the communication parameter in the predetermined storage area.
A gaming machine characterized in that a sum value of the communication data is generated based on data set in the plurality of general-purpose registers according to the plurality of types of communication parameters.

Further, in the gaming machine of the thirtieth invention, when the predetermined storage area in the second storage means is full, the communication data generation means sets the communication parameters set in the plurality of general-purpose registers. The communication data generation process may be terminated without storing in the predetermined storage area in the second storage means.

According to the gaming machine of the thirtieth invention, fraudulent activity can be suppressed without performing fraud prevention processing on the transmitted data (communication data), and the pressure on the program capacity of the main control circuit due to the fraud prevention processing is eliminated. be able to.

[Game machine of the 31st invention]
In the conventional game machine, a game machine having a function of updating the number of credits according to the number of medals paid out by the control of the main control circuit is known (for example, see JP2009-077777). ).

By the way, conventionally, in games during ART or bonus, medals are paid out more frequently, but at this time, the payout interval for each medal is often controlled uniformly (constantly). In this case, a wasteful waiting time occurs during the medal payout period. Therefore, for example, in a long-time game such as ART, the game period becomes unnecessarily long, which may be a mental burden on the player.

The 31st invention has been made to solve the above problems, and an object of the 31st invention is to reduce unnecessary waiting time and reduce the mental burden on the player during the medal payout period. It is to provide a possible gaming machine.

In order to solve the above problems, the 31st invention provides a gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When the variable display of the plurality of display columns is stopped by the stop control means, a symbol corresponding to the internal winning combination related to the payout of the game medium is placed on the determination line set across the plurality of display columns. A privilege grant determination means (for example, a winning search process) for determining whether or not the combination of
When it is determined by the privilege grant determination means that the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line, the game medium payout means (for example, the game medium payout means) for paying out the game medium. , Winning check, medal payout processing),
A game medium storage means (for example, a credit function) for storing the game medium, and
A calculation processing means (for example, main CPU 101) that performs calculation processing for controlling the payout operation of the game medium by the game medium payout means is provided.
The arithmetic processing means
It is determined by the privilege grant determination means that the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line, and the game medium stored in the game medium storage means. When the number of stored games is less than the upper limit, the game medium adding means (for example, S805 during the winning check / medal payout process) that adds 1 to the number of stored game media is used.
The game medium is given when the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed after the game medium is added to the stored number of the game media by the game medium adding means. A payout end determination means (for example, S807 during the winning check / medal payout process) for determining whether or not the total number of payouts of the game medium has been paid out, and
When it is determined by the payout end determination means that the payout of the total number of payouts of the game medium has not been completed, the weight generation means (for example, a winning check) that generates a weight that invalidates the operation related to the game for a predetermined period A gaming machine characterized by having S808) in the process of paying out medals.

Further, in the gaming machine of the 31st invention, the arithmetic processing means has an interrupt processing executing means for executing an interrupt processing at a predetermined cycle.
In the wait in which the operation related to the game by the wait generating means is invalid, the interrupt processing by the interrupt processing executing means may be executed a predetermined number of times.

According to the game machine of the thirty-first invention, it is possible to reduce unnecessary waiting time and reduce the mental burden on the player during the medal (game medium) payout period.

[Game machine of the 32nd invention]
In a conventional game machine, a program and a table are arranged in a fixed area in a ROM mounted on a main control board (see, for example, Japanese Patent Application Laid-Open No. 2012-110635).

By the way, the programs and tables that can be arranged in the ROM of the main control board like the game machine described in JP2012-110635A are limited by the rules of the game machine industry, and the ROM of the main control board. The extensibility of programs and tables within is extremely poor.

The 32nd invention has been made to solve the above problems, and an object of the 32nd invention is to provide a gaming machine capable of enhancing the expandability of a program and a table in a ROM of a main control board. It is to be.

In order to solve the above problems, the 32nd invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The first storage means includes a game storage area (for example, a game ROM area) in which information necessary for executing a process related to the game playability of the game performed by the player is stored, and the game memory. An out-of-specification storage area (for example, an out-of-specification ROM area) is provided, which is arranged in an area different from the area and stores information necessary for executing processing that is not related to the playability of the game performed by the player. A game machine characterized by being.

Further, in the gaming machine of the 32nd invention, the second storage means is a gaming work area in which information necessary for executing a process related to the playability of the game executed by the player is temporarily stored. And a game temporary storage area (for example, a game RAM area) including a game stack area, which is arranged in an area different from the game temporary storage area and is involved in the game playability of the game performed by the player. A non-standard work area for temporarily storing information necessary for executing a process and a non-standard temporary storage area (for example, a non-standard RAM area) including a non-standard stack area may be provided. ..

Further, in the gaming machine of the 32nd invention, the arithmetic processing means has a stack pointer as a dedicated register.
The arithmetic processing means
When executing a program stored in the non-standard storage area of the first storage means, the address of the non-standard stack area of the second storage means is set in the stack pointer.
When terminating the program stored in the non-standard storage area of the first storage means, the game of the second storage means saved when executing the program stored in the non-standard storage area. The address of the stack area may be set in the stack pointer to return to the program stored in the game storage area of the first storage area.

According to the gaming machine of the 32nd invention, the expandability of the program and the table in the ROM of the main control board can be enhanced.

1 ... Pachislot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 6 ... Information display, 11 ... Display device, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72 ... Sub control board, 90 ... Main control circuit, 91 ... Microprocessor, 101 ... Main CPU, 102 ... Main ROM, 103 ... Main RAM, 107 ... Arithmetic circuit, 114 ... First serial communication circuit, 115 ... Second serial Communication circuit, 200 ... Sub control circuit, 201 ... Sub CPU 201, 301 ... First interface board, 302 ... Second interface board

Claims (1)

A game control means that controls the game,
A production control means that controls the production and
In a game machine equipped with an effect execution means capable of executing an effect
The game control means
Arithmetic processing means that performs arithmetic processing to control the game,
A first storage means in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means for storing information necessary for executing the calculation process by the calculation processing means is provided.
There is a specific state as a state controlled by the execution of the arithmetic processing by the arithmetic processing means.
The specific state may at least continue from the start of the specific state to the elapse of the first period, or may continue from the start of the specific state to the elapse of a second period longer than the first period.
The effect executing means can suggest that the specific state continues at least until the lapse of the second period at a timing from the start of the specific state to before the lapse of the first period.
The arithmetic processing means
In the timer value counting process of a 2-byte soft timer
By executing a predetermined update instruction that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, the current timer value of the soft timer is compared with the lower limit value of the timer value, and the present If the timer value of the soft timer is larger than the lower limit value, the timer value of the soft timer is subtracted and updated, and if the current timer value of the soft timer is equal to or less than the lower limit value, the timer value of the soft timer is set. Hold at the lower limit and
After that, the gaming machine characterized in that the update start address of the soft timer in the second storage means is updated by 2 bytes.

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