JP2021002633A - Oxide semiconductor processing method and thin film transistor manufacturing method - Google Patents

Abstract

To provide a processing method of easily obtaining a desired shape in processing of an oxide semiconductor layer in which two oxide semiconductors having different crystallinities are laminated.SOLUTION: In a processing method, a semiconductor laminate in which a first semiconductor film S1 made of an oxide semiconductor and a second semiconductor film S2 made of an oxide semiconductor having higher crystallinity than the oxide semiconductor constituting the first semiconductor film are laminated from the substrate side is processed and molded by an ion milling method.SELECTED DRAWING: Figure 5

Description

The present invention relates to a method for processing an oxide semiconductor and a method for manufacturing a thin film transistor.

In recent years, a thin film transistor (TFT) using an oxide semiconductor layer such as an In-Ga-Zn-O system (IGZO) as a channel layer has been actively developed. As a method for manufacturing a thin film transistor using an oxide semiconductor layer as a channel layer, for example, in Patent Document 1, after forming an oxide semiconductor layer on a gate insulating layer by sputtering, a metal film is formed on the oxide semiconductor layer. A method of forming and etching the metal film to form a source electrode and a drain electrode is disclosed. In Patent Document 1, in order to form an oxide semiconductor layer having an excellent film quality at a high film forming rate, a first oxide semiconductor having low crystallinity is supplied by supplying only argon as a sputtering gas when sputtering is performed. It is described that a layer is first formed, and then a second oxide semiconductor layer having high crystallinity is formed by supplying a mixed gas of argon and oxygen as a sputtering gas.

International Publication WO2018 / 225822

By the way, when processing is performed by chemical etching such as wet etching on a laminated product of a plurality of oxide semiconductor layers having different crystallinity as described above, it is caused by the difference in film quality in the stacking direction (film thickness direction). , It may be difficult to obtain the desired shape. That is, since the oxide semiconductor layer having low crystallinity has a higher etching rate for chemical etching than the oxide semiconductor layer having higher crystallinity, when chemical etching is performed on these, there are two differences due to the difference in etching rate. A step may occur at the boundary of the oxide semiconductor layer. In particular, as described above, when the oxide semiconductor layer having high crystallinity is laminated on the oxide semiconductor layer having low crystallinity, when chemical etching is performed on these, the oxide semiconductor layer in the upper layer is formed. In comparison, the lower oxide semiconductor layer may be deeply scraped in the direction perpendicular to the stacking direction, and the processed cross section may be deepened. Therefore, for example, when a protective film or the like is applied in a subsequent process, it may be difficult for the protective film to reach the processed cross section of the oxide semiconductor layer underneath.

The present invention has been made in view of such a problem, and provides a processing method for easily obtaining a desired shape in the processing of an oxide semiconductor layer in which two oxide semiconductors having different crystallinities are laminated. This is the main issue.

As a result of diligent studies to solve the above problems, the present invention, when the ion milling method is used as the etching method, oxidizes even if two oxide semiconductors having different crystallinities are laminated. It has been found that etching can be performed at the same etching rate regardless of the difference in crystallinity of the physical semiconductor. That is, since the ion milling method is a physical etching that does not involve a chemical reaction, it was found that the etching rate does not differ greatly depending on the difference in crystallinity, and the present invention was conceived.

That is, the method for processing an oxide semiconductor of the present invention includes a first semiconductor layer made of an oxide semiconductor and a second semiconductor layer made of an oxide semiconductor having a higher crystallinity than the oxide semiconductor constituting the first semiconductor layer. Is characterized in that semiconductor laminates laminated in order from the substrate side are processed and formed by an ion milling method.

With such a processing method, the semiconductor laminate is processed by the ion milling method, so that the first semiconductor layer and the second semiconductor layer having different crystallinities can be etched at the same speed. .. Therefore, it is possible to prevent a situation in which only the first semiconductor layer having relatively low crystallinity is deeply scraped in the direction perpendicular to the stacking direction, which may occur when wet etching is performed, and it becomes easy to obtain a desired cross-sectional shape. ..
Further, since the first semiconductor layer and the second semiconductor layer can be etched at the same speed, the step at the boundary between the processed cross sections of the first semiconductor layer and the second semiconductor layer should be reduced. Can be done. Therefore, when a protective film or the like is applied in a subsequent step, the protective film can be easily spread over any of the processed cross sections of the first semiconductor layer and the second semiconductor layer.

As an aspect of the semiconductor laminate that makes the effect of the present invention remarkable, the semiconductor laminate processed by the processing method comprises the first semiconductor layer made of an amorphous oxide semiconductor and the second semiconductor layer. Can be mentioned as being composed of a crystalline oxide semiconductor.

As an aspect of the semiconductor laminate that makes the effect of the present invention remarkable, the composition of the oxide semiconductor constituting the first semiconductor layer and the composition of the oxide semiconductor constituting the second semiconductor layer are the same. Some can be mentioned.

As a specific embodiment of the semiconductor laminate in the method for processing an oxide semiconductor, the oxide semiconductor constituting the first semiconductor layer and the second semiconductor layer may be IGZO.

As a specific aspect of the semiconductor laminate in the method for processing an oxide semiconductor, it was confirmed at a diffraction angle of 2θ = 31 ° in the X-ray diffraction measurement by the θ-2θ method using Cu—Kα rays for the second semiconductor layer. It is preferable that the half-value full width of the peak is smaller than the half-value full width of the peak confirmed in the vicinity of the diffraction angle 2θ = 31 ° in the X-ray diffraction measurement with respect to the first semiconductor layer.

Further, the method for manufacturing a thin film of the present invention is a method for manufacturing a thin film in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode are sequentially arranged on a substrate, and is an oxide. A semiconductor lamination step of laminating a first semiconductor layer made of a semiconductor and a second semiconductor layer made of an oxide semiconductor having a higher crystallinity than the oxide semiconductor constituting the first semiconductor layer in order from the substrate side. It is characterized by having a semiconductor processing step of processing the laminated first semiconductor layer and the second semiconductor layer by an ion milling method to form the oxide semiconductor layer.

With such a method for manufacturing a thin film transistor, the same effect as the above-mentioned method for processing an oxide semiconductor can be obtained.

According to the present invention configured in this way, it is possible to provide a processing method that makes it easy to obtain a desired shape in the processing of an oxide semiconductor layer in which two oxide semiconductors having different crystallinities are laminated.

The vertical sectional view which shows typically the structure of the thin film transistor of this embodiment. The cross-sectional view which shows typically the manufacturing process of the thin film transistor of the same embodiment. The cross-sectional view which shows typically the manufacturing process of the thin film transistor of the same embodiment. The figure which shows typically the structure of the sputtering apparatus used in the semiconductor layer formation process of the thin film transistor of the same embodiment. An SEM photograph explaining the effect of the difference in the processing method on the processed cross section of the oxide semiconductor layer.

The thin film transistor and the manufacturing method thereof according to the embodiment of the present invention will be described below.

<1. Thin film transistor>
The thin film transistor 1 of the present embodiment is a so-called bottom gate type. Specifically, as shown in FIG. 1, it has a substrate 2, a gate electrode 3, a gate insulating layer 4, an oxide semiconductor layer 5 as a channel layer, a source electrode 6, and a drain electrode 7. They are arranged (formed) in this order from the substrate 2 side. Each part will be described in detail below.

The substrate 2 is made of a material capable of transmitting light, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), acrylic, polyimide and other plastics (synthetic resin). It may be composed of glass or the like.

A gate electrode 3 is provided on the surface of the substrate 2. The gate electrode 3 is made of a material having high conductivity, and may be made of one or more metals selected from, for example, Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag and the like. Further, the conductivity of metal oxides such as Al-Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and In-Ga-Zn-O (IGZO). It may be composed of a membrane. The gate electrode 3 may be composed of a single-layer structure of these conductive films or a laminated structure of two or more layers.

A gate insulating layer 4 is arranged on the gate electrode 3. The gate insulating layer 4 is made of a material having high insulating properties, and is selected from, for example, SiO ₂ , SiN _x , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , Hf _{2 and the} like 1 It may be an insulating film containing one or more oxides. The gate insulating layer 4 may have a single-layer structure or a laminated structure of two or more layers of these conductive films.

An oxide semiconductor layer 5 is arranged on the gate insulating layer 4. The oxide semiconductor layer 5 has a two-layer structure in which a first semiconductor layer 5a and a second semiconductor layer 5b made of an oxide semiconductor are arranged in order from the substrate 2 side.

The first semiconductor layer 5a and the second semiconductor layer 5b are preferably composed of oxide semiconductors having the same composition as each other, and preferably composed of oxide semiconductors composed of the same constituent elements and unavoidable impurities. .. In the present embodiment, both the first semiconductor layer 5a and the second semiconductor layer 5b are made of an oxide semiconductor containing an oxide containing In as a main component. The oxide containing In is, for example, an oxide such as In-Ga-Zn-O, In-Al-Mg-O, In-Al-Zn-O or In-Hf-Zn-O.

The first semiconductor layer 5a and the second semiconductor layer 5b are composed of oxide semiconductors having different crystallinities (degrees) from each other. Specifically, the crystallinity of the oxide semiconductor constituting the second semiconductor layer 5b is configured to be higher than the crystallinity of the oxide semiconductor constituting the first semiconductor layer 5a.

The lower the crystallinity of the first semiconductor a, the faster the film forming speed in the first film forming step described later, and the higher the productivity. Therefore, the oxide semiconductor constituting the first semiconductor layer a is preferably as low as its crystallinity, and more preferably amorphous.

The higher the crystallinity of the second semiconductor layer 5b forming the interface between the source electrode 6 and the drain electrode 7, the more oxygen defects can be reduced at the interface, and the gate threshold voltage _Vth of the thin film transistor 1 (drain current _Id = it is possible to increase the gate voltage _{V g)} in 1 nA. Therefore, the second semiconductor layer 5b is made of a crystalline oxide semiconductor, and the higher the crystallinity, the more preferable.

The high crystallinity (degree) of the oxide semiconductors constituting the first semiconductor layer 5a and the second semiconductor layer 5b is determined by, for example, XRD (X-ray diffraction) by the θ-2θ method using a Cu light source (Cu—Kα ray). ) It can be confirmed by the half-value full width (FWHM) of the peak that can be observed by measurement. Specifically, the first semiconductor layer 5a and the second semiconductor layer 5b contain an oxide containing In such as In-Ga-Zn-O (IGZO) as a main component (meaning that it contains 90% or more in volume fraction). In the case of an oxide semiconductor, it can be evaluated by the size of the half-value full width of the peak that can be confirmed in the vicinity of 2θ = 31 ° (for example, 30 ° to 32 °) in the X-ray diffraction measurement. More specifically, it can be evaluated that the smaller the full width at half maximum of the peak, the higher the crystallinity.

The fact that the crystallinity of the oxide semiconductor constituting the second semiconductor layer 5b is higher than the crystallinity of the oxide semiconductor constituting the first semiconductor layer 5a is that the diffraction angle 2θ in the X-ray diffraction measurement with respect to the second semiconductor layer 5b It can be confirmed that the half-value full width of the peak confirmed near = 31 ° is smaller than the half-value full width of the peak confirmed near the diffraction angle 2θ = 31 ° in the X-ray diffraction measurement with respect to the first semiconductor layer 5a. ..

The fact that the first semiconductor layer 5a is an amorphous oxide semiconductor means that when the first semiconductor layer 5a is an oxide semiconductor made of In-Ga-Zn-O (IGZO), the above-mentioned XRD (X-ray diffraction) ) Does not appear in the vicinity of 2θ = 31 °.

From the viewpoint of increasing the gate threshold voltage _Vth of the thin film transistor 1, the second semiconductor layer 5b has the full width at half maximum of the peak that can be confirmed in the vicinity of 2θ = 31 ° (for example, 30 ° to 32 °) in the measurement by XRD (X-ray diffraction). Is preferably 4.5 ° or less, more preferably 3.0 ° or less, and even more preferably 2.5 ° or less.

A source electrode 6 and a drain electrode 7 are arranged on the oxide semiconductor layer 5. The source electrode 6 and the drain electrode 7 are each made of a material having high conductivity so as to function as an electrode. For example, it may be made of the same material as the gate electrode 2, or it may be made of a different material. The source electrode 6 and the drain electrode 7 may be composed of a single-layer structure of a metal or a conductive oxide, or may be composed of a laminated structure of two or more layers.

If necessary, a protective film for protecting the oxide semiconductor 5, the source electrode 6, and the drain electrode 7 may be arranged. The protective film may be composed of, for example, a silicon oxide film (SiO ₂ ), a fluorinated silicon nitride film (SiN: F) containing fluorine in the silicon nitride film, or the like.

<2. Thin film transistor manufacturing method>
Next, a method for manufacturing the thin film transistor 1 having the above-mentioned structure will be described with reference to FIGS. 2 and 3.
The method for manufacturing the thin film transistor 1 of the present embodiment includes a gate electrode forming step, a gate insulating layer forming step, a semiconductor layer forming step, and a source / drain electrode forming step. Hereinafter, each step will be described.

(1) Gate Electrode Forming Step First, as shown in FIG. 2A, a substrate 2 made of, for example, quartz glass is prepared, and a gate electrode 3 is formed on the surface of the substrate 2. The method for forming the gate electrode 3 is not particularly limited, and the gate electrode 3 may be formed by a known method such as a vacuum vapor deposition method or a DC sputtering method.

(2) Gate Insulating Layer Forming Step Next, as shown in FIG. 2B, the gate insulating layer 4 is formed so as to cover the surfaces of the substrate 2 and the gate electrode 3. The method for forming the gate insulating layer 4 is not particularly limited, and the gate insulating layer 4 may be formed by a known method.

(3) Semiconductor Layer Forming Step Next, as shown in FIGS. 2 (c) to 3 (f), an oxide semiconductor layer 5 as a channel layer is formed on the gate insulating layer 4. The semiconductor layer forming step includes a semiconductor laminating step of laminating two types of oxide semiconductor films in order from the substrate 2 side, and a semiconductor processing step of processing the laminated oxide semiconductor film.

(3-1) In the semiconductor lamination process semiconductor lamination step, the first to form an oxide semiconductor film S ₁ on the gate insulating layer 4, on the crystalline than the first oxide semiconductor film S ₁ is higher the forming a second oxide semiconductor film _{S 2.} The semiconductor laminating step includes a first film forming step of forming the first oxide semiconductor film S ₁ and a second film forming step of forming the second oxide semiconductor film S ₂ .

In the present embodiment, both the first film forming step and the second film forming step form an oxide semiconductor film by sputtering the target using plasma. Specifically, it is performed by using a sputtering apparatus 100 that sputters the target T using an inductively coupled plasma P as shown in FIG. The sputtering apparatus 100 includes a vacuum vessel 20, a substrate holding portion 30 that holds the substrate 2 in the vacuum vessel 20, a target holding portion 40 that holds the target T facing the substrate 2 in the vacuum vessel 20, and a substrate holding unit. A plurality of antennas 50 arranged along the surface of the substrate 2 held by the portion 30 and generating the plasma P are provided. By using the sputtering apparatus 100, the high frequency voltage supplied to the antenna 50 and the bias voltage of the target T can be set independently. Therefore, the bias voltage can be set to a low voltage such that ions in the plasma are drawn into the target and sputtered independently of the generation of the plasma P, and the negative bias voltage applied to the target T during sputtering is -1 kV. It is possible to set the negative voltage to the above (that is, the absolute value is 1 kV or less). In the first film forming step and the second film forming step, the target T is arranged in the target holding portion 40, and the substrate 2 is arranged in the substrate holding portion 30. Here, as the target T, a conductive oxide sintered body such as InGaZnO, which is a raw material for the oxide semiconductor layer 5, is used.

In (3-1-1) the first film-forming step the first film forming step First, as shown in FIG. 2 (c), to form the first oxide semiconductor film _{S 1} on the gate insulating layer 4. Specifically, after the vacuum vessel 20 of the sputtering apparatus 100 is evacuated to 3 × ^10-6 Torr or less, the pressure inside the vacuum vessel 20 is 0.5 Pa or more and 3 while introducing the sputtering gas at 50 sccm or more and 200 sccm or less. .Adjust to 1 Pa or less. Then, high-frequency power of 1 kW or more and 10 kW or less is supplied to the plurality of antennas 50 to generate and maintain inductively coupled plasma. A DC voltage pulse is applied to the target to sputter the target. From the viewpoint of suppressing the formation of sputtered particles desorbed from oxygen and forming an oxide semiconductor film having few oxygen defects in the film, the voltage applied to the target T is set to a negative voltage of -1 kV or more and less than 0 V. The pressure in the vacuum vessel 20, the flow rate of the sputtering gas, and the amount of electric power supplied to the antenna may be changed as appropriate.

(3-1-2) after the second film-forming step the first film forming step, as shown in FIG. 2 (d), the second oxide semiconductor film _{S 2} on the first oxide semiconductor film _{S 1} Form. Specifically, similarly to the first film forming step, by using the sputtering apparatus 100, a second oxide semiconductor film S ₂ by performing sputtering of the target T. Similar to the first film forming step, in the second film forming step, it is preferable that the voltage applied to the target T is a negative voltage of -1 kV or more and less than 0 V. Conditions such as the pressure in the vacuum vessel 20, the flow rate of the sputtering gas, and the amount of power supplied to the antenna in the second film forming step may be the same as those in the first film forming step, and may be changed as appropriate.

(3-1-3) Oxygen Gas Concentration in Sputtering Gas In the present embodiment, the oxygen gas concentration contained in the sputtering gas supplied in the second film forming step is included in the sputtering gas supplied in the first forming step. Make it higher than the oxygen gas concentration. As a result, in the second film forming step, as compared with the first film forming step, the generation of sputtered particles desorbed from oxygen can be further suppressed, and the film can be formed while maintaining the oxidized state of the target. Therefore, the crystallinity of the second oxide semiconductor film S ₂ can be made higher than the crystallinity of the first oxide semiconductor film S ₁ .

The oxygen gas concentration in the sputtering gas supplied in the first film forming step may be lower than the oxygen gas concentration in the sputtering gas supplied in the second film forming step. In the first film forming step, from the viewpoint of forming a first oxide semiconductor film S ₁ of amorphous, preferably less 2Vol% oxygen gas concentration the volume fraction contained in the sputtering gas as a sputtering gas of argon gas only Is preferably supplied.

From the viewpoint of increasing the crystallinity of the second oxide semiconductor film S _2, the oxygen gas concentration in the sputtering gas supplied in the second film forming step is preferably at least 20Vol% in volume fraction, 50Vol More preferably, it is% or more. Most preferably, only oxygen gas (that is, a volume fraction of 99.999vоl% or more) is supplied as the sputtering gas.

(3-2) semiconductor processing step Next, in a semiconductor processing step, by processing the first oxide semiconductor film S ₁ and the second oxide semiconductor film S ₂ laminated to form the oxide semiconductor layer 5.

Specifically first, the resist R ₁ is coated on the second oxide semiconductor film S _2. Perform subsequent exposure and development or the like, as shown in (e) of FIG. 3, so as to leave the resist R ₁ only site with the oxide semiconductor layer 5 later. Then, as shown in (f) of FIG. 3, the first oxide semiconductor film S ₁ and the second oxide semiconductor film S ₂ is etched, the first semiconductor layer 5a and the second semiconductor layer 5b is the substrate 2 side The oxide semiconductor layer 5 laminated in order from the first is formed.

Here, in the manufacturing method of the embodiment, processing the physical second oxide by etching the semiconductor film S ₂ and the first oxide semiconductor film S ₁ by ion milling method. Specifically, using an ion milling apparatus, the second oxide semiconductor film S ₂ and the first oxide semiconductor film S _1, by the second oxide semiconductor film S ₂ side is irradiated with the ion beam Will be done.

Ion beam, the second oxide semiconductor film S ₂ and the first oxide semiconductor film S _1, are preferably irradiated in a direction parallel to the lamination direction (thickness direction). By doing so, the processed cross sections of the formed first semiconductor layer 5a and second semiconductor layer 5b can be made parallel to the stacking direction. The shape of the processed cross section of the first semiconductor layer 5a and the second semiconductor layer 5b is not limited to this, and may be formed so as to be tapered so as to spread toward the substrate 2.

The ionic material used in the ion milling method is not particularly limited, and examples thereof include Ne, Ar, Kr, and Xe. In addition, the implementation conditions of other ion milling methods are not particularly limited and can be exemplified as follows: ・ Ion acceleration voltage: 230 eV
・ Acceleration current: 100mA
・ Beam irradiation angle: 0 ° to ± 30 °

(4) the source and drain electrode formation step Next, after removing the resist R ₁ on the oxide semiconductor layer 5, a source electrode 6 and drain electrode 7 is formed on the oxide semiconductor layer 5. The source electrode 6 and the drain electrode 7 can be formed by, for example, a known method using RF magnetron sputtering or the like.

(5) Others After that, if necessary, a protective film may be formed so as to cover the upper surfaces of the formed oxide semiconductor layer 5, the source electrode 6, and the drain electrode 7, for example, by using a plasma CVD method. If necessary, the heat treatment may be performed in an atmosphere containing oxygen under atmospheric pressure.

From the above, the thin film transistor 1 of the present embodiment can be obtained.

<3. Observation of cross section of oxide semiconductor layer>
The influence on the cross-sectional shape of the oxide semiconductor layer 5 (first semiconductor layer 5a and second semiconductor layer 5b) due to the difference in the processing method in the above-mentioned semiconductor processing process was evaluated.

(1. Sample preparation)
Two silicon substrates are prepared, and an oxide semiconductor film made of In-Ga-Zn-O (IGZO1114) is formed on the silicon substrate based on the semiconductor lamination process of the manufacturing method described above to prepare two samples. did.

Specifically, using the sputtering apparatus 100, the pressure in the vacuum vessel is reduced to 0.9 Pa or less, high-frequency power of 7 kW is supplied to a plurality of antennas, and a DC pulse voltage of −400 V is applied to the target. The target was sputtered. Then, by changing the oxygen gas concentration in the supplied sputtering gas, an amorphous first oxide semiconductor film S ₁ (a-IGZO) is formed on the silicon substrate, and the first oxide semiconductor film S _{1 is formed.} and forming the second oxide crystalline semiconductor film _S 2 (c-IGZO) above.

(2. Processing and molding)
Next, the two prepared samples were etched from the second oxide semiconductor film side to the first oxide semiconductor film side.

Specifically, after resisting a predetermined region on the surface of the second oxide semiconductor film S2 of the _two samples, wet etching (chemical etching) is performed on one sample and the other sample is subjected to wet etching. Ion milling (physical etching) was performed. The specific conditions of the wet etching and ion milling performed are as follows.

(Conditions for wet etching)
・ Etching solution: HCl (0.05M)
・ Etching time: 210 seconds ・ Temperature: 25 ° C

(Conditions for ion milling)
・ Ion acceleration voltage: 230eV
・ Acceleration current: 100mA
・ Board rotation: 12 rpm
・ Etching time: 360 seconds ・ Beam irradiation angle: 0 °

(3. Etching process and observation of processed cross section)
In each sample was observed first processing section of the oxide semiconductor film S ₁ and the second oxide semiconductor film S ₂ by etching by SEM (scanning electron microscope). The result is shown in FIG.

As shown in FIG. 5 (a), the sample was processed by wet etching, a large step at the boundary between the first oxide semiconductor film S ₁ and the second oxide semiconductor film S ₂ has occurred. Specifically, first the semiconductor film S ₁ is high low etch rate crystallinity than the second semiconductor film S _2, in the vicinity of the boundary between the second semiconductor film S _2, oriented transversely to the stacking direction Etching was in progress.

On the other hand, as shown in FIG. 5 (b), in the samples was processed by ion milling, a large step does not occur at the boundary between the first oxide semiconductor film S ₁ and the second oxide semiconductor film S _2, smooth A series of cross sections was formed.

<4. Effect of this embodiment>
According to the manufacturing method of the thin film transistor 1 of the present embodiment as described above,
In semiconductor processing step, the processing the second oxide semiconductor film S ₂ and the first oxide semiconductor film S ₁ by ion milling, crystallinity different second oxide semiconductor film S ₂ and the first oxide semiconductor film etching can be performed at comparable rates for the S _1. Therefore, as may occur when performing the wet etching, can be prevented a situation only the first oxide semiconductor film S ₁ of amorphous resulting in scraped deep in a direction perpendicular to the stacking direction, the crystalline with second oxide semiconductor film S ₂ becomes easy to obtain a desired cross-sectional shape.

Further, since the second oxide semiconductor film S ₂ and the first oxide semiconductor film S ₁ can be etched at the same speed, the obtained first semiconductor layer 5a and second semiconductor layer 5b can be etched. It is possible to reduce the step at the boundary of each processed cross section of. Therefore, in the source / drain electrode forming step, which is a subsequent step, when the conductive film is formed so as to cover the oxide semiconductor layer 5 by sputtering or the like, either the processed cross section of the first semiconductor layer or the second semiconductor layer is processed. In addition, it becomes easy to form a conductive film.

<Other modified embodiments>
The present invention is not limited to the above embodiment.

In the above embodiment, the first semiconductor layer 5a and the second semiconductor layer 5b are composed of oxide semiconductors having the same composition, but the present invention is not limited to this. In another embodiment, the first semiconductor layer 5a and the second semiconductor layer 5b may be composed of oxide semiconductors having different compositions.

In the above embodiment, the first film forming step and the second deposition step, by changing the oxygen concentration in the sputtering gas, the crystallinity of the first oxide semiconductor film S ₁ and the second oxide semiconductor film S ₂ Was changed, but it is not limited to this. A first oxide semiconductor film S ₁ is formed, if on the second oxide semiconductor film S ₂ with high crystallinity as it can be formed by the first film forming process by another method and the second formation A membrane step may be performed.

The first semiconductor layer 5a is not limited to an amorphous one, and may be made of a crystalline oxide semiconductor. Any semiconductor having lower crystallinity than the oxide semiconductor constituting the second semiconductor layer 5b may be used.

The oxide semiconductor layer 5 of the above embodiment is obtained by laminating two oxide semiconductor layers having different crystallinities, but the present invention is not limited to this. The oxide semiconductor layer 5 of the other embodiment may be one in which three or more oxide semiconductor layers having different crystallinities are laminated.

In the above embodiment, the configuration has a plurality of target holding units 40, but a configuration having one target holding unit 40 may be used. Even in this case, a configuration having a plurality of antennas 50 is desirable, but a configuration having one antenna 50 may be used.

In addition, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the spirit of the present invention.

1 ・ ・ ・ Thin film transistor 2 ・ ・ ・ Substrate 3 ・ ・ ・ Gate electrode 4 ・ ・ ・ Gate insulating layer 5 ・ ・ ・ Oxide semiconductor layer 5a ・ ・ ・ First semiconductor layer 5b ・ ・ ・ Second semiconductor layer 6 ・ ・・ Source electrode 7 ・ ・ ・ Drain electrode

Claims (6)

A semiconductor laminate in which a first semiconductor layer made of an oxide semiconductor and a second semiconductor layer made of an oxide semiconductor having a higher crystallinity than the oxide semiconductor constituting the first semiconductor layer are laminated in order from the substrate side. , A processing method that processes and molds by the ion milling method. The processing method according to claim 1, wherein the first semiconductor layer is made of an amorphous oxide semiconductor, and the second semiconductor layer is made of a crystalline oxide semiconductor. The processing method according to claim 1 or 2, wherein the composition of the oxide semiconductor constituting the first semiconductor layer and the composition of the oxide semiconductor constituting the second semiconductor layer are the same. The processing method according to any one of claims 1 to 3, wherein the oxide semiconductor constituting the first semiconductor layer and the second semiconductor layer is IGZO. The full width at half maximum of the peak confirmed in the vicinity of the diffraction angle 2θ = 31 ° in the X-ray diffraction measurement by the θ-2θ method using Cu—Kα rays for the second semiconductor layer is the X-ray diffraction for the first semiconductor layer. The processing method according to any one of claims 1 to 4, which is smaller than the full width at half maximum of the peak confirmed in the vicinity of the diffraction angle 2θ = 31 ° in the measurement. A method for manufacturing a thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, and a drain electrode are arranged in this order on a substrate.
A semiconductor lamination step in which a first semiconductor layer made of an oxide semiconductor and a second semiconductor layer made of an oxide semiconductor having a higher crystallinity than the oxide semiconductor constituting the first semiconductor layer are laminated in order from the substrate side. When,
A semiconductor processing step of processing the laminated first semiconductor layer and the second semiconductor layer by an ion milling method to form the oxide semiconductor layer.
A method for manufacturing a thin film transistor having.