JP2020528181A - Computer-implemented systems and methods for translating electronic design verification commands - Google Patents

Abstract

A computer-implemented method of translating an electronic design validation command has at least one specification parameter that has at least one indirect branch contribution statement and a step to receive the electronic design and is stored in at least one specification database. A step of receiving at least one analog test harness model having at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database. At least one analog test harness model, at least one specification parameter stored in at least one specification database, at least one stimulus parameter stored in at least one specification database, and at least one stored in at least one specification database. Generate a netlist based on the step of translating at least one indirect branch contribution statement into multiple direct branch contribution operators, and at least partly based on the translation, at least partially based on at least one of the measurement parameters. Including steps.

Description

Mutual reference to related applications This application is filed on July 19, 2017, entitled "COMPUTER IMPLEMENTED SYSTEM AND METHOD OF TRANSRATION OF VERIFICATION COMMANDS OF AN ELECTRONIC DESIGN", US Pat. It claims the priority and / or benefit of (ZPLG-33603). U.S. Patent Application No. 15 / 654,469 was issued as U.S. Pat. No. 9,715,566 on July 25, 2017, and was filed on May 8, 2015. Part of U.S. Patent Application No. 14 / 707,689, entitled "COMPUTER IMPLEMENTED SYSTEM AND METHOD OF TRANSLATION OF VERIFICATION COMMANDS OF AN ELECTRONIC DESIGN" (agent reference number ZPLG-31865). U.S. Patent Application No. 14 / 707,689, entitled "COMPUTER IMPLEMENTED SYSTEM AND METHOD OF TRANSLATION OF VERIFICATION COMMANDS OF AN ELECTRONIC DESIGN," filed May 9, 2014, U.S.A. Claim the interests of specification 991,072 (agent reference number ZPLG-31865). U.S. Patent Application Nos. 14 / 707,689 and 61 / 991,072 and U.S. Pat. Nos. 9,715,566 are incorporated herein by reference in their entirety.

The methods and systems generally relate to the verification of analog and mixed signal integrated circuits, and more specifically to the systems and methods of translating verification subroutine commands (verification subroutine commands).

Electronic design automation (EDA) is software for designing electronic blocks. There are roughly several types of electronic signals, components, and blocks (digital and analog mixtures called digital, analog, and mixed signals). Electronic design generally includes at least one of the following levels of circuit information: system level, architecture level, data flow level, electrical level, device level, and technology level.

The digital signal has discrete input / output values "0" and "1" that occur at discrete time values and are typically associated with the clock signal. Digital components that input and output digital signals typically have static pin outputs and interaction protocols. Digital blocks composed of digital components have an established and documented physical layout and electrical interactions. The simulator for digital blocks is a discrete-time event-driven simulator.

Analog signals generally have continuous input / output values that can change over time. Analog components typically have a layout that can be customized to change inputs, outputs, triggers, biases, and so on. Therefore, due to customization, analog blocks composed of analog components may not have as well established or documented physical layout or electrical interactions as digital circuits. Simulators for analog blocks generally require a continuous time domain simulator.

A mixed signal block is a combination of digital and analog signal blocks within a simulated component. The most common options available for simulation are to simulate the components as a group of analog blocks, or analyze the analog components / blocks and digital components / blocks individually with the digital domain for inter-domain communication. It is to translate the input and output at the boundary with the analog domain.

Within EDA, there are two major related categories of circuit review: simulation and verification. A simulation is a set of numerical solutions that predict the behavior of a circuit. Verification is a systematic pursuit that describes the behavior of a circuit (parameter verification) across manufacturing process variations (functional verification) under relevant conditions. Therefore, verification generally requires a much wider review of circuits, circuit operating conditions, and manufacturing operational variations than simulations. It is possible to perform a large number of simulations without much verification of the functionality of the circuit. Verification is a mathematical modeling of circuit behavior and circuit performance evaluation over various conditions. Ultimately, the success measure of verification is to report how well the circuit design fits the circuit specifications. Analog and mixed-signal verification methodologies struggle to meet the ever-increasing complexity, cost, and computational demands of analog and mixed-signal circuits.

The number and complexity of validation test cases increases with the complexity of analog and mixed signal designs. In addition, as the size of the circuit increases, the simulation speed decreases and the memory usage increases. Therefore, the computational power to verify a circuit can increase dramatically with the complexity of the circuit. To make matters worse, validation is usually done at the end of the design cycle, where schedule delays are considered the most severe. Therefore, validation is generally an activity that requires a significant amount of simulation processing power in a small part of the entire design cycle, and therefore efficient use of validation resources is generally used to meet time-to-market requirements. Needed.

Today's complex verification solutions specifically focus engineering on verification activities to ensure that circuit operation is fully and efficiently verified under relevant conditions. This refined analog and mixed signal verification is performed much more manually and empirically than digital verification. This sporadic interactive analog verification puts the company at risk. The present disclosure may allow the validation task to be defined with a higher degree of abstraction. The present disclosure may allow efficient capture of complex relationships between stimulus or stimulus assertions and output measurements or output claims. The present disclosure may allow testing of transistor-level circuits, circuits implemented using behavioral models, or circuits that include combinations of behavioral models and transistor-level mounting. Standard branch contribution statements cannot be used in conditional, loop, naming, or parsing-based statements unless the conditional expression is a constant expression. For the sake of distinction, these standard branch contribution statements are referred to herein as direct branch contribution statements. In the present disclosure, indirect branch contribution statements (IBCS) are more powerful than direct branch contribution statements (DBCS). Specifically, the indirect branch contribution statement can be used in a dynamic conditional and loop structure for the user's design, design configuration, simulation / analysis configuration, verification state, and verification history. It has long been required to use independent branch contribution statements in conditional, loop, naming, or parsing-based statements, or to return different arguments from the analysis in progress.

In addition, increasing design complexity has increased the need for traceability to product specifications. Today, many customers and industries need to document specific validation tests that confirm each specification and test conditions. The present disclosure includes the concept of a high-level indirect branch contribution statement that can include parameters that link to a specification database. These parameters are not limited and can include specification limits, test stimulus conditions (eg, supply voltage), and measurement requirements (eg, net crossover of specific values). In the present disclosure, when translating a validation command, the specification database can be accessed and parameters can be replaced with the corresponding exact values from the specification database. Another option is to leave the linked parameters in the netlist, access the spec database during simulation, and extract the parameter values.

Robust verification of analog and mixed-signal circuits generally requires a significant investment in test benches, performance evaluation routines, and macro models that can be used to accelerate simulations. The complexity of this incidental fact increases with the complexity of the analog and mixed signal integrated circuits to be verified. When the design team adds design resources, it is necessary to add verification resources as well, which increases the design cost. When a company is about to bring a product to market, efficient use of those resources is a top priority due to the inevitable time constraints imposed at the end of the design cycle.

The current technology trajectory in the electronics manufacturing industry is increasingly moving towards single-chip designs called system-on-chip (SoC) or multi-chip modules (MCMs) in which multiple chips are contained in a single package. Most system-on-chip and multi-chip modules generally require some level of mixed-signal verification. As the size and complexity of mixed-signal designs increase, this creates an additional burden on validation to ensure the success of first-pass designs and reduce time-to-market. The complexity of analog and mixed-signal ASIC designs has followed Moore's Law, but technological innovations in design verification are generally not.

The method of translating the validation subroutine commands of the present disclosure can focus particularly on valuable design time and computational resources and expensive simulator resources. The method makes the capture of complex stimuli and the capture of power claims and measurements more efficient. The resulting intelligent test bench provides much more immediate feedback to the design team and design supervision by identifying areas where validation fails and significantly reducing the need to manually interpret the results. To do. Improved test efficiency (ie, less waste of simulation time and shorter output analysis time) allows for more efficient use of resources. In addition, by linking critical parameters to the specification database, translated commands can access the latest version of the specification and provide traceability from the specification to the generated validation tests and results.

The present disclosure relates to translating verification subroutine commands and linking critical parameters to a specification database during verification of the electronic design of analog and mixed signal (A / MS) application specific integrated circuits (ASICs). Analog and mixed-signal integrated circuits exist in many modern electronic devices, and these circuits need to be verified through simulation before manufacturing.

According to just one example and embodiment of a computer-implemented system and method of translating an electronic design verification command of the present disclosure, the specification comprises a step of receiving the electronic design and at least one indirect branch contribution statement. At least one indirect based on the step of receiving at least one analog test harness model with at least one specification or measurement parameter from the database and at least partly based on at least one analog test harness model. It is provided with a step of translating the branch contribution statement into multiple direct branch contribution operators and a step of generating a netlist based on the translation at least in part.

The present disclosure is more clearly understood by taking into account the following detailed description and drawings.

It is a block diagram which shows the computer system suitable for carrying out this disclosure. It is a block diagram which shows the computer network system suitable for carrying out this disclosure. An example of a low voltage loss (LDO) circuit is shown. An example of an amplifier circuit is shown. The test bench pin output for the amplifier is shown. An example of a general hierarchical structure is shown. An example of an instance-parsed test hierarchy is shown. An example of a first test bench of a power management integrated circuit is shown. A second test bench example of a power management integrated circuit is shown. An example of a third test bench of a power management integrated circuit is shown. An example of a multiplexer and an operational amplifier having a verification subroutine command translation of an electronic design is shown. An example of B level of verification subroutine command translation of electronic design is shown. An example of the D level of electronic design verification subroutine command translation is shown. Verification of electronic design An example of the hierarchical structure of subroutine command translation is shown. An example of E level of verification subroutine command translation of electronic design is shown. An electronic design verification subroutine A first example of command translation is shown. A second example of electronic design verification subroutine command translation is shown. A third example of electronic design verification subroutine command translation is shown. A fourth example of electronic design verification subroutine command translation is shown. A fifth example of electronic design verification subroutine command translation is shown. A sixth example of electronic design verification subroutine command translation is shown.

Reference numerals in the detailed description correspond to similar reference numerals in various figures, unless otherwise noted. Descriptive and directional terms such as right, left, rear, top, bottom, top, side, etc. used in the document refer to the drawings themselves as arranged on paper, unless otherwise noted. Does not mention physical limitations. The drawings are not to a constant scale and some features of the examples illustrated and discussed are simplified or exaggerated to illustrate the principles and features and advantages of the present disclosure.

Detailed Description The features and other details of the present disclosure will be described in more detail with reference to the accompanying drawings, and various examples of the matters disclosed will be shown and / or described in the accompanying drawings. It is understood that the particular examples described herein are presented as examples, not as limitations of the present disclosure. Moreover, the matters disclosed should not be construed as being limited to any of the examples described herein. These examples are provided to make this disclosure complete and complete and to fully inform those skilled in the art the scope of the matters to be disclosed. The essential features of the present disclosure may be adopted in various examples without departing from the scope of the present disclosure.

The terms used herein are for the purpose of describing specific examples only and are not intended to limit the matters disclosed. Throughout, similar numbers refer to similar elements. As used herein, the term "and / or (and / or)" includes any combination of one or more of the items listed in connection. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the circumstances clearly indicate otherwise. .. As used herein, the terms "comprising, including" and / or "comprising, including" are described features, integers, steps, actions, elements. , And / or specify the presence of a component, but it is understood that it does not exclude the presence or addition of one or more of other features, integers, steps, actions, elements, components, and / or groups of these. .. Also, as used herein, the first and second, upper and lower, and right related terms may be used only to distinguish one subject or action from another. , Does not necessarily require or suggest any actual such relationship or order between such actors or actions.

The cost of entry barriers to analog and mixed signal IC design is ASIC intellectual property, especially in the form of packaged ASICs or modules integrated into the customer's system-on-chip (SoC) or multi-chip modules (MCMs). It is unique to the fabless company that is developing. For example, if a fabless design center has five IC design engineers, having that team have design tools is financially equivalent to quadrupling the workforce. This is due to the high cost of owning EDA tools, not just annual license fees, installation and support, training, etc. Reducing system usage through translation of validation commands allows for more efficient resource allocation.

Analog and mixed signal verification are time and computer intensive. In order to ensure that the circuit works to specifications, it is generally necessary to simulate the functionality of the circuit for different inputs under different conditions and different manufacturing conditions.

Branch contribution statements are used to describe the behavior of analog nets and ports in continuous time. Direct contribution statements utilize the branch contribution operator <+ to describe the mathematical relationship between one or more analog nets. These direct contribution statements make use of arguments that are constant expressions. Standard branch contribution statements cannot be used in conditional, loop, naming, or parsing-based statements unless the conditional expression is a constant expression. For the sake of distinction, these standard branch contribution statements are referred to herein as direct branch contribution statements. In the present disclosure, indirect branch contribution statements (IBCS) are more powerful than direct branch contribution statements (DBCS). Specifically, the indirect branch contribution statement can be used in a dynamic conditional and loop structure for the user's design, design configuration, simulation / analysis configuration, verification state, and verification history. Indirect branch contribution statements allow dynamic code to generate direct branch contribution statements based on the contents of the netlist.

AMST ™ (Analog Mixed Signal Test) is a module that specifies analog / mixed signal (A / MS) stimuli and assertion and output measurements. AMST can efficiently capture complex relationships between stimuli and power claims. The validation model specified in the AMST language (AMSTR ™) subsequently captures relatively high level commands translated into Verilog-A / AMS ™. Verilog-A, Verilog-AMS, VHDL-AMS, SystemC-AMS, etc., which are standardized languages that define analog and mixed signals, respectively. This code could also be used to generate any language standard that supports the direct branch contribution statement of the analog simulator.

AMSTL can be used to capture relatively high level commands with IBCS, whether the resulting translated code is used in a circuit behavior model or in a test harness. .. The value of capturing claims within AMST rather than the circuit behavior model is that the validation commands can be reused regardless of the representation of the circuit. For example, in FIG. 15, the AMP_AMST block executes the same commands and claims regardless of whether the op amps and multiplexers are represented as transistor-level wiring diagrams or behavioral models. At this time, AMP_AMST functions as a verification intellectual property (VIP) that can be reused together with these circuits. This concept is especially valuable when considering providing analog design intellectual property (IP) to a third party. The purchaser has a verification IP that can be embedded in a larger SOC along with the purchased IP. This VIP reduces the risk of improper use of purchased design IP. Verification IP is a proven concept for digital circuits and top-level I / O, but it has traditionally been impractical to provide with embedded analog IP.

Language AMSTL is intended to describe behavior, stimuli, outputs, measurements, etc. for analog mixed signal integrated circuit design and is available in standard hardware description languages intended for input to analog simulators. It provides a higher standard of structure than the analog one. One advantage is the improvement in efficiency based on the availability of IBCS in AMSTR. In addition, the AMSTR code can be parsed to output any desired standard language. Module AMST is a behavioral model of analog mixed signal verification intellectual property and is intended to be present at any level of the hierarchical structure in the design. The module can be present with the IP being monitored, stimulating, and / or evaluating. The output format of the model (Verilog-A, Verilog-AMS, VHDL-AMS, etc.) can be input to the analog or mixed signal simulator through the netlist.

AMST can include parameters that link to the specification database. The specification database contains at least one of the following types of information: specification limits, measurement conditions, or stimulus conditions. The specification limit is a value that describes the performance limit allowed in a particular test. For example, SOC specifications may include a specification called supply current. The supply current may include a minimum limit value, a typical limit value, and / or a maximum limit value. For example, the supply current should never be below the minimum limit and never exceed the specified maximum limit during testing or under specified measurement conditions. A "typical" value is often provided as information about the performance of the part under normal conditions, which is defined as performance at room temperature. Strictly speaking, the "typical" value is not the limit of operation. "Measurement condition" is a term that can be used to broadly describe any test condition, including stimuli, but in this discussion, the measurement condition is a condition that defines when a measurement can be made. Used to describe. For example, the measurement conditions may describe that the supply current should be measured only if the voltage regulator output on the chip exceeds a certain value. The stimulus condition describes a stimulus such as voltage, current, temperature applied to the chip or a particular pin on the chip. For example, supply current measurement can also be defined as when the supply voltage is equal to a particular voltage. In this example, the supply voltage is a stimulus. The goal is to monitor or monitor specified parameters so that validation automation captures the measurement and stimulus requirements of a given measurement and allows a set of validation stimuli to indicate that the specification limits have been met. To measure.

These parameters linked to the specification database have a unique identifier. These identifiers provide a definitive traceability opportunity for validation activity vs. specifications. Today's typical implementation of analog verification involves the engineer describing (through a graphical interface, etc.) that the specification verification test is testing a given specification. For example, validation tests and output reading names can be associated with a particular specification, but there is no mechanism that can automatically update the validation test to match a specification change. There is also no link that allows automatic tracking of the time the change vs validation test is performed. In other words, if there is no link between the specification database and the validation test, there is no opportunity to automatically determine if the validation test was done before or after the specification change. In addition, if the values in the specifications and the values in the verification test do not match, a manual mismatch may occur. The techniques described in this disclosure maintain very important parameters related to the specification in the specification database, the high-level validation test contains parameters uniquely identified from that database, and the high-level AMSTR format Verilog- Allow instantiation of parameter values either when translating into a lower level implementation such as AMS or when simulating through a parameter file created by accessing the specification database. By definition, the parameters used during validation match the parameters in the specification database.

Netlist
1) Component attributes that make up the description and design of components (eg, transistors, resistors, capacitors, behavior models, AMST, digital gates) (eg, ProLiant 2 has W = 1um),
2) Design connectivity (eg, the drain of epitaxial 1 is the connection to the gate of NMOS 2),
3) Hierarchical configuration of the design for a particular simulation task (eg, PLL1 is represented as a model and LDO3 is represented at the transistor level),
4) Simulation type (eg, transient simulation), duration (eg, 2 ms), tolerance setting (eg, iabstal <10e-10), configuration of interface elements between digital and analog partitions, and output signal selection. Configuration of simulation tasks, including
5) Includes information about verification projects and simulation tasks, including but not limited to any information in the verification database such as predicted performance values, signal transitions, signal shapes, duty cycles, etc. of any signal or element related to verification activity 1 A representation of one or more databases.

The netlist is the input to the simulation. The purpose of the simulation is to predict the behavior of the circuits described in the netlist under the stimulus conditions and accuracy criteria specified in the netlist. Simulation is an essential part of integrated circuit (IC) design, because a) photomasks for IC design are very expensive, b) IC manufacturing takes a long time, and c) inside the IC. It is extremely difficult to examine the signal of d) because the breadboarding of modern IC design is impractical. The simulation is performed using a simulator. At high levels, there are three methods of simulating integrated circuits: SPICE level simulation, digital level simulation, and mixed mode simulation. The SPICE level simulator reduces the netlist to simultaneous nonlinear differential algebraic equations that can be solved using implicit integration, Newton's, and sparse matrix techniques. The SPICE level simulator stores charges under a set of absolute or relative tolerances and satisfies Kirchhoff's current law and Kirchhoff's voltage law. The digital simulator shrinks the netlist into a set of Boolean functions triggered by discrete events. Digital simulators do not store charges and do not satisfy Kirchhoff's current law and Kirchhoff's voltage law. However, digital simulators can simulate much larger circuits at higher levels of abstraction. Mixed mode (AMS) simulation combines a SPICE level simulator with a digital simulator. In this type of simulation, a SPICE level simulator is used to simulate part of the design to predict the net voltage and terminal current of the components in the SPICE level partition, while a digital simulator is used in the digital partition. Predict the digital output of the component. In a mixed mode simulation, the SPICE level partition and the digital partition are connected using an interface element, and the interface element is an idealized 1-bit analog (for the signal going from the SPICE partition to the digital partition) at the basic level. It is a digital converter, a 1-bit digital-to-analog converter (for signals going from the digital partition to the SPICE partition).

The simulation can produce the following output:
1) Continuous time / continuous value waveform of net voltage and terminal current;
2) Discrete time / discrete value digital waveform of logical net output;
3) Any data written by any behavioral model, including any AMST module included in the netlist;
4) Claim violation message;
5) Claimed measurements; and 5) Debugging information about model behavior, circuit convergence difficulty, etc.

The output from the simulation is stored in one or more databases. These outputs are subsequently used to evaluate the stability of the circuit. This process may be manual. The designer can, for example, review the waveform with a graphical waveform viewer. This process may be automated. The software program can analyze the waveform results and AMST output according to the program to build a spec compliance matrix summarizing a set of satisfied design objectives and a set of failed design objectives in the circuit simulation. Since these specification measurements can be linked to specific specifications described for specific measurement or stimulus conditions in the specification database, the results from the verification process can be linked directly to the desired specifications.

An example of what can be done using the Indirect Branch Contribution Statement (IBCS).
1. 1. Write an indirect branch contribution statement that supports a bus with an arbitrary number of pins (eg, a reference current bus). When the size of the bus is changed by the designer, the actual number of direct branch contribution statements is dynamically reconstructed.
2. 2. Write an indirect branch contribution statement that extracts the spec limits from the net name or circuit connectivity. This makes it possible to implement a supply connectivity check.
3. 3. Write an indirect branch contribution statement that sets limits based on the results of previous simulations.
4. Write an indirect branch contribution statement that adds additional checks only for the transistor-level implementation of the block.

In each of these cases, the code that makes up the indirect branch contribution statement produces a Verilog-A / AMS statement that is compatible with the language standard.

Therefore, the disclosed validation command translation systems and methods may solve one or more of the following challenges: enabling more efficient use of computer and human resources through reduced programming time. To reduce the time lag to market and / or to ensure a more focused and more complete verification confirmation.

The computer system of FIG. 1 illustrates the system architecture of an exemplary computer system 100 that may implement the present disclosure. The exemplary computer system of FIG. 1 is for illustration purposes only. In this description, terms commonly used when describing a specific computer system such as a personal computer can be referred to, but this description and this concept include systems having an architecture not similar to FIG. The same applies to the system of.

The computer system 100 typically includes a central processing unit (CPU) 110 that can be implemented using one or more microprocessors, a random access memory (RAM) 112 for temporary storage of information, and more. Includes a read-only memory (ROM) 114 for persistent storage of information. A memory controller 116 is provided to control the RAM. Bus 118 interconnects the components of a computer system. A bus controller 120 is provided to control the bus. An interrupt controller 122 is used to receive and process various interrupt signals from system components. Mass storage may be provided by flash 124, DVD® 126, or hard disk 128, such as a solid state drive. Data and software can be exchanged with computer systems via removable media such as flash drives and DVDs. The flash drive can be inserted into the universal serial bus (USB) drive 130, and the universal serial bus (USB) drive 130 is connected to the bus by the controller 132. Similarly, the DVD can be inserted into the DVD drive 134, which is connected to the bus by the controller 136. The hard disk is part of the fixed disk drive 138, which is connected to the bus by the controller 140.

User input to a computer system can be provided by several devices. For example, the keyboard 142 and the mouse 144 are connected to the bus by the controller 146. The audio converter 148 can function as a microphone and speaker and is connected to the bus by the audio controller 150 as shown. Other input devices such as pens and / or tablets may be connected to the bus and suitable controllers and software. A DMA controller 152 is provided for direct memory access to the system RAM.

A visual display is generated by the video subsystem 154 that controls the video display 156. The computer system also includes a communication adapter 158, which can interconnect the system to a local area network (LAN) or wide area network (WAN) or other suitable network, roughly represented by bus 160 and network 162. To do so.

The behavior of computer systems is generally the Windows® and Windows 7 operating systems, Windows®, Linux®, or Apple OS X® (registered trademarks) available from Microsoft Corporation, to name a few. ) It is controlled and adjusted by the operating system such as the operating system. The operating system controls the allocation of system resources and specifically performs tasks such as processing scheduling, memory management, networking, and I / O services.

Computer system FIG. 2 shows system 200, in which computer user 210 is connected to network 212 and network 212 is connected to cloud 214 and compute farm 216.

A schematic example of a low voltage loss (LDO) 300 circuit is shown in FIG. The LDO has an amplifier A1, which has an inverting input (“-input”), a non-inverting input (“+ input”), an output, a positive voltage input “+ V”, and a negative voltage input “-V”. .. The LDO circuit has a voltage input Vin and a voltage output Vout. The LDO has power output blocks Q1, Q2, and R2. The LDO feedback circuit is composed of R3, R4, D1 and R1. The amplifier A1 is called a symbol, and the elements D1, R1, R2, R3, R4, C1, C2, Q1 and Q2 are called primitives.

A schematic example of the amplifier A1 400 circuit is shown in FIG. The symbol of the amplifier is composed of transistors Q3, Q4, Q5, Q6, Q7, and Q8, and a resistor R5. The amplifier A1 has an inverting input (“− input”), a non-inverting input (“+ input”), an output, a positive voltage input “+ V”, and a negative voltage input “−V”.

FIG. 5 shows the test bench 500 of the amplifier A1 510. The test bench is a concrete configuration of inputs, outputs, test conditions, etc. executed on the connected device. The test bench has an inverting input 512, a non-inverting input 514, a positive power input 516, a negative power input 518, and an output 520. The test bench has associated connections, power supplies, IOs, etc., which are referred to as test bench collateral. The peripheral part of the circuit is called the verification harness. The pin output and verification harness operation must match the circuit being tested.

FIG. 6 shows an example 600 of a typical hierarchical structure of a test bench with a device under test (DUT). The hierarchy is arranged according to levels A, B, C and devices and according to instances 1, 2, and 3. Connection lines indicate which models are connected through a hierarchical structure in a particular validation. Multiple view types can exist within a level and instance. These examples show some possible hierarchical structures and are not intended to limit cases and views or view types.

The integrated circuit design hierarchical structure is an expression of integrated circuit design using the hierarchical structure representation. This representation allows for the more efficient creation of complex designs that can contain millions of components such as transistors, resistors, capacitors, and metal wires connecting devices. The design hierarchical representation used at any point in the design process can vary based on the design steps being performed and the type of design function, such as analog, digital, or memory.

If the design should be manufactured, the layout of the design is created so that the representation can be mapped. This mapping allows patterns to be created at the individual levels of the mask set to enable design and manufacture. In general, the design flow for creating layout representations is very different for analog compared to digital functional blocks and subsystems.

Early in the design process, most of the design is designed for the first time and can exist without any existing layout representation. Other parts of the design may have already been proven and these may be represented at a higher level of abstraction or may include layout representations in combination.

Some common types of design representations, referred to herein as views, may include various view types. A schematic view type is a picture of a block or component with a connection represented by a line or net and a connection to another level of hierarchical structure through pins. A Spice view type is a representation of a component and associated parameters, optionally including a particular device model that is instantiated into a spice netlist. LVSExtract is a view type created by tools that analyze layout views and reverse engineer individual components and connectivity. Variations on this type of view can also include extracted parasitic components that were not drawn by the designer, generated from the physical layout. A layout view type is a representation of a particular geometric arrangement that includes wiring for that part of the design. The Verilog ™ view type is a standardized Verilog ™ format text file. The Verilog-A ™ view type is a standardized Verilog-A ™ grammar text file. The Verilog-AMS ™ view type is a standardized Verilog-AMS ™ grammar text file. The name of the view type may vary depending on the electronic design automation tool provider, and examples thereof include Spectre HDL and HDL-A.

Other types of view types can support hierarchical organization and readability. As an example, graphic design tools such as schematic capture systems may use the symbol view type for the placed graphics. Symbols can include pins that connect instances through a hierarchical structure and drawings that show the functionality of the block. Examples include common symbols such as operational amplifiers, basic digital gates, transistors, and resistors.

In addition to the complexity of the description, a given block at some level of the design hierarchy can contain multiple views of the same view type. One example is various Verilog ™ representations of a given block, such as layout-based annotated timing representations, estimated timing representations, timingless representations, or gate level or register transfer levels. It is a design expression of a different level such as (RTL). Similarly, an analog view can have many schematic views: for example, a view that maps to a final transistor level design, a view that includes the placement of behavior blocks for higher level modeling, parasitic elements from the layout. A view that contains an interface element between the analog and digital blocks for mixed signal simulation. Also, in the case of analog blocks, there can be multiple Verilog-A ™ or Verilog-AMS ™ model views in the same block, where the models have different functionality and accuracy based on the purpose of different simulation exercises. including. These multiple views and view types are mapped to the configuration used for a particular task or analysis.

View names are often created to provide hints as to what type of analysis a particular view can be useful for. View names may include those listed below. Schematic is a schematic view that includes an arrangement of blocks that can be evaluated at some level of a hierarchical structure, such as a transistor level or a behavioral model. Schematic_behabialal is a schematic view that includes behavioral elements. Schematic_parasitics is a schematic view containing parasitic components extracted or deduced from the layout. A Spice is a spice view that contains information implemented in a netlist and components of a particular analog simulator. Behavioral_va is a text view in Verilog-A ™ format that models specific blocks of analog simulators that can evaluate Verilog-A ™, and Behavioral_vams evaluates Verilog-A ™ and Verilog. A text view in Verilog-AMS ™ format that models a particular block of the mixed signal simulator obtained.

In the specific example shown in FIG. 6, an example of a general hierarchical structure having device A1 and instance 1 under test is defined based on the following configuration: A1, instance 1 and B1, and instance 1 are Schematic level. It is modeled using a model. B2, instance 1 is modeled using the Schematic_behavioral model, and C1, instance 1 and C2, instance 1 are modeled using the Schematic model. C1, instance 2 and C3, instance 1 are modeled using the Behavioral_va model. At the bottom of the hierarchy, devices 1, 2, and 3, instances 1, 2, and 3 are modeled using Spice.

In the specific example shown in FIG. 6, the device 1 and the instance 2 are dummy devices, and therefore the simulator matrix is not changed. The device 1 and the instance 2 are arranged in the C1 and instance 1 schematics connected as dummy devices and are therefore not part of the A1 and instance 1 matrix stamped in the simulator.

Whether or not the change requires a rerun of validation depends in part on the connection through the hierarchy. In the device A1 and instance 1 under test, which is a concrete example of this in a general hierarchical structure example, if the Schematic view of device 1 and instance 2 is changed, this device is a dummy device and is in the simulator. There is no need to rerun the simulator as it does not change the matrix stamped with.

In the view to FIG. 6, the Schematic view of C1, Instance 1 is part of the configuration of the simulator model, where it is modified and the modification is substantive enough to affect the simulator matrix. , Testbench 1 needs to be rerun. The Schematic view of C1, instance 2 does not form part of the configuration of the simulator model example and therefore does not need to rerun Test Bench 1 if it changes.

At a more abstract level, if the Schematic view of C1 is modified and therefore the schematic view in Instances 1 and 2 is modified to affect the modification of the information stamped in the simulator matrix, test bench 1 is used. Need to be re-executed. If an insubstantial change to the Schematic view of C1 is made, for example, by adding a comment and the information stamped by the simulator in the matrix is not changed, then there is no need to re-execute this design configuration. It is clear that determining whether configuration changes have been made and the impact of matrix stamping can have a significant impact on the number of validation runs required.

FIG. 7 shows some of the various model views that can be selected to model the power management chip PMIC700. PMIC_testbench has a Behavioral_vams level and a Behavioral_va level with stimulation and output. The PMIC has a Schematic level and a Schematic_behavioral level. LDOs, LDO enable controls, and battery supervisors are defined at the Schematic level, the Schematic_behavioral level, and the Behavioral_vams level. Voltage references, LDO feedback, and LDO comparators are defined at the Schematic and Behavioral_va levels. LDO amplifiers are defined at the Schematic level and the Schematic_parasitics level. The Behavioral Amplifier and the Behavioral Bias are defined at the Behavioral_va level. LDO control logic is defined at the Schematic and Verilog ™ levels. Devices 1-X are defined at the Spece level.

FIG. 8 shows a first test hierarchical structure of the power management chip PMIC described in FIG. 6 of the power management chip 800. This figure shows a part of the hierarchical structure when the Spice primitive component configuration is defined. In this model, device 1 and instance 2 are dummy devices and do not change the simulator matrix.

FIG. 9 shows a second test hierarchical structure of the power management chip PMIC described in FIG. 7 of the power management chip 900. This figure shows part of one hierarchical structure of possible mixed configurations with some analog behavioral level models, some Verilog ™ representations, and some Spece primitive components.

FIG. 10 shows a third test hierarchical structure of the power management chip PMIC described in FIG. 7 of the power management chip 1000. This figure shows a part of the hierarchical structure when the behavioral configuration is defined.

FIG. 11 shows a simple example of an operational amplifier with some typical features of an amplifier contained within a relatively large system on chip (SOC). This simple example can also demonstrate the increasing complexity of today's validation challenges for mixed signal designs. It is a simple multiplexer (mux) that supplies the input to the amplifier. The control signal IN_CTRL to the multiplexer functions as a digital input signal to a series of logic gates in the multiplexer block. These gates then control the switch to select from two pairs of analog inputs: pair 1 (IN_POS_1 and IN_NEG_1) and pair 2 (IN_POS_2 and IN_NEG_1). For example, a value of IN_CTRL equal to logic level "0" can close the switch connected to IN_POS_1 and IN_NEG_1, while an IN_CTRL value of logic level "1" closes the switch connected to IN_POS_1 and IN_NEG_1. be able to. The selected analog input is then output from the multiplexer. At this time, these signals are connected to the amplifier input. The multiplexer block also has a connection to the power supply. In this case, the power supply connection is to the analog supply voltages A VDD and GND because the analog signal passes through the block.

Also for the amplifier block, the power supply connection is to the analog supply voltages A VDD and GND. It is not uncommon for a complex SOC to have multiple internal power supplies. Even in the case of analog blocks, there may be options such as different power supply levels. In other cases, the same voltage level can be supplied, but one source can be used for critical blocks that can be sensitive to any noise on the feed line. Other blocks that are noisier (typically due to features such as high frequency switching) may be connected to different sources of the same voltage level. For this reason, digital blocks are almost always powered separately from analog blocks. Moreover, with the increasing importance of power reduction, some power supplies can be turned off during various modes of operation. As a result, design engineers may need to verify that a given block is connected to an available source at the appropriate time.

Another common configuration within a relatively large chip is to have a common block that provides much of the bias current required for analog functionality. In this example, the amplifier has an input with a 1uA bias current. Other common options include trim and control or programmable signals. In this example, the amplifier has two control bits GAIN_CTRL <1: 0> in which the gain value can be set and a 3-bit GAIN_TRIM <2: 0> in which the gain value is slightly adjusted. Trimming is typically performed when each device is tested and used to compensate for manufacturing process variations and match the desired gain value as close as possible to the specified value. In this case, GAIN_CTRL is a programmable feature that selects the best gain setting for a particular application. The enable signal allows the amplifier to be powered on or off while the chip is operating. These types of controls are often provided to minimize power consumption, allow for a clean power-on sequence of the chip, and provide protection during failure situations.

In this simple example, there are many examples of verification requirements. These requirements can be divided into several categories:
-Operating function-Does the amplifier and multiplexer meet their respective functional requirements? -Does the multiplexer correctly pass the selected input signal to the multiplexer output? -The amplifier behaves as expected: gain, through rate, input range, output range, etc. Satisfies • Power supply and bias-Is the block connected to the proper power supply and is properly biased? -The source and bias are available when expected and operate within the expected range. -Whether the correct behavior is observed in all settings of the control signal-control signal-Failure status-If any of the block pins behaves in a manner outside the permissible or expected range, does the block behave appropriately? Or is the situation unmanageable (stopped elsewhere) or unpredictable?

In this patent, much of the value comes as a result of more efficient management of the process of stepping through a large number of possible combinations. One of the best examples is simply stepping through a large number of digital control or trim options. In addition, by linking to the specification database, requirements that change throughout the design process can be easily updated and managed, and simulations can be re-run if necessary based on changes in the specification database. In addition, the results from verification activities can then be compared to the requirements managed within the specification database.

Consider this simple example in the context of a relatively large SOC and a top-level test bench for this SOC. This test bench can be one of many test benches on the chip, but this example shows how the verification intellectual property developed for amplifiers can be leveraged from top-level test benches as well. Can be shown. The hierarchical concept shown in FIG. 6 can be embedded to show how the test bench example can be constructed. In this example, A1 from FIG. 6 is programmed through software with the chip and all the circuits or models needed to represent the system inputs, output loads, and other components of the external power supply or chip. Represents a top-level test bench that includes parts of the test configuration that can be. An example of this hierarchical structure can be seen in the figure of FIG. As mentioned above, each item in the hierarchy can be represented by many types of views, depending on the information available and the intended purpose of the block.

The second level of the hierarchical structure in this example, which correlates to level "B" in FIG. 6, includes all elements placed within this top level test bench. The first element is the chip itself. In this example, the chip is identified as cell B1. B2 can be a cell containing a circuit or model that represents a system input to the chip. B3 can be a cell containing a model or circuit that represents the system output load as seen from the system-provided power supply and chip. In this example, the B4 connects directly to the pins of the chip or to other blocks, provides values for any parameterized function within any block, and / or monitors specific performance during simulation. A block written in software for measurement. This simple example includes only the signals that lead to the production of the signal at the relatively low level of the amplifier block example.

This software-capturable block B4 typically uses high-level languages targeting integrated circuit design (SystemVerilog, Verilog, Verilog-AMS, Verilog-A, SystemC, VHDL, etc.), but C, C ++. , TCL, PERL, and other more versatile languages and scripts may be utilized. The software part can generate stimuli, define design values for parameters in existing circuits or system blocks, or measure and monitor performance throughout the simulation. For example, SystemVerilog's Universal Verification Methodology (UVM) includes a common structure for defining and monitoring scoreboard functions as well as defining stimuli. Digital verification methodologies also include many specific verification intellectual property (VIPs) targeting specific features or protocols. When instantiated, defined communication standards such as the Universal Serial Bus (USB) and Serial Peripheral Interface (SPI) Bus supply data through the interface during the verification process and the interface conforms to the protocol standard. You will have a specific verification IP that you can use to test and verify that you are doing so. In this example, digital trim and control are assumed to be programmed through the SPI interface or by the chip itself.

In the test bench of FIG. 12, the external power supply VDD_EXT is generated by the Verilog-A code in TOP_AMST. In this case, VDD_EXT is an input to the SUPPLIES_AND_OUTPUTS block. This block then outputs VDD, which is connected to the SOC as a main external power supply. For inputs, system inputs are generated within the INPUTS block and then pass through the TOP_AMST block before connecting to the SOC. As the input passes through the test harness, both the voltage and current of the input signal can be monitored (or used as parameters for other calculations) throughout the simulation. Similarly, the VOUT from the SOC passes through TOP_AMST before entering the SUPPLIES_AND_OUTPUTS block. Finally, VOUT_EXT is supplied from the SUPPLIES_AND_OUTPUTS block to TOP_AMST for monitoring. Determining which signal should pass through the AMST test harness block depends strongly on the system and the amount of circuit / model required around the chip to properly represent the entire system. Ultimately, those decisions depend on the system design and verification plan.

In FIG. 13, relatively low level signals of the hierarchical structure are inaccessible unless they are carried to the top level pins. Further consider the hierarchical structure of instance B1 representing the chip. In this example, the next level of chip hierarchy includes C1 SOC_CORE and C2 SOC_PAD_RING. Next, go down C1 and look at the D1 AMP_CORE subsystem, D2 PWR_MGMT (chip power management function), and D3 DIG_CTRL from the top.

FIG. 15 further descends into the amp_core subsystem and shows the E3 AMP_AMST, a Verilog AMS block containing subsystem elements: E1 mux, E2 amp, and verification IP for this subsystem.

Consider the case of a simple bandgap with a digital trim bit. The purpose of the circuit is to generate a predictable output voltage over environmental (eg, temperature) and process (eg, oxide thickness) changes. Digital trim bits provide a range of output values with a predictable step size. This bandgap AMST needs to define the entire bandgap test circuit, including power supply, load components, and digital trim values. First, let's take a look at a simple source definition:

# Supply start lamp time
my $ glSupplyRampStartObj = $ glAMSTObj-> create_variable ("glSupplyRampStartDbl", 50e-9);
# Supply end lamp time
my $ glSupplyRampEndObj = $ glAMSTObj-> create_variable ("glSupplyRampEndDbl", 100e-9);
# Supply voltage value
my $ glAvddValObj = $ glAMSTObj-> create_variable ("glAvddValDbl", 5);
# Generate supply PWL
$ glAMSTObj-> create_vpwl (
"arP0"=>"AVDD",
"arP1"=>"AVSS",
"arPwlRef"=> [
0, 0,
$ glSupplyRampStartObj, 0,
$ glSupplyRampEndObj,
$ glAvddValObj
]
);

This example produces a simple piecewise linear supply of 0V at t = 0, 0V at t = 50ns, and 5V at t = 100ns. Note that all variables are parameterized. The program can read this AMST file and then extract a list of variables and their types. This ability allows the user to modify / sweep these values and build various test vectors from the same group of AMST test benches. It is also possible to instantiate additional circuit components by reference. For example, the code below adds a Verilog-A load resistor to the bandgap:

# Programmatically define load resistors
$ glAMSTObj-> add_module_instance (
"arModuleName"=>"resistor",
"arModuleFilename"=>"behav_resistor.va",
"arParameterValueMap"=> {
"r"=> $ glOutputLoadObj
},
"arNodeNetMap"=> {
"IN_NODE0"=>"VBG",
"OUT_NODE1"=>"AVSS",
}
);

Bandgap should be tested for all possible combinations of trim bits. The following grammar sets up an all-factor experiment for all trim bits:

#Test all possible combinations of digital inputs
$ glAMSTObj-> create_voltage_full_factorial (
"arFactDelay"=> $ glSupplyRampEndObj,
"arFactStateValRef"=> [0, $ glAvddValObj],
"arFactStateDurRef"=> [0.50, 0.50],
"arFactChgTimeRef"=> [2e-9, 2e-9],
"arFactMinPeriod"=> 10e-6,
"arFactSignalRef"=> [
{"arP0"=>"DTRIM [0: 2]",
"arP1"=>"AVSS"}
]
);
gets expanded into:

module amst (...)
output [2: 0] DTRIM;
electrical [2: 0] DTRIM;
output AVSS;
electrical AVSS;
parameter real glSupplyRampEndDbl = 1e-07;
parameter real glAvddValDbl = 5;
real loDtrimVal2loAvssValBit0;
real loDtrimVal2loAvssValBit1;
real loDtrimVal2loAvssValBit2;
analog begin
@ (initial_step) begin
loDtrimVal2loAvssValBit0 = 0;
loDtrimVal2loAvssValBit1 = 0;
loDtrimVal2loAvssValBit2 = 0;
end
...
// DTRIM [0]
@ (timer (glSupplyRampEndDbl, 1e-05, 1p))
loDtrimVal2loAvssValBit0 = 0;
@ (timer ((glSupplyRampEndDbl + 0.5 * 1e-05), 1e-05, 1p))
loDtrimVal2loAvssValBit0 = glAvddValDbl;
V (DTRIM [0], AVSS) <+ transition (loDtrimVal2loAvssValBit0, 0, 2e-09, 2e-09);
// DTRIM [1]
@ (timer (glSupplyRampEndDbl, (1e-05 * 2), 1p))
loDtrimVal2loAvssValBit1 = 0;
@ (timer ((glSupplyRampEndDbl + (0.5 * 1e-05 * 2)), (1e-05 * 2), 1p))
loDtrimVal2loAvssValBit1 = glAvddValDbl;
V (DTRIM [1], AVSS) <+ transition (loDtrimVal2loAvssValBit1, 0, 2e-09, 2e-09);
// DTRIM [2]
@ (timer (glSupplyRampEndDbl, (1e-05 * 4), 1p))
loDtrimVal2loAvssValBit2 = 0;
@ (timer ((glSupplyRampEndDbl + (0.5 * 1e-05 * 4)), (1e-05 * 4), 1p))
loDtrimVal2loAvssValBit2 = glAvddValDbl;
V (DTRIM [2], AVSS) <+ transition (loDtrimVal2loAvssValBit2, 0, 2e-09, 2e-09);
...
endmodule

The above definition states that there are three trim signals. Each signal has two valid values that need to be tested. All factors list all possible states. Therefore, in the case of three binary variables, one set of eight periods is obtained to test all valid signal combinations. Once the test circuit and stimulus are defined, measurements and claims need to be defined. An example of a simple voltage measurement:

my $ glVbgTrim0MeasObj = $ glAMSTObj-> create_voltage_measure (
"arMeasureNet"=>"VBG",
"arRefNet"=>"AVSS",
"arMinVal"=> 0.850,
"arMaxVal"=> 0.900
);

This voltage measurement is true whenever the output node VBG is between 0.850 and 0.900. This measurement is performed and evaluated at every time step of the simulation. You can combine a collection of Boolean measurements to generate a conditional claim. For example, the following claim is that if the DTRIM [2: 0] bit is "000" and the VDD supply exceeds its minimum threshold, the $ glVbgTrim0MeasObj measurement defined above (0.850≤VBG≤0) .900) states that it must be true.

# When DTRIM = "000"=> VBG = 0.9
$ glAMSTObj-> create_conditional_assert (
"arAssertNameStr"=>'when DTRIM = \ "000 \"=> VBG = 0.9',
"arCondition"=> assert_and (
$ glVddAboveMin,
assert_not ($ glDtrim0MeasObj),
assert_not ($ glDtrim1MeasObj),
assert_not ($ glDtrim2MeasObj)
),
"arAssertDelay"=> $ loMeasureDelayDbl,
"arAssert"=> assert_and (
$ glVbgTrim0MeasObj,
$ glPgoodMeasObj
),
"arAssertAtLeastOnce"=> 1
);

It would be easier to measure the output voltage at some point (for example, at 100us VBG should be between 0.850 and 0.900). This type of check can also be easily implemented in AMSTR. However, the above claim explicitly captures a subset of the bandgap specs, not only at a single point in time, but whenever the claim conditions are met (eg, "For DTRIM = 000 => VBG =". 0.9 "), much more powerful to make sure that part of the spec is true.

In the following example, the following code generates a direct branch contribution statement for measurement purposes. In this example, there are 16 reference current wire buses. The following syntax is used to guarantee that the current is 0.9 ^* 750nA to 1.1 ^* 750nA after 1 us.

zip_setup_std_supplies (
50e-09, 100e-09,
[
["Ib_750n_AMST_IN [0:15]", "Ib_750n_AMST_OUT [0:15]", 0]
]
);

zip_assert_output_currents (
0.9, 1.1, 1e-06,
{
"Ib_750n_AMST_IN [0:15]"=> 750e-09
}
);

...
parameter real loSupplyRampStartDbl = 5e-08;
parameter real loSupplyRampEndDbl = 1e-07;
parameter real loIb_750n_AMST_INValDbl = 0;
parameter real arVolEnGndMin1 = 2.85;
parameter real arVolEnGndMax1 = 3.15;
parameter real arCurIb_750n_amst_in0Min1 = 6.75e-07;
parameter real arCurIb_750n_amst_in0Max1 = 8.25e-07;

real loChangeTimeV1;
real loIb_750n_amst_inValBit0;

// Create analog conditional claim 1
integer loVolEnGndAboveMin1;
integer loVolEnGndAboveMax1;
integer loCurIb_750n_amst_in0AboveMin1;
integer loCurIb_750n_amst_in0AboveMax1;
integer loCondition1;
integer loOldCondition1;
integer loSat1;
integer loFail1;
integer loDisplay1;
integer loAssert1;
integer loMeasure1;
real loCheckTime1;
integer loAssertOutOn1;

analog begin
@ (initial_step) begin
loChangeTimeV1 = 0;
loIb_750n_amst_inValBit0 = 0;

// Create analog conditional claim 1
loVolEnGndAboveMin1 = 0;
loVolEnGndAboveMax1 = 0;
loCurIb_750n_amst_in0AboveMin1 = 0;
loCurIb_750n_amst_in0AboveMax1 = 0;
loCondition1 = 0;
loOldCondition1 = 0;
loSat1 = 0;
loFail1 = 0;
loDisplay1 = 0;
loAssert1 = 0;
loMeasure1 = 0;
loCheckTime1 = 0;
loAssertOutOn1 = 0;
end

V (NEG_Ib_750n_amst_in0, Ib_750n_AMST_OUT [0]) <+ transition (loIb_750n_amst_inValBit0, 0, loChangeTimeV1, loChangeTimeV1);

V (Ib_750n_AMST_IN [0], NEG_Ib_750n_amst_in0) <+ 0;

// Current: 2.85 <EN <3.15 ==> 6.75e-07 <Ib_750n_AMST_IN [0] <8.25e-07
loDisplay1 = 1;
`ZIP_VCROSS_TO_BLN (EN, GND, arVolEnGndMin1, loVolEnGndAboveMin1);
`ZIP_VCROSS_TO_BLN (EN, GND, arVolEnGndMax1, loVolEnGndAboveMax1);
`ZIP_ICROSS_TO_BLN (Ib_750n_AMST_IN [0], NEG_Ib_750n_amst_in0, arCurIb_750n_amst_in0Min1, loCurIb_750n_amst_in0AboveMin1);
`ZIP_ICROSS_TO_BLN (Ib_750n_AMST_IN [0], NEG_Ib_750n_amst_in0, arCurIb_750n_amst_in0Max1, loCurIb_750n_amst_in0AboveMax1);
loCondition1 = (loVolEnGndAboveMin1 &&! loVolEnGndAboveMax1);
if (loCondition1 &&! loOldCondition1) begin
loAssertOutOn1 = 0;
loCheckTime1 = $ abstime + 1e-06;
end
@ (timer (loCheckTime1)) begin
loAssertOutOn1 = 1;
end
loAssert1 = (loCurIb_750n_amst_in0AboveMin1 &&! loCurIb_750n_amst_in0AboveMax1);
if (loCondition1 && loAssertOutOn1) begin
loMeasure1 = loAssert1;
if ((loSat1 &&! LoFail1 && loMeasure1) || (! loSat1 && loFail1 &&! LoMeasure1)) begin
loDisplay1 = 0;
end
if (loDisplay1) begin
if (loMeasure1) begin
loSat1 = 1;
loFail1 = 0;
$ fdisplay (fileDescriptor, "CURRENT: when 2.85 <EN <3.15 ==> 6.75e-07 <Ib_750n_AMST_IN [0] <8.25e-07 succeeds% e", $ abstime);
end else begin
loSat1 = 0;
loFail1 = 1;
$ fdisplay (fileDescriptor, "CURRENT: when 2.85 <EN <3.15 ==> 6.75e-07 <Ib_750n_AMST_IN [0] <8.25e-07 fails% e", $ abstime);
end
end
end
loOldCondition1 = loCondition1;
end

In one example, FIG. 16 has step 1610 to receive an electronic design and at least one indirect branch contribution statement, at least one specification parameter stored in at least one specification database, stored in at least one specification database. Electronic design, including at least one stimulus parameter, and step 1612 to receive at least one analog test harness model having at least one of the at least one measurement parameter stored in the at least one specification database. A computer-implemented method 1600 from electrical design to netlist of translation of verification commands is shown. The method also includes at least one analog test harness model, at least one specification parameter stored in at least one specification database, at least one stimulus parameter stored in at least one specification database, and at least one specification database. To translate at least one indirect branch contribution statement into multiple direct branch contribution operators, at least partially based on at least one of the at least one measurement parameter stored in, and at least partially based on the translation. 1616 includes step 1616 to generate a netlist. Electronic design can include multiple levels of hierarchy. The analog test harness can exist as a module at the lowest level, in which case it acts as a test bench packaged with the circuit for any hierarchical level. With reference to FIG. 6 again, the electronic design includes each block connected in the figure, incorporating different levels of hierarchy. The top level hierarchy is A1 and the next level hierarchy is B, which includes B1 and B2, and below the B hierarchy is a C hierarchy having C1, C2, and C3. In this specific example, below the B1 level, the model is composed of a Schematic model and a Spice model. At the B2 level, the models include the Schematic_behavioral model and the Behavioral_va model. In this example, the analog test model is connected to the A1, instance 1 level, and is connected through a netlist, which is a line connecting to each of the components under test.

In one example, an indirect branch contribution statement can loop, in which a series of instructions is repeated until the escape condition is met. The indirect statement may be conditional, where it parses true or false Boolean conditions and input, output, or device naming, infers a set of instructions, and outputs to the net. Alternatively, one of the inputs is analyzed and the operation is performed based on the analysis in which the judgment is made based on the analysis.

The analog test harness model can be placed at any level of the design hierarchy, from the top block level to individual circuits and the like. An example of an analog test harness model is described within a low level block to form a module within the design, where the test module is contained within a separate block. One advantage that can occur in connection with including the analog test harness model in separate blocks is that it can be transmitted with the circuit design to support self-verification within the module. In some usage models, the test harness model can be connected by the net or the port name used within the test harness, is not physically placed on the schematic, and the test harness model is included in the netlist. This technique can often be more easily managed as a separate text file, but is used in analog and mixed signal designs to contain the information contained within the netlist. Examples include SPICE model files for basic components such as transistors, behavioral models written in programming, or hardware language and register transfer level (RTL) descriptions for digital functions.

In one example, a netlist provides electronically designed connectivity, essentially which terminal of one device is connected to which terminal of another device. The netlist can also include device details for each device.

In one example, translating an indirect branch contribution statement into multiple direct branch contribution operators based on an analog test harness model translates one blanket statement into a series of individual statements that include the span of that blanket statement. That is. Basically, the statement "index connections <1:10>" is decomposed into "condition 1", "condition 2", ..., "Condition 10".

Translations may utilize standardized analog hardware description languages that can at least construct at least one of the Verilog-A grammar and the Verilog-AMS grammar.

In another example, FIG. 17 has at least one indirect branch contribution statement with step 1710 receiving the representation of the electronic design and the representation of the electronic design, and at least one stored in at least one specification database. Receives at least one analog test harness model having at least one specification parameter, at least one stimulus parameter stored in at least one specification database, and at least one measurement parameter stored in at least one specification database. A computer-implemented method 1700 of electronic design verification commands from electronic design to netlist, including with step 1712, is shown. The method further comprises at least one analog test harness model, at least one specification parameter stored in at least one specification database, at least one stimulus parameter stored in at least one specification database, and at least one specification database. In step 1714, translating at least one indirect branch contribution statement into multiple direct branch contribution operators, at least in part based on at least one of the at least one measurement parameter stored in and the electronic design. Includes step 1716 to generate a netlist based at least in part. With reference to FIG. 7 again, the hierarchical structure of the design example and each of the models are shown. One of the goals of the verification is to test each block of design and each model under appropriate conditions. Translating an indirect branch contribution statement assists in this multidimensional task by automating at least part of the cycle.

At least one analog test harness model can have at least one stimulus, at least one stimulus claim, at least one power claim, and / or at least one power measurement. The representation of the electronic design may be an analog or mixed signal, with at least one transistor level circuit, at least one behavior modeled circuit, and at least one parasitic model based on at least a physical design. It may include at least one circuit based on and / or at least one behavior modeled circuit.

In another example, FIG. 18 has at least one of step 1810 receiving a representation of the electronic design and at least one stimulus and at least one stimulus claim and is stored in at least one specification database. Receives at least one analog test harness model having one specification parameter, at least one stimulus parameter stored in at least one specification database, and at least one of at least one measurement parameter stored in at least one specification database. Step 1812 and step 1814 to receive at least one validation subroutine command for the electronic design, wherein at least one validation subroutine command receives at least one validation subroutine command having at least one indirect branch contribution statement. 1800 is a computer-implemented method of translating an electronic design verification command, from electronic design to netlist, with step 1814. This method also includes at least one validation subroutine command, at least one analog test harness model, at least one spec parameter stored in at least one spec database, and at least one stimulus stored in at least one spec database. Standardized analog hardware corresponding to at least one validation subroutine command based on at least one of the parameters and at least one measurement parameter stored in at least one specification database and the electronic design. It includes step 1816 translating into a descriptive language and step 1818 generating a netlist based at least in part on the translation. The stimulus claim can define attribute definitions, constraints, etc. in the electronic system. Referring again to FIG. 8, the electronic design includes each of the connected blocks following the PMIC_testbench, and at least one analog test harness model relates to the block marked PMIC_testbench. The netlist of the model shows each connection, which is the connection line of FIG. The hierarchical structure associated with this design indicates that the LDO, battery supervisor, and voltage reference blocks are lower in the hierarchical structure than the PMIC blocks. In addition, this model primarily reviews the outline of the design. The ability to translate at least one indirect branch contribution statement into multiple direct branch contribution operators can increase the efficiency of reviewing each hierarchy and each part of the design for each block in the design.

A standardized analog hardware description language may include at least one of the Verilog-A grammar and the Verilog-AMS grammar. At least one analog test harness model may have at least one output claim and at least one output measurement.

In another example, FIG. 19 has at least one of step 1910 receiving a representation of the electronic design and at least one output claim and at least one output measurement and is stored in at least one specification database. At least one analog test harness model having at least one specification parameter, at least one stimulus parameter stored in at least one specification database, and at least one of at least one measurement parameter stored in at least one specification database. 1912 and step 1914 to receive at least one validation subroutine command for the electronic design, wherein the at least one validation subroutine command has at least one indirect branch contribution statement for the electronic design. A computer-implemented method of translating an electronic design verification command, having step 1914 to receive one verification subroutine command, shows the electronic design for a netlist via the verification subroutine of 1900. This method also includes at least one validation subroutine command, at least one analog test harness model, at least one spec parameter stored in at least one spec database, and at least one stimulus stored in at least one spec database. A standardized analog hardware description language with at least one validation subroutine command based on at least one of the parameters, and at least one measurement parameter stored in at least one specification database, and electronic design. Includes step 1916 to translate into at least one corresponding and step 1918 to generate a netlist based at least in part on the translation. With reference to FIG. 9 again, the electronic design includes each of the connected blocks following the PMIC_testbench, and at least one analog test harness model relates to the block labeled PMIC_testbench. The netlist shows the connectivity indicated by the line connecting each block. The hierarchical structure associated with this design indicates that the LDO, battery supervisor, and voltage reference blocks are lower in the hierarchical structure than the PMIC blocks. This model is a schematic, schematic behavioral, and behavioral. Review each aspect of va. The overall electronic design is the same as in FIG. 8, but the objects tested, the hierarchy, and the connectivity are different. The ability to translate at least one indirect branch contribution statement into multiple direct branch contribution operators assists in a more complete review of various models and hierarchies.

A standardized analog hardware description language may consist of at least one of the Verilog-A grammar and the Verilog-AMS grammar. At least one validation subroutine command can have at least one specification subset. At least one analog harness model may confirm at least one specification subset based at least in part on at least one of at least one output claim and at least one output measurement. At least one specification subset may have data transformations.

In another example, FIG. 20 shows an electronic design via an extracted data comparison computer program product performed on a non-temporary computer-enabled medium 2000, where the non-temporary computer-enabled medium is a series of instructions. When a series of instructions is executed by the processor, it causes the processor to perform a method of translating the verification command of the electronic design, the method of receiving at least one analog test harness model in step 2010. The at least one analog test harness model has at least one stimulus and at least one stimulus claim, and the at least one analog test harness model is at least one stored in at least one specification database. It has at least one of one specification parameter, at least one stimulus parameter stored in at least one specification database, and at least one measurement parameter stored in at least one specification database, and at least one of the above parameters. Step 2010, which receives at least one analog test harness model treated as a parameterized variable, and step 2012, which receives at least one validation subroutine command for the electronic design, the at least one validation subroutine command is: It has a step 2012 of receiving at least one validation subroutine command having at least one indirect branch contribution statement. The method also finds at least one rule based on at least one analog test harness and at least one validation subroutine command in step 2014, at least one validation subroutine command, and at least one retrieved. One rule, at least one analog test harness model, at least one specification parameter stored in at least one specification database, at least one stimulus parameter stored in at least one specification database, and at least one specification database. At least one of the stored at least one measurement parameter, which treats at least one of the above parameters as a parameterized variable, at least one, and at least in part based on electronic design. Includes step 2016 to translate one validation subroutine command into the corresponding at least one standardized analog hardware description language. This method electrically simulates at least one subcomponent using at least a partial use of at least one analog test harness model and step 2018 to generate a netlist based at least partially on the translation. 2020, step 2022 to extract at least one performance attribute of the electronic design to be electrically simulated, and at least one extracted performance attribute and at least one output measurement stored in at least one specification database. It further includes step 2024 for comparison with one specification parameter. With reference to FIG. 10 again, the electronic design includes each of the connected blocks following the PMIC_testbench, and at least one analog test harness model relates to the block labeled PMIC_testbench. In this example, the PMIC hierarchy and the LDO, battery supervisor, and voltage reference hierarchy are reviewed. At the highest level, the PMIC is reviewed at the schematic level, the LDO is reviewed at the Behavioral_vams, the battery supervisor is reviewed at the Behavioral_vams, and the voltage reference is reviewed at the Behavioral_vams level.

The computer program product has a step of fixing at least one parameterized variable, a step of changing at least one parameterized variable in at least one separate simulation run, and / or at least within at least one simulation run. It may further include the step of changing one parameterized variable. At least one performance attribute can be extracted during or after the simulation. At least one analog test harness model may have at least one output claim and at least one output measurement.

In another example, FIG. 21 shows an electronic design through an extracted data comparison of computer program product 2100 performed on a non-temporary computer-enabled medium 2100, where the non-temporary computer-enabled medium is a series. When a series of instructions is executed by a processor, it causes the processor to perform a method of translating an electronic design verification command, the method of receiving at least one analog test harness model. 2110, at least one analog test harness model having at least one of at least one output claim and at least one output measurement, and at least one analog test harness model stored in at least one specification database. It has at least one of the specified parameters, at least one stimulus parameter stored in at least one specification database, and at least one measurement parameter stored in at least one specification database. At least one is treated as a parameterized variable, step 2110 receiving at least one analog test harness model and step 2112 receiving at least one verification subroutine command for the electronic design, at least one validation. The subroutine command includes step 2112 to receive at least one validation subroutine command having at least one indirect branch contribution statement. The method also retrieves at least one rule based on at least one analog test harness and at least one validation subroutine command, at least in part, in step 2114, at least one validation subroutine command, and at least one retrieved. In one rule, at least one analog test harness model, at least one specification parameter stored in at least one specification database, at least one stimulus parameter stored in at least one specification database, and at least one specification database. At least one of at least one stored measurement parameter, at least one of the above parameters being treated as a parameterized variable, at least one and at least in part based on electronic design. It includes step 2116 translating one validation subroutine command into the equivalent of at least one of the standardized analog hardware description languages, and step 2118 generating a netlist based at least in part on the translation. This method is at least partially utilized in at least one analog test harness model to electrically simulate at least one subcomponent in step 2120 and at least one performance of the electronic design undergoing electrical simulation. Step 2122 to extract the attributes and step 2124 to compare at least one of the extracted at least one performance attribute and at least one output claim and at least one output measurement with at least one specification in the at least one specification database. And further include. With reference to FIG. 10 again, the electronic design includes each of the connected blocks following the PMIC_testbench, and at least one analog test harness model relates to the block labeled PMIC_testbench. In this example, the PMIC hierarchy and the LDO, battery supervisor, and voltage reference hierarchy are reviewed. At the highest level, the PMIC is reviewed at the schematic level, the LDO is reviewed at the Behavioral_vams, the battery supervisor is reviewed at the Behavioral_vams, and the voltage reference is reviewed at the Behavioral_vams level.

A standardized analog hardware description language may include at least one of Verilog-A ™ and Verilog-AMS. In addition, this method modifies at least one analog test harness model based on at least partly based on the specified result, and modifies at least one validation subroutine command based on at least partly based on the specified result. , And / or at least one parameterized variable may include a step of changing. An electronic design can result in at least one of at least one active circuit and at least one passive circuit, and an electronic design that produces at least one active circuit has at least one gain and at least one. At least one of at least one direction of the electrical signal may be adjusted. At least one validation subroutine command can have at least one specification subset, and at least one analog harness model is at least partially based on at least one output claim and at least one output measurement. At least one specification subset can be identified.

Although the creation and use of examples for various embodiments of the present disclosure is considered herein, it should be understood that the present disclosure presents concepts that can be explained in a wide variety of specific situations. Although the present disclosure has been shown and described with respect to specific examples, it will be apparent to those skilled in the art who have read and understood the specification to come up with equivalents and modifications. The present disclosure includes such equivalents and modifications and is limited only by the appended claims.

It should be understood that the methods and devices can be performed locally or in a distributed manner or remotely, and the step data can be stored locally or remotely. For clarity, detailed descriptions of features, components, and systems common to those skilled in the art are not included. The methods and devices of the present disclosure provide one or more advantages including, but not limited to, improved speed efficiency, reduced calculation time, reduced number of revalidations, and the like. Although the present disclosure has been described with reference to examples for particular illustration, what is described herein is not intended to be construed in a limited sense. For example, in certain cases, variations or combinations of steps in the examples shown and described can be used without departing from the present disclosure. Various modifications and combinations of examples for illustration and other advantages and examples will be apparent to those skilled in the art with reference to the drawings, specification and claims.

Claims (45)

A computer-implemented method of translating electronic design verification commands,
The step of receiving the electronic design and
At least one specification parameter having at least one indirect branch contribution statement and stored in at least one specification database, at least one stimulus parameter stored in the at least one specification database, and in the at least one specification database. A step of receiving at least one analog test harness model having at least one of the stored at least one measurement parameter.
The at least one analog test harness model, at least one specification parameter stored in the at least one specification database, the at least one stimulus parameter stored in the at least one specification database, and the at least one specification database. The step of translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators, at least partially based on the at least one of the at least one measurement parameter stored in.
The steps to generate a netlist based at least in part on the translation,
Including methods. The translation is a computer-implemented method of translating the electronic design verification command according to claim 1, which has a standardized analog hardware description language. The computer for translating the electronic design verification command according to claim 2, wherein the standardized analog hardware description language includes at least one of the Verilog-A grammar and the Verilog-AMS grammar. How to be implemented. A computer-implemented method of translating electronic design verification commands,
The step of receiving the representation of the electronic design,
At least one specification parameter having at least one indirect branch contribution statement with said representation of the electronic design and stored in at least one specification database, at least one stimulus parameter stored in said at least one specification database. And the step of receiving at least one analog test harness model having at least one of the at least one measurement parameter stored in the at least one specification database.
The at least one analog test harness model, at least one specification parameter stored in the at least one specification database, the at least one stimulus parameter stored in the at least one specification database, and the at least one specification database. The step of translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators, at least in part based on the at least one of the at least one measurement parameter stored in the computer and the electronic design. The steps to generate a netlist based at least in part on the translation,
Including methods. The computer-implemented method of translating an electronic design verification command according to claim 4, wherein the at least one analog test harness model has at least one stimulus. The computer-implemented method of translating the electronic design verification command according to claim 4, wherein the at least one analog test harness model has at least one stimulus claim. The computer-implemented method of translating an electronic design verification command according to claim 4, wherein the at least one analog test harness model has at least one stimulus claim including at least one stimulus parameter from a specification database. The computer-implemented method of translating an electronic design verification command according to claim 4, wherein the at least one analog test harness model has at least one output claim. The computer-implemented method of translating an electronic design verification command according to claim 4, wherein the at least one analog test harness model has at least one output claim that includes at least one specification parameter from a specification database. The computer-implemented method of translating an electronic design verification command according to claim 4, wherein the at least one analog test harness model has at least one output measurement. The translation of the electronic design verification command according to claim 4, wherein the at least one analog test harness model has at least one output measurement having at least one output claim including at least one measurement parameter from the specification database. How to be implemented on a computer. A computer-implemented method of translating an electronic design verification command according to claim 4, wherein the representation of the electronic design is analog. A computer-implemented method of translating an electronic design verification command according to claim 4, wherein the representation of the electronic design is a mixed signal. The computer-implemented method of translating the electronic design verification command according to claim 4, wherein the representation of the electronic design has at least one transistor level circuit section. The computer-implemented method of translating an electronic design verification command according to claim 4, wherein the representation of the electronic design has at least one behavior-modeled circuit unit. The computer-implemented translation of the electronic design verification command according to claim 4, wherein the representation of the electronic design has at least one circuit based on at least one parasitic model that is at least partially based on the physical design. Method. The computer-implemented method of translating the electronic design verification command according to claim 4, wherein the representation of the electronic design has at least one behavior-modeled circuit. A computer-implemented method of translating electronic design verification commands,
The step of receiving the representation of the electronic design,
At least one specification parameter having at least one stimulus and at least one of the at least one stimulus claims and stored in at least one specification database, at least one stimulus parameter stored in the at least one specification database, and A step of receiving at least one analog test harness model having at least one of at least one measurement parameter stored in the at least one specification database.
A step of receiving at least one verification subroutine command for the electronic design, wherein the at least one verification subroutine command has at least one indirect branch contribution statement and a step of receiving at least one verification subroutine command.
The at least one verification subroutine command, the at least one analog test harness model, at least one specification parameter stored in the at least one specification database, and at least one stimulus parameter stored in the at least one specification database. , And standardized analog hardware corresponding to the at least one verification subroutine command, at least in part based on at least one of the at least one measurement parameter from the at least one specification database and the electronic design. Steps to translate into a description language,
The steps to generate a netlist based at least in part on the translation,
Including methods. The computer for translating the electronic design verification command according to claim 18, wherein the standardized analog hardware description language includes at least one of the Verilog-A grammar and the Verilog-AMS grammar. How to be implemented. The computer-implemented method of translating an electronic design verification command according to claim 18, wherein the at least one analog test harness model has at least one output claim and at least one output measurement. A computer-implemented method of translating electronic design verification commands,
The step of receiving the representation of the electronic design,
At least one specification parameter having at least one output claim and at least one output measurement and stored in at least one specification database, at least one stimulus parameter stored in the at least one specification database. And the step of receiving at least one analog test harness model having at least one of the at least one measurement parameter stored in the at least one specification database.
A step of receiving at least one verification subroutine command for the electronic design, wherein the at least one verification subroutine command has at least one verification subroutine command for the electronic design having at least one indirect branch contribution statement. Steps to receive and
The at least one verification subroutine command, the at least one analog test harness model, at least one specification parameter stored in the at least one specification database, and at least one stimulus parameter stored in the at least one specification database. And the standardized analog hardware description of the at least one verification subroutine command based at least in part on the at least one of the at least one measurement parameter from the at least one specification database and the electronic design. Steps to translate into at least one corresponding language, and
The steps to generate a netlist based at least in part on the translation,
Including methods. The computerized implementation of the translation of the electronic design verification command according to claim 21, wherein the standardized analog hardware description language includes at least one of the Verilog-A grammar and the Verilog-AMS grammar. How to be done. The computer-implemented method of translating an electronic design verification command according to claim 21, wherein the at least one verification subroutine command has at least one subset of specifications. 23. The electronic design validation of claim 23, wherein the at least one analog harness model confirms the at least one specification subset based at least in part on at least one output claim and at least one output measurement. A computer-implemented method of translating commands. The at least one analog harness model includes at least one of the at least one output claim, at least one specification parameter stored in at least one specification database, and at least one stimulus parameter stored in the at least one specification database. The electronic design according to claim 23, which confirms the at least one specification subset, at least in part, based on at least one of the at least one measurement parameter stored in the at least one specification database. A computer-implemented method of translating validation commands. A computer-implemented method of translating an electronic design verification command according to claim 23, wherein the at least one specification subset has data conversion. A computer program product implemented on a non-temporary computer-enabled medium, wherein the non-temporary computer-enabled medium stores a series of instructions, and when the series of instructions is executed by a processor, The series of instructions causes the processor to execute a method of translating an electronic design verification command.
A step of receiving at least one analog test harness model, wherein the at least one analog test harness model has at least one stimulus and at least one stimulus claim, said at least one analog test harness. The model has at least one measurement parameter stored in at least one specification database, at least one stimulus parameter stored in the at least one specification database, and at least one specification parameter stored in the at least one specification database. A step of receiving at least one analog test harness model, which has at least one of the above and at least one of the parameters is treated as a parameterized variable.
A step of receiving at least one verification subroutine command for the electronic design, wherein the at least one verification subroutine command has at least one indirect branch contribution statement and a step of receiving at least one verification subroutine command.
A step of searching for at least one rule based at least in part on the at least one analog test harness and the at least one verification subroutine command.
The at least one validation subroutine command, the at least one retrieved rule, the at least one analog test harness model, the at least one measurement parameter stored in the at least one specification database, the at least one specification. At least one of the at least one stimulus parameter stored in the database and at least one of the at least one specification parameter stored in the at least one specification database, and at least one of the parameters as a parameterized variable. A step of translating the at least one validation subroutine command into the corresponding at least one standardized analog hardware description language, at least in part based on the at least one and the electronic design, which deals with one.
The steps to generate a netlist based at least in part on the translation,
A step of electrically simulating at least one subcomponent, at least partially utilizing the at least one analog test harness model.
The step of extracting at least one performance attribute of the electronic design to be subjected to the electrical simulation,
A step of comparing at least one extracted performance attribute and at least one output measurement with at least one specification parameter stored in at least one specification database.
Computer program products that implement how to translate electronic circuit design verification commands, including. A computer program product that implements a method of translating a validation command for an electronic circuit design according to claim 27, further comprising fixing the at least one parameterized variable. A computer program product that implements a method of translating a validation command for an electronic circuit design according to claim 27, further comprising changing the at least one parameterized variable in at least one separate simulation run. A computer program product that implements the method of translating a validation command for electronic circuit design according to claim 27, further comprising changing the at least one parameterized variable within at least one simulation run. A computer program product that implements the method of translating the electronic circuit design verification command according to claim 27, wherein the at least one performance attribute is extracted during the simulation. A computer program product that implements the method of translating the electronic circuit design verification command according to claim 27, wherein the at least one performance attribute is extracted after the simulation. The computer program that implements the method of translating the electronic circuit design verification command of claim 27, wherein the at least one analog test harness model has at least one output claim and at least one output measurement. Product. The at least one analog test harness model includes at least one specification parameter stored in the at least one specification database, the at least one measurement parameter stored in the at least one specification database, and the at least one specification database. 27. The electronic circuit design verification command according to claim 27, which has at least one of the at least one stimulus parameter and at least one of the at least one output claim and at least one output measurement value stored in. A computer program product that implements how to translate. A computer program product implemented on a non-temporary computer-enabled medium, wherein the non-temporary computer-enabled medium stores a series of instructions, and when the series of instructions is executed by a processor, The series of instructions causes the processor to execute a method of translating an electronic design verification command.
A step of receiving at least one analog test harness model, wherein the at least one analog test harness model has at least one of at least one output claim and at least one output measurement, said at least one analog. The test harness model has at least one measurement parameter stored in at least one specification database, at least one stimulus parameter stored in the at least one specification database, and at least one stored in the at least one specification database. A step of receiving at least one analog test harness model that has at least one of the specification parameters and at least one of the parameters is treated as a parameterized variable.
A step of receiving at least one verification subroutine command for the electronic design, wherein the at least one verification subroutine command has at least one indirect branch contribution statement and a step of receiving at least one verification subroutine command.
A step of searching for at least one rule based at least in part on the at least one analog test harness and the at least one verification subroutine command.
The at least one verification subroutine command, the at least one searched rule, the at least one analog test harness model, the at least one specification parameter stored in the at least one specification database, or the at least one. A step of translating the at least one validation subroutine command into at least one of the corresponding standardized analog hardware description languages, at least in part based on the measurement parameters and the electronic design.
The steps to generate a netlist based at least in part on the translation,
A step of electrically simulating at least one subcomponent that is at least partially utilized in the at least one analog test harness model.
A step of extracting at least one performance attribute of the electronic design undergoing the electrical simulation,
A step of comparing at least one of the extracted at least one performance attribute and at least one output claim and at least one output measurement with at least one specification in the at least one specification database.
Including computer program products. The method of translating the electronic circuit design verification command according to claim 35, wherein the standardized analog hardware description language includes at least one of a Verilog-A grammar and a Verilog-AMS grammar. Computer program products to implement. A computer program product that implements a method of translating a validation command for an electronic circuit design according to claim 35, further comprising modifying the at least one analog test harness model based on at least a part of the specified result. A computer program product that implements the method of translating a verification command for an electronic circuit design according to claim 35, further comprising the step of modifying the at least one verification subroutine command based on at least a portion of the specified result. A computer program product that implements a method of translating a validation command for an electronic circuit design according to claim 35, further comprising the step of modifying the at least one parameterized variable. A computer program product that implements a method of translating a verification command for an electronic circuit design according to claim 35, wherein the electronic design produces at least one of at least one active circuit and at least one passive circuit. The verification command for an electronic circuit design according to claim 35, wherein the electronic design produces at least one active circuit that adjusts at least one gain and at least one direction of at least one electrical signal. A computer program product that implements how to translate. A computer program product that implements a method of translating a verification command for an electronic circuit design according to claim 35, wherein the at least one verification subroutine command has at least one subset of specifications. The at least one validation subroutine command has at least one specification subset, the at least one measurement parameter stored in the at least one specification database, and the at least one stimulus stored in the at least one specification database. A computer program product that implements a method of translating a verification command for an electronic circuit design according to claim 35, which has parameters and at least one of the at least one specification parameter stored in the at least one specification database. 42. The electronic according to claim 42, wherein the at least one analog harness model confirms the at least one specification subset based on at least one of the at least one output claim and at least one output measurement. A computer program product that implements how to translate circuit design verification commands. The at least one analog harness model includes the at least one measurement parameter stored in the at least one specification database, the at least one stimulus parameter stored in the at least one specification database, and the at least one specification database. Confirm the at least one specification subset based on at least one of the at least one specification parameter stored in, and at least one of the at least one output claim and at least one output measurement. A computer program product that implements the method of translating the verification command of the electronic circuit design according to claim 42.

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