JP2020205408A - Semiconductor device - Google Patents

Abstract

To alleviate electric field concentration near a bottom of a guard ring.SOLUTION: A semiconductor device comprises a semiconductor substrate including a drift region of a first conductivity type, an active region provided in the semiconductor substrate, and an edge termination structure part provided in the semiconductor substrate and provided between the active region and an end part of the semiconductor substrate on an upper surface of the semiconductor substrate. The edge termination structure part comprises a plurality of guard rings of a second conductivity type in contact with the upper surface of the semiconductor substrate, and a high concentration region of the first conductivity type provided from a position shallower than a lower end of the guard ring to a position deeper than the lower end of the guard ring between two adjacent guard rings and having a higher doping concentration than the drift region. When viewed from a lower surface side of the semiconductor substrate, each guard ring includes a region not covered by the high concentration region.SELECTED DRAWING: Figure 5

Description

The present invention relates to a semiconductor device.

Conventionally, there is known a structure in which a P-type guard ring is provided on an outer peripheral portion of an N-type semiconductor substrate on which a semiconductor element such as an IGBT (insulated gate type bipolar transistor) is formed (see, for example, Patent Document 1).
Patent Document 1 Japanese Patent Application Laid-Open No. 8-167715

In the vicinity of the bottom of the guard ring, the electric field may become stronger.

In order to solve the above problems, in one aspect of the present invention, a semiconductor device including a semiconductor substrate having a first conductive type drift region is provided. The semiconductor device may include an active region provided on the semiconductor substrate. The semiconductor device may include an edge termination structure provided on the semiconductor substrate and provided between an active region and an end portion of the semiconductor substrate on the upper surface of the semiconductor substrate. The edge termination structure may have a plurality of second conductive type guard rings in contact with the upper surface of the semiconductor substrate. The edge termination structure is a first conductive type having a higher doping concentration than the drift region, which is provided between two adjacent guard rings from a position shallower than the lower end of the guard ring to a position deeper than the lower end of the guard ring. It may have a high concentration region. Each guard ring may have a region not covered by a high concentration region when viewed from the lower surface side of the semiconductor substrate.

At least a portion of the lower surface of each guard ring may be in contact with the drift region.

The high concentration region may be in contact with the upper surface of the semiconductor substrate.

The high concentration region may have an upper portion in contact with the upper surface of the semiconductor substrate. The high concentration region may have a lower portion that is provided separately from the upper portion and is provided from a position shallower than the lower end of the guard ring to a position deeper than the lower end of the guard ring.

The upper portion may contain a first conductive type first dopant. The lower portion may contain a first conductive type second dopant of an element different from the first dopant.

The second dopant may be hydrogen.

The active region may have a second conductive type base region. The active region may have a second conductive type well region that has a higher doping concentration than the base region and is provided from the upper surface of the semiconductor substrate to a position deeper than the base region. The doping concentration in the lower portion may be lower than the doping concentration in the well region.

The lower end of the lower portion may be arranged at a position shallower than the lower end of the well region. The upper end of the high concentration region may be arranged below the upper end of the adjacent guard ring. The guard ring may be in contact with the upper surface of the semiconductor substrate. The upper end of the high concentration region may be arranged below the upper surface of the semiconductor substrate. The semiconductor device may include an interlayer insulating film that covers a high concentration region.

The outline of the above invention does not list all the necessary features of the present invention. Sub-combinations of these feature groups can also be inventions.

It is a top view which shows an example of the semiconductor device 100 which concerns on one Embodiment of this invention. It is an enlarged view of the area A in FIG. It is a figure which shows an example of the bb cross section in FIG. It is a figure which shows an example of the cc cross section in FIG. FIG. 4 is an enlarged view of the semiconductor substrate 10 in the vicinity of the well region 11 and the guard ring 92 in FIG. It is a figure which shows another example of a high concentration region 202. It is a figure explaining a part manufacturing process of a semiconductor device 100. It is a figure explaining another example of a part manufacturing process of a semiconductor device 100. It is sectional drawing in the vicinity of the emitter electrode 52 and the outer peripheral gate wiring 130. It is a figure which shows another example of the cross section in the vicinity of the emitter electrode 52 and the outer peripheral gate wiring 130. It is a figure explaining another example of a part manufacturing process of a semiconductor device 100. It is a figure which shows another example of the cross section in the vicinity of the emitter electrode 52 and the outer peripheral gate wiring 130. It is a figure which shows the other structural example of the edge termination structure part 90. It is a figure which shows the other arrangement example of the field plate 94. It is a figure which shows another example of the cc cross section in FIG. It is a figure which shows the other structural example between the guard ring 92 arranged on the outermost side, and the channel stopper 174. It is a figure which shows the other structural example of the semiconductor device 100. It is a figure which shows the other structural example of the interlayer insulating film 38. It is a figure which shows the other structural example of the interlayer insulating film 38.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the inventions claimed in the claims. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

In the present specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper" and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The "up" and "down" directions are not limited to the direction of gravity or the direction when the semiconductor device is mounted.

In the present specification, technical matters may be described using orthogonal coordinate axes of the X-axis, the Y-axis, and the Z-axis. The orthogonal coordinate axes only specify the relative positions of the components and do not limit the specific direction. For example, the Z axis does not limit the height direction with respect to the ground. The + Z-axis direction and the −Z-axis direction are opposite to each other. When the positive and negative directions are not described and the Z-axis direction is described, it means the direction parallel to the + Z axis and the −Z axis.

In the present specification, the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are defined as the X axis and the Y axis. Further, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is defined as the Z axis. In the present specification, the direction of the Z axis may be referred to as a depth direction. Further, in the present specification, the direction parallel to the upper surface and the lower surface of the semiconductor substrate including the X-axis and the Y-axis may be referred to as a horizontal direction.

When referred to as "same" or "equal" in the present specification, it may include a case where there is an error due to manufacturing variation or the like. The error is, for example, within 10%.

In the present specification, the conductive type of the doping region doped with impurities is described as P type or N type. As used herein, an impurity may mean either an N-type donor or a P-type acceptor in particular, and may be referred to as a dopant. As used herein, doping means that a donor or acceptor is introduced into a semiconductor substrate to obtain a semiconductor exhibiting an N-type conductive type or a semiconductor exhibiting a P-type conductive type.

As used herein, the doping concentration means the concentration of a donor or the concentration of an acceptor in a thermal equilibrium state. As used herein, the net doping concentration means the net concentration of the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration N _D, the acceptor concentration and N _A, the net doping concentration of the net at any position is N _D -N _A.

The donor has a function of supplying electrons to the semiconductor. The acceptor has a function of receiving electrons from a semiconductor. Donors and acceptors are not limited to the impurities themselves. For example, a VOH defect in which pores (V), oxygen (O) and hydrogen (H) are bonded in a semiconductor functions as a donor that supplies electrons.

In the present specification, the description of P + type or N + type means that the doping concentration is higher than that of P type or N type, and the description of P-type or N-type means that the doping concentration is higher than that of P type or N type. It means that the concentration is low. Further, when described as P ++ type or N ++ type in the present specification, it means that the doping concentration is higher than that of P ++ type or N + type.

As used herein, the chemical concentration refers to the concentration of impurities measured regardless of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by a voltage-capacity measurement method (CV method). Further, the carrier concentration measured by the spread resistance measurement method (SR method) may be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method may be a value in a thermal equilibrium state. Further, in the N-type region, the donor concentration is sufficiently higher than the acceptor concentration, so that the carrier concentration in the region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in the region may be used as the acceptor concentration.

When the concentration distribution of donor, acceptor or net doping has a peak, the peak value may be used as the concentration of donor, acceptor or net doping in the region. When the concentration of donor, acceptor or net doping is substantially uniform, the average value of the concentration of donor, acceptor or net doping in the region may be used as the concentration of donor, acceptor or net doping.

The carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor. In the range in which a current flows when measuring the spread resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to disorder (disorder) of the crystal structure due to lattice defects or the like.

The concentration of the donor or acceptor calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic as a donor in a silicon semiconductor, or the acceptor concentration of boron (boron) as an acceptor is about 99% of these chemical concentrations. On the other hand, the donor concentration of hydrogen as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.

FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. FIG. 1 shows a position where each member is projected onto the upper surface of the semiconductor substrate 10. In FIG. 1, only a part of the members of the semiconductor device 100 is shown, and some members are omitted.

The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has an end side 102 when viewed from above. When simply referred to as a top view in the present specification, it means that the semiconductor substrate 10 is viewed from the top surface side. The semiconductor substrate 10 of this example has two sets of end sides 102 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to either end 102. The Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

The semiconductor substrate 10 is provided with an active portion 160. The active portion 160 is a region in which a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode is provided above the active portion 160, but is omitted in FIG.

The active unit 160 is provided with at least one of a transistor unit 70 including a transistor element such as an IGBT and a diode unit 80 including a diode element such as a freewheeling diode (FWD). In the example of FIG. 1, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (X-axis direction in this example) on the upper surface of the semiconductor substrate 10. In another example, the active portion 160 may be provided with only one of the transistor portion 70 and the diode portion 80.

In FIG. 1, a symbol “I” is attached to the region where the transistor portion 70 is arranged, and a symbol “F” is attached to the region where the diode portion 80 is arranged. In the present specification, the direction perpendicular to the arrangement direction in top view may be referred to as a stretching direction (Y-axis direction in FIG. 1). The transistor portion 70 and the diode portion 80 may each have a longitudinal length in the stretching direction. That is, the length of the transistor portion 70 in the Y-axis direction is larger than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is larger than the width in the X-axis direction. The stretching direction of the transistor portion 70 and the diode portion 80 may be the same as the longitudinal direction of each trench portion described later.

The diode portion 80 has an N + type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In the present specification, the region provided with the cathode region is referred to as a diode portion 80. That is, the diode portion 80 is a region that overlaps with the cathode region in the top view. A P + type collector region may be provided on the lower surface of the semiconductor substrate 10 in a region other than the cathode region. In the present specification, the diode portion 80 may also include an extension region 81 in which the diode portion 80 is extended in the Y-axis direction to the gate wiring described later. A collector region is provided on the lower surface of the extension region 81.

The transistor portion 70 has a P + type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Further, in the transistor portion 70, a gate structure having an N-type emitter region, a P-type base region, a gate conductive portion and a gate insulating film is periodically arranged on the upper surface side of the semiconductor substrate 10.

The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is arranged in the vicinity of the end side 102. The vicinity of the end side 102 refers to a region between the end side 102 and the emitter electrode in top view. At the time of mounting the semiconductor device 100, each pad may be connected to an external circuit via wiring such as a wire.

A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion. In FIG. 1, diagonal hatching is attached to the gate wiring.

The gate wiring of this example has an outer peripheral gate wiring 130 and an active side gate wiring 131. The outer peripheral gate wiring 130 is arranged between the active portion 160 and the end side 102 of the semiconductor substrate 10 in a top view. The outer peripheral gate wiring 130 of this example surrounds the active portion 160 in a top view. The region surrounded by the outer peripheral gate wiring 130 in the top view may be the active portion 160. Further, the outer peripheral gate wiring 130 is connected to the gate pad 112. The outer peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The outer peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

The active side gate wiring 131 is provided in the active portion 160. By providing the active side gate wiring 131 in the active portion 160, it is possible to reduce the variation in the wiring length from the gate pad 112 in each region of the semiconductor substrate 10.

The active side gate wiring 131 is connected to the gate trench portion of the active portion 160. The active side gate wiring 131 is arranged above the semiconductor substrate 10. The active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

The active side gate wiring 131 may be connected to the outer peripheral gate wiring 130. The active side gate wiring 131 of this example is provided so as to extend in the X-axis direction from one outer peripheral gate wiring 130 to the other outer peripheral gate wiring 130 at substantially the center in the Y-axis direction so as to cross the active portion 160. There is. When the active portion 160 is divided by the active side gate wiring 131, the transistor portion 70 and the diode portion 80 may be alternately arranged in the X-axis direction in each divided region.

Further, the semiconductor device 100 includes a temperature sense unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160. May be good.

The semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the end side 102. The edge termination structure 90 of this example is arranged between the outer peripheral gate wiring 130 and the end side 102. The edge termination structure 90 relaxes the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 has a plurality of guard rings 92. The guard ring 92 is a P-shaped region in contact with the upper surface of the semiconductor substrate 10. The guard ring 92 may surround the active portion 160 in top view. The plurality of guard rings 92 are arranged at predetermined intervals between the outer peripheral gate wiring 130 and the end side 102. The guard ring 92 arranged on the outer side may surround the guard ring 92 arranged on the inner side. The outside refers to the side close to the end side 102, and the inside refers to the side close to the outer peripheral gate wiring 130. By providing the plurality of guard rings 92, the depletion layer on the upper surface side of the active portion 160 can be extended outward, and the withstand voltage of the semiconductor device 100 can be improved. The edge termination structure 90 may further include at least one of a field plate and a resurf provided in an annular shape surrounding the active portion 160.

FIG. 2 is an enlarged view of the region A in FIG. The region A is a region including the transistor portion 70, the diode portion 80, and the active side gate wiring 131. The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are examples of trench portions, respectively. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.

An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in FIG. In the interlayer insulating film of this example, a contact hole 54 is provided so as to penetrate the interlayer insulating film. In FIG. 2, each contact hole 54 is hatched with diagonal lines.

The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 passes through the contact hole 54 and comes into contact with the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10. Further, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.

The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

The emitter electrode 52 is made of a material containing metal. FIG. 2 shows a range in which the emitter electrode 52 is provided. For example, at least a part of the emitter electrode 52 is formed of an aluminum or aluminum-silicon alloy, for example, a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like in the lower layer of the region formed of aluminum or the like. Further, the contact hole may have a plug formed by embedding tungsten or the like so as to be in contact with the barrier metal and aluminum or the like.

The well region 11 is provided so as to overlap the active side gate wiring 131. The well region 11 is also extended to a predetermined width so as not to overlap with the active side gate wiring 131. The well region 11 of this example is provided away from the end of the contact hole 54 in the Y-axis direction on the active side gate wiring 131 side. The well region 11 is a second conductive type region having a higher doping concentration than the base region 14. The base region 14 of this example is P-type, and the well region 11 is P + type.

Each of the transistor portion 70 and the diode portion 80 has a plurality of trench portions arranged in the arrangement direction. In the transistor portion 70 of this example, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately provided along the arrangement direction. The diode portion 80 of this example is provided with a plurality of dummy trench portions 30 along the arrangement direction. The diode portion 80 of this example is not provided with the gate trench portion 40.

The gate trench portion 40 of this example connects two straight portions 39 (a trench portion that is linear along the stretching direction) and two straight portions 39 that extend along the stretching direction perpendicular to the arrangement direction. It may have a tip 41. The stretching direction in FIG. 2 is the Y-axis direction.

It is preferable that at least a part of the tip portion 41 is provided in a curved shape in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction to each other, the electric field concentration at the ends of the straight portions 39 can be relaxed.

In the transistor portion 70, the dummy trench portion 30 is provided between the straight portions 39 of the gate trench portion 40. One dummy trench portion 30 may be provided between the straight portions 39, and a plurality of dummy trench portions 30 may be provided. The dummy trench portion 30 may have a linear shape extending in the stretching direction, and may have a straight portion 29 and a tip portion 31 as in the gate trench portion 40. The semiconductor device 100 shown in FIG. 2 includes both a linear dummy trench portion 30 having no tip portion 31 and a dummy trench portion 30 having a tip portion 31.

The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 in the top view. That is, at the end of each trench in the Y-axis direction, the bottom of each trench in the depth direction is covered with the well region 11. As a result, the electric field concentration at the bottom of each trench can be relaxed.

A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region sandwiched between trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion of this example is provided on the upper surface of the semiconductor substrate 10 by extending in the stretching direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. When simply referred to as a mesa portion in the present specification, it refers to each of the mesa portion 60 and the mesa portion 61.

A base region 14 is provided in each mesa portion. Of the base region 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active side gate wiring 131 is referred to as the base region 14-e. In FIG. 2, the base region 14-e arranged at one end in the extending direction of each mesa portion is shown, but the base region 14-e is also arranged at the other end of each mesa portion. Has been done. At least one of the first conductive type emitter region 12 and the second conductive type contact region 15 may be provided in each mesa portion in the region sandwiched between the base regions 14-e in the top view. The emitter region 12 of this example is N + type, and the contact region 15 is P + type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with an exposed contact region 15 on the upper surface of the semiconductor substrate 10.

Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion in the X-axis direction to the other trench portion. As an example, the contact region 15 and the emitter region 12 of the mesa portion 60 are alternately arranged along the stretching direction (Y-axis direction) of the trench portion.

In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extending direction (Y-axis direction) of the trench portion. For example, an emitter region 12 is provided in a region in contact with the trench portion, and a contact region 15 is provided in a region sandwiched between the emitter regions 12.

The emitter region 12 is not provided in the mesa portion 61 of the diode portion 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. A contact region 15 may be provided in contact with the respective base regions 14-e in the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61. A base region 14 may be provided in a region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61. The base region 14 may be arranged over the entire region sandwiched between the contact regions 15.

A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched between the base regions 14-e. The contact hole 54 of this example is provided above each region of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in the region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged at the center of the mesa portion 60 in the arrangement direction (X-axis direction).

In the diode section 80, an N + type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P + type collector region 22 may be provided on the lower surface of the semiconductor substrate 10 in a region where the cathode region 82 is not provided. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

The cathode region 82 is arranged away from the well region 11 in the Y-axis direction. As a result, the pressure resistance can be improved by securing a distance between the P-shaped region (well region 11) formed to a deep position and having a relatively high doping concentration and the cathode region 82. The end portion of the cathode region 82 of this example in the Y-axis direction is arranged farther from the well region 11 than the end portion of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be located between the well region 11 and the contact hole 54.

FIG. 3 is a diagram showing an example of a bb cross section in FIG. The bb cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the cross section. The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film containing at least one layer of an insulating film such as silicate glass to which impurities such as boron and phosphorus are added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described in FIG.

The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In the present specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as a depth direction.

The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in each of the transistor portion 70 and the diode portion 80.

The mesa portion 60 of the transistor portion 70 is provided with an N + type emitter region 12 and a P− type base region 14 in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. The mesa portion 60 may be provided with an N + type storage region 16. The storage region 16 is arranged between the base region 14 and the drift region 18.

The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

The base region 14 is provided below the emitter region 12. The base region 14 of this example is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

The storage region 16 is provided below the base region 14. The accumulation region 16 is an N + type region having a higher doping concentration than the drift region 18. By providing a high-concentration storage region 16 between the drift region 18 and the base region 14, the carrier injection promoting effect (IE effect) can be enhanced and the on-voltage can be reduced. The storage region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

The mesa portion 61 of the diode portion 80 is provided with a P-shaped base region 14 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In the mesa portion 61, the accumulation region 16 may be provided below the base region 14.

In each of the transistor portion 70 and the diode portion 80, an N + type buffer region 20 may be provided below the drift region 18. The doping concentration in the buffer region 20 is higher than the doping concentration in the drift region 18. The buffer region 20 has one or more donor concentration peaks with higher donor concentrations than the drift region 18. The plurality of donor concentration peaks are arranged at different positions in the depth direction of the semiconductor substrate 10. The donor concentration peak in the buffer region 20 may be, for example, a hydrogen (proton) or phosphorus concentration peak. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P + type collector region 22 and the N + type cathode region 82.

In the transistor section 70, a P + type collector region 22 is provided below the buffer region 20. The acceptor concentration in the collector region 22 is higher than the acceptor concentration in the base region 14. The collector region 22 may include the same acceptors as the base region 14, or may include different acceptors. The acceptor of the collector region 22 is, for example, boron.

In the diode section 80, an N + type cathode region 82 is provided below the buffer region 20. The donor concentration in the cathode region 82 is higher than the donor concentration in the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. The elements that serve as donors and acceptors in each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may come into contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum.

One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reaches the drift region 18. In the region where at least one of the emitter region 12, the contact region 15 and the storage region 16 is provided, each trench portion also penetrates these doping regions and reaches the drift region 18. The penetration of the trench portion through the doping region is not limited to those manufactured in the order of forming the doping region and then forming the trench portion. Those in which a doping region is formed between the trench portions after the trench portion is formed are also included in those in which the trench portion penetrates the doping region.

As described above, the transistor portion 70 is provided with a gate trench portion 40 and a dummy trench portion 30. The diode portion 80 is provided with a dummy trench portion 30 and is not provided with a gate trench portion 40. In this example, the boundary between the diode portion 80 and the transistor portion 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 provided on the upper surface 21 of the semiconductor substrate 10. The gate insulating film 42 is provided so as to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and inside the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. The gate trench portion 40 in the cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed on the surface layer of the interface of the base region 14 in contact with the gate trench portion 40.

The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

The gate trench portion 40 and the dummy trench portion 30 of this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom of the dummy trench portion 30 and the gate trench portion 40 may be curved downward (curved in cross section).

FIG. 4 is a diagram showing an example of a cc cross section in FIG. The cc cross section is an XZ plane that passes through the edge termination structure portion 90, the transistor portion 70, and the diode portion 80. The structures of the transistor portion 70 and the diode portion 80 are the same as those of the transistor portion 70 and the diode portion 80 described with reference to FIGS. 2 and 3. In FIG. 4, the structures of the gate trench portion 40 and the dummy trench portion 30 are shown in a simplified manner.

In the semiconductor substrate 10, a well region 11 is provided between the edge termination structure portion 90 and the transistor portion 70. The well region 11 is a P + type region in contact with the upper surface 21 of the semiconductor substrate 10. The well region 11 may be provided deeper than the lower ends of the gate trench portion 40 and the dummy trench portion 30. A part of the gate trench portion 40 and the dummy trench portion 30 may be arranged inside the well region 11.

An interlayer insulating film 38 that covers the well region 11 may be provided on the upper surface 21 of the semiconductor substrate 10. Above the interlayer insulating film 38, electrodes and wiring such as an emitter electrode 52 and an outer peripheral gate wiring 130 are provided. The emitter electrode 52 is provided so as to extend from above the active portion 160 to above the well region 11. The emitter electrode 52 may be connected to the well region 11 via a contact hole provided in the interlayer insulating film 38.

The outer peripheral gate wiring 130 is arranged between the emitter electrode 52 and the edge terminal structure portion 90. The emitter electrode 52 and the outer peripheral gate wiring 130 are arranged separately from each other, but in FIG. 4, the gap between the emitter electrode 52 and the outer peripheral gate wiring 130 is omitted. The outer peripheral gate wiring 130 is electrically insulated from the well region 11 by the interlayer insulating film 38.

The edge termination structure 90 is provided with a plurality of guard rings 92, a plurality of high concentration regions 202, a plurality of field plates 94, and a channel stopper 174. A collector region 22 may be provided in the region of the edge termination structure portion 90 in contact with the lower surface 23. Each guard ring 92 may be provided on the upper surface 21 so as to surround the active portion 160. The plurality of guard rings 92 may have a function of spreading the depletion layer generated in the active portion 160 to the outside of the semiconductor substrate 10. As a result, electric field concentration inside the semiconductor substrate 10 can be prevented, and the withstand voltage of the semiconductor device 100 can be improved.

The guard ring 92 of this example is a P + type semiconductor region formed by ion implantation in the vicinity of the upper surface 21. The depth of the bottom of the guard ring 92 may be deeper than the depth of the bottom of the gate trench 40 and the dummy trench 30. The depth of the bottom of the guard ring 92 may be the same as or different from the depth of the bottom of the well region 11.

The upper surface of the guard ring 92 is covered with an interlayer insulating film 38. The field plate 94 is formed of a metal such as aluminum or a conductive material such as polysilicon. The field plate 94 may be formed of an aluminum-silicon alloy, for example, a metal alloy such as AlSi or AlSiCu. The field plate 94 may be made of the same material as the outer peripheral gate wiring 130 or the emitter electrode 52. The field plate 94 is provided on the interlayer insulating film 38. The field plate 94 of this example is connected to the guard ring 92 through a through hole provided in the interlayer insulating film 38.

The channel stopper 174 is provided so as to be exposed on the upper surface 21 and the side wall in the vicinity of the end side 102 of the semiconductor substrate 10. The channel stopper 174 is an N-type region having a higher doping concentration than the drift region 18. The channel stopper 174 has a function of terminating the depletion layer generated in the active portion 160 in the vicinity of the end side 102 of the semiconductor substrate 10. In FIG. 4, the transistor portion 70, the diode portion 80, and the interlayer insulating film 38 of the edge termination structure portion 90 are drawn with the same thickness, but the thickness may be different, and the forming process is different. The composition may be different. Although at least a part of the field plate 94, the outer peripheral gate wiring 130, and the emitter electrode 52 is covered with a protective film such as polyimide or a nitride film, the protective film may be omitted in the drawings of the present specification.

The high concentration region 202 is an N-type region having a higher doping concentration than the drift region 18. The high concentration region 202 is provided between two adjacent guard rings 92 from a position shallower than the lower end of the guard ring 92 to a position deeper than the lower end of the guard ring 92. The high concentration region 202 may also be provided between the well region 11 and the guard ring 92. The high concentration region 202 may be provided deeper than the lower end of the well region 11.

The high concentration region 203 is arranged between the guard ring 92 closest to the channel stopper 174 and the channel stopper 174. The high concentration region 203 may have the same structure and doping concentration distribution as the high concentration region 202. In another example, the high concentration region 203 may be provided at a depth position different from that of the high concentration region 202. The high concentration region 203 may be provided to a position shallower than the lower end of the high concentration region 202, or may be provided to a deep position. The high density region 203 of this example is provided from the upper surface 21 of the semiconductor substrate 10 to a position deeper than the lower end of the guard ring 92.

Further, the high concentration region 203 may have a higher or lower doping concentration than the high concentration region 202. As a result, the electric field concentration between the outermost guard ring 92 and the channel stopper 174 can be relaxed.

FIG. 5 is an enlarged view of the semiconductor substrate 10 in the vicinity of the well region 11 and the guard ring 92 in FIG. In this example, the position of the lower end of the guard ring 92 in the Z-axis direction is Z1.

The high-concentration region 202 has a region arranged on the upper surface 21 side of the position Z1 and a region arranged on the lower surface 23 side of the position Z1. The high-concentration region 202 of this example is continuously provided from the position Z0 in contact with the upper surface 21 of the semiconductor substrate 10 to the depth position Z2. The position Z2 is a position farther from the upper surface 21 than the position Z1.

The high-concentration region 202 of this example covers a part of the guard ring 92 when viewed from the lower surface 23 side of the semiconductor substrate 10. That is, in the Z-axis direction, a part of the high concentration region 202 overlaps with a part of the guard ring 92. Of the high-concentration region 202, a region provided at depth positions Z1 to Z2 may cover a part of the guard ring 92. As a result, the electric field concentration near the lower end of the guard ring 92 can be alleviated and the expansion of the depletion layer can be suppressed.

FIG. 5 schematically shows the equipotential lines 262. As shown in FIG. 5, the electric field may be concentrated in the vicinity of the lower region 260 of the guard ring 92. The lower region 260 may be a region where the curvature of the boundary line between the guard ring 92 and the N-shaped region is maximized. The lower region 260 may be a region where the change in the inclination of the boundary line between the guard ring 92 and the N-type region (that is, the second derivative value) is maximized. The lower region 260 is arranged near the lower end of the guard ring 92. The lower end of the guard ring 92 is a portion of the guard ring 92 arranged at the deepest position.

The guard ring 92 may have a lower region 260 and a lower region 261. When the cross-sectional shape of the guard ring 92 is line-symmetric with respect to the center line parallel to the Z axis, the guard ring 92 has a lower region 260 and a lower region 261 at line-symmetrical positions. Of the two lower regions 260, the one closer to the well region 11 is referred to as the lower region 261 and the one farther from the well region 11 is referred to as the lower region 260. As shown in FIG. 5, the electric field tends to concentrate in the vicinity of the lower region 260.

By providing the high concentration region 202, a high concentration N-type region can be arranged in the vicinity of the lower region 260 and the lower region 261. As a result, the electric field concentration in the vicinity of the lower region 260 and the lower region 261 can be alleviated and the expansion of the depletion layer can be suppressed. The high concentration region 202 preferably covers the lower region 260. That is, the high concentration region 202 is preferably in contact with the lower region 260. The high concentration region 202 may further cover the lower region 261. The cross-sectional shape of the high concentration region 202 may be axisymmetric with respect to the center line parallel to the Z axis.

Further, since the electric field is concentrated between the guard rings 92 and in the region near the lower end of the guard ring 92, if the donor concentration in the region varies, the withstand voltage also varies. If the high concentration region 202 is not provided, a drift region 18 is formed in the region. Since the donor concentration in the drift region 18 is the concentration of the donor contained in the semiconductor substrate 10 from the time of manufacture, it is relatively easy to vary. On the other hand, in this example, a high concentration region 202 is provided in the region. The high concentration region 202 is formed by ion implantation or the like. Since the concentration of ion implantation is relatively easy to control, the variation in donor concentration in the high concentration region 202 is relatively small. Therefore, by providing the high concentration region 202, the withstand voltage variation of the semiconductor device 100 can be reduced.

The high concentration region 202 is provided in at least one of the regions sandwiched between the guard rings 92. The high concentration region 202 may be arranged in the entire region sandwiched by the guard ring 92.

Each guard ring 92 has a region 204 that is not covered by the high density region 202 when viewed from the lower surface 23 side of the semiconductor substrate 10. The region 204 may be a region including the lower end of the guard ring 92 at the center in the X-axis direction. The region 204 may be in contact with the drift region 18. When the high concentration guard ring 92 is entirely covered by the high concentration region 202, the electric field strength also increases at the bottom surface of the guard ring 92. Therefore, the electric field strength tends to reach the critical electric field strength at a relatively low voltage, avalanche breakdown occurs, and the withstand voltage of the semiconductor device 100 decreases. By providing the region 204, the bottom surface of the guard ring 92 is in contact with the low-concentration drift region 18, so that an increase in the electric field strength is suppressed.

Let Dmax be the maximum value of the donor concentration in the high concentration region 202. Further, the donor concentration in the drift region 18 is defined as Db. The donor concentration of the drift region 18 below the guard ring 92 and in the center of the semiconductor substrate 10 in the depth direction may be defined as the donor concentration Db. The donor concentration Dmax may be 10 times or more higher than the donor concentration Db. In this case, the position where the donor concentration is twice that of Db may be the boundary between the high concentration region 202 and the drift region 18. Alternatively, the position where the donor concentration in the drift region 18 starts to increase higher than Db may be defined as the boundary between the high concentration region 202 and the drift region 18.

The width W2 of the region 204 in the X-axis direction is smaller than the width W1 of the guard ring 92 on the upper surface 21 of the semiconductor substrate 10. The width W2 may be 10% or more, 30% or more, 50% or more, or 70% or more of the width W1.

FIG. 6 is a diagram showing another example of the high concentration region 202. The structure other than the high concentration region 202 is the same as the example shown in FIG. The high concentration region 202 of this example has an upper portion 206 and a lower portion 208. The upper portion 206 and the lower portion 208 are provided separately from each other. In this example, a drift region 18 is provided between the upper portion 206 and the lower portion 208. When the N-type dopant is injected from the upper surface 21 to the lower portion 208, a donor may be formed in the region through which the N-type dopant has passed. In this case, the donor concentration gradually decreases from the lower portion 208 toward the upper surface 21. Between the lower portion 208 and the upper portion 206, the donor concentration may gradually decrease from the lower portion 208 to the upper portion 206. For example, when hydrogen is used as the N-type dopant, pore defects (V) formed in the region through which hydrogen has passed, oxygen (O) contained in the semiconductor substrate 10, and hydrogen diffused from the lower portion 208 (H). ) Combines to form a VOH defect. The VOH defect acts as a donor.

The upper portion 206 is provided between the two guard rings 92 in contact with the upper surface 21 of the semiconductor substrate 10. The upper portion 206 may be disposed apart from the guard ring 92. As a result, it is possible to prevent the donor highly doped in the upper portion 206 from diffusing into the guard ring 92. In another example, the upper portion 206 may be in contact with the guard ring 92.

The lower portion 208 is provided from a position shallower than the lower end of the guard ring 92 to a position Z2 deeper than the lower end of the guard ring 92. The lower portion 208 of this example is provided in contact with the side surface 93-2 of the two side surfaces 93-1 and 93-2 of the guard ring 92, which is farther from the well region 11. The side surface 93-1 of the guard ring 92 in FIG. 6 is a surface of the guard ring 92 on the well region 11 side of the center in the X-axis direction. The side surface 93-2 of the guard ring 92 is a surface opposite to the side surface 93-1. The lower portion 208 does not have to be in contact with the side surface 93-1 and may be in contact with it. By providing the lower portion 208 in contact with the side surface 93-2, it is possible to protect the region where the electric field is likely to concentrate. The lower portion 208 is preferably in contact with the lower region 260. Further, the width W2 of the region 204 of this example is larger than half the width W1 of the guard ring 92.

The position of the upper end of the lower portion 208 in the Z-axis direction is Z3. The distance Z1-Z3 between the positions Z1 and Z3 in the Z-axis direction may be the same as the distance Z2-Z1 between the positions Z1 and Z2 in the Z-axis direction. The distance Z2-Z1 may be larger than the distance Z1-Z3. This makes it easier to protect the area where the electric field is likely to concentrate. The distance Z2-Z1 may be smaller than the distance Z1-Z3.

The guard ring 92 and the high concentration region 202 described with reference to FIGS. 1 to 6 may be formed by injecting a dopant from the upper surface 21 of the semiconductor substrate 10. The guard ring 92 can be formed by selectively injecting a P-type dopant such as boron from the upper surface 21 of the semiconductor substrate 10 and heat-treating it.

The high concentration region 202 (upper portion 206 and lower portion 208 in this example) can be formed by selectively injecting an N-type dopant such as hydrogen or phosphorus from the upper surface 21 of the semiconductor substrate 10 and heat-treating it. The N-type dopant may be injected at multiple depth positions with varying acceleration energies.

By using hydrogen as the N-type dopant, a high concentration region 202 at a deep position can be easily formed. However, if heat treatment is performed at a high temperature for a long time after injecting hydrogen, the hydrogen donor disappears. Therefore, it is preferable that the hydrogen injection and heat treatment steps are performed at the end of the manufacturing process of the semiconductor device 100. For example, by injecting hydrogen after forming a protective film on the field plate 94 or the like, the disappearance of the hydrogen donor can be suppressed. Hydrogen injection may be performed from the upper surface 21 of the semiconductor substrate 10 or from the lower surface 23.

In the example described with reference to FIGS. 1 to 6, at least a part of the high concentration region 202 may be provided in a region not covered by the field plate 94. That is, at least a part of the high concentration region 202 does not overlap with the field plate 94 in the Z-axis direction. At least a part of the high concentration region 202 may be formed by injecting an N-type dopant using the field plate 94 as a mask.

Further, the high concentration region 202 may be formed by using a plurality of types of N-type dopants. For example, a first dopant such as phosphorus may be injected to form the upper portion 206, and a second dopant such as hydrogen may be injected to form the lower portion 208. In this case, the upper portion 206 contains a first dopant (phosphorus) having a higher concentration than the second dopant (hydrogen), and the lower portion 208 has a higher concentration than the first dopant (phosphorus). Second dopant (hydrogen) is included.

Further, the dose amount of the N-type dopant injected into the high concentration region 202 may be adjusted according to the specific resistance of the semiconductor substrate 10 or the donor concentration before the injection of the N-type dopant. Thereby, the specific resistance or the donor concentration of the semiconductor substrate 10 after forming the high concentration region 202 can be adjusted more accurately.

7A and 7B are diagrams illustrating a part of the manufacturing process of the semiconductor device 100. In FIGS. 7A and 7B, a step of forming the lower portion 208 of the high concentration region 202 is shown. In this example, the N-type dopant is injected into the lower portion 208 using each electrode such as the field plate 94, the outer peripheral gate wiring 130, and the emitter electrode 52 as a mask. In the edge termination structure 90, the N-type dopant is injected from the gap 95 of the field plates 94 adjacent to each other.

In this example, the N-type dopant is injected after forming each electrode such as the interlayer insulating film 38 and the field plate 94. The N-type dopant is, for example, hydrogen. Further, after forming the well region 11, the upper portion 206 and the guard ring 92, the N-type dopant may be injected into the lower portion 208. After injecting the N-type dopant to form the lower portion 208, a protective film such as polyimide or a nitride film may be formed above each electrode such as the field plate 94, the outer peripheral gate wiring 130, and the emitter electrode 52.

According to this example, since the field plate 94 is used as a mask, the manufacturing process of the semiconductor device 100 can be simplified. At least a portion of the lower portion 208 of this example overlaps the gap 95 in the Z-axis direction. In the lower portion 208, the region where the donor concentration is maximum may overlap with the gap 95 in the Z-axis direction.

The field plate 94 may overlap a portion of the lower portion 208 in the Z-axis direction. By diffusing the N-type dopant injected into the lower portion 208 in the X-axis direction, a part of the lower portion 208 can be formed at a position overlapping the field plate 94. The field plate 94 may overlap some or all of the area of the upper portion 206.

The center position of the field plate 94 in the X-axis direction is X1, and the center position of the guard ring 92 in the X-axis direction is X2. The central position X1 of the field plate 94 may be arranged closer to the well region 11 than the central position X2 of the guard ring 92. As a result, the lower portion 208 is not formed in the lower region 261 shown in FIG. 5, and the lower portion is easily formed in the lower region 260.

In this example, the position of the lower end of the well region 11 in the Z-axis direction is Z4. In FIG. 7A, the lower end position Z1 of the guard ring 92 coincides with the lower end position Z4 of the well region 11. That is, the lower portion 208 is arranged deeper than the well region 11. On the other hand, in FIG. 7B, the position Z4 at the lower end of the well region 11 is arranged at a position deeper than the position Z1 at the lower end of the guard ring 92. Further, in FIG. 7B, the lower end position Z2 of the lower portion 208 is arranged closer to the upper surface 21 than the lower end position Z4 of the well region 11. That is, the lower portion 208 is arranged in a region shallower than the well region 11. Further, in both FIGS. 7A and 7B, the doping concentration of the lower portion 208 is lower than the doping concentration of the well region 11.

8A and 8B are cross-sectional views in the vicinity of the emitter electrode 52 and the outer peripheral gate wiring 130. FIG. 8A corresponds to the example of FIG. 7A and FIG. 8B corresponds to the example of FIG. 7B. That is, the depth position Z4 of the well region 11 in FIG. 8A is the same as the example shown in FIG. 7A, and the depth position Z4 of the well region 11 in FIG. 8B is the same as the example shown in FIG. 7B. In FIGS. 8A and 8B, the structure of the trench and the like is simplified, and the contact hole in the interlayer insulating film 38 is omitted. A gap 95 is provided between the emitter electrode 52 and the outer peripheral gate wiring 130.

When the N-type dopant is injected using each electrode such as the field plate 94, the outer peripheral gate wiring 130, and the emitter electrode 52 as a mask, the N-type dopant is also injected from the gap 95 between the outer peripheral gate wiring 130 and the emitter electrode 52. It ends up. In FIGS. 8A and 8B, the region into which the N-type dopant is injected is defined as region 209. The region 209 is arranged at the same depth position as the lower portion 208 shown in FIGS. 7A, 7B and the like.

A well region 11 is formed below the gap 95. Therefore, when the well region 11 and the lower end of the guard ring 92 are aligned as shown in FIG. 7A, if the lower portion 208 is arranged at a position deeper than the well region 11, it protrudes from the lower end of the well region 11 as shown in FIG. 8A. The lower portion 208 is formed so as to.

On the other hand, as shown in FIG. 7B, when the lower end position Z4 of the well region 11 is deeper than the lower end position Z1 of the guard ring 92, the lower portion 208 is arranged in a region shallower than the well region 11. By doing so, as shown in FIG. 8B, the lower portion 208 can be prevented from protruding from the lower end of the well region 11. In this case, the lower end position Z4 of the well region 11 is farther from the upper surface 21 of the semiconductor substrate 10 than the lower end position Z2 of the guard ring 92. That is, the well region 11 is provided deeper than the guard ring 92. As a result, the lower portion 208 can be formed deeper than the guard ring 92 and shallower than the well region 11. In the examples of FIGS. 7A and 8A, a mask for decelerating or shielding ions may be provided at a position covering the gap 95 above the well region 11. This also prevents the lower portion 208 from protruding from the lower end of the well region 11.

Further, when the doping concentration of the lower portion 208 is higher than the doping concentration of the well region 11, the conductive type of the region 209 of FIGS. 8A and 8B is inverted from the P type to the N type. Therefore, a PN junction may be formed at an unintended position, and the characteristics of the semiconductor device 100 may fluctuate.

On the other hand, by making the doping concentration of the lower portion 208 lower than the doping concentration of the well region 11, it is possible to prevent the conductive type of the region 209 from becoming N type. The doping concentration of the well region 11 may be higher, the same, or lower than the doping concentration of the guard ring 92. The doping concentration of the guard ring 92 may be 1.0 × 10 ¹⁷ atoms / cm ³ or less.

In the examples of FIGS. 7A to 8B, an example in which the lower portion 208 is ion-implanted using the field plate 94 as a mask has been described. In another example, after forming a protective film such as polyimide on the field plate 94 or the like, ion implantation may be performed using the protective film as a mask.

9 and 10 are views showing an example of ion implantation using the protective film 140 as a mask. FIG. 9 is a diagram showing another example of the cross section in the vicinity of the edge terminal structure portion 90. FIG. 10 is a diagram showing another example of the cross section in the vicinity of the emitter electrode 52 and the outer peripheral gate wiring 130.

As shown in FIG. 9, the protective film 140 has an opening 98 above the lower portion 208. The opening 98 passes through the gap 95 of the field plate 94. Neither the protective film 140 nor the field plate 94 is provided at the position where the opening 98 and the gap 95 overlap. In this example, the N-type dopant is injected into the region of the lower portion 208 through the opening 98 and the gap 95. At this time, as shown in FIG. 10, by not providing the opening of the protective film 140 above the well region 11, it is possible to prevent ion implantation into the well region 11. A dent may be used instead of the opening 98. The depression may be formed by etching the protective film 140, or may be formed when the protective film 140 is deposited. When the protective film 140 is a nitride film or the like, a depression reflecting the presence or absence of a gap 95 in the field plate 94 can be formed at the time of deposition.

Further, instead of the protective film 140, an N-type dopant may be injected by forming a mask pattern with a photoresist or the like. Alternatively, when ion implantation of the lower portion 208 is performed using the gap of the field plate 94 above the guard ring 92 as a mask, the gap 95 of the field plate 94 above the well region 11 may be covered with a resist. In that case, it is possible to prevent ions from being implanted into the semiconductor substrate 10 by shielding with a resist, or by decelerating by the resist, the region 209 becomes shallow and does not protrude below the well region 11. You can also do it.

FIG. 11 is a diagram showing another structural example of the edge termination structure portion 90. The edge termination structure 90 of this example is different from the edge termination structure 90 described with reference to FIGS. 1 to 10 in that the upper surface 21 of the semiconductor substrate 10 has a recess 97. The structure other than the recessed portion 97 may be the same as the edge termination structure portion 90 described with reference to FIGS. 1 to 10.

The recessed portion 97 is a recessed portion provided in the Z-axis direction on the upper surface 21 of the semiconductor substrate 10. The recessed portion 97 can be formed by etching the upper surface 21 of the semiconductor substrate 10. The recessed portion 97 of this example is formed in a region where the guard ring 92 is provided. That is, the guard ring 92 is exposed on the bottom surface of the recessed portion 97. The high concentration region 202 is not exposed on the bottom surface of the recessed portion 97 of this example. In another example, the high concentration region 202 may also be exposed on the bottom surface of the recessed portion 97.

As shown in FIG. 11, an interlayer insulating film 38 may be provided inside the recessed portion 97. A field plate 94 may be provided inside the recess 97. As shown by the broken line in FIG. 11, the field plate 94 may come into contact with the guard ring 92 on the bottom surface of the recess 97. The field plate 94 does not have to be in contact with the guard ring 92.

After forming the recess 97, a P-type dopant for forming the guard ring 92 may be injected. This facilitates the formation of the guard ring 92 to a deep position. In another example, the recess 97 may be formed after the guard ring 92 is formed.

The recessed portion 97 may be formed in a region provided with a high concentration region 202 instead of the guard ring 92. In this case, the high concentration region 202 can be easily formed to a deep position.

FIG. 12 is a diagram showing another arrangement example of the field plate 94. The arrangement of the field plate 94 of this example may be applied to each of the examples described in FIGS. 1 to 6 and 11.

The field plate 94 of this example is arranged above the high concentration region 202. The field plate 94 may be arranged so as to cover the entire high concentration region 202. That is, the width W3 of the field plate 94 in the X-axis direction is larger than the width W4 of the high concentration region 202 in the X-axis direction. The field plate 94 may be arranged so as to straddle two adjacent guard rings 92 in the X-axis direction. In this example, the field plate 94 is not connected to the guard ring 92.

FIG. 13 is a diagram showing another example of the cc cross section in FIG. The semiconductor device 100 of this example is different in that the configuration of the semiconductor device 100 described in relation to FIG. 4 and the like does not include the high concentration region 203. The other structure is the same as the semiconductor device 100 of any aspect described in the present specification and the like. That is, the semiconductor device 100 does not have to include the high concentration region 203.

FIG. 14 is a diagram showing another structural example between the guard ring 92 arranged on the outermost side and the channel stopper 174. The semiconductor device 100 of this example includes an upper portion 207 and a lower portion 211 in place of the high concentration region 203 shown in FIG. The upper portion 207 and the lower portion 211 are N-type regions having a higher doping concentration than the drift region 18. That is, the upper portion 207 and the lower portion 211 are examples of the high concentration region.

The upper portion 207 may have the same structure and doping concentration distribution as the upper portion 206 described in FIG. 6 and the like. The lower portion 211 may have the same structure and doping concentration distribution as the lower portion 208 described in FIG. 6 and the like. In another example, the upper portion 207 may be provided to a position shallower than the lower end of the upper portion 206, or may be provided to a deep position. Further, the lower portion 211 may be provided to a position shallower than the lower end of the lower portion 208, or may be provided to a deep position. The upper portion 207 may have a higher or lower doping concentration than the upper portion 206. The lower portion 211 may have a higher or lower doping concentration than the lower portion 208.

FIG. 15 is a diagram showing another configuration example of the semiconductor device 100. In this example, the upper end 221 of the high concentration region 202 is arranged below the upper end 241 of the adjacent guard rings 92 (that is, the side closer to the lower surface 23 of the semiconductor substrate 10). Other structures are the same as the semiconductor device 100 of any aspect described herein.

In this example, the guard ring 92 is in contact with the upper surface 21 of the semiconductor substrate 10. That is, the upper end 241 of the guard ring 92 is arranged at the same depth as the upper surface 21 of the semiconductor substrate 10. Further, the upper end 221 of the high concentration region 202 is arranged below the upper surface 21 of the semiconductor substrate 10.

The high concentration region 202 may be covered with the interlayer insulating film 38. At least a part of the interlayer insulating film 38 of this example is arranged below the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be arranged in the recess formed on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 of this example is entirely arranged below the upper surface 21. The upper end of the interlayer insulating film 38 may be arranged at the same depth as the upper surface 21 of the semiconductor substrate 10.

Further, the interlayer insulating film 38 may be formed by locally oxidizing a part of the upper surface 21 of the semiconductor substrate 10. Even in this case, the lower end of the interlayer insulating film 38 may be arranged below the upper surface 21. In this example, the upper end 221 of the high concentration region 202 has been described, but the upper end of the high concentration region 203, the upper end of the upper portion 206, and the upper end of the upper portion 207 may be arranged at the same positions.

FIG. 16 is a diagram showing another structural example of the interlayer insulating film 38. The structure other than the interlayer insulating film 38 is the same as that of the semiconductor device 100 of any aspect described in the present specification. The sidewall of the interlayer insulating film 38 of this example is formed in a tapered shape. The interlayer insulating film 38 has a larger cross-sectional area on the XY plane toward the upper side. The interlayer insulating film 38 of this example can be formed by flattening a LOCOS film formed by locally oxidizing the upper surface 21 of the semiconductor substrate 10 to the same height as the upper surface 21 of the semiconductor substrate 10. Alternatively, the interlayer insulating film 38 of this example can also be formed by etching the upper surface 21 of the semiconductor substrate 10 into a recess and then locally oxidizing the recess portion to form a LOCOS film. Alternatively, the interlayer insulating film 38 of this example can be obtained by thermally oxidizing the semiconductor substrate 10 after etching the upper surface 21 of the semiconductor substrate 10 in a recess and removing the thermal oxide film so that the entire surface becomes flat to expose Si. Can be formed.

FIG. 17 is a diagram showing another structural example of the interlayer insulating film 38. The structure other than the interlayer insulating film 38 is the same as that of the semiconductor device 100 of any aspect described in the present specification. In the interlayer insulating film 38 of this example, the lower portion is arranged below the upper surface 21 and the upper portion is arranged above the upper surface 21. Further, at least a part of the lower portion of the interlayer insulating film 38 of this example is formed in a tapered shape. The lower part of the interlayer insulating film 38 has a larger cross-sectional area on the XY plane toward the upper side. At least a part of the upper part of the interlayer insulating film 38 is also formed in a tapered shape. The lower part of the interlayer insulating film 38 has a larger cross-sectional area on the XY plane. The interlayer insulating film 38 of this example is a LOCOS film formed by locally oxidizing the upper surface 21 of the semiconductor substrate 10. Alternatively, the interlayer insulating film 38 of this example can also be formed by thermally oxidizing the semiconductor substrate 10 after etching the upper surface 21 of the semiconductor substrate 10 to recess, and selectively removing the thermal oxide film to expose Si.

In addition to the above-mentioned steps, the interlayer insulating film 38 and the like may be manufactured in various forms having different compositions and shapes depending on the manufacturing process and the manufacturing method. As an example, the interlayer insulating film 38 of the active portion 160 and the interlayer insulating film 38 of the edge terminal structure portion 90 may have different materials or film thicknesses. Further, in the examples of FIGS. 15 to 17, the interlayer insulating film 38 is formed on the lower surface 23 side of the upper surface 21. This is called a recess, and the interlayer insulating film 38 of the active portion 160 may be formed in the + Z direction from the upper surface 21 without being recessed.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that such modified or improved forms may also be included in the technical scope of the present invention.

10 ... Semiconductor substrate, 11 ... Well region, 12 ... Emitter region, 14 ... Base region, 15 ... Contact region, 16 ... Storage region, 18 ... Drift region, 20 ... Buffer area, 21 ... Top surface, 22 ... Collector area, 23 ... Bottom surface, 24 ... Collector electrode, 29 ... Straight part, 30 ... Dummy trench part, 31 ... -Tip part, 32 ... Dummy insulating film, 34 ... Dummy conductive part, 38 ... Interlayer insulating film, 39 ... Straight part, 40 ... Gate trench part, 41 ... Tip part, 42 ... Gate insulating film, 44 ... Gate conductive part, 52 ... Emitter electrode, 54 ... Contact hole, 60, 61 ... Mesa part, 70 ... Transistor part, 80 ... Diode part, 81 ... extension area, 82 ... cathode area, 90 ... edge termination structure part, 92 ... guard ring, 93 ... side surface, 94 ... field plate, 95 ... Gap, 97 ... recess, 98 ... opening, 100 ... semiconductor device, 102 ... edge, 112 ... gate pad, 130 ... outer gate wiring, 131 ... active side Gate wiring, 140 ... protective film, 160 ... active part, 174 ... channel stopper, 202, 203 ... high concentration region, 204 ... region, 206, 207 ... upper part, 208 , 211 ... lower part, 209 ... region, 221 ... 241 ... upper end, 260 ... lower region, 261 ... lower region, 262 ... isopotential line

Claims (11)

A semiconductor substrate having a first conductive type drift region and
The active region provided on the semiconductor substrate and
The semiconductor substrate is provided with an edge termination structure portion provided on the upper surface of the semiconductor substrate between the active region and the end portion of the semiconductor substrate.
The edge termination structure is
A plurality of second conductive type guard rings in contact with the upper surface of the semiconductor substrate, and
A first conductive type high concentration region having a higher doping concentration than the drift region, which is provided between two adjacent guard rings from a position shallower than the lower end of the guard ring to a position deeper than the lower end of the guard ring. And have
Each of the guard rings is a semiconductor device having a region not covered by the high concentration region when viewed from the lower surface side of the semiconductor substrate. The semiconductor device according to claim 1, wherein at least a part of the lower surface of each guard ring is in contact with the drift region. The semiconductor device according to claim 1 or 2, wherein the high concentration region is in contact with the upper surface of the semiconductor substrate. The high concentration region
An upper portion of the semiconductor substrate in contact with the upper surface and
The semiconductor device according to claim 1 or 2, which is provided separately from the upper portion and has a lower portion provided from a position shallower than the lower end of the guard ring to a position deeper than the lower end of the guard ring. .. The upper portion contains a first conductive type dopant.
The semiconductor device according to claim 4, wherein the lower portion contains a first conductive type second dopant having an element different from that of the first dopant. The semiconductor device according to claim 5, wherein the second dopant is hydrogen. The active region is
The second conductive type base area and
It has a second conductive type well region that has a higher doping concentration than the base region and is provided from the upper surface of the semiconductor substrate to a position deeper than the base region.
The semiconductor device according to any one of claims 4 to 6, wherein the doping concentration of the lower portion is lower than the doping concentration of the well region. The semiconductor device according to claim 7, wherein the lower end of the lower portion is arranged at a position shallower than the lower end of the well region. The semiconductor device according to claim 1 or 2, wherein the upper end of the high concentration region is arranged below the upper end of the adjacent guard ring. The guard ring is in contact with the upper surface of the semiconductor substrate.
The semiconductor device according to claim 9, wherein the upper end of the high concentration region is arranged below the upper surface of the semiconductor substrate. The semiconductor device according to claim 10, further comprising an interlayer insulating film covering the high concentration region.

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