JP2020191559A - Receiver and receiving method - Google Patents

Abstract

To enable communication even in an environment with large interference.SOLUTION: A receiver that receives radio signals transmitted multiple times from a transmitter includes: an antenna that receives the radio signals; a plurality of demodulators that demodulate each of the signals received by the antenna; a decoder that decodes a signal demodulated by the plurality of demodulators; a de-interleaver that performs de-interleave processing of interchanging the order of codes of outputs of the demodulators; an interleaver that performs interleave processing of interchanging the order of codes of output of the decoder; and a plurality of first adders that reduce the output of the demodulators or the output of the demodulators that have undergone the de-interleave processing after the output of the decoder is copied for being input to each of the demodulators.SELECTED DRAWING: Figure 6

Description

The present invention relates to a receiver that receives a radio signal, and particularly to a reception process under the influence of interference.

Interference cancellers are known as a technique for improving reception quality by suppressing the influence of interference from other radio stations and the like. According to Patent Document 1, in an OFDM signal transmission system, an OFDM signal transmitter inserts a training signal consisting of no signal and a known pattern into a data signal at regular intervals, and the OFDM signal receiver has two receiving antennas. Using the training signal included in the received signal received in, an interference canceller control signal for suppressing the interference signal in the received signal is generated, and the interference signal in the received signal is suppressed based on the interference canceller control signal. , An OFDM signal transmission method that corrects the transmission path based on the training signal for the output is described (see summary).

It is also possible to improve the resistance to interference from other systems by improving the noise resistance of the receiver. Non-Patent Document 1 describes noise resistance performance by iterative processing between differential demodulation processing and decoding processing corresponding to convolutional coding in reception of a signal transmitted by differentially modulating a convolutional coded signal. Techniques for improving the above are described.

JP-A-2007-288263 International Publication 2016/162993 International Release 2017/013767

P. Hoeher and J. Lodge, "Turbo DPSK": Iterative Differential PSK Demodulation and Channel Decoding, IEEE Transactions on Communications, Vol. 47, No. 6, pp.837-843, June 1999

There is a technique of transmitting the same data multiple times to increase the possibility of successful demodulation on the receiving side and improving the noise resistance of the receiver, but Non-Patent Document 1 transmits the same data multiple times. The application to the system is not considered. Therefore, the invention disclosed in the present application first applies the technique described in Non-Patent Document 1 to a system for transmitting the same data a plurality of times to improve noise resistance and interference resistance. The purpose of.

Further, in the technique described in Patent Document 1, FFT (Fast Fourier Transform) for demodulating an OFDM (Orthogonal Frequency Division Multiplex) signal is performed before interference suppression, and the technique comprises a known pattern. It is necessary to identify the timing of FFT (boundary of OFDM symbols) using the preamble. However, in situations where the preamble is heavily interfered with, it becomes difficult to capture the preamble. Therefore, the second object of the invention disclosed in the present application is to improve the interference resistance of both the preamble and the data portion.

A typical example of the invention disclosed in the present application is as follows. That is, a receiver that receives a radio signal transmitted a plurality of times from the transmitter, an antenna that receives the radio signal, a plurality of demodulators that demodulate each of the signals received by the antenna, and the plurality of demodulators. A decoder that decodes the signal demodulated by the demodulator, a deinterleaver that executes a deinterleave process that changes the order of the codes of the outputs of the demodulator, and an interleave process that changes the order of the codes of the outputs of the decoder. And a plurality of firsts that reduce the output of the demodulator or the output of the deinterleaved demodulator after the output of the decoder is replicated for input to each of the demodulators. It is characterized by being provided with an adder of.

According to one aspect of the present invention, communication is possible even in an environment where large interference exists. Issues, configurations and effects other than those mentioned above will be clarified by the description of the following examples.

It is a figure which shows the interference suppression method with respect to a preamble and a data signal in 1st Example. It is a figure which shows the structure of the receiver in 1st Example. It is a figure which shows the structure of the interference canceller with respect to the data signal in 1st Example. It is a figure which shows the operation of the interference canceller with respect to the preamble in the 1st Example. It is a figure which shows the structure of the antenna selection part in 1st Example. It is a figure which shows the structure of the demodulation / decoding apparatus in the 1st Example. It is a figure which shows the structure of the demodulation / decoding apparatus in the 2nd Example. It is a figure which shows the structure of the demodulation / decoding apparatus in the 3rd Example. It is a figure which shows the structure of the demodulation / decoding apparatus of the comparative example.

Hereinafter, examples of the present invention will be described with reference to the drawings.

<Example 1>
FIG. 1 shows an interference suppression method according to the first embodiment of the present invention. The present invention is premised on performing communication in synchronization with the time slot. For example, as shown in the lower part of FIG. 1, transmission 106 and reception 107 are alternately repeated according to a specified time slot. The receiver measures the interference of the no-signal section 100 immediately before the start of the preamble in the reception time slot. The interference suppression coefficient for the preamble section 101 is suppressed according to the interference suppression coefficient calculated by the preamble interference suppression coefficient calculation unit 104 using the measured interference. In the OFDM (Orthogonal Frequency Division Multiplex) data signal 102 transmitted following the preamble section 101, a plurality of non-signal symbols 103 are arranged. This method is disclosed in, for example, Patent Document 2. Next, the interference is measured using the no-signal symbol 103. Then, the interference of the OFDM data signal 102 is suppressed according to the interference suppression coefficient calculated by the data signal interference suppression coefficient calculation unit 105 using the interference measured in the OFDM data signal 102.

FIG. 2 shows the configuration of the receiver of the first embodiment. In FIG. 2, components that are general to wireless communication devices such as RF (Radio Frequency) circuits and that are not related to the present invention are omitted. Antennas 201 and 202 receive the same signal transmitted from the transmitter. In particular, in the embodiments of the present invention, the transmitter transmits the same signal multiple times. In addition, the receiver receives signals with different propagation paths with a plurality of antennas. In the no-signal section 100 of FIG. 1, the signals received by the antennas 201 and 202 are converted into signals in the frequency domain by the overlap FFT (Fast Fourier Transform) 203 and 204, respectively.

The operation of the overlap FFT 203 and 204 will be described with reference to FIG. The Input Signal is delimited by a predetermined sample section. For example, in FIG. 4, it is separated by a section of N / 2 samples. The two N / 2 sample sections are combined to form an N sample section, which is multiplied by the first window function to perform an FFT (Fast Fourier Transform) operation. At this time, in the next N sample, the signal behind the N / 2 sample is used to overlap the N / 2 sample with the immediately preceding N sample. The FFT calculation is also performed on the next N sample in the same manner to convert it into a signal in the frequency domain. Similarly, the window function processing and the FFT calculation are sequentially performed while shifting N / 2 samples at a time. The signal converted into the signal in the frequency domain by the overlap FFT 203 and 204 is input to the antenna selection unit 205.

The antenna selection unit 205 is configured as shown in FIG. 5, for example. Selectors 501 and 502 select signals so that the power comparison unit 500 compares the signal powers from multiple antennas (two in the figure) and outputs the one with the larger average power from the upper side and the one with the smaller average power from the lower side. To do.

After that, the phase calculation unit 206 calculates the phase of the signal on the upper side (the one having the larger average power) output from the antenna selection unit 205. Then, the phase rotation calculation units 207 and 208 rotate the phase of the signal output from the antenna selection unit 205 in the opposite direction of the phase calculated by the phase calculation unit 206. The phase-rotated signals are averaged by the averaging units 209 and 210 over a plurality of neighboring frequencies and a plurality of overlapping FFT sections, and the mean value is maintained over the preamble section 101. The retained mean is multiplied by the multipliers 211 and 212, respectively, with different outputs of the antenna selection unit 205 in the preamble interval 101, and the adder 213 is used to subtract the other from one.

In this way, the first interference suppression unit 231 that removes interference from the preamble signal is configured by the configuration from the overlap FFTs 203 and 204 to the adder 213, and the preamble signal in the frequency domain in which the interference is removed can be obtained. The preamble signal in the frequency domain from which the interference has been removed is converted into a signal in the time domain by the overlap IFFT (Inverse Fast Fourier Transform) 214. The operation of the overlap Fourier will be described with reference to FIG. The preamble signal in the frequency domain from which the interference has been removed is subjected to an IFFT calculation for each N sample, and is converted into a preamble signal in the time domain from which the interference of the N samples has been removed. The preamble signal in the time domain from which the interference of the N sample is removed is multiplied by the second window function to obtain the output of the N sample. The output of the N sample is sequentially added to the output of the next N sample while shifting by N / 2 sample to obtain a continuous signal in the time domain in which the interference is removed. The first window function and the second window function are functions that have a small value at the start and end of the N sample and a large value at the center, respectively, and are the first window function and the second window function. It is a function that becomes a constant value when the product of is sequentially added while shifting by N / 2 samples. For example, if sin ((i / N) * π) (i = 0 to N-1) is adopted as the first window function and the second window function, the product of the first window function and the second window function. Is sin2 ((i / N) * π) = (1-cos (2 * (i / N) * π)) / 2, and when this is added while shifting N / 2 samples, it becomes 1, and the above condition is satisfied. You can see that it meets.

Then, the preamble capture unit 215 detects the preamble of the preamble signal in the continuous time region in which the interference output from the overlap IFFT 214 is removed. The preamble capture unit 215 can adopt a conventional method of configuring by cross-correlation calculation using a matched filter (Matched Filter), or by autocorrelation calculation in the case of a preamble signal including repetition of the same pattern. Based on the preamble timing detected by the preamble capture unit 215, the FFT calculation units 216 and 217 perform an FFT calculation of the OFDM data signals received by the antennas 201 and 202, respectively.

The data signal interference suppression coefficient calculation unit 105 calculates the interference suppression coefficient using the FFT calculation result. The calculated interference suppression coefficient is calculated by the interference suppression weight application unit 218 with the FFT calculation result, and the interference is suppressed and output. A second interference suppression unit 232 that removes interference from the data signal is configured by the interference suppression coefficient calculation unit 105 for the data signal and the interference suppression weight application unit 218. The data signal interference suppression coefficient calculation unit 105 can be configured as shown in FIG. 3, for example. The signal separation unit 300 separates the outputs of the FFT calculation units 216 and 217 into symbols that do not include data signals (Null in FIG. 3), reference symbols (Reference in FIG. 3), and data symbols (Data in FIG. 3), respectively. .. For symbols that do not include data signals, interference is measured by the interference propagation path estimation unit 301. The first interference suppression unit 302 performs interference suppression on a symbol that does not include a data signal, based on the measured interference. As the calculation for interference suppression here, the same calculation as the interference suppression coefficient calculation method in the preamble interference suppression coefficient calculation unit 104 and the interference elimination calculation in the multipliers 211, 212 and the adder 213 can be adopted. Since only interference and noise are received in the symbol that does not include the data signal, only noise remains as a result of the interference suppression calculation. Therefore, the noise power can be estimated by measuring the power after the interference suppression calculation. The noise level can be estimated by the noise level estimation unit 304.

Similarly, the interference suppression calculation is performed by the first interference suppression unit 303 with respect to the reference symbol. At this time, since at least one of the time and frequency of the reference symbol is different from that of the symbol that does not include the data signal, the interference propagation path estimation unit 301 interferes with the symbol other than the symbol that does not include the data signal by interpolation by moving average calculation or the like. It is necessary to estimate the propagation path. The signal propagation path estimation unit 305 estimates the signal propagation path using at least one of the reference symbol output from the signal separation unit 300 and the reference symbol that has undergone interference suppression processing. For example, when the interference of the received signal is small, the reference symbol output from the signal separation unit 300 may be used, and when the interference of the received signal is large, the reference symbol subjected to the interference suppression process may be used for estimation. Further, it is preferable to estimate the propagation path by changing the weighting coefficient of the reference symbol output from the signal separation unit 300 and the weighting coefficient of the reference symbol processed for interference suppression depending on the magnitude of interference of the received signal.

The output I of the interference propagation path estimation unit 301, the output N of the noise level estimation unit 304, and the output S of the signal propagation path estimation unit 305 are interpolated and output in the time and frequency directions. These outputs I, N, and S suppress interference with respect to symbols, reference symbols, and data symbols that do not include a data signal at the interference suppression weight application unit 218 (306, 307) as interference suppression coefficients. The calculation executed by the interference suppression weight application units 306 and 307 is preferably a MMSE (Mini-Mean Square Error) process. In this process, for example, when the signal propagation path estimation result is _Sn1 and _Sn2 , the interference propagation path measurement result is Γ _n1 and Γ _n2 , and the noise level estimation result is σ ² , the equation (1) and the equation (1) and the equation ( This can be achieved by multiplying the interference suppression coefficient W _n calculated using 2).

The interference suppression result of the symbol not including the data signal is input to the noise level estimation unit 308, and the noise level estimation unit 308 obtains the second noise level estimation result. Further, the interference suppression result of the reference symbol and the data symbol is input to the demodulator 220 together with the second noise level estimation result, and the demodulation process is executed by the demodulator 220. The demodulation result output from the demodulator 220 is input to the demodulator 221 and the decoding process is executed.

The first embodiment provides a demodulation / decoding method that reduces the influence of interference by improving the noise immunity. The first embodiment presupposes a transmission method in which the same data is transmitted a plurality of times in order to improve the reliability of data transmission. Further, in the first embodiment, the transmission signal is differentially modulated.

FIG. 6 shows the configuration of the demodulation / decoding unit 219. In this embodiment, the transmitter shall transmit the same signal n times. In the receiver of the first embodiment, the received signals 1 to n are stored in the memories 600-1 to n, respectively. The differential signal demodulation unit 601-1 to n demodulates the stored received signals 1 to n and outputs an n-set first LLR (Log Likelihood Ratio). In FIG. 6, the signal line corresponding to the first LLR is designated by a reference numeral (1), and the same applies hereinafter to the eighth LLR (8). As the differential signal demodulators 601-1 to n, for example, the demodulator described in Patent Document 3 can be adopted. Further, as another demodulator, a demodulator of the maximum likelihood sequence estimation (MLSE: Maximum Likelihood Sequence Estimation) method may be adopted. More generally, a demodulator that outputs a demodulation result by referring to a number of received symbols exceeding 2 in the vicinity can be adopted.

The first LLR of the n sets is deinterleaved by changing the order of the codes corresponding to the interleaves adopted by the transmitting side by the deinterleavers 603-1 to n, respectively, and the second LLR of the n sets is output. Will be done. Then, the adder 604 adds the second LLR of this n set and outputs the third LLR. After that, the decoder 221 decodes the third LLR and outputs the posterior LLR (fourth LLR: a posteriori LLR). As the decoder 221 can be used as a SISO (Soft Input Soft Output) decoder that inputs LLR and outputs LLR after the fact. This is, for example, a decoder to which the BCJR algorithm is applied.

This fourth LLR is replicated in n sets, and adders 606-1 to n subtract the second LLR and output the fifth LLR in n sets. The fifth LLR of the n sets is subjected to interleaving in which the order of the codes is changed in the same manner as the interleaving adopted on the transmitting side by the interleavers 607-1 to n, and the sixth LLR of the n sets is output. The differential signal demodulators 601-1 to n use the input n sets of the sixth LLR as a pre-LLR (a priori LLR) to receive the received signals 1 to stored in the memories 600-1 to n. n is demodulated again and n sets of the seventh LLR are output.

The adders 602-1 to n subtract n sets of the sixth LLR from n sets of the seventh LLR, respectively, and output n sets of the eighth LLR. The eighth LLR of the n set is deinterleaved again by the deinterleaver 603-1 to n, and the updated second LLR is output.

After that, the second to eighth LLRs are sequentially updated by repeating the above-described processing. After repeating the process a predetermined number of times, the soft determination decoding result output from the decoder 221 is hard-determined to obtain the decoding result.

In this embodiment, the LLR of the data bits obtained from all n differential signal demodulators 601-1 to n after the posterior LLR (fourth LLR: a posteriori LLR) output from the decoder 221 and before and after the LLR thereof. Contains all LLRs of bits of. Therefore, in the subtraction process in the adders 606-1 to n, the second LLR including the influence of the LLR given by the differential signal demodulation unit 601-1 to n is subtracted from the fourth LLR to reduce the external LLR. (Extrinsic LLR) is calculated. As a result, the pre-LLR (sixth LLR: a preori LLR) given to the differential signal demodulation unit 601-1 to n does not include the LLR of the bit output by itself, and is another differential signal demodulation unit. It is possible to calculate the pre-LLR including the LLR of the bit output by 601-1 to n and the LLR of other bits output by itself.

Similarly, the seventh LLR, which is the result of the differential signal demodulation processing, includes the influence of the pre-LLR (sixth LLR: a priori LLR) of the bit and the preceding and following bits. Therefore, in the subtraction process in the adders 602-1 to n, the external LLR (Extrinsic LLR) is calculated by subtracting the prior LLR (sixth LLR: a priori LLR) of the bit from the seventh LLR. There is.

Further, although the differential signal demodulation units 601-1 to n are shown in parallel in FIG. 6, one differential signal demodulation unit may be used n times to execute n sets of demodulation processing.

As described above, according to the first embodiment, in a wireless communication device that communicates using a signal composed of a preamble signal 101 and an OFDM-modulated data signal 102, a signal is received by using a plurality of antennas. Then, the interference is suppressed based on the interference measured in the non-signal section 100 before the start of the preamble, and the timing is synchronized using the preamble (synchronization signal) after the interference is suppressed, and after the timing synchronization, it is in the OFDM signal (data). Interference is suppressed based on the interference measured using the non-signal portion 103 arranged in portion 102). Therefore, communication is possible even in an environment where large interference exists. In particular, communication is possible even in an environment where there is greater interference than the signal.

According to the demodulation / decoding unit 219 of the first embodiment, in the communication method in which the same data is transmitted a plurality of times, both the characteristic improvement by the repeated demodulation / decoding and the characteristic improvement by the synthesis of the plurality of data can be enjoyed, and the noise immunity resistance. Demodulation / decoding with improved performance is possible. For example, in comparison with Comparative Example no iterative detection and decoding (see FIG. 9), packet error rate (PER) is interference resistance performance is 6dB improvement in ^10-2. That is, it can withstand about four times as much power interference.

Further, when the number of the same data transmitted from the transmitter (continuous transmission composite number) is set to 5, the interference resistance performance is improved by 12 dB from the configuration described in FIG. 3 of Non-Patent Document 1. That is, it can withstand about 16 times more power interference.

<Example 2>
Next, a second embodiment of the present invention will be described. In the second embodiment, the differences from the first embodiment will be mainly described, the same functions and processes as in the first embodiment will be designated by the same reference numerals, and the description thereof will be omitted.

FIG. 7 shows the configuration of the demodulation / decoding unit 219 of the second embodiment of the present invention. In the second embodiment, the positions of the adders 606-1 to n are different from those in the first embodiment. In the demodulation / decoding unit 219 of the first embodiment, the second LLR is subtracted (606-1 to n) before the interleaving (607-1 to n), but in the second embodiment, the interleaving (607) The eleventh or eighteenth LLR is subtracted (606-1 to n) after -1 to n). The operation of the demodulation / decoding unit 219 of the second embodiment is the same as that of the first embodiment except that the order of processing is different.

According to the demodulation / decoding unit 219 of the second embodiment, the equivalent demodulation / decoding process can be executed with a configuration different from that of the first embodiment.

<Example 3>
Next, a third embodiment of the present invention will be described. In the third embodiment, the differences from the first embodiment will be mainly described, the same functions and processes as in the first embodiment will be designated by the same reference numerals, and the description thereof will be omitted.

FIG. 8 shows a third embodiment of the present invention. The configuration of the third embodiment can be adopted when the interleaves of the signals transmitted a plurality of times are the same, and the deinterleaver and interleaver of each signal are shared. Therefore, the circuit scale is larger than that of the first and second embodiments. Can be reduced. In FIG. 8, the signal line corresponding to the 21st LLR is designated by a reference numeral (21), and the same applies hereinafter to the 28th LLR (28).

In the third embodiment, the operations of the memories 600-1 to n and the differential signal demodulation unit 601-1 to n are the same as those in the first embodiment. The adder 604 adds the n sets of 21 LLRs output from the differential signal demodulation units 601-1 to n, and outputs the 22nd LLR. The deinterleaver 603 deinterleaves the 22nd LLR and outputs the 23rd LLR. The decoder 221 decodes the 23rd LLR and outputs a posterior LLR (24th LLR: a posteriori LLR).

The interleaver 607 interleaves the twenty-fourth LLR and outputs the twenty-fifth LLR. The twenty-fifth LLR is replicated in n sets.
Each of the adders 606-1 to n subtracts the 21st LLR from the duplicated 25th LLR and outputs the 26th LLR. The differential signal demodulation unit 601-1 to n demodulates the received signals 1 to n stored in the memories 600-1 to n again by using the 26th LLR as a prior LLR (a priori LLR). , N sets of 27 LLRs are output.

The adders 602-1 to n subtract n sets of 26 LLRs from n sets of 27 LLRs, respectively, and output n sets of 28 LLRs. The twenty-eighth LLRs of the n sets are added again by the adder 604 and output the updated twenty-two LLRs.

After that, by repeating the above-described processing, the LLRs 22 to 28 are sequentially updated. In the second and subsequent repetitions, the adders 606-1 to n subtract the 28 LLR instead of the 21 LLR. After repeating the process a predetermined number of times, the soft determination decoding result output from the decoder 221 is hard-determined to obtain the decoding result.

According to the demodulation / decoding unit 219 of the third embodiment, the same noise resistance characteristics can be realized with a smaller circuit scale than that of the first and second embodiments.

As described above, the receiver of the embodiment of the present invention receives the radio signal transmitted a plurality of times from the transmitter, and an antenna for receiving the radio signal (for example, a plurality of antennas 201, 202). ), A plurality of demodulators 601 that demodulate each of the signals received by the plurality of antennas 201 and 202, a decoder 221 that decodes the signals demodulated by the plurality of demodulators 601 and the output codes of the demodulator 220. The deinterleaver 603 that executes the deinterleave process that changes the order of the deinterleavers, the interleaver 607 that executes the interleave process that changes the order of the codes of the outputs of the decoder 221 and the output of the decoder 221 are input to each of the plurality of demodulators 601. Since it is provided with a plurality of first adders 606 that reduce the output of the demodulator 601 or the output of the deinterleaved demodulator 601 after being duplicated to be performed, the interference resistance performance is improved and large interference is caused. Communication is possible even in an existing environment.

Further, the output of the decoder 221 is interleaved and input to the demodulator 601. The demodulator 601 executes the demodulation process using the output of the interleaved decoder, and the output of the demodulator 601 is demodulated. It is interleaved and input to the decoder 221. The loop between the demodulator 601 and the decoder 221 is repeated a predetermined number of times to execute the demodulation and decoding processing, so that the interference resistance performance is improved and large interference exists. Communication is possible even in the environment.

Further, since the demodulator 601 outputs the demodulation result by referring to a number of received symbols exceeding 2 in the vicinity, the demodulation result which is the most plausible estimated amount can be obtained.

Further, each of the plurality of demodulators 601 outputs the first LLR (1) as a result of the demodulation process, and each of the plurality of deinterleavers 603 performs the deinterleave process on the first LLR and second. The LLR (2) of the above is output, and the decoder 221 performs soft determination decoding using the third LLR (3) obtained by synthesizing a plurality of second LLRs, and the soft determination decoding result is the post-LLR. The fourth LLR (4) is output, the fourth LLR is distributed to a number of demodulators, and the first adder 606 subtracts the second LLR from the distributed fourth LLR. , The fifth LLR (5) is output, the interleaver 607 performs interleaving processing on the fifth LLR, outputs the sixth LLR (6), and the demodulator 601 preliminarily outputs the sixth LLR. The demodulation process is performed again, and the seventh LLR (7) is output, and the second adder 602 subtracts the sixth LLR from the seventh LLR to reduce the sixth LLR to the eighth LLR (8). Is output, each of the plurality of demodulators 603 performs deinterleave processing on the eighth LLR again, outputs the second LLR (2), and calculates from the second LLR to the eighth LLR. The process is repeated a predetermined number of times, and after the predetermined number of repetitions, the decoder 221 makes a hard determination of the soft determination decoding result and outputs the decoding result, so that the interference resistance performance is improved and communication is possible even in an environment where large interference exists. It becomes.

Further, each of the plurality of demodulators 601 outputs the eleventh LLR (11) as a result of the demodulation processing, and each of the plurality of deinteravers 603 performs the deinterleaving processing on the eleventh LLR. The twelfth LLR (12) is output, and the decoder 221 performs soft judgment decoding using the thirteenth LLR (13) obtained by synthesizing a plurality of twelfth LLRs, and the soft judgment decoding result. Outputs the fourteenth LLR (14), which is the ex post facto LLR, the fourteenth LLR is distributed to a plurality of demodulators, and the interleaver 607 performs interleaving processing on the distributed fourteenth LLR. The fifteenth LLR (15) is output, and the first adder 606 subtracts the eleventh LLR from the fifteenth LLR and outputs the sixteenth LLR (16). The demodulator 601 uses the sixteenth LLR as a pre-LLR to perform demodulation processing again, outputs the seventeenth LLR (17), and the second adder 602 is from the seventeenth LLR. The sixteenth LLR is subtracted to output the eighteenth LLR (18), and each of the plurality of demodulators 603 performs demodulation processing on the eighteenth LLR again, and the twelve LLRs ( 12) is output, and the process of calculating from the twelfth LLR to the eighteenth LLR is repeated a predetermined number of times. Since it outputs, the interference resistance performance is improved, and communication is possible even in an environment where large interference exists.

Further, each of the plurality of demodulators 601 outputs the 21st LLR (21) as a result of the demodulation processing, and the deinterer 603 outputs the 22nd LLR obtained by synthesizing the plurality of 21 LLRs. The LLR (22) is subjected to demodulation processing to output the 23rd LLR (23), and the decoder 221 performs soft judgment decoding using the 23rd LLR to perform the soft judgment decoding. From the result, the twenty-fourth LLR (24), which is the ex post facto LLR, is output, and the interleaver 607 performs interleaving processing on the twenty-fourth LLR, outputs the twenty-fifth LLR (25), and outputs the 25th LLR. The twenty-five LLRs are distributed to a number of demodulators 601 and the first adder 606 subtracts the twenty-one LLRs from the distributed twenty-five LLRs to make the twenty-sixth. The LLR (26) of the above is output, and the demodulator 601 uses the 26 LLR as a preliminary LLR to perform the demodulation process again, outputs the 27 LLR (27), and outputs the second LLR (27). The adder 602 subtracts the 26 LLR from the 27 LLR and outputs the 28 LLR (28), and the demodulator 603 demodulates to the 28 LLR again. The process of performing the process, outputting the 22nd LLR (22), and calculating from the 22nd LLR to the 28th LLR is repeated a predetermined number of times, and the decoder 221 repeats the process a predetermined number of times. Later, since the soft determination decoding result is hard-determined and the decoding result is output, the interference resistance performance can be improved with a small circuit scale, and communication becomes possible even in an environment where large interference exists.

Among the inventions disclosed in the specification of the present application, the following are typical viewpoints other than those described in the claims.

(1) A receiver that receives a radio signal including a preamble signal and an OFDM-modulated data signal.
A plurality of antennas that receive the radio signal,
Interference is measured in the non-signal section prior to the preamble signal, the first interference suppression coefficient is calculated based on the interference measurement result, and the first interference suppression coefficient is calculated using the calculated first interference suppression coefficient. A receiver comprising a first interference suppressor that performs the above.

(2) A receiver that receives a radio signal including a preamble signal and an OFDM-modulated data signal.
A plurality of antennas that receive the radio signal,
After the timing synchronization using the preamble signal, the interference is measured in the non-signal portion arranged in the data signal, the second interference suppression coefficient is calculated based on the interference measurement result, and the calculated second A receiver including a second interference suppression unit that performs a second interference suppression using the interference suppression coefficient of the above.

(3) A receiver that receives a radio signal including a preamble signal and a data signal.
An antenna that receives the radio signal and
A first interference suppression unit that measures interference in a non-signal section prior to the preamble signal and performs first interference suppression based on the interference measurement result.
After timing synchronization using the preamble signal in which the first interference suppression is performed, the interference is measured in the non-signal portion arranged in the data signal, and the second interference suppression is performed based on the interference measurement result. A receiver including a second interference suppression unit.

(4) An FFT calculation unit that multiplies the time domain signal by the first window function to convert it into a frequency domain signal.
It is equipped with an IFFT calculation unit that multiplies the signal in the frequency domain by the second window function and converts it into a signal in the time domain.
The first interference suppression unit performs the first interference suppression on the signal converted into a signal in the frequency domain by the FFT calculation unit.
The receiver according to each of the above items, wherein the product of the first window function and the second window function is added by shifting the product by a predetermined number of samples to obtain a constant value.

(5) The antenna is a plurality of antennas including at least a first antenna and a second antenna.
The first interference suppression unit is
A phase calculation unit that calculates the phase of the interference wave in the non-signal section received by the first antenna, and
A first phase rotation calculation unit that rotates the signal received by the first antenna in the opposite direction of the calculated phase, and
A second phase rotation calculation unit that rotates the signal received by the second antenna in the opposite direction of the calculated phase, and
A first multiplier that multiplies the signal received by the first antenna and the signal whose phase is rotated by the second phase rotation calculation unit.
A second multiplier that multiplies the signal received by the second antenna and the signal whose phase has been rotated by the first phase rotation calculation unit.
The receiver according to each of the above items, comprising an adder for calculating the difference between the output of the first multiplier and the output of the second multiplier.

(6) The second interference suppression unit has a signal separation unit that extracts a reference symbol from the input signal and a propagation path estimation unit that estimates the propagation path of the signal.
The propagation path estimation unit
Propagation path using at least one of the first reference symbol output from the signal separation unit and the second reference symbol whose interference suppression is performed on the first reference symbol in the first interference suppression unit. To estimate
The receiver according to each of the above items, wherein the propagation path is estimated by changing the weights of the first reference symbol and the second reference symbol according to the magnitude of interference of the received signal.

It should be noted that the present invention is not limited to the above-described examples, but includes various modifications and equivalent configurations within the scope of the attached claims. For example, the above-described examples have been described in detail in order to explain the present invention in an easy-to-understand manner, and the present invention is not necessarily limited to those having all the described configurations. In addition, a part of the configuration of one embodiment may be replaced with the configuration of another embodiment. In addition, the configuration of another embodiment may be added to the configuration of one embodiment. In addition, other configurations may be added / deleted / replaced with respect to a part of the configurations of each embodiment.

Further, each of the above-described configurations, functions, processing units, processing means, etc. may be realized by hardware by designing a part or all of them by, for example, an integrated circuit, and the processor realizes each function. It may be realized by software by interpreting and executing the program to be executed.

Information such as programs, tables, and files that realize each function can be stored in a memory, a hard disk, a storage device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

In addition, the control lines and information lines indicate those that are considered necessary for explanation, and do not necessarily indicate all the control lines and information lines necessary for implementation. In practice, it can be considered that almost all configurations are interconnected.

100: No signal section 101: Preamble 102: OFDM data signal 103: No signal OFDM symbol 104: Interference suppression coefficient calculation unit for preamble 105: Interference suppression coefficient calculation unit for data signal 106: Transmission signal 107: Received signals 201, 202: Antennas 203, 204: Overlap FFT
205: Antenna selection unit 206: Phase calculation unit 207, 208: Phase rotation calculation unit 209, 210: Average calculation unit 211, 212: Multiplier 213: Adder 214: Overlap Fourier
215: Preamble capture unit 216, 217: FFT calculation unit 218: Interference suppression weight application unit 219: Demodulation / decoding unit 220: Demodulator 221: Decoder 300: Signal separation unit 301: Interference propagation path estimation unit 302, 303: No. One interference suppression unit 304, 308: noise level estimation unit 305: signal propagation path estimation unit 306, 307: interference suppression weight application unit 500: power comparison unit 501, 502: selector 600-1 to n: memory 601-1 to n: Differential signal demodulator 602-1 to n, 604, 606-1 to n: Adder 603-1 to n, 603: Deintereriver 607-1 to n, 607: Interferer

Claims (12)

A receiver that receives radio signals transmitted multiple times from the transmitter.
An antenna that receives the radio signal and
A plurality of demodulators that demodulate each of the signals received by the antenna,
A decoder that decodes the signals demodulated by the plurality of demodulators, and
A deinterleaver that executes deinterleave processing that changes the order of the codes of the outputs of the demodulator, and
An interleaver that executes an interleave process that changes the order of the codes of the output of the decoder, and
With a plurality of first adders that reduce the output of the demodulator or the output of the deinterleaved demodulator after the output of the decoder has been replicated for input to each of the demodulators. A receiver characterized by being equipped with. The receiver according to claim 1.
The output of the decoder is interleaved and input to the demodulator.
The demodulator uses the output of the interleaved decoder to perform demodulation processing.
The output of the demodulator is deinterleaved and input to the decoder.
A receiver characterized in that a demodulation and decoding process is executed by repeating a loop between the demodulator and the decoder a predetermined number of times. The receiver according to claim 1.
The demodulator is a receiver characterized in that the demodulation result is output by referring to a number of received symbols exceeding 2 in the vicinity. The receiver according to claim 1.
A second adder that subtracts the output of the interleaved decoder from the output of the plurality of demodulators is provided.
Each of the plurality of demodulators outputs the first LLR as a result of the demodulation process.
Each of the plurality of deinterleavers performs deinterleave processing on the first LLR and outputs a second LLR.
The decoder performs soft determination decoding using a third LLR obtained by synthesizing a plurality of the second LLRs, and outputs a fourth LLR which is a subsequent LLR from the soft determination decoding result.
The fourth LLR is distributed to the number of the plurality of demodulators.
The first adder subtracts the second LLR from the distributed fourth LLR and outputs the fifth LLR.
The interleaver performs interleaving processing on the fifth LLR, outputs the sixth LLR, and outputs the sixth LLR.
The demodulator uses the sixth LLR as a pre-LLR to perform the demodulation process again, and outputs the seventh LLR.
The second adder subtracts the sixth LLR from the seventh LLR to output the eighth LLR.
Each of the plurality of deinterleavers performs deinterleave processing on the eighth LLR again, outputs the second LLR, and outputs the second LLR.
The process of calculating from the second LLR to the eighth LLR is repeated a predetermined number of times.
The decoder is a receiver characterized in that after repeating the predetermined number of times, the soft determination decoding result is hard-determined and the decoding result is output. The receiver according to claim 1.
A second adder that subtracts the output of the interleaved decoder from the output of the plurality of demodulators is provided.
Each of the plurality of demodulators outputs the eleventh LLR as a result of the demodulation process.
Each of the plurality of deinterleavers performs deinterleave processing on the eleventh LLR and outputs the twelfth LLR.
The decoder performs soft determination decoding using the thirteenth LLR obtained by synthesizing the plurality of the twelfth LLRs, and outputs the fourteenth LLR which is the posterior LLR from the soft determination decoding result.
The fourteenth LLR is distributed to the number of the plurality of demodulators.
The interleaver performs interleaving processing on the distributed fourteenth LLR, outputs the fifteenth LLR, and outputs the fifteenth LLR.
The first adder subtracts the eleventh LLR from the fifteenth LLR and outputs the sixteenth LLR.
The demodulator uses the sixteenth LLR as a pre-LLR to perform the demodulation process again, and outputs the seventeenth LLR.
The second adder subtracts the sixteenth LLR from the seventeenth LLR to output the eighteenth LLR.
Each of the plurality of deinterleavers performs deinterleave processing on the eighteenth LLR again, outputs the twelfth LLR, and outputs the twelfth LLR.
The process of calculating from the twelfth LLR to the eighteenth LLR is repeated a predetermined number of times.
The decoder is a receiver characterized in that after repeating the predetermined number of times, the soft determination decoding result is hard-determined and the decoding result is output. The receiver according to claim 1.
A second adder that subtracts the output of the interleaved decoder from the output of the plurality of demodulators is provided.
Each of the plurality of demodulators outputs the 21st LLR as a result of the demodulation process.
The deinterleaver performs deinterleave processing on the 22 LLRs obtained by synthesizing the plurality of the 21 LLRs, and outputs the 23 LLRs.
The decoder performs soft judgment decoding using the 23rd LLR, and outputs the 24th LLR which is the post-LLR from the soft judgment decoding result.
The interleaver performs interleaving processing on the twenty-fourth LLR and outputs the twenty-fifth LLR.
The twenty-fifth LLR is distributed to the number of the plurality of demodulators.
The first adder subtracts the 21st LLR from the 25th distributed LLR and outputs the 26th LLR.
The demodulator uses the 26 LLR as a preliminary LLR, performs the demodulation process again, and outputs the 27 LLR.
The second adder subtracts the 26 LLR from the 27 LLR to output the 28 LLR.
The deinterleaver performs deinterleave processing on the 28th LLR again, outputs the 22nd LLR, and outputs the 22nd LLR.
The process of calculating from the 22nd LLR to the 28th LLR is repeated a predetermined number of times.
The decoder is a receiver characterized in that after repeating the predetermined number of times, the soft determination decoding result is hard-determined and the decoding result is output. A receiving method in which the receiver receives a wireless signal transmitted multiple times from the transmitter.
The receiver
The antenna that receives the signal and
A plurality of demodulators that demodulate each of the signals received by the antenna,
A decoder that decodes the signals demodulated by the plurality of demodulators, and
A deinterleaver that executes deinterleave processing that changes the order of the codes of the outputs of the demodulator, and
It has an interleaver that executes an interleave process that changes the order of the codes of the outputs of the decoder.
The receiving method is
A receiving method comprising reducing the output of the demodulator or the output of the deinterleaved demodulator after the output of the decoder has been replicated for input to each of the plurality of demodulators. The receiving method according to claim 7.
The decoded signal is interleaved and used as an input for the demodulation process.
In the demodulation process, the demodulation process is executed using the interleaved signal.
The demodulated signal is deinterleaved and used as an input for the decoding process.
A receiving method comprising repeating a loop between the demodulation process and the decoding process a predetermined number of times to execute the demodulation and decoding process. The receiving method according to claim 7.
The demodulator is a receiving method characterized in that a demodulation result is output by referring to a number of reception symbols exceeding 2 in the periphery. The receiving method according to claim 7.
The receiver
A plurality of first adders that subtract the output of the deinterleaved demodulator from the output of the decoder, and
It has a second adder that subtracts the output of the decoder that has been interleaved from the output of the plurality of demodulators.
The receiving method is
Each of the plurality of demodulators outputs the first LLR as a result of the demodulation process.
Each of the plurality of deinterleavers performs deinterleave processing on the first LLR and outputs a second LLR.
The decoder performs soft determination decoding using a third LLR obtained by synthesizing a plurality of the second LLRs, and outputs a fourth LLR which is a posterior LLR from the soft determination decoding result.
The fourth LLR is distributed to the number of the plurality of demodulators.
The first adder subtracts the second LLR from the distributed fourth LLR and outputs the fifth LLR.
The interleaver performs interleaving processing on the fifth LLR and outputs the sixth LLR.
The demodulator uses the sixth LLR as a pre-LLR to perform the demodulation process again, and outputs the seventh LLR.
The second adder subtracts the sixth LLR from the seventh LLR to output the eighth LLR.
Each of the plurality of deinterleavers performs deinterleave processing on the eighth LLR again, outputs the second LLR, and outputs the second LLR.
The process of calculating from the second LLR to the eighth LLR is repeated a predetermined number of times.
A receiving method, wherein the decoder makes a hard determination of the soft determination decoding result and outputs the decoding result after the repetition of the predetermined number of times. The receiving method according to claim 7.
The receiver
A plurality of first adders that subtract the output of the demodulator from the output of the interleaved decoder,
It has a second adder that subtracts the output of the decoder that has been interleaved from the output of the plurality of demodulators.
The receiving method is
Each of the plurality of demodulators outputs the eleventh LLR as a result of the demodulation process.
Each of the plurality of deinterleavers performs deinterleave processing on the eleventh LLR and outputs the twelfth LLR.
The decoder performs soft determination decoding using the thirteenth LLR obtained by synthesizing the plurality of the twelfth LLRs, and outputs the fourteenth LLR which is the posterior LLR from the soft determination decoding result.
The fourteenth LLR is distributed to the number of the plurality of demodulators.
The interleaver performs interleaving processing on the distributed fourteenth LLR and outputs the fifteenth LLR.
The first adder subtracts the eleventh LLR from the fifteenth LLR and outputs the sixteenth LLR.
The demodulator uses the sixteenth LLR as a pre-LLR to perform the demodulation process again, and outputs the seventeenth LLR.
The second adder subtracts the sixteenth LLR from the seventeenth LLR to output the eighteenth LLR.
Each of the plurality of deinterleavers performs deinterleave processing on the eighteenth LLR again, outputs the twelfth LLR, and outputs the twelfth LLR.
The process of calculating from the twelfth LLR to the eighteenth LLR is repeated a predetermined number of times.
A receiving method, wherein the decoder makes a hard determination of the soft determination decoding result and outputs the decoding result after the repetition of the predetermined number of times. The receiving method according to claim 7.
The receiver
A plurality of first adders that subtract the output of the deinterleaved demodulator from the output of the decoder, and
It has a second adder that subtracts the output of the decoder that has been interleaved from the output of the plurality of demodulators.
The receiving method is
Each of the plurality of demodulators outputs the 21st LLR as a result of the demodulation process.
The deinterleaver performs deinterleave processing on the 22 LLR that synthesizes the plurality of the 21 LLR, and outputs the 23 LLR.
The decoder performs soft judgment decoding using the 23rd LLR, and outputs the 24th LLR which is the post-LLR from the soft judgment decoding result.
The interleaver performs interleaving processing on the twenty-fourth LLR and outputs the twenty-fifth LLR.
The twenty-fifth LLR is distributed to the number of the plurality of demodulators.
The first adder subtracts the 21st LLR from the distributed 25th LLR and outputs the 26th LLR.
The demodulator uses the 26 LLR as a pre-LLR to perform the demodulation process again, and outputs the 27 LLR.
The second adder subtracts the 26 LLR from the 27 LLR to output the 28 LLR.
The deinterleaver performs deinterleave processing on the 28th LLR again, outputs the 22nd LLR, and outputs the 22nd LLR.
The process of calculating from the 22nd LLR to the 28th LLR is repeated a predetermined number of times.
A receiving method, wherein the decoder makes a hard determination of the soft determination decoding result and outputs the decoding result after the repetition of the predetermined number of times.

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