JP2020185924A - Vehicle control device - Google Patents

Abstract

To provide a vehicle control device capable of improving a data delivering speed between processor cores.SOLUTION: A vehicle control device 3 provided with a processor 30 for controlling a vehicle 1 includes a plurality of processor cores. The plurality of processor cores include a function for detecting difference data showing difference between prescribed sensor data received from a sensor 7 and sensor data to be stored in a large capacity memory, and a function for delivering the prescribed sensor data by delivering address information of the large capacity memory storing the difference data among the plurality of processor cores through a core memory. A plurality of prescribed processor cores of acquiring the prescribed sensor data perform a plurality of prescribed processes on the basis of the prescribed sensor data.SELECTED DRAWING: Figure 1

Description

The present invention relates to a vehicle control device.

Conventionally, there is known a control device that completes a plurality of processes within a predetermined time by using a multi-core processor. For example, a vehicle control device used for automatic driving allows a vehicle to travel safely by executing engine control, course control, or the like within a predetermined time. As the amount of data used for control increases, the access time to the data stored in the storage unit increases. This makes it difficult for the vehicle control device to control the vehicle within a predetermined time. Therefore, the vehicle control device is required to improve the data transfer speed between the processor cores.

The technique of Patent Document 1 can efficiently perform processing in an apparatus having a plurality of processor cores. In the information processing device, processor cores each having a local memory are connected in series via a shared memory which is a dual port memory. By inputting / outputting data between each processor core via the shared memory, it is possible to avoid a state of waiting for access. As a result, the information processing apparatus can improve the processing efficiency.

Japanese Unexamined Patent Publication No. 2006-285724

In Patent Document 1, processing efficiency is improved by allowing each processor core to access the shared memory at the same time. However, since each processor core calls the data to be processed from the shared memory, the time required for data transfer between the processor cores increases as the data capacity of the processing target increases.

Therefore, the present invention has been made to solve the above problems, and provides a vehicle control device capable of improving the data transfer speed between processor cores.

A vehicle control device 3 including a processor 30 for controlling a vehicle 1, wherein the processor includes a plurality of processor cores 31 and a core memory 33 connected to the processor cores so as to be able to exchange data, and further controls the vehicle. The apparatus includes a large-capacity memory 34 having a larger storage area than the core memory and a slower access speed to data than the core memory, and the plurality of processor cores receive predetermined sensor data and a large-capacity memory received from the sensor 7. By passing the function of detecting the difference data indicating the difference from the sensor data stored in the data and the address information of the large-capacity memory in which the difference data is stored between a plurality of processor cores via the core memory, it is determined. A plurality of predetermined processor cores having a function of passing the sensor data of the above and acquiring predetermined sensor data perform a plurality of predetermined processes based on the predetermined sensor data.

According to the present invention, the data transfer speed between processor cores can be improved.

The explanatory view of the vehicle control device in 1st Example. Explanatory drawing of an in-vehicle network. Hardware configuration diagram of the vehicle control device. Explanatory diagram of data transfer between each processor core. Flow chart of the data transmission processing unit. Explanatory drawing of data transmission processing part. Flow diagram of the receiving processor core. Explanatory drawing of data transfer between each processor core in 2nd Example. Flow chart of the destination switching unit. Flow chart of the difference save part. Explanatory drawing of the difference data storage part. Flow diagram of the receiving processor core. The explanatory view of the transfer of data between each processor core in the 3rd Example. Flow chart of the difference data transmitter. The explanatory view of the transfer of data between each processor core in 4th Example. Flow diagram of the receiving processor core. The explanatory view of the transfer of data between each processor core in 5th Example. Flow diagram of the transmitting processor core. The explanatory view of the transfer of data between each processor core in 6th Example.

Hereinafter, the present embodiment will be described with reference to the accompanying drawings, but the present embodiment is not limited to the configuration described in the drawings. The present embodiment relates to a vehicle control device (which may be referred to as an ECU (Electronic Control Unit) in the figure) 3 capable of improving the data transfer speed between the processor cores 31 (1) to 31 (m). .. The vehicle control device 3 of the present embodiment can be used in a vehicle control system that controls a vehicle 1 based on data from a sensor 7 or the like.

The vehicle control device 3 includes, for example, a processor 30 and a large-capacity memory (may be referred to as Glo1bal RAM in the figure) 34. The processor 30 includes, for example, a plurality of processor cores 31 (1) to 31 (m) and a core memory (may be referred to as Local RAM in the figure) 33. Each processor core 31 (1) to 31 (m) may be referred to as a processor core 31 unless otherwise specified.

The processor core 31 is, for example, a core part of a processor that performs arithmetic processing for controlling a vehicle 1. The processor core 31 (1) is, for example, a transmitting side processor core (may be referred to as a transmitting side core in the figure) 32 that passes sensor data from a sensor 7 or the like to another processor core. The processor cores 31 (2) to 31 (m) are, for example, a receiving side processor core (may be referred to as a receiving side core in the figure) 35 that acquires sensor data passed from the transmitting side processor core 32.

The sensor data is not limited to data showing a predetermined value, and may be a data group in which a plurality of data are aggregated. The data indicating a predetermined value is, for example, a value of the rotational speed of the engine, a value of the temperature of the vehicle, or the like. The data group in which a plurality of data are aggregated is, for example, image data or control history.

The core memory 33 is a storage device that is connected to the processor core 31 so as to transfer data. The core memory 33 is, for example, connected to each receiving processor core 35 so as to be able to transfer data by a plurality of communication paths 36.

The large-capacity memory 34 is a storage device having a larger storage area than the core memory 33 and a slower data access speed than the core memory 33. The large-capacity memory 34 is connected to each receiving processor core 35 so as to be able to transfer data by, for example, a plurality of communication paths 37.

Since the communication speed of the communication path 36 is internal communication of the processor 30, it is faster than the communication speed of the communication path 37 that communicates with the large-capacity memory 34. The receiving processor core 35 takes longer time to access the data of the large-capacity memory 34 than the time to access the data of the core memory 33.

The transmitting processor core 32 detects the difference data D3 based on the predetermined sensor data D2 (see FIG. 6) received from the sensor 7. The difference data D3 shows the difference between the predetermined sensor data D2 and the sensor data D1 stored in the large-capacity memory 34.

The transmitting processor core 32 stores the predetermined sensor data D2 in the large-capacity memory 34. The transmitting processor core 32 stores the address information (may be indicated as Addless in the figure) D4 of the large-capacity memory 34 in which the difference data D3 is stored in the core memory 33.

Each receiving side processor core 35 acquires the address information D4 from the core memory 33 via the plurality of communication paths 36. Each receiving side processor core 35 acquires the difference data D3 from the address information D4 of the large-capacity memory 34 via the plurality of communication paths 37.

The receiving processor core 35 generates predetermined sensor data D2 based on the difference data D3. The receiving processor core 35 performs a plurality of processes belonging to a predetermined group as an example of "a plurality of predetermined processes" based on the predetermined sensor data D2. A given group indicates that the same sensor data is used between each process.

The vehicle control device 3 shown above can pass the predetermined sensor data D2 between the processor cores 31 at a higher speed than passing the predetermined sensor data D2 via the large-capacity memory 34. As a result, the vehicle control device 3 can improve the data transfer speed between the processor cores 31. As a result, the vehicle control device 3 can suppress the difficulty in controlling the vehicle 1 as the predetermined sensor data D2 becomes larger.

The core memory 33 is allocated to the transmitting processor core 32, and each receiving processor core 35 may not be directly accessible. In this case, each receiving-side processor core 35 may access the data in the core memory 33 via the transmitting-side processor core 32.

An embodiment of the vehicle control device will be described with reference to each drawing.

FIG. 1 is an explanatory diagram of the vehicle control device 3. The vehicle control device 3 is a device that controls the vehicle 1. The vehicle control device 3 is connected to, for example, a communication device 4, another vehicle network 5, a drive device 6, a sensor 7, an output device 8, an input device 9, a notification device 10, and the like by an vehicle-mounted network 2. The in-vehicle network 2 will be described later in FIG.

The communication device 4 wirelessly communicates with an external server. The communication device 4 acquires, for example, information on the outside world from an external server. The information of the outside world is, for example, information on infrastructure, information on distance from other vehicles, and the like. The communication device 4 transmits information from the outside world to the vehicle-mounted network 2. The communication device 4 acquires information about the vehicle 1 from the vehicle-mounted network 2, for example. The communication device 4 transmits information about the vehicle 1 to an external server. The information about the vehicle 1 is, for example, the speed information of the vehicle 1.

The communication device 4 may be provided with a diagnostic terminal (OBD (On Board Diagnostics)), a wired connection terminal, a terminal for connecting an external recording medium, or the like. The external recording medium is, for example, a USB (Universal Serial Bus) memory, an SD (Secure Digital) card, or the like.

The other vehicle-mounted network 5 is composed of, for example, a protocol different from that of the vehicle-mounted network 2 or a network using the same protocol as the vehicle-mounted network 2. The drive device 6 is, for example, an actuator such as a machine that controls the vehicle 1 under the control of the vehicle-mounted network 2 or an electric device that controls the vehicle 1 under the control of the vehicle-mounted network 2. Machines that control vehicles or electrical devices that control vehicles are, for example, engines, transmissions, wheels, brakes, steering devices, and the like.

The sensor 7 is, for example, an image acquisition sensor such as a camera, a radar, a LIDAR (Laser Imaging Detection And Ranking), or an ultrasonic sensor. The sensor 7 may be a dynamical sensor or the like that recognizes the state of the vehicle 1. The state of the vehicle 1 is, for example, an exercise state or position information. The dynamical system sensor is, for example, an acceleration sensor, a wheel speed detector, GPS (Global Positioning System), or the like. The sensor 7 transmits the measured sensor data to the in-vehicle network 2.

The output device 8 acquires information from the vehicle-mounted network 2 and outputs the acquired information to the user. The output device 8 is, for example, a liquid crystal display, a warning light, a speaker, or the like.

The input device 9 is a function of receiving an operation from the user. The input device 9 transmits the operation information to the vehicle-mounted network 2. The input device 9 is, for example, a steering wheel, a pedal, a button, a lever, a touch panel, or the like.

The notification device 10 notifies the state of the vehicle 1 to the outside. The notification device 10 is, for example, a lamp, an LED (Light Emitting Diode), a speaker, or the like.

The vehicle control device 3 includes, for example, at least one processor 30 and a large-capacity memory 34.

The processor 30 includes, for example, a plurality of processor cores 31 and a core memory 33. The processor core 31 includes a transmitting side processor core 32 and a plurality of receiving side processor cores 35. The transmitting side processor core 32 includes, for example, a function of acquiring predetermined sensor data D2 (see FIG. 6) from a sensor 7 or the like, and a function of storing predetermined sensor data D2 in a large-capacity memory 34. The transmitting processor core is, for example, the processor core 31 (1).

Each receiving processor core 35 performs a plurality of processes belonging to a predetermined group based on the predetermined sensor data D2. A given group indicates that the same sensor data is used between each process. The plurality of receiving processor cores 35 are, for example, processor cores 31 (2) to 31 (m). That is, for example, the receiving side processor cores (2) to (m) perform engine control, course control, collision detection, or the like using the same predetermined sensor data.

The core memory 33 is a storage device that is connected to the processor core 31 so as to transfer data. The core memory 33 is, for example, connected to each receiving processor core 35 so as to be able to transfer data by a plurality of communication paths 36.

The large-capacity memory 34 is a storage device having a larger storage area than the core memory 33 and a slower data access speed than the core memory 33. The large-capacity memory 34 is connected to each receiving processor core 35 so as to be able to transfer data by, for example, a plurality of communication paths 37.

FIG. 2 is an explanatory diagram of the in-vehicle network 2. The vehicle-mounted network 2 includes a plurality of vehicle control devices 3, a gateway (may be referred to as GW (Gate Way) in the figure) 11, and a network link 12.

The gateway 11 connects a plurality of network links 12 and transmits / receives data to / from each network link 12.

The network link 12 connects the vehicle control device 3 on the vehicle-mounted network 2. The network link 12 is, for example, a CAN (Control Area Network) bus or the like.

The predetermined vehicle control device 3 that has acquired the sensor data from the sensor 7 transmits the sensor data to another vehicle control device 3 via the network link 12. The vehicle control device 3 that controls the drive device 6 acquires sensor data via, for example, a network link 12 or another vehicle control device 3 and controls the drive device 6.

The network topology of the vehicle-mounted network 2 is not limited to the bus type in which a plurality of vehicle control devices 3 are connected to the two network links 12, for example, a star in which the plurality of vehicle control devices 3 are directly connected to the gateway 11. A type, a link type in which vehicle control devices are connected in series and connected in a ring shape, a mixed type in which each type is mixed and composed of a plurality of networks, and the like may be used. The gateway 11 and the vehicle control device 3 may be a vehicle control device 3 having a gateway 11 function, a gateway 11 having a function of the vehicle control device 3, or the like.

FIG. 3 is a hardware configuration diagram of the vehicle control device 3. The vehicle control device 3 is, for example, a case where at least one processor 30, a large-capacity memory 34, a timer 38, a storage unit 39, and an input / output terminal (I / O (Input / Output) in the figure) are shown. There is) 40, buses 41, 42, and a bridge 43.

In the figure, "part" may be omitted. For example, the storage unit 39 may be abbreviated as "memory" in the figure.

The timer 38 is a function for managing time. The storage unit 39 is a non-volatile storage medium (ROM (Read Only Memory)) for storing programs and data. The storage unit 39 may be, for example, a non-volatile storage medium such as EEPROM (Electrically Erasable Programmable Read-Only Memory), SSD (Solid State Drive), or HDD (Hard Disk Drive). A plurality of storage units 39 may be provided in the vehicle control device 3.

The input / output terminal 40 is a function of transmitting / receiving data to / from the network link 12. The bus 41 is, for example, a communication path that connects each processor core 31, a timer 38, and an input / output terminal 40. The bus 42 is, for example, a communication path that connects the storage unit 39 and the large-capacity memory 34. The bridge 43 is a communication path connecting the bus 41 and the bus 42.

The data transfer between the processor cores 31 will be described below by taking the image data captured by the sensor 7 as an example. The data passed between the processor cores 31 is not limited to the image data acquired from the sensor 7.

FIG. 4 is an explanatory diagram of data transfer between each processor core 31. The transmitting processor core 32 passes the predetermined sensor data D2 to the receiving processor core 35 by using the core memory 33 and the large capacity memory 34.

The transmitting processor core 32 includes, for example, a processing unit 321 and a data transmission processing unit 322. The processing unit 321 acquires predetermined sensor data D2 from the sensor 7, for example.

The data transmission processing unit 322 is a function of storing data in the core memory 33 and the large-capacity memory 34. The data transmission processing unit 322 includes, for example, a difference data detection unit 323 and a data transmission unit 324.

The difference data detection unit 323 is a function of detecting the difference data D3 based on the predetermined sensor data D2. The difference data detection unit 323 acquires the predetermined sensor data D2 from the processing unit 321. The difference data detection unit 323 transmits information regarding the predetermined sensor data D2 and the difference data D2 to the data transmission unit 324. The difference data D3 will be described in detail in FIG.

The data transmission unit 324 includes a function of executing a sensor data storage process for storing the predetermined sensor data D2 in the large-capacity memory 34, and a function of storing the address information D4 in the core memory 33. The address information D4 will be described later in FIG.

The core memory 33 includes an address information storage unit 331. The address information D4 is stored in the address information storage unit 331. The large-capacity memory 34 includes a sensor data storage unit 341. Predetermined sensor data D2 is stored in the sensor data storage unit 341.

Each receiving side processor core 35 includes, for example, a difference data receiving unit 351 and a processing unit 352, respectively. The difference data receiving unit 351 is a function of acquiring predetermined sensor data D2.

The difference data receiving unit 351 acquires the address information D4 from the address information storage unit 331. The difference data receiving unit 351 acquires the difference data D3 from the sensor data storage unit 341 based on the address information D4. The difference data receiving unit 351 generates predetermined sensor data D2 based on the difference data D3. The difference data receiving unit 351 will be described later with reference to FIG. The processing unit 352 is a function of controlling the vehicle 1 based on the predetermined sensor data D2.

FIG. 5 is a flow chart of the data transmission processing unit 322. Hereinafter, the data transmission processing unit 322 will be described with reference to FIG. The data transmission processing unit 322 is executed by, for example, the processing of the difference data detection unit 323 (S11, S12) and the processing of the data transmission unit 324 (S13 to S15).

The difference data detection unit 323 acquires the predetermined sensor data D2 from the processing unit 321. The difference data detection unit 323 acquires the sensor data D1 stored in the sensor data storage unit 341. (S11). The difference data detection unit 323 compares the sensor data D1 with the predetermined sensor data D2 and detects the difference data D3 (S12).

The sensor data D1 and D2 are, for example, image data represented by pixel data arranged in five rows and five columns. The sensor data D1 and D2 are not limited to image data, but may be data showing a predetermined value. The position of the pixel data may be indicated as (X, Y) depending on the number of columns X from the left side of the image and the number of rows Y from the top of the image. For example, when showing the pixels in the fourth column and the third row, it may be shown as (4, 3).

In the pixel data of (2,2), (3,2), and (4,2), white is displayed in the sensor data D1 and black is displayed in the predetermined sensor data D2. The difference data detection unit 323 determines that, for example, the pixel data of (2,2), (3,2), and (4,2) is the difference data D3 between the sensor data D1 and the predetermined sensor data D2. To detect.

The data transmission unit 324 stores the predetermined sensor data D2 in the sensor data storage unit 341 (S13). The data transmission unit 324 detects the difference data D3 from the predetermined sensor data D2 stored in the sensor data storage unit 341. The data transmission unit 324 acquires the address information D4 in which the difference data D3 is stored (S14).

The data transmission unit 324 stores the address information D4 in the address information storage unit 331 (S15). The data transmission unit 324 is not limited to storing the address information D4 in a predetermined area of the address information storage unit 331, and may be arbitrarily stored in a storeable location.

FIG. 7 is a flow chart of the difference data receiving unit 351. The difference data receiving unit 351 may execute the processing (S21 to S27) by being called from the processing unit 352, for example.

The difference data receiving unit 351 confirms whether the address information D4 is stored in the core memory 33 (S21). When the address information D4 is saved (S21: Yes), the difference data receiving unit 351 acquires the address information D4 from the core memory 33 (S22).

The difference data receiving unit 351 determines whether another difference data receiving unit 351 has acquired the address information D4 (S23). When all the other difference data receiving units 351 acquire the address information D4 (S23: Yes), the difference data receiving unit 351 deletes the acquired address information D4 from the core memory 33 (S24). When there is another difference data receiving unit 351 for which the address information D4 has not been acquired (S23: No) and when the process (S24) is completed, the process (S25) is executed.

The difference data receiving unit 351 acquires the difference data D3 from the sensor data storage unit 341 based on the acquired address information D4 (S25). The difference data receiving unit 351 generates predetermined sensor data D2 based on the difference data D3 (S26). The difference data receiving unit 351 may generate predetermined sensor data D2 by holding the sensor data D1 in the memory of the receiving side processor core 35 and synthesizing the sensor data D1 and the difference data D3, for example. ..

The difference data receiving unit 351 transmits the predetermined sensor data D2 to the processing unit 352 (S27). The difference data receiving unit 351 ends after the process (S27) or the case where the address information D4 is not saved (S21: No).

The processing unit 352 controls the vehicle 1 based on the predetermined sensor data D2. When the address information D4 is not stored in the core memory 33 (S21: No), the processing unit 352 uses, for example, the sensor data D1 held in the memory of the receiving processor core 35 to store the vehicle 1. You may control it.

The vehicle control device 3 shown above includes the difference data detection unit 323, the data transmission unit 324, and the difference data reception unit 351 so as to pass the predetermined sensor data D2 via the large-capacity memory 34. Predetermined sensor data D2 can be passed between the processor cores 31 at high speed. As a result, the vehicle control device 3 can improve the data transfer speed between the processor cores 31. As a result, the vehicle control device 3 can suppress the difficulty in controlling the vehicle 1 as the predetermined sensor data D2 becomes larger.

When the vehicle control device is used for controlling an autonomous driving vehicle, the amount of data acquired from the sensor is increased as compared with a normal vehicle in order to grasp the external environment in detail. The vehicle control device used for automatic driving is required to be controlled within a predetermined cycle in order to ensure safety. As the amount of data acquired from the sensor increases, the data transfer time between each processor core increases, which makes it difficult for the vehicle control device to control within a predetermined cycle. Since the vehicle control device 3 can suppress an increase in the data transfer time between the processor cores, it can be used for controlling an autonomous driving vehicle.

Since this embodiment corresponds to a modified example of the first embodiment, the differences from the first embodiment will be mainly described. FIG. 8 is an explanatory diagram of data transfer between a plurality of processor cores 31a. The plurality of processor cores 31a suppress data access contention generated in the large-capacity memory 34 by the transmission destination switching unit 325. The vehicle control device 3a includes, for example, a plurality of processor cores 31a and a large-capacity memory 34. The processor core 31a includes a transmitting side processor core 32a and a plurality of receiving side processor cores 35a, and is connected to a core memory 33a.

The transmitting side processor core 32a is a function of passing predetermined sensor data D2 to each receiving side processor core 35a. The transmitting processor core 32a includes, for example, a processing unit 321 and a data transmission processing unit 322a. The data transmission processing unit 322a is a function of storing data in the core memory 33a and the large-capacity memory 34. The data transmission processing unit 322a includes, for example, a difference data detection unit 323a, a data transmission unit 324, a transmission destination switching unit 325, and a difference data transmission 326.

The difference data detection unit 323a is a function of detecting the difference data D3 based on the predetermined sensor data D2. The difference data detection unit 323a acquires the predetermined sensor data D2 from the processing unit 321. The difference data detection unit 323a acquires the sensor data D1 from the sensor data storage unit 341. The difference data detection unit 323a transmits the predetermined sensor data D2 and the difference data D3 to the transmission destination switching unit 325.

The destination switching unit 325 is a function of stopping the sensor data storage process when at least one receiving side processor core 35a receives the difference data D3 from the large-capacity memory 34. That is, the transmission destination switching unit 325 is a function of switching the storage destination of the predetermined sensor data D2 or the difference data D3 based on the reception determination storage unit 333 described later.

When at least one receiving side processor core 35a is receiving the difference data D3 from the large-capacity memory 34, the transmission destination switching unit 325 transmits the difference data D3 to the difference data transmission unit 326. When the receiving side processor core 35a finishes receiving the difference data D3, the transmission destination switching unit 325 transmits information regarding the predetermined sensor data D2 and the difference data D3 to the data transmission unit 324. The processing of the destination switching unit 325 will be described later in FIG.

The difference data transmission 326 is a function of storing the difference data D3 in the difference data storage unit 332 described later. The process of the difference data transmission 326 will be described later in FIG.

The core memory 33a is a storage device that is connected to the processor core 31a so as to exchange data. The core memory 33a includes an address information storage unit 331, a difference data storage unit 332, and a reception determination storage unit 333.

The difference data D3 is stored in the difference data storage unit 332. The reception determination storage unit 333 stores a determination value as to whether each receiving side processor core 35a is accessing the large-capacity memory 34.

Each receiving processor core 35a performs a plurality of processes belonging to a predetermined group based on the predetermined sensor data D2. Each receiving side processor core 35a includes, for example, a difference data receiving unit 351a and a processing unit 352, respectively.

The difference data receiving unit 351a is a function of acquiring predetermined sensor data D2. The difference data receiving unit 351a acquires the difference data D3 from the difference data storage unit 332.

The difference data receiving unit 351a may acquire the address information D4 from the address information storage unit 331. The difference data receiving unit 351a may acquire the difference data D3 from the sensor data storage unit 341 based on the address information D4.

The difference data receiving unit 351a generates predetermined sensor data D2 based on the difference data D3. The difference data receiving unit 351 will be described later with reference to FIG.

FIG. 9 is a flow chart of the transmission destination switching unit 325. The destination switching unit 325 acquires the predetermined sensor data D2 and the difference data D3 from the difference data detection unit 323 (S31). The destination switching unit 325 refers to the reception determination storage unit 333 (S32).

The destination switching unit 325 determines whether or not at least one receiving-side processor core 35 is accessing the large-capacity memory 34 (S33). When at least one receiving-side processor core 35 is accessing the large-capacity memory 34 (S33: Yes), the transmission destination switching unit 325 transmits the difference data D3 to the difference data transmission unit 326. When all the receiving side processor cores 35 do not access the large-capacity memory 34 (S34: No), the transmission destination switching unit 325 transmits the predetermined sensor data D2 and the difference data D3 to the data transmission unit 324. (S35). The destination switching unit 325 ends after the process (S34) or the process (S35).

FIG. 10 is a flow chart of the difference data transmission unit 326. The difference data transmission 326 acquires the difference data D3 from the transmission destination switching unit 325 (S41). The difference data transmission 326 sets the storage area of the difference data D3 in the difference data storage unit 332 (S42). The storage area of the difference data D3 will be described later in FIG. The difference data transmission unit 326 stores the difference data D3 in the set storage area.

FIG. 11 is an explanatory diagram of the difference data storage unit 332. The difference data D3 is composed of, for example, "n" pieces of data. In addition, "n" is an arbitrary constant. The first data in the difference data D3 is shown as, for example, the first data (may be referred to as Data (1) in the figure) D5. The "n" th data in the difference data D3 is shown as, for example, the nth data (may be referred to as Data (n) in the figure) D6.

The difference data transmission 326 sets, for example, the address information D7 for storing the first data D5. The difference data transmission 326 sets, for example, the address information D8 for storing the nth data D6. That is, the difference data transmission 326 sets an area for storing n pieces of data including the first data D5 to the nth data D6 between the address information D7 and the address information D8.

FIG. 12 is a flow chart of the receiving side processor core 35a. The receiving processor core 35a is executed by the processing of the processing unit 352 (S51) and the processing of the difference data receiving unit 351a (S52 to S54, S25, S26).

The processing unit 352 requests the difference data receiving unit 351a for the predetermined sensor data D2 (S51). The difference data receiving unit 351a confirms whether the difference data D3 is stored in the difference data storage unit 332 (S52). When the difference data D3 is stored in the difference data storage unit 332 (S52: Yes), the difference data receiving unit 351a acquires the difference data D3 from the difference data storage unit 332 (S53).

The difference data receiving unit 351a sets the predetermined address information of the difference data storage unit 332 as the reference destination address information, and acquires the difference data D3 stored in the address information that matches the reference destination address information. May be good. For example, the difference data receiving unit 351a sets the address information D8 as the reference destination address information and acquires the nth data D6. The difference data receiving unit 351a fluctuates the value of the reference destination address information and acquires the nth data D6 to the first data D5.

When the difference data D3 is not stored in the difference data storage unit 332 (S52: No), the difference data receiving unit 351a performs a process (S54) of acquiring the difference data D3 from the sensor data storage unit 341. The process (S54) is the process (S21 to S25) shown in FIG. 7.

The difference data receiving unit 351a generates predetermined sensor data D2 (S25) after the processing (S53) or the processing (S54). The difference data receiving unit 351a transmits the predetermined sensor data D2 to the processing unit 352 (S26).

By providing the transmission destination switching unit 325 in the vehicle control device 3a shown above, it is possible to suppress competition when each processor core 31a accesses the large-capacity memory 34. As a result, the vehicle control device 3a can prevent the data in the large capacity memory 34 from being updated by the transmitting side processor core 32a while the receiving side processor core 35a is reading the data from the large capacity memory 34.

Since this embodiment corresponds to a modified example of the first embodiment and the second embodiment, the differences from the first embodiment and the second embodiment will be mainly described. FIG. 13 is an explanatory diagram of data transfer between a plurality of processor cores 31b. The vehicle control device 3b updates the data of the sensor data storage unit 341 when the receiving side processor core 35 ends the access to the large-capacity memory 34. The vehicle control device 3b includes, for example, a plurality of processor cores 31b and a large-capacity memory 34. Each processor core 31b includes a transmitting side processor core 32b and a receiving side processor core 35, and is connected to a core memory 33b.

The transmitting processor core 32b includes, for example, a processing unit 321 and a data transmission processing unit 322b. The data transmission processing unit 322b is a function of storing data in the core memory 33 and the large-capacity memory 34. The data transmission processing unit 322b includes, for example, a difference data detection unit 323, a transmission destination switching unit 325, a data transmission unit 324, a difference data transmission 326, and a difference data reflection unit 327.

The difference data reflection unit 327 is a function of storing the difference data D3 stored in the difference data storage unit 332b in the large-capacity memory 34. The difference data reflection unit 327 will be described later with reference to FIG.

The core memory 33b is a storage unit that is connected to each processor core 31 so that data can be exchanged. The core memory 33b includes, for example, an address information storage unit 33, a difference data storage unit 332b, and a reception determination storage unit 333. The difference data D3 is stored in the difference data storage unit 332b. In the difference data storage unit 332b, the difference data D3 is read out by the difference data reflection unit 327.

FIG. 14 is a flow chart of the difference data reflecting unit 327. The difference data reflection unit 327 refers to the reception determination storage unit 333 (S61). When the receiving side processor core 35a has completed the acquisition of the difference data D3 (S61: Yes), the difference data reflection unit 327 acquires the difference data D3 from the difference data storage unit 332b (S62). The difference data reflection unit 327 transmits the difference data D3 to the data transmission unit 324 (S64).

When the receiving side processor core 35a is acquiring the difference data D3 (S61: No), the difference data reflecting unit 327 waits until the receiving side processor core 35a completes the acquisition of the difference data D3. The difference data transmission unit 324 updates the sensor data of the sensor data storage unit 341. The difference data transmission unit 324 may update the sensor data storage unit 341 by synthesizing the sensor data stored in the sensor data storage unit 341 and the difference data D3.

The vehicle control device 3b shown above includes the difference data reflecting unit 327, so that the transmitting side processor core 32b makes a difference to the difference data storage unit 332 while the plurality of receiving side processor cores 35 acquire the difference data D3. Data D3 can be saved. As a result, the plurality of receiving processor cores 35 belonging to a predetermined group can execute the process using the same sensor data.

Since this embodiment corresponds to a modified example of the first to third embodiments, the differences from the first to third embodiments will be mainly described. FIG. 15 is an explanatory diagram of data transfer between a plurality of processor cores 31c. The vehicle control device 3c includes a duplicate data storage unit 342 and stores the data received by the difference data reception unit 351c. The vehicle control device 3c includes, for example, a plurality of processor cores 31c and a large-capacity memory 34c. Each processor core 31c includes, for example, a transmitting side processor core 32b and a plurality of receiving side processor cores 35c, and is connected to a core memory 33b.

The large-capacity memory 34c is a storage unit having a storage area having a larger capacity than the core memory 33a and having a slower data access speed than the core memory 33a. The large-capacity memory 34c includes a sensor data storage unit 341 and a duplicate data storage unit 342. The duplicate data storage unit 342 stores the predetermined difference data D3 acquired by the receiving processor core 35c.

The receiving processor core 35c is a function of executing a plurality of processes belonging to a predetermined group based on predetermined sensor data. Each receiving side processor core 35c includes, for example, a difference data receiving unit 351c and a processing unit 352, respectively. The processing unit 352 is a function of performing a predetermined process based on the sensor data stored in the stored data area.

The difference data receiving unit 351c is a function of acquiring predetermined sensor data D2. The difference data receiving unit 351c acquires the address information D4 from the address information storage unit 331. The difference data receiving unit 351c acquires the difference data D3 from the sensor data storage unit 341 based on the address information D4. The difference data receiving unit 351c stores the difference data D3 in the duplicate data storage unit 342.

FIG. 16 is a flow chart of the receiving processor core 35c. The receiving processor core 35c is executed by, for example, the processing of the processing unit 352 (S51) and the difference data receiving unit 351c (S71 to S74, S25, S26).

The processing unit 352 requests the predetermined sensor data D2 from the difference data receiving unit 351c (S51). The difference data receiving unit 351c confirms whether the difference data D3 is stored in the duplicate data storage unit 342 (S71). When the duplicate data storage unit 342 does not have the difference data D3 (S71: Yes), the difference data reception unit 351c starts the reception process (S72) of the difference data D3. The reception process (S72) of the difference data D3 is, for example, the processes (S52) to the processes (S54) shown in FIG. The difference data receiving unit 351c stores the difference data D3 in the duplicate data storage unit 342 (S73).

When the duplicate data storage unit 342 has the difference data D3 (S72: No), the difference data receiving unit 351c acquires the difference data D3 from the duplicate data storage unit 342 (S74). After the processing (S73) or the processing (S74) is completed, the difference data receiving unit 351c generates predetermined sensor data D2 based on the difference data D3 (S25), and transmits the predetermined sensor data D2 to the processing unit 352 (). S26).

By providing the duplicate data storage unit 342, the vehicle control device 3c shown above can control the vehicle using the same sensor data between the receiving side processor cores 35c. As a result, the consistency of the predetermined sensor data D2 used between the receiving side processor cores 35c can be ensured.

If an error or the like occurs during the processing of the predetermined receiving side processor core 35c, the predetermined receiving side processor core 35c recovers from the error and acquires the difference data D3 again. By updating the sensor data of the sensor data transmission unit 341 during the restoration, the consistency of the predetermined sensor data D2 used between the receiving side processor cores 35c is lost.

The duplicate data storage unit 342 stores the difference data D3 acquired by the receiving processor core 35c. As a result, the predetermined receiving side processor core 35c after recovery acquires the difference data D3 from the duplicate data storage unit 342, thereby ensuring the consistency of the predetermined sensor data D2 used between the respective receiving side processor cores 35c. be able to.

Since this embodiment corresponds to a modified example of the first embodiment, the differences from the first embodiment will be mainly described. FIG. 17 is an explanatory diagram of data transfer between a plurality of processor cores 31d. The vehicle control device 3d includes a completion notification unit 328, and notifies each receiving side processor core 35d of the completion of writing the predetermined sensor data D2. The vehicle control device 3d includes, for example, a plurality of processor cores 31d and a large-capacity memory 34. Each processor core 31d includes, for example, a transmitting processor core 32d and a plurality of receiving processor cores 35d, and is connected to a core memory 33.

The transmitting processor core 32d is a function of sending predetermined sensor data D3 to the receiving processor core 35d. The transmitting processor core 32d executes an initialization process after the vehicle control unit 3d is activated. The initialization process is, for example, a process of acquiring sensor data from the sensor 7 and storing the sensor data in a large-capacity memory 34 in which the sensor data is not stored.

The transmitting processor core 32d includes, for example, a processing unit 321 and a data transmission processing unit 322d. The data transmission processing unit 322d is a function of storing data in the core memory 33 and the large-capacity memory 34.

The data transmission processing unit 322d includes, for example, a difference data detection unit 323, a data transmission unit 324, and a completion notification unit 328. The completion notification unit 328 transmits a notification that the predetermined sensor data storage process has been completed to each receiving processor core 35d.

The receiving processor core 35d is a function of executing a plurality of processes belonging to a predetermined group based on predetermined sensor data. The receiving processor core 35d includes, for example, a difference data receiving unit 351d and a processing unit 352.

The difference data receiving unit 351d is a function of acquiring predetermined sensor data D2. The difference data receiving unit 351d acquires the address information D4 from the address information storage unit 331. The difference data receiving unit 351d acquires the difference data D3 from the sensor data storage unit 341 based on the address information D4.

After the vehicle control device 3d is activated, the difference data receiving unit 351d stands by. The difference data receiving unit 351d starts the process of receiving the difference data D3 by the notification from the completion notification unit 328.

Hereinafter, the processing of the transmitting side processor core 32d will be described by taking the initialization processing of the vehicle control device 3d as an example. The transmitting processor core 32d is not limited to the initialization process, and may be used for normal processing.

FIG. 18 is a flow chart of the transmitting processor core 32d. The processing of the transmission side processor core 32d is executed by the processing of the processing unit 321 (S81), the processing of the difference data detection unit 323 (S82), and the processing of the data transmission unit 324d (S83 to S84).

The processing unit 321 acquires initial data from the sensor 7 (S81). The initial data is, for example, image data taken by the sensor 7. The processing unit 321 transmits the initial data to the difference data detection unit 323.

The difference data detection unit 323 transmits the initial data to the data transmission unit 324. The data transmission unit 324 stores the initial data in the sensor data storage unit 341 (S82). The completion notification unit 328 determines whether or not the data transmission unit 324 has completed saving the initial data in the sensor data storage unit 341 (S83). When the saving is completed (S83: Yes), the completion notification unit 328 transmits the saving completion notification to the receiving processor core 35d. If the data is being saved (S83: No), the completion notification unit 328 waits until the data transmission unit 324 completes the storage (S83).

By providing the completion notification unit 328, the vehicle control device 3d shown above can suppress the receiving side processor core 35 from performing the difference data receiving process while storing the predetermined sensor data D2.

By activating the receiving processor core 35d after the notification of the completion notification unit 328, the receiving processor core 35d accesses the sensor data storage unit 341 when the sensor data is not stored in the sensor data storage unit 341. It can be suppressed.

Since this embodiment corresponds to a modified example of the first to fourth embodiments, the differences from the first to fourth embodiments will be mainly described. FIG. 19 is an explanatory diagram of data transfer between a plurality of processor cores 31e. The vehicle control device 3e includes a reception request unit 329, and can request the reading of the difference data D3 from the transmission side processor core 32 to the reception side processor core 35. The vehicle control device 3e includes, for example, a plurality of processor cores 31e and a large-capacity memory 34c. Each processor core 31e includes a transmitting side processor core 32e and a receiving side processor core 35e, and is connected to a core memory 33b.

The transmitting side processor core 32e is a function of sending predetermined sensor data D2 to the receiving side processor core 35e. The transmitting processor core 32e includes, for example, a processing unit 321 and a data transmission processing unit 322e. The data transmission processing unit 322e is a function of storing data in the large-capacity memory 34 and the core memory 33. The data transmission processing unit 322e includes, for example, a difference data detection unit 323, a data transmission unit 324, a transmission destination switching unit 325, a difference data transmission unit 326, a difference data reflection unit 327, and a reception request unit 329.

The reception request unit 329 is a function of starting the difference data D3 acquisition process of the difference data reception unit 351e described later. The reception request unit 329 observes the progress of data transmission of the data transmission unit 324, and starts the processing of the difference data reception unit 351e in a predetermined case.

Each receiving-side processor core 35e acquires predetermined sensor data D2 and executes a plurality of processes belonging to a predetermined group. Each receiving side processor core 35e includes, for example, a difference data receiving unit 351e and a processing unit 352, respectively.

The difference data receiving unit 351e is a function of acquiring the difference data D3. The difference data receiving unit 351e is started by the receiving requesting unit 329. The difference data receiving unit 351e acquires the address information D4 from the address information storage unit 331.

The difference data receiving unit 351e acquires the difference data D3 from the sensor data storage unit 341 based on the address information storage unit 331. The difference data receiving unit 351e is not limited to starting the processing by the reception requesting unit 329, and may be started by the processing unit 351.

The reception request unit 329 may transmit the difference data acquisition range of the sensor data storage unit 341 to the difference data reception unit 351e. The difference data acquisition range is, for example, the range in which the transmitting processor core 32 has finished saving the sensor data. Even if the receiving side processor core 35 accesses the difference data acquisition range, the receiving side processor core 35 avoids the data race with the transmitting side processor core 32. In this case, the difference data receiving unit 351e acquires the difference data D3 from the sensor data in the difference data acquisition range.

By including the reception request unit 329, the vehicle control device 3e shown above can start the difference data D3 acquisition process of the difference data reception unit 351e even during the sensor data storage process. As a result, even if the sensor data storage process of the data transmission unit 324 takes time, the difference data D3 acquisition process can be performed in parallel.

A computer program for operating a computer as a vehicle control device has a function of detecting difference data indicating a difference between predetermined sensor data received from a sensor and sensor data stored in a large-capacity memory on the computer. By passing the address information of the large-capacity memory in which the difference data is stored between multiple processor cores via the core memory, multiple data can be passed at a higher speed than passing predetermined sensor data via the large-capacity memory. A function of passing predetermined sensor data between the processor cores of the above and a function of performing a plurality of processes belonging to a predetermined group based on the predetermined sensor data are realized.

The present invention is not limited to the above-described embodiment, and includes various modifications. The above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations. It is also possible to replace a part of the configuration of one embodiment with the configuration of another embodiment. It is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, other configurations can be added / deleted / replaced with respect to a part of the configurations of each embodiment.

Each of the above configurations, functions, processing units, processing means, and the like may be realized by hardware, for example, by designing a part or all of them with an integrated circuit. Further, each of the above configurations, functions, and the like may be realized by software by the processor interpreting and executing a program that realizes each function. Information such as programs, tables, and files that realize each function is stored in memory, hard disk, recording device such as SSD (Solid State Drive), IC (Integrated Circuit) card, SD (Secure Digital) card, DVD (Digital Versail Disc). It can be stored in a recording medium such as.

Further, the technical features included in the above-described embodiment are not limited to the combinations specified in the claims, and can be appropriately combined. The communication method between the transmitting processor core and the receiving processor core does not prevent the application to other than the vehicle system.

1 ... Vehicle, 2 ... In-vehicle network, 3 ... Vehicle control device, 4 ... Communication device, 5 ... In-vehicle network, 6 ... Drive device, 7 ... Sensor, 8 ... ... Output device, 9 ... Input device, 10 ... Notification device, 30 ... Processor, 31 ... Processor core, 32 ... Transmitter processor core, 33 ... Core memory, 34.・ ・ Large-capacity memory, 35 ・ ・ ・ Receiving processor core, 36 ・ ・ ・ Communication path, 37 ・ ・ ・ Communication path

Claims (8)

A vehicle control device equipped with a processor that controls a vehicle.
The processor
With multiple processor cores
A core memory that is connected to the processor core so that data can be exchanged,
With
Further, the vehicle control device includes a large-capacity memory having a larger storage area than the core memory and a slower access speed to data than the core memory.
The plurality of processor cores
A function to detect the difference data indicating the difference between the predetermined sensor data received from the sensor and the sensor data stored in the large-capacity memory, and
It has a function of passing the predetermined sensor data by passing the address information of the large-capacity memory in which the difference data is stored between the plurality of processor cores via the core memory.
A vehicle control device in which a plurality of predetermined processor cores that acquire the predetermined sensor data perform a plurality of predetermined processes based on the predetermined sensor data. Further, the plurality of processor cores
A transmitting processor core including a processing unit that acquires the predetermined sensor data from the sensor, and a data transmission processing unit that passes data to the large-capacity memory and the core memory.
A plurality of receiving processor cores that acquire the predetermined sensor data and perform the predetermined plurality of processes,
With
The data transmission processing unit
The difference data detection unit that detects the difference data and
A data transmission unit having a function of storing the predetermined sensor data in the large-capacity memory and a function of storing the address information in the core memory.
When at least one receiving processor core receives the difference data from the large-capacity memory, it includes a transmission destination switching unit that stops the sensor data storage process.
The plurality of receiving side processor cores include a difference data receiving unit that acquires the difference data from the large-capacity memory based on the address information and generates the predetermined sensor data based on the difference data. The vehicle control device described in. The vehicle control device according to claim 1, wherein the sensor data is image data captured by the sensor. Further, the core memory includes a difference data storage unit for storing the difference data.
The vehicle control according to claim 2, wherein the destination switching unit stores the difference data in the difference data storage unit when at least one receiving processor core receives the difference data from the large-capacity memory. apparatus. Further, the transmitting processor core is
The vehicle control device according to claim 4, further comprising a difference data reflecting unit that stores the difference data stored in the difference data storage unit in the large-capacity memory. The large-capacity memory includes a duplicate data storage unit that stores a predetermined difference data acquired by the difference data reception unit.
Further, the difference data receiving unit is
A function of acquiring the predetermined difference data from the duplicate data storage unit, and
The vehicle control device according to claim 2, further comprising a function of generating the predetermined sensor data based on the predetermined difference data. Further, the data transmission processing unit includes a completion notification unit that determines whether the sensor data storage processing has been completed and executes the difference data receiving unit.
The vehicle control device according to claim 2, wherein the difference data receiving unit waits until execution is started by the completion notification unit. The vehicle control device according to claim 2, wherein the data transmission processing unit includes a reception requesting unit that observes the progress of the sensor data storage processing and executes the difference data receiving unit.

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