JP2020173605A - Clock distribution circuit and clock distribution method, and error rate measuring device and error rate measuring method - Google Patents

Abstract

To eliminate complexity of setting to improve usability.SOLUTION: A clock distribution circuit 12 has a plurality of clock routes R1, R2, R3 with high-frequency devices 12c provided respectively for operation frequency ranges having different band widths. In the clock distribution circuit, the operation frequency ranges with same frequency magnification as input clock frequency ranges corresponding to one-to-one a plurality of bit rate ranges consisting of different ranges are integrated. When the input clock frequency range corresponding to the bit rate range set from the plurality of bit rate ranges is within the operation frequency range, the clock distribution circuit selectively switches the clock route to the clock route corresponding to the input clock frequency range, and outputs clock obtained by correcting the high-frequency device 12c according to the set bit rate range.SELECTED DRAWING: Figure 1

Description

The present invention has a plurality of clock routes equipped with high-frequency devices such as a band variable filter and a gain variable amplifier for each internal operating frequency range having different bands, and switches the clock route according to the internal operating frequency range to obtain a bit rate. The present invention relates to a clock distribution circuit and a clock distribution method that output a clock corrected for a high-frequency device according to the frequency, an error rate measuring device and an error rate measuring method for measuring an error rate of a measured object using the clock distribution circuit and the clock distribution method. ..

For example, as disclosed in Patent Document 1 below, the error rate measuring device transmits a test signal of a known pattern including fixed data to the object to be measured, and receives the test signal back from the object to be measured as the test signal is transmitted. It has been conventionally known as a device for measuring a bit error rate (BER) by comparing a measured signal and a reference reference signal in bit units.

By the way, in recent years, there has been a demand for error rate measurement at a higher bit rate, and the operating clock of the error rate measuring device is becoming higher in frequency. As a result, high-frequency devices such as band-variable filters and gain-variable amplifiers used inside the error rate measuring device are also required to support higher frequencies.

Japanese Unexamined Patent Publication No. 2007-274474

However, high-frequency devices have restrictions on the operating frequency band, and it is difficult for one high-frequency device to cover a wide band from several hundred MHz to several tens of GHz. Therefore, in the clock distribution circuit in the error rate measuring device, a plurality of clock routes having different bands are provided by using a plurality of high frequency devices. Then, when a bit rate range is selected from the pull-down menu on the clock setting screen 51 of FIG. 7, one clock route according to the input clock frequency range corresponding to the selected bit rate range on a one-to-one basis is a plurality of clocks. It is designed to be selected from the routes.

Further, as shown in FIG. 7A, on the conventional clock setting screen 51, the bit rate range option (Operation Bit Rate) 51a displayed in the pull-down menu and the input clock frequency range instruction (Input Clock Freq) are further described. ) 51b is displayed as a one-to-one correspondence setting item. Specifically, as shown in FIG. 6, the bit rate range selection and the input clock frequency range indication are "2.4-32.1 [Gbit / s]" and "1.2-16.05 (. 1/2 Clock) [GHz] ”(clock setting screen 51 in FIG. 7 (a)),“ 32.1-40 [Gbit / s] ”and“ 8.025-10 (1/4 Clock) [GHz] ”( Clock setting screen 51) in FIG. 7B, "40-64.2 [Gbit / s]" and "10-16.05 (1/4 Clock) [GHz]" (clock setting screen in FIG. 7C). 51) have a one-to-one correspondence with each other.

Then, on the conventional clock setting screen 51, when the bit rate range option (Operation Bit Rate) is selected from the pull-down menu, the input clock frequency range instruction (Input Clock Freq) corresponding to the selected bit rate range option is displayed. Will be done. For example, if "2.4-32.1 [Gbit / s]" is selected from the pull-down menu as a bit rate range option, "1.2-16.05 (1 / 2Lock) [GHz]" is the input clock frequency range. It is set as an instruction of.

Then, when controlling the clock route, as shown in FIG. 8, the bit rate range is selected on the clock setting screen described above (ST11). When the bit rate range is selected, one clock route with a clock frequency corresponding to this bit rate range on a one-to-one basis is set (ST12), and a correction value of a high-frequency device for indefinite frequency is temporarily set (ST13). ).

After that, synchronization processing is performed at predetermined cycles (for example, 100 ms intervals) (ST14), the input clock frequency range is acquired from the clock counter (ST15), and it is determined whether or not the acquired input clock frequency range is within the operating frequency range. (ST16).

Then, if the input clock frequency range is within the operating frequency range (ST16-Yes), the correction value according to the frequency is set to correct the high frequency device (ST17), and the process returns to the synchronization process of a predetermined cycle (ST14). On the other hand, if the input clock frequency range is not indefinite or within the operating frequency range (ST16-No), the correction value for indefinite frequency is reset (ST18), and the process returns to the synchronization process of a predetermined cycle (ST14).

As described above, conventionally, the user has been required to control the clock route by selecting from the bit rate range options according to the bit rate to be measured. However, since the error rate measuring device expands the bit rate range in response to the recent increase in bit rate, the choices of the bit rate range and the clock route on the clock setting screen increase. And as the number of bit rate range choices and clock routes increases, the user has to select a preferred bit rate range from a large number of bit rate ranges so that the optimum clock route is controlled, which complicates the operation. There was a problem. Further, when the optimum clock route cannot be controlled due to a mistake in selecting the bit rate range, normal measurement cannot be performed, and there is a problem that it takes time and effort for the user to investigate the cause.

Therefore, the present invention has been made in view of the above problems, and a clock distribution circuit, a clock distribution method, an error rate measuring device, and an error rate measurement capable of eliminating the complexity of setting and improving usability. It is intended to provide a method.

In order to achieve the above object, the clock distribution circuit according to claim 1 according to the present invention has a plurality of clock routes R1, R2, R3 provided with high frequency devices 12c for operating frequency ranges having different bands. A clock distribution circuit in which the operating frequency range having the same frequency magnification as the input clock frequency range corresponding to one-to-one correspondence with a plurality of bit rate ranges consisting of different ranges is integrated.
When the input clock frequency range corresponding to the bit rate range set from the plurality of bit rate ranges is within the operating frequency range, the clock route corresponding to the input clock frequency range is selectively switched and set. It is characterized by outputting a clock corrected for the high frequency device according to a bit rate range.

The clock distribution method according to claim 2 has a plurality of clock routes R1, R2, R3 having a high frequency device 12c for each operating frequency range having a different band, and has a plurality of bit rate ranges including different ranges and 1 It is a clock distribution method using a clock distribution circuit in which the operating frequency range having the same frequency magnification as the input clock frequency range corresponding to one-to-one is integrated.
When the input clock frequency range corresponding to the bit rate range set from the plurality of bit rate ranges is within the operating frequency range, the clock route corresponding to the input clock frequency range is selectively switched and set. It is characterized by including a step of outputting a clock corrected for the high frequency device according to a bit rate range.

The error rate measuring device according to claim 3 inputs a test signal of a known pattern from the pulse pattern generator 4 to the object W to be measured, and receives input data from the object to be measured in connection with the input of the test signal. In the error rate measuring device for measuring the bit error rate of the above with the error rate measuring device 5.
The clock signal output by the clock distribution circuit of claim 1 is input to the pulse pattern generator or the error rate measuring device as a timing signal.

In the error rate measuring method according to claim 4, a test signal of a known pattern is input from the pulse pattern generator 4 to the object to be measured W, and input data received from the object to be measured in association with the input of the test signal. In the error rate measuring method for measuring the bit error rate of the above with the error rate measuring device 5.
It is characterized by including a step of inputting a clock signal output by the clock distribution method of claim 2 into the pulse pattern generator or the error rate measuring device as a timing signal.

The error rate measuring device according to claim 5 is the error rate measuring device according to claim 3.
The clock setting screen 2a for selecting and setting one bit rate range with the plurality of bit rate ranges as options is displayed and controlled.

The error rate measuring method according to claim 6 is the error rate measuring method according to claim 4.
It is characterized by including a step of displaying and controlling a clock setting screen 2a for selecting and setting one bit rate range with a plurality of bit rate ranges as options.

According to the present invention, automatic switching control can be performed internally so as to select the optimum clock route from a plurality of clock routes, measurement troubles caused by selection of the clock route can be prevented, and usability is improved. ..

It is a figure which shows an example of the clock distribution circuit which concerns on this invention. It is a figure which shows the schematic structure of the error rate measuring apparatus including the clock distribution circuit which concerns on this invention. It is a figure which shows the display example of (a), (b) clock setting screen. It is a figure which shows the relationship of the bit rate range selection of a clock setting screen, the instruction of an input clock frequency range, and the internal operation frequency range. It is a flowchart of the control method of the clock route which concerns on this invention. It is a comparative figure which shows the relationship between the present invention and the choice of the bit rate range of the conventional clock setting screen, and the indication of an input clock frequency range. It is a figure which shows the display example of the conventional clock setting screen. It is a flowchart of the control method of the conventional clock route.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the attached drawings.

As shown in FIG. 2, the error rate measuring device 1 of the present embodiment includes an operation display 2, a clock generator 3, a pulse pattern generator 4, an error rate measuring device 5, a storage unit 6, and a control unit 7. Is roughly configured. The configuration of each part will be described below.

[Operation indicator]
The operation display 2 includes, for example, a pointing device such as a mouse or a touch screen for operating a pointer or an icon on the display screen of the display, keys, switches, buttons, etc. provided on the main body of the device.

The operation display 2 is a setting for controlling the clock route, which will be described later, an instruction to start or stop measurement of the object W to be measured, a specification of a measurement channel, a setting / change / reference of a measurement parameter, and the like. Perform operations related to various measurements including error rate measurement.

The operation display 2 displays the clock setting screen 2a shown in FIG. 3 as a setting screen for controlling the clock route described later. The clock setting screen 2a of FIG. 3 shows a display example when the measurement is performed by the error rate measuring device 1 for half-rate operation. For example, the Clock Source (2a1), the Bit Rate (2a2), and the Output Lock Rate (2a3). ), Operation Bit Rate (2a4), and Input Clock Freq (2a5) are displayed as setting items.

Among the above-mentioned setting items, the Operation Bit Rate (2a4) is set by selecting a plurality of bit rate ranges consisting of different ranges from the pull-down menu and selecting one bit rate range. In addition, Input Clock Freq (2a5) is an instruction of the input clock frequency range, and when one bit rate range is selected and set, the input clock frequency range corresponding to the set bit rate range on a one-to-one basis is automatically set. Is displayed.

FIG. 3A shows the bit rate range “2.40-32.10 [2.40-32.10] when “2.40-32.10 [Gbit / s]” is selected from the pull-down menu and set to the bit rate range. It has a one-to-one correspondence with "Gbit / s]" and shows a state in which the input clock frequency range "1.200-16.050 GHz (1/2 Lock)", which is 1/2 times the bit rate range, is automatically displayed. ing. Further, FIG. 3B shows the bit rate range “32.10-64.” When “32.10-64.20 [Gbit / s]” is selected from the pull-down menu and set to the bit rate range. There is a one-to-one correspondence with "20 [Gbit / s]", and the input clock frequency range "8.025-16.050 GHz (1/4 Lock)", which is 1/4 times the bit rate range, is automatically displayed. Is shown.

Here, FIG. 4 shows the relationship between the selection of the bit rate range of the clock setting screen 2a, the instruction of the input clock frequency range, and the internal operating frequency range (hereinafter, also referred to as the operating frequency range).

As shown in FIG. 4, there is a one-to-one correspondence between a plurality of bit rate range choices and input clock frequency range indications, and the input clock frequency range has a different frequency magnification (1/2, It consists of a plurality of ranges of 1/4). Further, the operating frequency range is associated with the input clock frequency range by integrating the same frequency magnification as the input clock frequency range. Specifically, in the example of FIG. 4, the operating frequency range “8.025-10 [GHz]” and “10-16.05 [GHz]” are integrated to form the input clock frequency range “8.025-16. It is associated with "05 (1/4 Clock) [GHz]".

The operation display 2 may have an input operation function and a display function independent of each other. In this case, a plurality of keys, switches, etc. that accept input operations such as settings and instructions may be provided for the input operation function, and a liquid crystal display or the like may be provided for the display function.

[Clock generator]
The clock generator 3 generates a clock having a reference frequency for inputting to the pulse pattern generator 4.

[Pulse pattern generator]
The pulse pattern generator 4 generates a pulse pattern signal input to the object W as a test signal, and is a clock input unit 11, a clock distribution circuit 12, a signal generation unit 13, a clock output unit 14, and a PPG clock count. A unit 15 is provided.

The clock input unit 11 is connected to the clock generator 3, receives the clock generated by the clock generator 3 as an input, and transmits the clock in the input clock frequency range acquired from the PPG clock count unit 15 by the control unit 7 to the clock distribution circuit 12. Output.

[Clock distribution circuit]
As shown in FIG. 1, the clock distribution circuit 12 has a plurality of clock routes (route 1: R1, route 2: R2, route 3: R3 in FIG. 1) provided with high-frequency devices 12c for operating frequency ranges having different bands. The clock route is switched according to the operating frequency range, and the clock corrected for the high frequency device 12c according to the bit rate is output.

As shown in FIG. 1, the clock distribution circuit 12 includes a circuit including a switch 12a, a multiplier 12b, and a high-frequency device 12c.

The switch 12a includes a first switch 12a1, a second switch 12a2, a third switch 12a3, and a fourth switch 12a4, and routes 1: R1 and route in FIG. 1 according to the bit rate range selected and set on the clock setting screen 2a. Switching control is performed by the control unit 7 so as to switch from 2: R2 and route 3: R3 to one clock route.

As shown in FIG. 1, in the switch 12a, the first switch 12a1 is connected to the input side, the second switch 12a2 is connected to the output side, and one output of the first switch 12a1 and one input of the second switch 12a2 are connected. Route 1: R1 is formed between and.

Further, the third switch 12a3 is connected to the other output of the first switch 12a1, and the fourth switch 12a4 is connected to the other input of the second switch 12a2. Then, a route 2: R2 is formed between one output of the third switch 12a3 and one input of the fourth switch 12a4, and the other output of the third switch 12a3 and the other input of the fourth switch 12a4 The space forms Route 3: R3.

The multiplier 12b multiplies the frequency of the input clock signal. In the example of FIG. 1, multipliers (frequency 2 multipliers) 12b1 and 12b2 are connected to the rear stage of the third switch 12a2 on the route 2: R2 and the rear stage of the third switch 12a3 on the route 3: R3, respectively.

The high frequency device 12c is composed of, for example, a band variable filter and a gain variable amplifier. In the example of FIG. 1, the gain variable amplifier 12c1 is connected between the first switch 12a1 and the second switch 12a2 in route 1: R1. Further, the band variable filter 12c2 and the gain variable amplifier 12c3 are connected in order to the subsequent stage of the multiplier 12b1 between the third switch 12a3 and the fourth switch 12a4 in the route 2: R2. Further, the band variable filter 12c4 and the gain variable amplifier 12c5 are sequentially connected to the subsequent stage of the multiplier 12b2 between the third switch 12a3 and the fourth switch 12a4 in the route 3: R3.

In this embodiment, it is defined that the default clock route is temporarily set for each bit rate range option on the clock setting screen 2a of the operation display 2. In the clock distribution circuit 12 of FIG. 1, for example, when "2.4-32.1 [Gbit / s]" is selected and set as an option of the bit rate range, route 1: R1 is temporarily set. Further, when "32.1-64.2 [Gbit / s]" is selected and set as a bit rate range option, route 2: R2 is temporarily set.

The signal generation unit 13 generates a desired pulse pattern signal using the clock divided or multiplied by the clock distribution circuit 12 as a timing signal. The pulse pattern signal generated by the signal generation unit 13 is input to the object W to be measured as a test signal of a known pattern when performing various measurements.

The clock output unit 14 outputs a clock divided or multiplied by the clock distribution circuit 12.

The PPG clock counting unit 15 is composed of a frequency counter, measures the clock frequency of the clock divided or multiplied by the clock distribution circuit 12, and outputs the measured clock frequency to the control unit 7.

[Error rate measuring instrument]
The error rate measuring device 5 measures the error rate, and includes a clock input unit 21, a signal receiving unit 22, a clock reproducing unit 23, a frequency dividing / multiplying unit 24, and an ED clock counting unit 25.

The clock input unit 21 receives the clock output from the clock output unit 14 of the pulse pattern generator 4 as an input, and divides / multiplies the clock in the input clock frequency range acquired by the control unit 7 from the ED clock count unit 25. Output to.

The signal receiving unit 22 uses the clock divided or multiplied by the frequency dividing / multiplying unit 24 as a timing signal, and accompanies the input of the test signal from the signal generating unit 13 of the pulse pattern generator 4 to the object W to be measured. The signal returned from the object W to be measured is received.

The clock reproduction unit 23 reproduces the clock from the signal received by the signal reception unit 22.

The frequency dividing / multiplying unit 24 divides or multiplies the clock from the clock input unit 21 or the clock reproduction unit 23 under the control of the control unit 7.

The ED clock count unit 25 is composed of a frequency counter, and the frequency division / multiplication unit 24 measures the clock frequency of the clock to be divided or multiplied, and outputs the measured clock frequency to the control unit 7.

[Memory]
As information for correcting the high frequency device 12c, the storage unit 6 includes a voltage table and a band variable filter 12c2 corresponding to the gains of the gain variable amplifiers 12c1, 12c3, 12c5 of the high frequency device 12c for each predetermined step according to the bit rate. Stores information on the center frequency of 12c4. Further, the storage unit 17 stores various information necessary for measuring the error rate of the object to be measured W.

[Control unit]
The control unit 7 performs switching control of the clock route (route 1: R1, route 2: R2, route 3: R3) and correction of the high frequency device in order to execute the control process of the clock route of FIG. 5 described later. That is, the control unit 7 switches 12a (12a1) so as to switch from route 1: R1, route 2: R2, and route 3: R3 in FIG. 1 to one clock route according to the bit rate range selected on the clock setting screen. , 12a2, 12a3, 12a4) are switched and controlled.

Further, the control unit 7 acquires an input clock frequency range from the PPG clock count unit 15 by synchronous processing of a predetermined cycle (for example, 100 ms interval), and determines whether or not the acquired input clock frequency range is within the operating frequency range. When it is determined that the input clock frequency range is within the operating frequency range, the high frequency device 12c of the clock route (either route 1: R1, route 2: R2, route 3: R3) at that time is stored in the storage unit 6. Make corrections based on the information provided.

Further, when the control unit 7 inputs the pulse pattern signal generated by the signal generation unit 13 of the pulse pattern generator 4 to the object W as a test signal of a known pattern, the control unit 7 is measured in accordance with the input of the test signal. The bit error rate (BER) of the input data received by the signal receiving unit 22 of the error rate measuring device 5 is measured from the object W.

Further, the control unit 7 sets the operation display 2 and the pulse pattern when performing various measurements including the bit error rate (BER) by using a communication device or device corresponding to a high bit rate defined by the communication standard as the object W to be measured. The generator 4 and the error rate measuring device 4 are collectively controlled.

By the way, in the error rate measuring device 1 of FIG. 2 described above, the case where the clock distribution circuit 12 of FIG. 1 is adopted for the pulse pattern generator 4 has been described, but the same applies to the frequency dividing / multiplying unit 24 of the error rate measuring device 5. A clock distribution circuit based on the above idea can be adopted.

Next, a method of controlling the clock route of the clock distribution circuit 12 of the error rate measuring device 1 configured as described above will be described with reference to FIG.

When controlling the clock route, one bit rate range is selected and set from a plurality of bit rate ranges on the clock setting screens 2a of FIGS. 3A and 3B (ST1). For example, as shown in FIG. 3 (b), "32.10-64.20 [Gbit / s]" is selected and set as the bit rate range from the pull-down menu of the Operation Bit Rate.

Next, the control unit 7 temporarily sets the default clock route (ST2). For example, when "32.10-64.20 [Gbit / s]" is selected and set as the bit rate range, route 2: R2 in FIG. 1 is temporarily set as the default clock route.

Next, the control unit 7 temporarily sets the correction value of the high-frequency device 12c for when the frequency is indefinite (ST3). That is, the correction value of the high frequency device 12c when the input clock frequency range is not within the operating frequency range is temporarily set.

After that, the control unit 7 performs synchronous processing at a predetermined cycle (for example, 100 ms interval) (ST4), acquires an input clock frequency range from the clock counter (PPG clock count unit 15) (ST5), and acquires the input clock frequency range. Determines if is within the operating frequency range (ST6).

Then, when it is determined that the input clock frequency range is within the operating frequency range (ST6-Yes), the optimum clock route according to the input clock frequency range is set (ST7). For example, if it is determined that the input clock frequency range is within the operating frequency range "10-16.05 [GHz]", the clock route corresponding to the input clock frequency range within "10-16.05 [GHz]" is used. Route 3: The switch 12a of the clock distribution circuit 12 is switched and controlled so as to be set to R3.

Then, a correction value corresponding to the input clock frequency range is set to correct the high frequency device 12c (ST8), and the process returns to the synchronization process of a predetermined cycle (ST4). For example, when route 3: R3 is set, the correction value corresponding to the input clock frequency range is read out from the storage unit 6 and set to correct the band variable filter 12c4 and the gain variable amplifier 12c5 of the high frequency device 12c.

On the other hand, if it is determined that the input clock frequency range is indefinite or not within the operating frequency range (ST6-No), the default clock route is reset (ST9).

Then, the correction value of the high-frequency device 12c for indefinite frequency is reset (ST10), and the process returns to the synchronization process of a predetermined cycle (ST4).

As described above, according to the present embodiment, one bit rate range is selected and set from a plurality of different bit rate ranges on the clock setting screen 2a, and a plurality of clock routes (route 2: R2, route 3: R3) are selected and set. When the integrated bit rate range is set, the input clock frequency range acquired from the frequency counter (PPG clock count unit 15) is within the operating frequency range of each route (route 2: R2, route 3: R3). Internally, automatic switching control can be performed so as to select the optimum clock route from a plurality of clock routes (route 2: R2, route 3: R3) based on whether or not. Moreover, since the optimum clock route is surely selected within the same frequency magnification, measurement troubles caused by the selection of the clock route can be prevented, and usability is improved.

In addition, the operating frequency range having the same frequency magnification as the input clock frequency range is integrated and associated with the input clock frequency range, and the bit rate range corresponding to the input clock frequency range for each different frequency magnification on a one-to-one basis is set on the clock setting screen 2a. Since it is displayed as options on the top, the number of options on the clock setting screen 2a can be reduced, and the complexity of the user's setting can be eliminated.

Further, when one bit rate range is selected and set from a plurality of bit rate ranges and the clock route is automatically switched, the internal switching point (for example, 40 [Gbit / s] in FIG. 6) is not shown to the user. It also has the secondary effect of finishing. Moreover, since a wide range of bit rates can be measured by setting one clock route, it is possible to reduce the trouble of switching the clock route setting in the test of the object to be measured with a variable bit rate.

The best modes of the clock distribution circuit, the clock distribution method, the error rate measuring device, and the error rate measuring method according to the present invention have been described above, but the description and drawings in this form do not limit the present invention. That is, it goes without saying that all other forms, examples, operational techniques, and the like made by those skilled in the art based on this form are included in the scope of the present invention.

1 Error rate measuring device 2 Operation display 2a Clock setting screen 2a1,2a2, 2a3, 2a4, 2a5 Setting items 3 Clock generator 4 Pulse pattern generator 5 Error rate measuring device 6 Storage unit 7 Control unit 11 Clock input unit 12 Clock Distribution circuit 12a (12a1,12a2,12a3,12a4) Switch 12b (12b1,12b2) Multiplier 12c (12c1,12c2,12c3,12c4,12c5) High-frequency device 13 Signal generator 14 Clock output unit 15 PPG clock count unit 21 Clock Input unit 22 Signal reception unit 23 Clock reproduction unit 24 Dividing / multiplying unit 25 ED clock counting unit 51 Clock setting screens 51a, 51b Setting items R1, R2, R3 Clock route W Measured object

Claims (6)

It has a plurality of clock routes (R1, R2, R3) equipped with a high-frequency device (12c) for each operating frequency range having a different band, and has a one-to-one correspondence with a plurality of bit rate ranges consisting of different ranges. A clock distribution circuit in which the operating frequency range having the same frequency magnification as the range is integrated.
When the input clock frequency range corresponding to the bit rate range set from the plurality of bit rate ranges is within the operating frequency range, the clock route corresponding to the input clock frequency range is selectively switched and set. A clock distribution circuit characterized by outputting a clock corrected for the high frequency device according to a bit rate range. It has a plurality of clock routes (R1, R2, R3) equipped with a high frequency device (12c) for each operating frequency range having a different band, and has a one-to-one correspondence with a plurality of bit rate ranges consisting of different ranges. It is a clock distribution method using a clock distribution circuit in which the operating frequency range having the same frequency magnification as the range is integrated.
When the input clock frequency range corresponding to the bit rate range set from the plurality of bit rate ranges is within the operating frequency range, the clock route corresponding to the input clock frequency range is selectively switched and set. A clock distribution method comprising a step of outputting a clock corrected for the high frequency device according to a bit rate range. A test signal of a known pattern is input to the object to be measured (W) from the pulse pattern generator (4), and the bit error rate of the input data received from the object to be measured in connection with the input of this test signal is determined by the error rate measuring device. In the error rate measuring device measured in (5)
An error rate measuring device, characterized in that a clock signal output by the clock distribution circuit of claim 1 is input to the pulse pattern generator or the error rate measuring device as a timing signal. A test signal of a known pattern is input to the object to be measured (W) from the pulse pattern generator (4), and the bit error rate of the input data received from the object to be measured in connection with the input of this test signal is determined by the error rate measuring device. In the error rate measuring method measured in (5),
A method for measuring an error rate, which comprises a step of inputting a clock signal output by the clock distribution method according to claim 2 into the pulse pattern generator or the error rate measuring device as a timing signal. The error rate measuring device according to claim 3, wherein the clock setting screen (2a) for selecting and setting one bit rate range with the plurality of bit rate ranges as options is displayed and controlled. The error rate measuring method according to claim 4, further comprising a step of displaying and controlling a clock setting screen (2a) for selecting and setting one bit rate range with a plurality of bit rate ranges as options.

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