JP2020167778A - Control apparatus for direct type power converter - Google Patents

Abstract

To reduce a harmonic component of a current to flow to a power converter.SOLUTION: Control signals SSup, SSvp, SSwp, SSun, SSvn and SSwn controlling operation of an inverter 5 using a first duty drec that is a duty for a current irec1 to flow from a rectifier circuit 3 to a DC link 7, a second duty dc that is a duty for a current ic to flow from a charge/discharge circuit 4 to the DC link 7 and a command value of a modulation factor of the inverter 5 are outputted from a control apparatus 10. The command value of the modulation factor includes a DC component and an AC component in a six-times frequency as high as a fundamental frequency of AC voltages Vu, Vv and Vw at least during a first period. The first period is a period in which the current irec1 flows.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a technique for converting electric power.

The power obtained from a single-phase AC power supply has a component that pulsates at a frequency twice the power supply frequency. A large-capacity energy storage element is desired in order to obtain a constant DC voltage using a rectifier circuit.

A technique has been proposed in which a capacitor constituting an active buffer is connected to a DC link via a switching element to function as a voltage source for applying a voltage to an inverter.

Patent Document 1 is mentioned as a prior art document related to the present disclosure.

Japanese Patent No. 5920520

When the inverter drives, for example, a motor, the current flowing through the inverter contains harmonics. For example, the harmonic has a frequency that is an integral multiple of the frequency that drives the motor.

The technique according to the present disclosure provides a technique for reducing a harmonic component of a current flowing through a power converter.

The control device of the present disclosure is a control device (10) that controls a direct current power converter (100), and the direct current power converter is applied with a DC link (7) and a single-phase AC voltage (Vin). A rectifier circuit (3) having an input terminal pair (3A, 3B) connected to the DC link and performing full-wave rectification, and a rectifier circuit (3) charged from the rectifier circuit to the DC link. It includes a charge / discharge circuit (4) for discharging and an inverter (5) for converting a DC voltage in the DC link into an AC voltage (Vu, Vv, Vw).

The first aspect of the control device of the present disclosure is a first duty (drec) in which a first current (irec1) flows from the rectifier circuit to the DC link, and a second duty (drec) from the charge / discharge circuit to the DC link. A duty generating unit (11) that generates a second duty (dc) that is a duty through which an electric current (ic) flows, the first duty (dec), the second duty (dc), and the modulation factor of the inverter. It is provided with an inverter control unit (10b) that outputs control signals (SSup, SSbp, SSwp, SSun, SSvn, SSwen) that control the operation of the inverter by using the command values (k1, k2) of.

The command value is a second frequency (6φ / 2πt) which is 6 times the frequency of the first DC component (ks-ks6) and the fundamental frequency (φ / 2πt) of the AC voltage in at least the first period (Trec). ) Has an AC component (ks6 · cos (6φ / 2πt) + θ). The first period is a period during which the first current flows.

The second aspect of the control device of the present disclosure is the first aspect thereof, in which the command value has only the second DC component (ks) in at least the second period (Tc). The second period is a period during which the second current flows.

A third aspect of the control device of the present disclosure is the first or second aspect thereof, wherein in the third aspect, the direct power converter is provided between the rectifier circuit and the DC link. The filter (2) is further provided. The first current (irec1) flows from the rectifier circuit to the DC link through the filter, and the DC link includes a first DC power supply line (LH) and a second DC power supply line (LL).

The filter has a reactor (L2) connected in series with the first DC power supply line or the second DC power supply line between the inverter and the rectifier circuit, and the reactor in series with the output terminal pair. It has a capacitor (C2) connected to.

The third current (iL) for charging the charge / discharge circuit (4) decreases as the voltage (VL) of the reactor increases.

According to the control device for the direct power converter according to this disclosure, the harmonic component of the current flowing through the power converter is reduced.

It is a block diagram which illustrates the structure of the direct type power converter. It is a circuit diagram which shows the equivalent circuit of the direct type power converter. It is a graph which shows the operation of a discharge circuit and an inverter. It is a circuit diagram which shows a part equivalent circuit of a direct type power converter. It is the figure which rewrote the equivalent circuit of FIG. 4 as a block diagram. It is a block diagram which performed the equivalent conversion to the block diagram of FIG. It is a block diagram which performed the equivalent conversion to the block diagram of FIG. It is a block diagram which performed the equivalent conversion to the block diagram of FIG. It is a block diagram which performed the equivalent conversion to the block diagram of FIG. It is a block diagram which performed the equivalent conversion to the block diagram of FIG. It is a block diagram which performed the equivalent conversion to the block diagram of FIG. It is a spectrum showing the distortion of the current. It is a spectrum showing the distortion of the current. It is a graph which shows the relationship between the gain of a control system and a distortion factor. It is a graph which shows the relationship between the gain of a control system and a distortion factor. It is a graph which shows the relationship between the rotation speed of a synchronous machine, and a modulation rate. It is a block diagram which shows an example of the conceptual structure of a control device.

{A. Configuration of power converter and its control device}
FIG. 1 is a block diagram illustrating the configuration of the direct power converter 100. The control technology according to the present disclosure can be applied to the direct power converter 100. The direct power converter 100 includes a rectifier circuit 3, a filter 2, a charge / discharge circuit 4, an inverter 5, and the like. It is provided with a DC link 7.

A single-phase AC voltage Vin (= Vm · sin (ωt)) is input to the rectifier circuit 3 from the single-phase AC power supply 1. The rectifier circuit 3 obtains a rectified voltage Vrec (= | Vin |) after single-phase full-wave rectification of the single-phase AC voltage Vin, and outputs the rectified voltage Vrec to the filter 2. The current Iin flows into the rectifier circuit 3 from the single-phase AC power supply 1. The rectifier circuit 3 outputs a current irec (= | Iin |; Iin = Im · sin (ωt)).

The rectifier circuit 3 employs, for example, a diode bridge and includes diodes D31 to D34. The diodes D31 to D34 form a bridge circuit.

The filter 2 includes a reactor L2 and a capacitor C2. The capacitor C2 is connected in series with the reactor L2 between the output terminal pairs 3A and 3B of the rectifier circuit 3.

One end of the reactor L2 is connected to both the high potential end 3A of the output terminal pairs 3A and 3B of the rectifier circuit 3, specifically the cathodes of the diodes D31 and D33. The other end of the reactor L2 is connected to both the low potential end 3B of the output terminal pairs 3A and 3B of the rectifier circuit 3, specifically the anodes of the diodes D32 and D34, via the capacitor C2.

In the filter 2, the rectified voltage Vrec is input in the series connection between the reactor L2 and the capacitor C2, and the voltage V2 supported by the capacitor C2 is output.

The DC link 7 has a DC power supply line LL and a DC power supply line LH having a higher potential than the DC power supply line LL. The DC power supply line LH is connected to the high potential end 3A of the rectifier circuit 3 via the reverse current blocking circuit 8 and the reactor L2, which will be described later. The DC power line LL is connected to the low potential end 3B of the rectifier circuit 3.

The reactor L2 is connected in series with the DC power supply line LH or the DC power supply line LL between the inverter 5 and the rectifier circuit 3.

The charge / discharge circuit 4 has a discharge circuit 4a and a charging circuit 4b. The charge / discharge circuit 4 functions as an active buffer for transmitting and receiving electric power between the rectifier circuit 3 and the DC link 7.

The discharge circuit 4a includes the capacitor C4 as a buffer capacitor, and the charging circuit 4b boosts the voltage V2 to charge the capacitor C4.

The discharge circuit 4a further includes a diode D42 and a transistor (here, an insulated gate bipolar transistor: hereinafter abbreviated as “IGBT”) Sc connected in antiparallel to the diode D42. The transistor Sc is connected in series between the DC power supply lines LH and LL on the DC power supply line LH side with respect to the capacitor C4.

Here, the antiparallel connection means that the forward directions are opposite to each other and the connections are made in parallel. Specifically, the forward direction of the transistor Sc is the direction from the DC power supply line LL to the DC power supply line LH, and the forward direction of the diode D42 is the direction from the DC power supply line LH to the DC power supply line LL. The transistor Sc and the diode D42 can be collectively grasped as one switch element (switch Sc). The capacitor C4 is connected to the DC link 7 by the continuity of the switch Sc, and the capacitor C4 is discharged to pass a current ic to the DC link 7.

The charging circuit 4b includes, for example, a diode D40, a reactor L4, and a transistor (here, an IGBT) SL. The diode D40 includes a cathode and an anode, and the cathode is connected between the switch Sc and the capacitor C4. Such a configuration is known as a so-called boost chopper.

The reactor L4 is connected between the high potential end 3A and the anode of the diode D40. The transistor SL is connected between the DC power line LL and the anode of the diode D40. A diode D41 is connected in antiparallel to the transistor SL, and both can be collectively grasped as one switch element (switch SL). Specifically, the forward direction of the transistor SL is the direction from the high potential end 3A to the low potential end 3B, and the forward direction of the diode D41 is the direction from the low potential end 3B to the high potential end 3A.

The capacitor C4 is charged by the charging circuit 4b, and the voltage Vc across the capacitor C4 (hereinafter, also simply referred to as “voltage across”) is higher than the rectified voltage Vrec. The switch SL connects the rectifier circuit 3 to the reactor L4 (via the reactor L2 if the filter 2 is taken into consideration) by conducting itself, and stores energy in the reactor L4. Specifically, energy is stored in the reactor L4 by passing a current from the high potential end 3A to the low potential end 3B via the switch SL. After that, by turning off the switch SL, the energy is stored in the capacitor C4 via the diode D40.

Since the voltage across the ends Vc is higher than the rectified voltage Vrec, basically no current flows through the diode D42. Therefore, the conduction / non-conduction of the switch Sc depends exclusively on that of the transistor Sc. Here, the diode D42 secures a reverse withstand voltage when the voltage Vc across the ends is lower than the rectified voltage Vrec, and reverse-conducts the current returned from the inductive load 6 to the DC link 7 when the inverter 5 stops abnormally. It works.

Further, since the forward direction of the diode D41 is the direction from the low potential end 3B to the high potential end 3A, basically no current flows through the diode D41. Therefore, the conduction / non-conduction of the switch SL depends exclusively on that of the transistor SL. Here, the diode D41 is a diode for causing reverse withstand voltage and reverse conduction, and is exemplified as a diode built in the transistor SL realized by the IGBT, but the diode D41 itself is not involved in the circuit operation.

The reverse current blocking circuit 8 is provided between the filter 2 and the DC power supply line LH, and blocks the current flowing back from the discharge circuit 4a to the filter 2. The reverse current blocking circuit 8 is realized by, for example, the diode D43. The anode of the diode D43 is connected to the high potential end 3A via the filter 2, more specifically the reactor L2. The cathode of the diode D43 is connected to the DC power line LH. Such a reverse current blocking circuit 8 is known, for example, in Japanese Patent No. 5772915 (hereinafter referred to as "Patent Document 2").

The current irec1 flowing from the rectifying circuit 3 to the DC power supply line LH via the reverse current blocking circuit 8, the current iL flowing from the rectifying circuit 3 to the charging / discharging circuit 4 (specifically, to the charging circuit 4b), and the capacitor C2. When the current I2 is introduced, the current irec output from the rectifying circuit 3 is the sum of the currents irec1, iL, and I2. A current iL flows through the reactor L4, and there is a relationship of iL = irec-irec1-I2. The current iL can be measured by, for example, a well-known current sensor.

Since the voltage Vc across both ends is higher than the rectified voltage Vrec, the current irec1 takes a value of 0 when the switch Sc is conducting.

The reactor L4 can also be directly connected to the high potential end 3A without going through the reactor L2. In this case, no current iL flows through the filter 2. From the viewpoint of reducing the current capacity of the filter 2 and thus reducing the size of the filter 2, it is desirable to connect the reactor L4 closer to the rectifier circuit 3 than the filter 2.

The inverter 5 converts the DC voltage between the DC power lines LH and LL in the DC link 7 into three-phase (U-phase, V-phase, W-phase) AC voltage, and outputs the output ends Pu, Pv, Output to Pw. The DC voltage takes a voltage Vc across the switch when the switch Sc is conducting. The DC voltage takes a rectified voltage Vrec when the switch Sc does not conduct, ignoring the voltage drop in the reverse current blocking circuit 8 and the reactor L2.

The inverter 5 is, for example, a three-phase voltage type inverter, and includes six switching elements Supp, Sbp, Swp, Sun, Svn, and Swn. The switching element Sup is connected between the output end Pu and the DC power supply line LH, the switching element Svp is connected between the output end Pv and the DC power supply line LH, and the switching element Swp is connected between the output end Pw and the DC power supply line LH. The switching element Sun is connected between the output terminal Pu and the DC power supply line LL, the switching element Svn is connected between the output terminal Pv and the DC power supply line LL, and the switching element Swn is output. It is connected between the end Pw and the DC power supply line LL. The inverter 5 constitutes a so-called voltage type inverter, and includes six diodes Dup, Dbp, Dwp, Dun, Dvn, and Dwn.

The diodes Dup, Dbp, Dwp, Dun, Dvn, and Dwn are all arranged with their cathodes facing the DC power line LH side and their anodes facing the DC power line LL side. The diode Dup is connected in parallel with the switching element Up between the output terminal Pu and the DC power supply line LH. Similarly, the diode Dvp is connected in parallel with the switching element Svp, the diode Dwp is connected in parallel with the switching element Swp, the diode Dun is connected in parallel with the switching element Sun, and the diode Dvn is connected in parallel with the switching element Svn. The diode Dwn is connected in parallel with the switching element Swn. The load current iu is output from the output end Pu, the load current iv is output from the output end Pv, and the load current iwa is output from the output end Pw. The load currents iu, iv, and iwa constitute a three-phase alternating current. For example, the IGBT is adopted for all of the switching elements Sup, Sbp, Swp, Sun, Svn, and Swn.

The inductive load 6 is, for example, a rotating machine and is illustrated by an equivalent circuit indicating that it is an inductive load. Specifically, the reactor Lu and the resistor Ru are connected in series with each other, and one end of the series is connected to the output end Pu. The same applies to the reactors Lv and Lw and the resistors Rv and Rw. Further, the other ends of these series are connected to each other.

The inductive load 6 will be described as a synchronous machine. The speed detection unit 9 detects the load currents iu, iv, and iwa flowing through the inductive load 6. The speed detection unit 9 directly forms the rotation angular velocities ωm, q-axis current Iq, and d-axis current Id of the synchronous machine 6 obtained from the load currents iu, iv, and iw (to be exact, the information indicating them; the same applies hereinafter). It is given to the control device 10 for the power converter.

The control device 10 includes a rotation angular velocity ωm, a q-axis current Iq and a d-axis current Id, an amplitude Vm of a single-phase AC voltage Vin, an angular velocity ω (or a phase θ = ωt which is the product of this and time t). The command value ωm * of the rotational angular velocity ωm and the voltage VL applied to the reactor L2 are input. In this embodiment, the voltage VL will be described by adopting the potential at the end of the reactor L2 on the high potential end 3A side with reference to the potential at the end of the reactor L2 on the capacitor C2 side.

{B. Equivalent circuit of direct power converter and various duties}
FIG. 2 is a circuit diagram showing an equivalent circuit of the direct power converter 100 shown in FIG. The equivalent circuit is introduced, for example, in Patent Document 2. However, in the present embodiment, the voltage source is shown by integrating both the rectifier circuit 3 and the filter 2. The voltage source outputs a voltage V2 and a current (irec-I2).

In the equivalent circuit, the current irec1 is equivalently represented as the current irec1 that passes through the switch Srec when it conducts. Similarly, the current ic is equivalently represented as the current ic that passes through the switch Sc when it conducts.

When the output ends Pu, Pv, and Pw of the inverter 5 are commonly connected to either one of the DC power lines LH and LL, the current flowing through the inverter 5 to the inductive load 6 is when the switch Sz is conducting. It is equivalently represented as a zero-phase current iz flowing through the inverter.

The inverter 5 and the inductive load 6 are equivalently represented as a current source Idc that carries a direct current Idc.

In FIG. 2, the reactor L4, the diode D40, and the switch SL constituting the charging circuit 4b are shown. The current iL flowing through the reactor L4 is shown.

In the equivalent circuit, the respective duty drec, dc, dz in which the switches Srec, Sc, and Sz are conductive are introduced. As is known from Patent Document 2, 0 ≦ drec ≦ 1,0 ≦ dc ≦ 1,0 ≦ dz ≦ 1, drec + dc + dz = 1.

The duty drc is a duty that sets a period during which the rectifier circuit 3 can pass a current through the DC link 7 to the inverter 5. Hereinafter, the duty for setting the period during which the rectifier circuit 3 can pass a current through the DC link 7 to the inverter 5 may be referred to as a "first duty".

The duty dc is the duty at which the capacitor C4 is discharged. Hereinafter, the duty that the capacitor C4 discharges may be referred to as a "second duty".

The duty dz is a duty at which the zero-phase current iz always flows regardless of the voltage output by the inverter 5. The duty that the zero-phase current iz always flows in the inverter 5 regardless of the output voltage may be referred to as "third duty" below.

The direct current Idc is a current flowing through the inductive load 6 via the inverter 5. The currents irec1, ic, and iz are the products of the direct current Idc and the duty drec, dc, and dz, respectively. The currents irec1, ic, and iz are average values in the switching period of the switches Srec, Sc, and Sz, respectively. The duty drec, dc, and dz can also be regarded as the duty of the direct current Idc with respect to the respective currents irec1, ic, and iz.

When a diode bridge is adopted for the rectifier circuit 3, the rectifier circuit 3 cannot actively switch with the first duty drec. The current irec1 can be obtained by switching the inverter 5 and the switch Sc, respectively, according to the third duty dz and the second duty dc.

FIG. 3 is a graph showing the operation of the discharge circuit 4a and the inverter 5 in the present embodiment. Carrier C3 is a sawtooth wave with a period ts having a minimum value of 0 and a maximum value of 1.

As described above, the current irec1 can be obtained by switching the inverter 5 and the switch Sc, respectively, according to the third duty dz and the second duty dc.

The on of the switches Srec, Sc, and Sz is indicated by the high value of each square wave. The off of the switches Srec, Sc, and Sz is indicated by the low value of each square wave.

The switch Sc is turned on when the value of the carrier C3 is 0 or more and less than the second duty dc, and is turned off when the value of the second duty dc or more is 1 or less.

The switch Sz (see FIG. 2) is turned on when the value of the carrier C3 is the second duty dc or more and less than the value (dc + dz / 2), and when the value (dc + dz / 2 + drc) or more and 1 or less. The switch Sz is turned off when the value of the carrier C3 is 0 or more and less than the second duty dc (the switch Sc is turned on at this time), and when the value (dc + dz / 2) or more and less than the value (dc + dz / 2 + drec).

The switch Srec (see FIG. 2) is turned on when the value of the carrier C3 is equal to or greater than the value (dc + dz / 2) and less than the value (dc + dz / 2 + drec). The switch Srec is turned off when the value of the carrier C3 is 0 or more and less than a value (dc + dz / 2), and when the value (dc + dz / 2 + drec) or more and 1 or less.

The length of the period tc, trec, tz is introduced. The length tc is the period during which the value of the carrier C3 is 0 or more and the second duty dc or less (hereinafter, also referred to as “period Tc”: this is the moment when the carrier C3 takes the second duty dc, so that the switch Sc is conducted. It can be regarded as a period of time).

The length trec is the period during which the value of the carrier C3 is equal to or greater than the value (dc + dz / 2) (dc + dz / 2 + drec) (hereinafter, also referred to as “period Trec”: this is the moment when the carrier C3 takes the value (dc + dz / 2 + drec). By ignoring it, it can be regarded as the period during which the switch Srec conducts.)

The length tz is a period in which the value of the carrier C3 is equal to or greater than or equal to the value dc (dc + dz / 2) (hereinafter, also referred to as “period Tz1”: this is by ignoring the moment when the carrier C3 takes the value (dc + dz / 2). It is twice the length (which can be considered as one of the periods during which the switch Sz is continuously conductive). The length tz is the period during which the value of the carrier C3 is equal to or greater than the value (dc + dz / 2 + drec) and is 1 or less (hereinafter, also referred to as “period Tz2”: this can be regarded as another one of the periods during which the switch Sz is continuously conductive). It can be said that it is twice the length.

The carrier C1 has a triangular wave C11 having a length (trec + tz) as one cycle over the periods Tz1, Trec, and Tz2, and a triangular wave C12 having a length tc as one cycle in the period Tc. The triangular waves C11 and C12 are both symmetrical triangular waves.

Both the triangular waves C11 and C12 have a minimum value of 0 at both ends of the period Tc. The triangular wave C12 has a maximum value equal to the second duty dc at the center of the period Tc. The triangular wave C11 has a maximum value equal to the value (1-dc) at the center of the period Trec. For convenience of later expression, the value (1-dc) may be referred to as supplementary duty (1-dc).

The on of the switching elements Sup, Svp, and Swp is indicated by the high value of each square wave. The off of the switching elements Sup, Svp, and Swp is indicated by the lower value of each square wave.

The on and off of the switching element Sun correspond to the off and on of the SUP, respectively. The on and off of the switching element Svn correspond to the off and on of Svp, respectively. The on and off of the switching element Swn correspond to the off and on of Swp, respectively. Therefore, in FIG. 3, the operation of the switching elements Sun, Svn, and Swn is not shown.

The switching element SUP is turned on when the triangular wave C12 takes a value larger than the value dc (1-Vu2 *) and when the triangular wave C11 takes a value larger than the value ((1-dc) -drec · Vu1 *). To do. The switching element Svp is turned on when the triangular wave C12 takes a value larger than the value dc (1-Vv2 *) and when the triangular wave C11 takes a value larger than the value ((1-dc) -drec · Vv1 *). To do. The switching element Swp is turned on when the triangular wave C12 takes a value larger than the value dc (1-Vw2 *) and when the triangular wave C11 takes a value larger than the value ((1-dc) -drec · Vw1 *). To do.

FIG. 3 illustrates a case where a so-called two-phase modulation method is adopted. Such an operation is known, for example, in Japanese Patent No. 5962804 (hereinafter referred to as "Patent Document 3"), and therefore detailed description thereof will be omitted. Here, a state in which the switching element Swp is turned off and the switching element Swn is turned on will be described. In such a state, the phase φ of the three-phase AC voltages Vu, Vv, and Vw output by the output terminals Pu, Pv, and Pw is introduced, and 0 ≦ φ ≦ 2π / 3 (however, Vv = at φ = 0). It can be explained as a state where Vw = Vv when φ = π / 3 and Vw = Vu when φ = 2π / 3).

However, due to the symmetry of the three phases, the switching element Sup is off and the switching element Sun is on (2π / 3 ≦ φ ≦ 4π / 3), or the switching element Svp is off and the switching element Svn is on. It is clear that the same state can be explained for the state (4π / 3 ≦ φ ≦ 2π).

The state in which all of the switching elements Sup, Svp, and Swp are off is indicated by the period V0. The state in which the switching element Sup is on and both the switching elements Svp and Swp are off is indicated by the period V4. The state in which both the switching elements Sup and Svp are on and the switching element Swp is off is indicated by the period V6.

It is known in Patent Document 3, for example, to control the on / off of switching elements Sup, Sbp, Swp, Sun, Svn, and Swn by using different sets of signal waves for each of the triangular waves C11 and C12.

In the above example, the triangular wave C11 is a signal wave ((1-dc) -drec · Vu1 *), ((1-dc) -drec · Vv1 *), ((1-dc) -drec · Vw1 *). The triangular wave C12 is compared with the set of signal waves dc (1-Vu2 *), dc (1-Vv2 *), and dc (1-Vw2 *).

In the present embodiment, the command value ks (> 0) and the value ks6 (> 0) of the modulation factor are introduced and set as follows in 0 ≦ φ ≦ 2π / 3.
Vu1 * = (τ41 + τ61) / ts, Vv1 * = τ61 / ts, Vw1 * = 0 ... (1);
Vu2 * = (τ42 + τ62) / ts, Vv2 * = τ62 / ts, Vw2 * = 0 ... (2);
τ41 / ts = k1 · sin (π / 3-φ), τ61 / ts = k1 · sin (φ)… (3);
τ42 / ts = k2 · sin (π / 3-φ), τ62 / ts = k2 · sin (φ)… (4);
k1 = ks-ks6 + ks6 · cos (6φ / 2πt + θ) ... (5);
k2 = ks ... (6).

The modulation factor is the ratio of the AC voltage output by the inverter 5 to the DC voltage input to the inverter 5 (here, the DC voltage at the DC link 7), and is sometimes referred to as the voltage control rate (for example, Patent No. 4488122 (for example, Patent No. 4488122). (Hereinafter referred to as "Patent Document 4")).

In equations (5) and (6), corrected (modulation rate) command values k1 and k2 were introduced. It is known, for example, in Patent Document 3, that the operation of the inverter 5 is controlled by using the command values k1 and k2 corrected in this way and the duty dc and drec.

The values Vu1 * and Vu2 * correspond to the command values of the AC voltage Vu, the values Vv1 * and Vv2 * correspond to the command values of the AC voltage Vv, and the values Vw1 * and Vw2 * correspond to the command values of the AC voltage Vw. ..

Equation (5) shows the relationship between the command value ks and the command value k1. The command value k1 is the DC component (ks-ks6) and the AC component ks6 · cos (6φ / 2πt + θ) with a frequency (6φ / 2πt) (however, t is time) that is 6 times the fundamental frequency of the AC voltages Vu, Vv, and Vw. And have. The command value k1 is a signal wave for the triangular wave C11 ((1-dc) -drec · Vv1 *), ((1-dc) -drec · Vv1 *), (( The set of 1-dc) -drec · Vw1 *) is set together with the duty drec and dc.

Equation (6) shows the relationship between the command value ks and the command value k2. The command value k2 has a command value ks as a DC component ks and does not have an AC component. The command value k1 is the duty of the set of the signal waves dc (1-Vu2 *), dc (1-Vv2 *), and dc (1-Vw2 *) for the triangular wave C12 via the equations (4) and (2). Set with dc.

The period Trec is a period during which the switch Srec is conducted and the current irec1 flows. In such a period, the current irec1 flows from the rectifier circuit 3 to the inverter 5. For example, when the inductive load 6 is a synchronous machine, harmonics derived from the armature slot of the synchronous machine are superimposed on the current irec. As the harmonics, the 5th and 7th harmonics with respect to the fundamental frequencies of the AC voltages Vu, Vv, and Vw applied to the synchronous machine are remarkable.

As disclosed in Patent Document 4, the modulation factor has a DC component and an AC component having a frequency 6 times the basic frequency of the AC voltages Vu, Vv, and Vw, so that the current irec and thus the current Iin 5 The second and seventh harmonics are reduced.

Therefore, in the period Trec, the signal waves according to the equations (1), (3), and (5) ((1-dc) -drec · Vu1 *), ((1-dc) -drec · Vv1 *), ((1). Comparing the set of −dc) −drec · Vw1 *) with the triangular wave C11, controlling the operation of the switching elements Sup, Sbp, Swp, Sun, Svn, Swn of the inverter 5 is a direct power converter. It is advantageous from the viewpoint of reducing the harmonic component of the current flowing through 100, for example, the current Iin.

The command value ks is the modulation factor of the inverter 5 when the harmonic component of the current airc is not suppressed. In the above example, when the DC voltage at the DC link 7 is maintained, the larger the command value ks is, the more the inverter. The amplitudes of the AC voltages Vu, Vv, and Vw output by 5 increase.

During the periods Tc, Tz1 and Tz2, the current irec1 does not flow, and even if a harmonic derived from the armature slot is generated in the inverter 5, the harmonic is not superimposed on the current irec. Therefore, the modulation factor in these periods requires only the DC component, and is set as in the equations (2), (4), and (6).

In the periods Tc, Tz1 and Tz2, even if a harmonic derived from the armature slot is generated in the inverter 5, the harmonic is not superimposed on the current irec. Therefore, even if the equations (1), (3), and (5) are adopted in the periods Tc, Tz1, and Tz2, the effect of reducing the 5th and 7th harmonics of the current irec is not impaired.

However, as can be seen from equations (1) to (6), the set of signal waves depends on the modulation factor. Then, the triangular wave C11 and the set of the signal wave ((1-dc) -drec · Vv1 *), ((1-dc) -drec · Vv1 *), and ((1-dc) -drec · Vw1 *) are combined with the current alert. From the viewpoint of reducing the 5th and 7th harmonics superimposed on the above, it is desirable that the command value k1 is 1 or less. From this point of view, the DC component (ks-ks6) of the command value k1 is smaller than the DC component ks of the command value k2.

Therefore, from the viewpoint of increasing the modulation factor of the inverter 5 and increasing the amplitude of the AC voltages Vu, Vv, Vw, the signal wave dc is based on the equations (2), (4), and (6) in the periods Tc, Tz1, and Tz2. It is advantageous to adopt a set of (1-Vu2 *), dc (1-Vv2 *), and dc (1-Vw2 *).

{C. Equivalent circuit of direct power converter and control of current iL based on voltage VL}
FIG. 4 is a circuit diagram showing a part of the direct power converter 100 shown in FIG. 1, specifically, an equivalent circuit of the rectifier circuit 3, the filter 2, and the charge / discharge circuit 4. In the equivalent circuit, the currents iL and irec1 are represented as current sources, respectively.

The current iL is a value obtained by subtracting the values k · VL (however, the coefficient k is positive) that is directly proportional to the voltage VL from the value I0 that does not depend on the voltage VL. The value I0 is the value of the current iL when the voltage VL is equal to the command value VL *.

Adopting a current iL that is smaller as the voltage VL is higher in this way is advantageous from the viewpoint of suppressing resonance in the filter 2. Such a technique is known in itself, for example, in Patent Document 1.

FIG. 5 is a diagram in which the equivalent circuit of FIG. 4 is rewritten as a block diagram. Further, in FIG. 5, a command value VL * is introduced instead of the value I0 to perform equivalent conversion, and the block diagram of FIG. 6 is obtained. Further, the equivalent conversion is performed to sequentially obtain the block diagrams of FIGS. 7, 8, 9, 10, and 11. Such an equivalent conversion is known, for example, in Japanese Patent No. 5257533 (hereinafter referred to as "Patent Document 5").

As understood from the block diagram shown in FIG. 11 and as explained in Patent Document 5, the configuration in which the command value VL * is input to obtain the voltage VL is a differential system surrounded by a broken line. The processing and the processing of the secondary system surrounded by the chain line are represented as a control system connected in series.

When the resonance of the filter 2 is suppressed by adopting the smaller current iL as the voltage VL is higher, the coefficient k may be set only from the viewpoint of obtaining a desired attenuation coefficient.

By increasing the coefficient k, it is possible to try to reduce the harmonics derived from the slot of the armature. The 5th and 7th harmonics derived from the armature slot appear as 6th harmonics on the DC link 7. For example, if the rotation speed of the synchronous machine is 20 to 120 rotations per second and the number of pole pairs of the armature of the synchronous machine is 3, the sixth harmonic is 360 to 2160 Hz. For example, the resonance frequency of the filter 2 is 1700 Hz. When both the harmonics derived from the armature slot and the harmonics derived from the resonance of the filter 2 are present, a frequency component is generated by synthesizing the waveforms. Therefore, by increasing the coefficient k to such an extent that the band of the control system expands to 360 to 3040 (= 1700 × 2-360) Hz, the harmonics derived from the armature slot can also be reduced.

Increasing the coefficient k may affect the operation of the inverter 5 to distort the waveforms of the AC voltages Vu, Vv, and Vw, and rather increase the lower harmonics. This is because when the control signal (described later) adopted in the control of the inverter 5 is obtained by pulse width modulation using the carrier C1 (for example, its frequency is 5.9 kHz), the above band extends to the frequency component of the control signal. This is because the width is widened.

12 and 13 show the harmonic current content of each order of the current Iin, the total harmonic distortion (denoted as TH in the figure), and the partial weighted harmonic distortion (in the figure). It is a spectrum showing PW). The harmonic current content indicates the content of the harmonic current for each order with respect to the effective value of the current Iin.

The standard IEC61000-3-12 (2011 version) for harmonics stipulates the permissible value (upper limit) for harmonic components up to the 13th order. The permissible value is shown by polygonal lines G21, G22, G23, G24, and G25 in FIGS. 12 and 13.

The polygonal line G21 has a short-circuit ratio (short-circuit capacity at the customer's point / equipment capacity: Rsce) of 350 or more, the polygonal line G22 has a short-circuit ratio of 250, the polygonal line G23 has a short-circuit ratio of 120, and the polygonal line G24 has a short-circuit ratio of 120. The short circuit ratio is 66, and the polygonal line G25 is 33.

The standard IEC61000-3-12 also stipulates allowable values (upper limits) for total harmonic distortion and partially weighted harmonic distortion for current. In FIGS. 12 and 13, these permissible values are indicated by straight lines G31, G32, G33, G34, and G35. Since the permissible value for total harmonic distortion and the permissible value for partially weighted harmonic distortion are equal, the straight lines G31, G32, G33, G34, and G35 are not polygonal lines.

All of these allowable values are shown by converting the ratio of the effective value of the harmonic current to the effective value of the current Iin into the content rate. The partially weighted harmonic distortion is obtained by weighting the components of the 13th order or higher. Therefore, among the current components generated by the AC voltages Vu, Vv, Vw 5th harmonic and 7th harmonic, which are the harmonics derived from the slots of the armature, the components that are 14th or higher of the fundamental frequency of the current Iin are reduced. This is desirable from the viewpoint of ensuring a margin for partially weighted harmonic distortion and thus suppressing total harmonic distortion.

The straight line G31 has a short-circuit ratio of 350 or more, the straight line G32 has a short-circuit ratio of 250, the straight line G33 has a short-circuit ratio of 120, the straight line G34 has a short-circuit ratio of 66, and the straight line G35 has a short-circuit ratio. The case where is 33 is shown respectively.

In both FIGS. 12 and 13, bar graphs showing harmonic current rates are arranged in sets of five for each order. Among the five shown in the same order, the bar graph arranged on the right side has a larger coefficient k. Of the five, the bar graph arranged on the leftmost side has k = 0. In addition, the values of the coefficients k are aligned in the bar graphs of different orders for the remaining four of the five, and the coefficients k are also aligned in FIGS. 12 and 13.

FIG. 12 shows a case where the above-mentioned command values k1 and k2 are not used, that is, a case where ks6 = 0 (at this time, k1 = k2 = ks) is set for convenience in the equation (5).

FIG. 13 shows a case where a positive constant value is adopted as the value ks6. As described, even if the inverter 5 is controlled by a set of signal groups using the command value k1 other than the period Trec, the effect of suppressing harmonics does not change.

From FIGS. 12 and 13, it can be seen that in odd-numbered orders, the larger the coefficient k, the higher the harmonic current rate. It is considered that this is because the control of the current iL based on the voltage VL affected the operation of the inverter 5 as described above.

From FIGS. 12 and 13, it can be seen that both the total harmonic distortion and the partially weighted harmonic distortion take the minimum value with respect to the increase in the coefficient k. From this, it is shown that attempting to reduce the sixth harmonic of the input power by increasing the coefficient k does not necessarily work advantageously.

From the comparison between FIGS. 12 and 13, the control of the inverter 5 using the command values k1 and k2 is compared with the control of the inverter 5 using the command value ks.
(i) When the coefficient k is large (the one arranged on the rightmost side of the five sets of bar graphs), the odd-order harmonics are reduced, and
(ii) Even if the coefficient k is small, both total harmonic distortion and partially weighted harmonic distortion are reduced.
Is recognized.

14 and 15 are graphs showing the relationship between the gain of the control system and the distortion factor. In each case, the distortion factor is adopted on the vertical axis, and the control gain is adopted on the horizontal axis. The control gain is the gain of the control system and has a positive correlation with the coefficient k.

The distortion factor in FIG. 14 is the value obtained by dividing the partially weighted harmonic distortion of the current Iin by the effective value of the current Iin as a percentage. The distortion factor in FIG. 15 is the value obtained by dividing the total harmonic distortion of the current Iin by the effective value of the current Iin as a percentage.

In FIG. 14, the polygonal line G41 shows the distortion factor when ks6 = 0, and the polygonal line G42 shows the distortion factor when a positive constant value is adopted as the value ks6. In FIG. 15, the polygonal line G51 shows the distortion factor when ks6 = 0, and the polygonal line G52 shows the distortion factor when a positive constant value is adopted as the value ks6.

By comparing the broken lines G41 and G42 in FIG. 14, the control of the inverter 5 using the command values k1 and k2 is compared with the control of the inverter 5 using the command values ks, and the presence or absence of control of the current iL by the voltage VL is compared. It is recognized that the partially weighted harmonic distortion is reduced regardless of (that is, whether or not the coefficient k is 0). From FIG. 14, it is also recognized that the partial weighted harmonic distortion is reduced by increasing the gain of the control system.

By comparing the polygonal lines G51 and G52 in FIG. 15, the control of the inverter 5 using the command values k1 and k2 is compared with the control of the inverter 5 using the command values ks, and the presence or absence of control of the current iL by the voltage VL is compared. Nevertheless, it is recognized that the total harmonic distortion is reduced.

FIG. 16 is a graph showing the relationship between the rotation speed of the synchronous machine having the inductive load 6 and the modulation factor. The modulation factor adopted on the vertical axis is the ratio of the amplitude of the AC voltage Vu to the DC voltage at the DC link 7. The higher the rotation speed adopted on the horizontal axis, the greater the power output by the inverter 5.

The polygonal line G61 shows a case where neither the control of the current iL based on the voltage VL nor the control of properly using the command values k1 and k2 is adopted.

The polygonal line G62 shows a case where the control of the current iL based on the voltage VL and the control in which the command value k1 is adopted in the period Trec and the command value k2 is adopted in the periods Tz1, Tz2, Tc are adopted.

The polygonal line G63 shows a case where the control of the current iL based on the voltage VL and the control in which the command value k1 is adopted in all of the periods Trec, Tz1, Tz2, and Tc are adopted.

From the comparison between the polygonal line G61 and the polygonal lines G62 and G63, it was found that the amplitude of the AC voltage Vu is reduced by performing the control based on the DC component (ks-ks6) and the AC component ks6 · cos6φ / 2πt. To. Such a decrease in amplitude corresponds to a decrease in the modulation factor of the inverter 5.

From the comparison between the polygonal lines G62 and G63, the adoption of the command value k2 in the periods Trec, Tz1, Tz2, and Tc is advantageous from the viewpoint that the modulation factor of the inverter 5 is not easily lowered.

{D. Configuration example of control device 10}
FIG. 17 is a block diagram showing an example of the conceptual configuration of the control device 10. The control device 10 has a block 10a that mainly controls the charge / discharge circuit 4 and a block 10b that mainly functions as an inverter control device that controls the inverter 5.

The block 10a includes a duty generation unit 11, comparators 12, 13, and 14, a resonance suppression control unit 15, a subtractor 17, a chopper control unit 16, and carrier generation units 23 and 24.

The block 10b includes a speed control unit 30, an output voltage command generation unit 37, calculation units 31, 32, comparators 33, 34, and a logic synthesis unit 36.

The duty generation unit 11 inputs the amplitude Vm of the single-phase AC voltage Vin, the command value Vc * for the voltage Vc across both ends, and the angular velocity ω. The amplitude Vm and the angular velocity ω are detected by a known technique and input to the duty generation unit 11. The command value Vc * is input from an external configuration (not shown).

The duty generation unit 11 outputs the duty drec, dc, dz, and the current command value iL *.

The current command value iL * is a command value of the current iL input to the charging circuit 4b, more specifically, to be passed through the reactor L4 when the suppression of resonance of the filter 2 is not taken into consideration. For example, iL * = I0.

Since the method for determining the duty drec, dc, dz, and the current command value iL * is described in detail in Patent Document 2 and the like, the details are omitted here.

A voltage VL is input to the resonance suppression control unit 15. The voltage VL is detected by a known technique. In FIG. 1, the voltage VL is indicated by an arrow from the filter 2 to the control device 10 so as not to complicate the drawing.

The resonance suppression control unit 15 outputs a larger correction value as the voltage VL increases. For example, the correction value is proportional to the voltage VL. In the present embodiment, the product of the voltage VL and the coefficient k is output as the correction value k · VL.

The subtractor 17 subtracts the correction value k · VL from the current command value iL * and outputs the corrected current command value (iL * −k · VL). The current I2 following the current command value iL * takes a value (I0-k · VL) (see FIG. 4).

The second duty dc is compared with the carrier C3 in the comparator 12. The carrier C3 is generated by the carrier generation unit 23. For example, carrier C3 is a sawtooth wave (see FIG. 3).

The comparison result of the comparator 12 is output as a control signal SSc. The control signal SSc is given to the switch Sc. Controls the on / off of the switch Sc. In FIG. 1, the control signal SSc is indicated by an arrow to the discharge circuit 4a so that the drawing is not complicated.

For example, the control signal SSc is active when the value of the carrier C3 is 0 or more and less than the second duty dc, and is inactive when the value of the second duty dc or more is 1 or less. The switch Sc is turned on by the activity of the control signal SSc.

Duties dc, drec, and dz are input to the comparator 13. The comparator 13 outputs a signal SSr that distinguishes the period Trec from the period Tc, Tz1, Tz2. For example, the signal SSr is active in the period Trec and inactive in any of the periods Tc, Tz1, Tz2.

The signal SSr is active when the carrier C3 is greater than or equal to the value (dc + dz / 2) and less than the value (dc + dz / 2 + drec), and is active when the carrier C3 is greater than or equal to the value (dc + dz / 2 + drec) and less than or equal to 1 and the value 0 or more (dc + dz / 2) Inactive when less than 2).

The comparator 13 obtains a value (1 + dc-drec) / 2 (= dc + dz / 2) and a value (1 + dc + drec) / 2 (= dc + dz / 2 + drec) using the duty dc and drec, and obtains these values as the carrier C3. The signal SSr is generated and the signal SSr is output.

The chopper control unit 16 inputs a voltage across Vc and a single-phase AC voltage Vin (more accurately, values indicating each), and outputs a boost duty dL based on the corrected current command value (iL * -k · VL). To do. A technique for determining the boost duty dL from the voltage across the ends Vc, the single-phase AC voltage Vin, and the inductance Lm of the reactor L4 based on the given current command value is also a technique known in Patent Document 2, for example. Details are omitted.

The boost duty dL is compared to the carrier C5 in the comparator 14. The carrier C5 is generated by the carrier generation unit 24. The comparison result of the comparator 14 is output as a control signal SSL that controls the opening and closing of the switch SL.

For example, the comparator 14 outputs a signal activated during the period when the carrier C5 becomes the boost duty dL or less as a control signal SSL. The switch SL is turned on by the activity of the control signal SSL. In FIG. 1, the control signal SSL is indicated by an arrow to the charging circuit 4b so that the drawing is not complicated.

The rotation angular velocity ωm, the q-axis current Iq, and the d-axis current Id of the synchronous machine 6 are input to the speed control unit 30 from the speed detection unit 9 (see FIG. 1). The command value ωm * of the rotational angular velocity ωm is also input to the speed control unit 30 by an external configuration (not shown).

The speed control unit 30 obtains the phase φ and the command value ks by a known method. The speed control unit 30 further obtains command values k1 and k2 according to the equations (5) and (6).

The phase φ and the command values ks1 and ks2 are input to the output voltage command generation unit 37 from the speed control unit 30. The output voltage command generation unit 37 generates the values Vu1 *, Vu2 *, Vv1 *, Vv2 *, Vw1 *, and Vw2 * according to the equations (1) to (4).

The duty dc and drc are input to the calculation unit 31 from the duty generation unit 11, and the value Vx1 * (where x represents u, v, w: the same applies hereinafter) is input from the output voltage command generation unit 37. The calculation unit 31 obtains a value (1-dc-drec-Vx1 *).

The second duty dc is input to the calculation unit 32 from the duty generation unit 11, and the value Vx2 * is input from the output voltage command generation unit 37. The calculation unit 32 obtains the value dc (1-Vx2 *).

The value (1-dc-drec-Vx1 *) is compared with carrier C1 in the comparator 33. The comparator 33 outputs, for example, a signal to be activated when the carrier C1 is equal to or higher than the value (1-dc-drec-Vx1 *).

The value dc (1-Vx2 *) is compared to carrier C1 in the comparator 34. The comparator 34 outputs a signal activated during a period in which the carrier C1 has a value of dc (1-Vx2 *) or more, for example.

Since the carrier C1 can be used for any of the blocks 10a and 10b in this way, the carrier generation unit 23 is shown in FIG. 2 so as to be provided across the boundary between the blocks 10a and 10b.

The comparison results of the comparators 33 and 34 are input to the logic synthesis unit 36. The logic synthesis unit 36 outputs control signals SSup, SSbp, SSwp, SSun, SSvn, SSwn. The control signals SUP, SSbp, SSwp, SSun, SSvn, SSsw control the operation of the switching elements SUP, SUP, Swp, Sun, Svn, and Swn, respectively. In FIG. 1, the control signals SSup, SSvp, SSwp, SSun, SSvn, and SSwn are indicated by arrows to the inverter 5 so that the drawing is not complicated.

The values Vu1 *, Vv1 *, Vw1 * are preferably used in the period Trec, and the values Vu2 *, Vv2 *, Vw2 * are preferably used in the periods Tz1, Tc, Tz2. Therefore, the signal SSr is also input to the logic synthesis unit 36.

The logic synthesis unit 36 obtains the logical product of each of the three comparison results by the comparator 33 and the signal SSr. The logic synthesizer 36 obtains the logical product of each of the three comparison results by the comparator 34 and the negative logic of the signal SSr. Therefore, a pair of logical products are obtained for each phase. The logic synthesis unit 36 obtains the logical sum of a pair of logical products for each phase. The control signal SSup is active when the disjunction corresponding to the U phase is active. The control signal SSvp is active when the disjunction corresponding to the V phase is active. The control signal SSsw is active when the disjunction corresponding to the W phase is active.

The activities of the control signals SUP, SSvp, and SSsw correspond to high values indicating the ON of the switching elements SUP, SUP, and Swp in FIG. 3, respectively. The inactivity of the control signals SUP, SSvp, and SSsw corresponds to low values indicating off of the switching elements SUP, SUP, and Swp in FIG. 3, respectively.

The control signals SSun, SSvn, SSwn are active when the control signals SSup, SSvp, SSwp are inactive. The control signals SSun, SSvn, SSwn are inactive when the control signals SSup, SSvp, SSswp are active.

The activities of the control signals SSun, SSvn, and SSwn correspond to the low values indicating the off of the switching elements Sup, Spp, and Swp in FIG. 3, respectively. The inactivity of the control signals SSun, SSvn, and SSwn corresponds to high values indicating the ON of the switching elements Sup, Spp, and Swp in FIG. 3, respectively.

The control device 10 configured in this way controls the operation of the direct power converter 100. In the direct power converter 100, the above-mentioned operation is performed under the control of the control device 10.

The control device 10 includes a microcomputer and a storage device. The microcomputer executes each processing step (in other words, a procedure) described in the program. The storage device can be configured by one or more of various storage devices such as ROM (Read Only Memory), RAM (Random Access Memory), and rewritable non-volatile memory (EPROM (Erasable Programmable ROM), etc.). ..

The storage device stores various information, data, and the like, stores a program executed by a microcomputer, and provides a work area for executing the program. It should be noted that the microcomputer can be grasped as functioning as various means corresponding to each processing step described in the program, or can be grasped as realizing various functions corresponding to each processing step. Further, the control device 10 is not limited to this, and various procedures executed by the control device 10, various means to be realized, or a part or all of various functions may be realized by hardware.

{E. Modification example}
The control using the command values k1 and k2 does not presuppose the control of the current iL based on the voltage VL. When the current iL is not controlled based on the voltage VL, the resonance suppression control unit 15 and the subtractor 17 can be omitted.

The comparison in the comparator 33 is significant in the period Trec. Therefore, the comparator 33 is provided with the triangular wave C11 which is a part of the carrier C1 and does not have to be provided with the triangular wave C12.

The comparison in the comparator 34 is significant in the periods Tz1, Tc, Tz2. Therefore, the comparator 34 is provided with the triangular wave C12 which is a part of the carrier C1 and does not have to be provided with the triangular wave C11.

The command value k1 may be adopted not only in the period Trec but also in the periods Tz1, Tc, and Tz2 (see the polygonal line G63 in FIG. 16). In this case, since the signal SSr is unnecessary, the comparator 13 can be omitted.

The command value k2 may be adopted only in the period Tc. This is because in the periods Tz1 and Tz2, the DC voltage in the DC link 7 does not contribute to the voltage Vx output by the inverter 5, and the command values k1 and k2 do not contribute to the actual modulation factor in the inverter 5. That is, the modulation factor is improved by adopting the command value k2 instead of the command value k1 at least during the period Tc.

{F. Other explanation}
From the above description, the present embodiment can be described as follows. The control device 10 controls the direct power converter 100. The direct power converter 100 includes a DC link 7, a rectifier circuit 3, a charge / discharge circuit 4, and an inverter 5.

The rectifier circuit 3 has an input terminal pair to which a single-phase AC voltage Vin is applied and output terminal pairs 3A and 3B connected to the DC link 7, and performs full-wave rectification. The charge / discharge circuit 4 is charged from the rectifier circuit 3 and discharged to the DC link 7. The inverter 5 converts the DC voltage at the DC link 7 into AC voltages Vu, Vv, Vw.

The control device 10 includes a duty generation unit 11 and a block 10b. The block 10b functions as an inverter control unit.

The duty generation unit 11 generates a first duty drec and a second duty dc. The first duty drec is the duty at which the current irec1 flows from the rectifier circuit 3 to the DC link 7. The second duty dc is the duty at which the current ic flows from the charge / discharge circuit 4 to the DC link 7.

The block 10b outputs control signals SSup, SSvp, SSsw, SSun, SSvn, SSwn by using the first duty drec, the second duty dc, and the command values k1 and k2 of the inverter. The control signals SSup, SSvp, SSsw, SSun, SSvn, SSswn control the operation of the inverter 5.

The command value of the modulation factor includes the DC component (ks-ks6) and the AC component ks6 having a frequency of 6φ / 2πt, which is 6 times the fundamental frequency φ / 2πt of the AC voltages Vu, Vv, Vw, at least during the period Trec. -A command value k1 having cos6φ / 2πt is adopted. The period Trec is the period during which the current irec flows.

By adopting the command value k1 at least in the period Trec, the harmonic component of the current irec and, by extension, the current Iin is reduced. That is, the harmonic component of the current flowing through the direct power converter 100 is reduced.

Further, as the command value of the modulation factor, the command value k2 having only the DC component ks is adopted at least in the period Tc. The period Tc is the period during which the current ic flows.

In the period Tc, the harmonic component of the current irec has little relation to the command value of the modulation factor. Therefore, the modulation factor is improved by adopting the command value k2.

A case where the direct power converter 100 further includes a filter 2 provided between the rectifier circuit 3 and the DC link 7 will be described. The current irec1 flows from the rectifier circuit 3 to the DC link 7 via the filter 2. The DC link 7 includes DC power lines LH and LL. The filter 2 has a reactor L2 and a capacitor C2. The reactor L2 is connected in series with the DC power supply line LH or the DC power supply line LL between the inverter 5 and the rectifier circuit 3. The capacitor C2 is connected in series with the reactor L2 between the output terminal pairs 3A and 3B. The current iL for charging the charge / discharge circuit 4 decreases as the voltage VL of the reactor L2 increases.

By controlling the current iL based on the voltage VL, the harmonics derived from the resonance of the filter 2 are reduced.

Although the embodiments have been described above, it will be understood that various modifications of the embodiments and details are possible without departing from the purpose and scope of the claims. The above embodiments and modifications can be combined with each other.

2 Filter 3 Rectifier circuit 3A, 3B Output terminal pair (high potential end, low potential end)
4 Charge / discharge circuit 5 Inverter 7 DC link 10 Control device 10b block (inverter control unit)
11 Duty generator 100 type power converter C2 capacitor L2 reactor LH, LL DC power supply line Ssup, SSvp, SSwp, SSun, SSvn, SSsw control signal Tc, Trec period VL voltage Vin single-phase AC voltage Vu, Vv, Vw AC voltage dc, drec duty iL, ic, irec1 current k1, k2 command value ks DC component (command value)
ks-ks6 DC component

Claims (3)

A control device (10) that controls a direct power converter (100).
The direct power converter
DC link (7) and
A rectifier circuit (3) having an input terminal pair to which a single-phase AC voltage (Vin) is applied and an output terminal pair (3A, 3B) connected to the DC link and performing full-wave rectification.
A charge / discharge circuit (4) that is charged from the rectifier circuit and discharged to the DC link, and
It is provided with an inverter (5) that converts a DC voltage in the DC link into an AC voltage (Vu, Vv, Vw).
The control device
The first duty (drec), which is the duty at which the first current (irec1) flows from the rectifier circuit to the DC link, and the second duty, which is the duty at which the second current (ic) flows from the charge / discharge circuit to the DC link. The duty generation unit (11) that generates (dc) and
Control signals (SSup, SSvp,) that control the operation of the inverter by using the first duty (dec), the second duty (dc), and the command values (k1, k2) of the modulation factor of the inverter. It is equipped with an inverter control unit (10b) that outputs SSwp, SSun, SSvn, SSwn).
The command value is a second frequency (6φ / 2πt) which is 6 times the frequency of the first DC component (ks-ks6) and the fundamental frequency (φ / 2πt) of the AC voltage in at least the first period (Trec). ) With the AC component (ks6 · cos (6φ / 2πt) + θ)
The first period is a period in which the first current flows, and is a control device for a direct power converter. The command value has only a second DC component (ks) at least in the second period (Tc).
The control device for a direct power converter according to claim 1, wherein the second period is a period during which the second current flows. The direct power converter
A filter provided between the rectifier circuit and the DC link (2)
With more
The first current (irec1) flows from the rectifier circuit to the DC link via the filter.
The DC link includes a first DC power line (LH) and a second DC power line (LL).
The filter
A reactor (L2) connected in series with the first DC power supply line or the second DC power supply line between the inverter and the rectifier circuit, and
It has a capacitor (C2) connected in series with the reactor between the output terminal pairs.
The control device for a direct power converter according to claim 1 or 2, wherein the third current (iL) for charging the charge / discharge circuit (4) decreases as the voltage (VL) of the reactor increases.

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