JP2020167334A - Solar cell - Google Patents

Abstract

To suppress a decrease in the output due to a contact portion for plating in a solar cell equipped with a plated electrode.SOLUTION: A solar cell according to an embodiment includes a silicon wafer with a polygonal shape in a plan view, a first conductive type first amorphous semiconductor layer provided on a first surface of the silicon wafer, a second conductive type second amorphous semiconductor layer provided on the first surface of the silicon wafer, a first plated electrode provided on the first amorphous semiconductor layer, and a second plated electrode provided on the second amorphous semiconductor layer. On the first surface of the silicon wafer, at least one contact portion for plating is formed only at the first end portion along one side of the plurality of sides.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a solar cell, and more particularly to a solar cell in which a plated electrode is provided only on one surface of a silicon wafer.

Conventionally, a silicon wafer, a first amorphous semiconductor layer provided on one surface of the wafer, and a second amorphous semiconductor layer provided on one surface of the wafer are provided on each semiconductor layer, respectively. A so-called back-to-back type solar cell equipped with an electrode is known. The electrode of the back surface bonded type solar cell is generally a plated electrode and is formed by an electrolytic plating method (see, for example, Patent Document 1). In the electrolytic plating method, for example, terminal pins are attached to both ends along two opposing sides of one surface of a silicon wafer, and a plurality of plating contact portions, which are connection marks of the terminal pins, are formed on the plating electrode. ..

International Publication No. 2017/056371

By the way, a plating pad portion (plating feeding portion) is generally formed in a portion of the plating electrode where a plating contact portion is formed. Alternatively, the portion where the contact portion for plating is formed is formed wider than the other portions. When the electrode area becomes large due to the plating pad portion or the like, for example, the film formation range of the amorphous semiconductor layer that affects the photoelectric conversion characteristics becomes small, and the output of the solar cell may decrease.

An object of the present disclosure is to suppress a decrease in output due to a contact portion for plating in a solar cell provided with a plated electrode.

The solar cell according to one aspect of the present disclosure includes a silicon wafer having a polygonal shape in a plan view having a first surface and a second surface, and a first conductive type first surface provided on the first surface of the silicon wafer. An amorphous semiconductor layer, a second conductive type second amorphous semiconductor layer provided on the first surface of the silicon wafer, and a first plated electrode provided on the first amorphous semiconductor layer. And a second plated electrode provided on the second amorphous semiconductor layer. At least one plating contact portion is formed only at the first end portion along one side of the plurality of sides of the first surface of the silicon wafer.

According to one aspect of the present disclosure, in a solar cell provided with a plating electrode, it is possible to suppress a decrease in output due to a contact portion for plating.

It is the figure which looked at the solar cell which is 1st Embodiment from the 1st surface side. It is an enlarged view of part A in FIG. FIG. 2 is a cross-sectional view taken along the line BB in FIG. It is an enlarged view of part C in FIG. 1, and is the figure which shows the region where the 1st amorphous semiconductor layer and the 2nd amorphous semiconductor layer are provided. It is a figure which shows the structure of the conventional solar cell. It is the figure which looked at the solar cell which is 2nd Embodiment from the 1st surface side. It is a figure which shows the modification of the 2nd Embodiment.

Hereinafter, an example of the embodiment of the solar cell according to the present disclosure will be described in detail with reference to the drawings. The solar cell according to the present disclosure is not limited to the embodiment described below. The drawings referred to in the description of the embodiments are schematically described, and the dimensional ratios of the components drawn in the drawings should be determined in consideration of the following description.

FIG. 1 is a view of the solar cell 10 according to the first embodiment as viewed from the first surface side, and FIG. 2 is an enlarged view of part A in FIG. FIG. 3 is a cross-sectional view taken along the line BB in FIG.

As illustrated in FIGS. 1 to 3, the solar cell 10 has a silicon wafer 11 having a polygonal shape in a plan view having a first surface and a second surface, and a first surface provided on the first surface of the silicon wafer 11. A conductive type first amorphous semiconductor layer 12 and a second conductive type second amorphous semiconductor layer 13 provided on the first surface of the silicon wafer 11 are provided. Further, the solar cell 10 includes a first plated electrode 20 provided on the first amorphous semiconductor layer 12 and a second plated electrode 30 provided on the second amorphous semiconductor layer 13. As will be described in detail later, in the solar cell 10, at least one plating contact portion 34 is formed only at the first end portion along one of the plurality of sides of the first surface of the silicon wafer 11. There is.

Hereinafter, the first surface of the silicon wafer 11 will be referred to as a “back surface”, and the second surface will be referred to as a “light receiving surface”. The light receiving surface of the silicon wafer 11 means a surface on which sunlight is mainly incident (over 50% to 100%) when the solar cell 10 is modularized, and the back surface is opposite to the light receiving surface. Means a face.

The silicon wafer 11 may be a polycrystalline silicon wafer, but is preferably a single crystal silicon wafer. In this embodiment, an n-type single crystal silicon wafer is used as the silicon wafer 11. Phosphorus (P) is generally used as the n-type dopant. It is preferable that a texture structure (not shown) is formed on the surface of the silicon wafer 11. The texture structure is a surface uneven structure for suppressing surface reflection and increasing the amount of light absorption, and is formed only on the light receiving surface of the silicon wafer 11, for example.

The silicon wafer 11 generally has a substantially square shape in a plan view in which four corners are cut diagonally. On the back surface of the silicon wafer 11, the first side 11A and the second side 11B facing each other, and the third side 11C and the fourth side 11D facing each other are parallel to each other. A hypotenuse 11E connecting the sides 11A and 11B and the sides 11C and 11D is formed at the corners of the silicon wafer 11. The lengths of the four sides 11A, 11B, 11C, and 11D are the same, and the lengths of the four hypotenuses 11E are the same. The thickness of the silicon wafer 11 is, for example, 50 μm to 300 μm.

The solar cell 10 includes an insulating layer 14 provided on the light receiving surface of the silicon wafer 11. In the example shown in FIG. 3, a passivation layer 15 is provided between the silicon wafer 11 and the insulating layer 14. The insulating layer 14 and the passivation layer 15 are preferably provided over substantially the entire light receiving surface of the silicon wafer 11. There are no electrodes on the light receiving surface of the silicon wafer 11. The solar cell 10 is a back surface bonding type cell in which electrodes are provided only on the back surface of the silicon wafer 11.

The insulating layer 14 is composed of a metal compound such as silicon nitride (SiN), silicon oxide, or silicon oxynitride. Of these, SiN is preferable. The passivation layer 15 is a layer that suppresses carrier recombination on the light receiving surface of the silicon wafer 11, and is, for example, substantially intrinsic amorphous silicon (hereinafter, may be referred to as “i-type amorphous silicon”). Alternatively, it is composed of amorphous silicon having a dopant concentration lower than that of the first amorphous semiconductor layer 12.

As described above, the back surface of the silicon wafer 11 is provided with the first amorphous semiconductor layer 12, the second amorphous semiconductor layer 13, the first plating electrode 20, and the second plating electrode 30. In the present embodiment, the silicon wafer 11 is an n-type single crystal silicon wafer, and the first amorphous semiconductor layer 12 is the same conductive n-type amorphous silicon layer and second amorphous semiconductor layer as the silicon wafer 11. Reference numeral 13 denotes a p-type amorphous silicon layer. On the back surface of the silicon wafer 11, an n-type region doped with n-type by the first amorphous semiconductor layer 12 and a p-type region doped with p-type by the second amorphous semiconductor layer 13 are formed. To.

The first amorphous semiconductor layer 12 is provided in the first region on the back surface of the silicon wafer 11, and the second amorphous semiconductor layer 13 is provided in the second region on the back surface of the silicon wafer 11. Further, an insulating layer 16 is provided on a part of the first amorphous semiconductor layer 12, and a second amorphous semiconductor layer 13 is provided on the second region and the insulating layer 16. In the present embodiment, on the back surface of the silicon wafer 11, the first region where the first amorphous semiconductor layer 12 is provided is an n-type region, and the second region where the second amorphous semiconductor layer 13 is provided is p. It becomes a type area. The p-type region forming the pn junction with the n-type silicon wafer 11 may be formed in a larger area than the n-type region.

The region where the first amorphous semiconductor layer 12 and the second amorphous semiconductor layer 13 are formed is formed in the entire area except the outer peripheral edge of the back surface of the silicon wafer 11, for example. Therefore, a part of the first amorphous semiconductor layer 12 and a part of the second amorphous semiconductor layer 13 overlap each other to form a film without a gap. In the present embodiment, a part of the second amorphous semiconductor layer 13 overlaps the first amorphous semiconductor layer 12 via the insulating layer 16, and each semiconductor layer is formed on the back side 11A of the silicon wafer 11. They are arranged in a stripe shape alternately arranged in the α direction along 11B. The insulating layer 16 is made of, for example, SiN, and is interposed between the semiconductor layers at a portion where the first amorphous semiconductor layer 12 and the second amorphous semiconductor layer 13 overlap.

The solar cell 10 may include a passivation layer interposed between the silicon wafer 11 and the first amorphous semiconductor layer 12 and between the silicon wafer 11 and the second amorphous semiconductor layer 13. The passivation layer is a layer that suppresses carrier recombination on the back surface of the silicon wafer 11, and is composed of, for example, i-type amorphous silicon or amorphous silicon having a dopant concentration lower than that of the corresponding amorphous semiconductor layer. Will be done.

It is preferable that the first amorphous semiconductor layer 12 is composed mainly of n-type amorphous silicon, and the second amorphous semiconductor layer 13 is mainly composed of p-type amorphous silicon. The concentration of the dopant in each semiconductor layer is, for example, 1 × 10 ²⁰ atoms / cm ³ or more. Boron (B) is generally used as the p-type dopant. An example of the thickness of each semiconductor layer is 1 to 25 nm. Each semiconductor layer can be deposited by CVD or sputtering. Further, the insulating layers 14 and 16 and the passivation layer can also be formed by CVD or sputtering.

The first plated electrode 20 is preferably provided on the first amorphous semiconductor layer 12 via the first transparent conductive layer 23. Similarly, the second plating electrode 30 is preferably provided on the second amorphous semiconductor layer 13 via the second transparent conductive layer 33. In the present embodiment, the first plating electrode 20 and the first transparent conductive layer 23 serve as n-side electrodes that collect carriers from the n-type region, and the second plating electrode 30 and the second transparent conductive layer 33 provide carriers from the p-type region. It becomes the p-side electrode to collect. The n-side electrode and the p-side electrode are separated by a groove formed in a groove shape.

The first plating electrode 20 and the second plating electrode 30 are formed by an electrolytic plating method. Each plated electrode is made of a metal such as nickel (Ni), copper (Cu), or silver (Ag), and may have a laminated structure of a Ni layer and a Cu layer, and is the outermost surface in order to improve corrosion resistance. May have a tin (Sn) layer. An example of the thickness of each plated electrode is 50 nm to 1 μm, and the first plated electrode 20 may be formed thicker than the second plated electrode 30.

The first transparent conductive layer 23 and the second transparent conductive layer 33 are generally composed of metal oxides such as indium oxide (In ₂ O ₃ ) and zinc oxide (ZnO), tungsten (W), Sn, and antimony (Sb). ) Etc. are doped with transparent conductive oxides (IWO, ITO, etc.). Each transparent conductive layer can be formed by sputtering. The thickness of each transparent conductive layer is, for example, 30 nm to 500 nm.

The first plated electrode 20 includes a plurality of first fingers 21 and a first bus bar 22 to which the plurality of first fingers 21 are connected. Similarly, the second plated electrode 30 includes a plurality of second fingers 31 and a second bus bar 32 to which the plurality of second fingers 31 are connected. The first bus bar 22 is provided at the second end along the second side 11B of the silicon wafer 11, and the second bus bar 32 is provided at the first end along the first side 11A parallel to the side 11B. Provided. Further, a part of the first bus bar 22 and the second bus bar 32 is provided along the hypotenuse 11E formed at the corner of the silicon wafer 11.

The plurality of first fingers 21 and the plurality of second fingers 31 extend in the β direction along the sides 11C and 11D in parallel with the third side 11C and the fourth side 11D of the silicon wafer 11. Further, the first finger 21 and the second finger 31 are alternately arranged in the α direction along the sides 11A and 11B. The first finger 21 and the first bus bar 22 have a plan-view comb-like shape in which they mesh with each other with a groove-like gap formed on the insulating layer 16.

As described above, the solar cell 10 has at least one plating contact portion 34 formed only on the first end portion along the first side 11A on the back surface of the silicon wafer 11. By limiting the formation location of the plating contact portion 34 to the first end portion of the silicon wafer 11, it is possible to suppress a decrease in the output of the solar cell 10 due to the provision of the plating contact portion 34. In the present embodiment, the plating contact portion 34 is formed on the second plating electrode 30 provided on the second amorphous semiconductor layer 13 of the conductive type (p type) different from the n-type silicon wafer 11.

The plating contact portion 34 is a connection mark of a terminal pin attached to the back surface of the silicon wafer 11 in the electrolytic plating process. The plating contact portion 34 has, for example, a metal plating layer, but the thickness thereof may be thinner than the thickness of other portions of the second plating electrode 30. The plan-view shape of the plating contact portion 34 depends on the shape of the terminal pin and is not particularly limited. There may be one plating contact portion 34, but a plurality of plating contact portions 34 are preferably formed at the first end portion on the back surface of the silicon wafer 11. In this case, it is easy to make the thickness of the plating layer uniform over a wide range on the back surface of the silicon wafer 11.

A plating pad portion 35 (plating feeding portion 35) including a plating contact portion 34 connected to the second bus bar 32 is formed at the first end portion of the silicon wafer 11. The plating pad portion 35 has a metal plating layer like the second bus bar 32, and forms a part of the second plating electrode 30. A plurality of second fingers 31 may extend from the plating pad portion 35. The portion to be the plating pad portion 35 is a portion to which the terminal pin is attached in the electrolytic plating process, and is provided in a size capable of attaching the terminal pin. There is no plating pad portion connected to the first plating electrode 20, and the plating pad portion is formed only on the first end portion of the silicon wafer 11.

The shape of the plating pad portion 35 is not particularly limited, but a preferable example is a rectangular shape in a plan view. The plating pad portion 35 can be said to be a convex portion formed by projecting a part of the second bus bar 32, and is formed by projecting a part of the second bus bar 32 inside the silicon wafer 11 to make it wider. To. The plating contact portion 34 may be formed in a portion adjacent to the plating pad portion 35 and the plating pad portion 35 of the second bus bar 32.

It is preferable that a plurality of plating pad portions 35 are formed at intervals in the α direction along the longitudinal direction of the second bus bar 32. In the example shown in FIG. 1, three plating pad portions 35 are formed at equal intervals in the longitudinal direction of the second bus bar 32. One of the plating pad portions 35 is formed at the central portion in the longitudinal direction of the second bus bar 32, and the other two are formed near the end portion in the longitudinal direction of the second bus bar 32, respectively. The plating contact portion 34 is formed on each plating pad portion 35. That is, a plurality of plating contact portions 34 are formed at the first end portion of the silicon wafer 11 at intervals in the longitudinal direction of the second bus bar 32.

FIG. 4 is an enlarged view of part C in FIG. As a comparative example, FIG. 5 shows the structure of a conventional solar cell in which a plating pad portion 50 forming a part of the first plating electrode 20 is formed. In FIGS. 4 and 5, of the regions where the first amorphous semiconductor layer 12 on the back surface of the silicon wafer 11 is formed, the region R1 (one of the n-type regions) directly formed on the back surface and in contact with the n-side electrode. Part) is indicated by diagonal hatching. Further, of the p-type region in which the second amorphous semiconductor layer 13 on the back surface of the silicon wafer 11 is formed, the region R2 (a part of the p-type region) directly formed on the back surface and in contact with the p-side electrode Shown by cross-hatching.

As shown in FIG. 4, in the solar cell 10, the plating pad portion does not exist on the second end portion side along the side 11B of the silicon wafer 11, and as described above, only on the first end portion of the silicon wafer 11. A plating pad portion 35 including a plating contact portion 34 is formed. In the solar cell 10, the plating pad portion is not formed on the first plating electrode 20. In this case, the area R2 can be extended to the vicinity of the first bus bar 22.

On the other hand, as shown in FIG. 5, when the plating pad portion 50 is formed, the region R2 overlapping the plating pad portion 50 in the β direction cannot be formed up to the vicinity of the first bus bar 22, and the length of the region R2 is different. It becomes shorter than the region R2 of. That is, in the solar cell 10, the area of the p-type region forming the pn junction region, which is the carrier separation region, can be increased as compared with the conventional solar cell having the plating pad portion 50, and the output characteristics are improved. improves. In other words, it is possible to suppress a decrease in output due to the provision of the plating pad portion 50.

Here, an example of a method for manufacturing the solar cell 10 having the above configuration will be described. In the manufacturing process of the solar cell 10, first, a silicon wafer 11 having a textured structure is prepared. For the silicon wafer 11, for example, an n-type single crystal silicon wafer in which a texture structure is formed only on one surface to be a light receiving surface is used. Next, the first amorphous semiconductor layer 12 and the insulating layer 16 are provided in this order on the other surface, which is the back surface of the silicon wafer 11. These layers are formed over substantially the entire area of the other surface.

Next, each of the above layers provided on the back surface of the silicon wafer 11 is patterned. Specifically, after etching the insulating layer 16, the exposed first amorphous semiconductor layer 12 is etched using the patterned insulating layer 16 as a mask. After that, the second amorphous semiconductor layer 13 is provided over substantially the entire area of the other surface of the silicon wafer 11. The portion formed on the insulating layer 16 of the second amorphous semiconductor layer 13 is patterned, and the exposed portion of the insulating layer 16 is etched to expose a part of the first amorphous semiconductor layer 12. Further, a passivation layer 15 and an insulating layer 14 are provided on one surface of the silicon wafer 11 in this order.

Next, a transparent conductive layer covering the entire area of the first amorphous semiconductor layer 12 and the second amorphous semiconductor layer 13 is provided. Then, a patterned resist film is placed on the transparent conductive layer. As the arrangement pattern of the resist film at this time, a pattern is used so that the completed solar cell can have the plating pad portion 35. After the resist film is provided, terminal pins are attached to the portion of the surface of the transparent conductive layer that becomes the plating pad portion 35 in the solar cell, and the metal plating layer is formed by electrolytic plating.

A plurality of terminal pins are, for example, clip-shaped members that sandwich the silicon wafer 11, and are attached to only the first end portion of the silicon wafer 11, and the silicon wafer 11 is immersed in the plating solution in a suspended state. When the terminal pin is attached only to the first end portion, the thickness of the metal plating layer tends to vary, but a uniform metal is obtained by slowly moving the silicon wafer 11 immersed in the plating solution or by flowing the plating solution. A plating layer can be formed.

The design of the first embodiment described above can be appropriately changed as long as the object of the present disclosure is not impaired. For example, the second embodiment shown in FIG. 6 differs from the first embodiment in that the first plating electrode 20 does not include a bus bar. The first plated electrode 20 is composed of only a plurality of first fingers 21 arranged in parallel with each other in the gaps between the plurality of second fingers 31, and each of the first fingers 21 is not electrically connected.

In the embodiment shown in FIG. 6, since the bus bar does not exist at the second end of the silicon wafer 11 along the side 11B, the first finger 21 and the second finger 31 extend to the vicinity of the side 11B which is the wafer edge. ing. In this case, the formation area of the p-type region forming the n-type silicon wafer 11 and the pn junction region is expanded, and further improvement in output characteristics is expected. In the form shown in FIG. 6, the distance from the side 11B to one end of each of the first finger 21 and each second finger 31 in the longitudinal direction is the same, and the positions of one end in the longitudinal direction of each finger are aligned.

The form illustrated in FIG. 7 is different from the form illustrated in FIG. 6 in that the first finger 21 extends toward the wafer edge side of the second finger 31. That is, the distance from the side 11B, which is the wafer edge, to one end in the longitudinal direction of each second finger 31 is longer than the distance from the side 11B to one end in the longitudinal direction of each first finger 21. In this case, when the solar cell 10 is modularized, it can be easily connected to adjacent cells by using a general strip-shaped wiring material. The second amorphous semiconductor layer 13 (p-type region) may extend beyond one end in the longitudinal direction of the second finger 31 toward the side 11B.

Further, in the above-described embodiment, the silicon wafer 11 is an n-type silicon wafer, but the silicon wafer 11 may be a p-type silicon wafer doped with a p-type. In this case, for example, the first amorphous semiconductor layer 12 is a p-type amorphous silicon layer, the first plating electrode 20 is a p-side electrode, and the second amorphous semiconductor layer 13 is an n-type amorphous silicon layer. Then, the second plating electrode 30 becomes the n-side electrode. The plating pad portion including the plating contact portion is preferably formed as a part of the second plating electrode 30 which is the n-side electrode. In other words, it is preferable that the p-side electrode does not have a plating pad portion.

Further, in the above-described embodiment, there is a plating pad portion 35 formed by projecting a part of the second bus bar 32, but the embodiment may not have such a plating pad portion. For example, the contact portion 34 for plating may be formed on the second bus bar 32 which is formed to be wide over the entire length.

10 Solar cell, 11 Silicon wafer, 12 1st amorphous semiconductor layer, 13 2nd amorphous semiconductor layer, 14, 16 Insulation layer, 15 Passivation layer, 20 1st plating electrode, 21 1st finger, 22nd 1 bus bar, 23 first transparent conductive layer, 24 plating contact part, 25 plating pad part, 30 second plating electrode, 31 second finger, 32 second bus bar, 33 second transparent conductive layer, 34 plating contact part, 35 Plated pad part

Claims (6)

A silicon wafer having a polygonal shape in a plan view having a first surface and a second surface,
A first conductive type first amorphous semiconductor layer provided on the first surface of the silicon wafer, and
A second conductive type second amorphous semiconductor layer provided on the first surface of the silicon wafer, and
The first plated electrode provided on the first amorphous semiconductor layer and
A second plated electrode provided on the second amorphous semiconductor layer and
With
A solar cell in which at least one plating contact portion is formed only at a first end portion along one side of a plurality of sides of the first surface of the silicon wafer. The silicon wafer is a first conductive type and has a first conductive type.
The solar cell according to claim 1, wherein the plating contact portion is formed on the second plating electrode. The second plating electrode includes a plurality of second fingers and a second bus bar provided at the first end portion of the silicon wafer and to which the plurality of second fingers are connected.
The solar cell according to claim 2, wherein a plating pad portion including the plating contact portion connected to the second bus bar is formed at the first end portion of the silicon wafer. The solar cell according to claim 3, wherein a plurality of plating pad portions are formed on the first end portion of the silicon wafer at intervals in the longitudinal direction of the second bus bar. The solar cell according to any one of claims 1 to 4, wherein the first plated electrode is composed of only a plurality of first fingers arranged in parallel with each other. The solar cell according to claim 5, wherein at the second end portion facing the first end portion of the silicon wafer, the first finger extends toward the wafer edge side of the second finger.

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