JP2020160907A - Regulator circuit - Google Patents

Abstract

To realize an output current detection circuit that can detect an output current with high accuracy in a regulator circuit.SOLUTION: A regulator circuit is comprised of: a voltage divider circuit that divides a voltage of an output terminal to generate a feedback voltage; an error amplifier that outputs a voltage according to a deviation of a feedback voltage with respect to a reference voltage; an output transistor; and an output current detection circuit that detects an output current flowing through an output terminal. The output transistor outputs a constant voltage to the output terminal by outputting a current corresponding to the output voltage of the error amplifier. The output current detection circuit includes: a first current detection circuit configured to detect a current flowing through the output transistor; a second current detection circuit configured to detect a current flowing through the voltage divider circuit; and an output circuit configured to output a current or a voltage according to a difference between the current detected by the first current detection circuit and the current detected by the second current detection circuit.SELECTED DRAWING: Figure 1

Description

The present invention relates to a regulator circuit.

The regulator circuit is a circuit configured to supply a constant voltage flow to a load, and is mainly built in a semiconductor integrated device as a power supply circuit such as an IC or a sensor. In such a regulator circuit, if the output current exceeds the rated current of the load, the load may be damaged. Therefore, for the purpose of overcurrent protection, an output current detection circuit for detecting the output current may be provided inside the regulator circuit.

For example, Japanese Patent Application Laid-Open No. 2005-215716 (Patent Document 1) discloses a configuration in which a detection resistor for detecting an output current is connected between an output transistor and an output terminal. In this configuration, the output current is detected by detecting the voltage drop that occurs in the detection resistor.

Further, Japanese Patent Application Laid-Open No. 2007-226392 (Patent Document 2) discloses a configuration in which a current detection transistor for detecting an output current and a detection resistor are connected in series. In this configuration, a current proportional to the current flowing through the output transistor flows through the current detection transistor. The output current is detected by detecting the voltage drop caused by the current flowing through the detection resistor.

Japanese Unexamined Patent Publication No. 2005-215716 JP-A-2007-226392

However, the output current detection circuit described in the above patent document cannot detect a pure output current, and detects a current including a bias current. Therefore, there is a concern that an offset error depending on the bias current may occur in the detected current.

The present invention has been made to solve the above problems, and an object of the present invention is to realize an output current detection circuit capable of accurately detecting an output current in a regulator circuit.

The regulator circuit according to the present invention generates a constant voltage based on a reference voltage and outputs it to an output terminal. The regulator circuit is a voltage dividing circuit that divides the voltage of the output terminal to generate a feedback voltage, an error amplifier that outputs a voltage corresponding to the deviation of the feedback voltage with respect to the reference voltage, and a current corresponding to the output voltage of the error amplifier. It includes an output transistor that outputs a constant voltage to the output terminal by outputting, and an output current detection circuit that detects the output current flowing through the output terminal. The output current detection circuit includes a first current detection circuit configured to detect the current flowing through the output transistor, a second current detection circuit configured to detect the current flowing through the voltage dividing circuit, and a second current detection circuit. It includes an output circuit configured to output a current or a voltage corresponding to a difference between the current detected by the current detection circuit 1 and the current detected by the second current detection circuit.

According to the present invention, the output current of the regulator circuit can be detected with high accuracy.

It is a circuit diagram which shows the structure of the regulator circuit which concerns on Embodiment 1. FIG. It is a circuit diagram which shows the structure of the regulator circuit which concerns on Embodiment 2. It is a circuit diagram which shows the structure of the regulator circuit which concerns on Embodiment 3. It is a circuit diagram which shows the structure of the regulator circuit which concerns on Embodiment 4. FIG. It is a circuit diagram which shows the structure of the regulator circuit which concerns on Embodiment 5. It is a circuit diagram which shows the structure of the regulator circuit which concerns on Embodiment 6. It is a circuit diagram which shows the 1st structural example of the output current detection circuit of the regulator circuit which concerns on the prior art example. It is a circuit diagram which shows the 2nd structural example of the output current detection circuit of the regulator circuit which concerns on the prior art example. It is a circuit diagram which shows the structural example of a general regulator circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the figure are designated by the same reference numerals, and the explanations are not repeated in principle.

<Example of general regulator circuit configuration>
FIG. 9 is a circuit diagram showing a configuration example of a general regulator circuit.

With reference to FIG. 9, the regulator circuit includes an error amplifier 2, an output transistor 3, resistors R1 and R2, and an output terminal T1. The output transistor 3, the resistor R2, and the resistor R1 are electrically connected in series between the power supply line PL that supplies the power supply voltage VDD and the ground line NL that supplies the ground voltage GND. The feedback voltage V2 is output to the node between the resistors R2 and R1.

The output transistor 3 outputs a current or a voltage to the load. As the output transistor 3, a MOSFET (Metal Oxide Semiconductor Filed Effect Transistor), a bipolar transistor, or the like is used. In the example of FIG. 9, the output transistor 3 is a p-type MOSFET. The power supply voltage VDD is supplied to the source of the output transistor 3, and the step-down output voltage VOUT is output to the drain.

The resistor R2 is connected between the output terminal T1 and the ground wire NL. The resistor R1 is connected between the resistor R2 and the ground wire NL. The resistors R1 and R2 function as output voltage adjusting resistors for adjusting the output voltage VOUT.

The error amplifier 2 receives the reference voltage VREF at the inverting input terminal (-terminal) and the feedback voltage V2 at the non-inverting input terminal (+ terminal). The output terminal of the error amplifier 2 is connected to the gate of the output transistor 3. The error amplifier 2 compares the reference voltage VREF with the feedback voltage V2, and controls the voltage V3 applied to the gate of the output transistor 3 so that the deviation of the feedback voltage V2 with respect to the reference voltage VREF becomes zero.

When the open gain of the error amplifier 2 is sufficiently high, the inverting input terminal and the non-inverting input terminal are virtually grounded, so that the reference voltage VREF and the feedback voltage V2 become equal. Therefore, assuming that the resistance values of the resistors R1 and R2 are R1 and R2, respectively, the current I2 (hereinafter, also referred to as "bias current") flowing through the output voltage adjusting resistors R1 and R2 is represented by the following equation (1). ..

Further, the output voltage VOUT is represented by the product of the bias current I2 and the sum of the resistance values (= R1 + R2) of the output voltage adjusting resistors R1 and R2, as shown in the following equation (2).

In this way, the regulator circuit is configured to output a stable output voltage VOUT from the power supply voltage VDD to the output terminal T1. The regulator circuit is a power supply circuit for supplying power to a load (for example, an external circuit such as a sensor and an IC) connected to the output terminal T1. The regulator circuit may be provided with an output current detection circuit for detecting the output current I3 for overcurrent protection. Various circuit configurations have been proposed for the output current detection circuit as described below.

<Configuration example of output current detection circuit of regulator circuit according to the conventional example>
FIG. 7 is a circuit diagram showing a first configuration example of the output current detection circuit of the regulator circuit according to the conventional example. With reference to FIG. 7, the output current detection circuit according to the first configuration example is composed of a detection resistor Rsense for detecting the output current I3. The detection resistor Rsense is connected between the drain of the output transistor 3 and the output terminal T1. In the following, the resistance value of the detection resistor Rsense will be referred to as Rsense.

The drain-source current I1 of the output transistor 3 flows through the detection resistor Rsense. In the first configuration example, the detection of the output current I3 is realized by detecting the voltage Vunitor generated between the terminals of the detection resistor Rsense.

Here, the drain-source current I1 of the output transistor 3 is the sum (= I2 + I3) of the output current I3 and the bias current I2. Therefore, the voltage Vunitor generated in the detection resistor Rsense is represented by the following equation (3).

As is clear from the equation (3), the voltage Vunitor includes a voltage component based on the bias current I2. Therefore, the pure output current I3 cannot be detected depending on the voltage Vunitor.

Here, if the detection resistor Rsense is connected in series with the load instead of the first configuration example, the voltage Vunitor is the product of the output current I3 and the resistance value of the detection resistor Rsense. Therefore, it is possible to detect the pure output current I3 based on the voltage Vunitor. However, since the power supply supplied to the load is affected by the voltage drop caused by the voltage Vunitor generated in the detection resistor Rsense, the constant voltage function of the regulator circuit is lost.

FIG. 8 is a circuit diagram showing a second configuration example of the output current detection circuit of the regulator circuit according to the conventional example. With reference to FIG. 8, the output current detection circuit according to the second configuration example includes a current detection transistor 4 for detecting the output current I3 and a detection resistor Rsense. The current detection transistor 4 is electrically connected between the power supply line PL and the detection resistor Rsense. The detection resistor Rsense is electrically connected between the current detection transistor 4 and the ground wire NL.

As the current detection transistor 4, a MOSFET, a bipolar transistor, or the like is used. In the example of FIG. 8, the current detection transistor 4 is a p-type MOSFET. A power supply voltage VDD is supplied to the source of the current detection transistor 4, and a detection resistor Rsense is connected to the drain. The gate of the current detection transistor 4 is connected to the output terminal of the error amplifier 2 and the gate of the output transistor 3.

The drain-source current I4 of the current detection transistor 4 flows through the detection resistor Rsense. In the second configuration example, the detection of the output current I3 is realized by detecting the voltage Vunitor generated between the terminals of the detection resistor Rsense.

Specifically, since the output transistor 3 and the current detection transistor 4 have the same gate-source voltage, the drain-source current I1 of the output transistor 3 and the drain-source current I4 of the current detection transistor 4 The ratio with and is determined by the size ratio of the two transistors 3 and 4.

Further, the drain-source current I1 of the output transistor 3 is the sum of the output current I3 and the bias current I2 (= I2 + I3). Therefore, assuming that the size ratio of the current detection transistor 4 and the output transistor 3 is 1: N, the voltage Vunitor generated in the detection resistor Rsense can be expressed by the following equation (4).

As is clear from the equation (4), the voltage Vunitor includes a voltage component based on the bias current I2. Therefore, the pure output current I3 cannot be detected depending on the voltage Vunitor.

As described above, the output current detection circuit of the regulator circuit according to the conventional example cannot detect the pure output current I3, but detects the current including the bias current I2. Therefore, there is a concern that the detected current may have an offset error depending on the bias current I2.

Therefore, in the present embodiment, a novel configuration of an output current detection circuit capable of detecting a pure output current I3 from which the bias current I2 has been removed is provided.

<Structure of output current detection circuit of regulator circuit according to the embodiment>
Embodiment 1.
FIG. 1 is a circuit diagram showing a configuration of a regulator circuit according to a first embodiment.

With reference to FIG. 1, the regulator circuit according to the first embodiment includes an error amplifier 2, an output transistor 3, output voltage adjusting resistors R1 and R2, and an output terminal T1. Since the connection relationship between the error amplifier 2, the output transistor 3, and the output voltage adjusting resistors R1 and R2 is the same as the general regulator circuit shown in FIG. 9, the description will not be repeated.

The regulator circuit according to the first embodiment further includes a current source 1 and a resistor R3. The current source 1 and the resistor R3 are electrically connected in series between the power supply line PL and the ground line NL. The current source 1 outputs the current I0. The voltage V1 is output to the node between the current source 1 and the resistor R3. Assuming that the resistance value of the resistor R3 is R3, the voltage V1 is represented by the product of the current I0 and the resistance value of the resistor R3 (V1 = I0 · R3). The voltage V1 is input to the inverting input terminal (− terminal) of the error amplifier 2 as a reference voltage. The resistor R3 functions as a reference voltage adjusting resistor for adjusting the reference voltage.

The error amplifier 2 receives a reference voltage V1 at the inverting input terminal (− terminal) and a feedback voltage V2 at the non-inverting input terminal (+ terminal). The error amplifier 2 compares the reference voltage V1 and the feedback voltage V2, and controls the voltage V3 applied to the gate of the output transistor 3 so that the deviation of the feedback voltage V2 with respect to the reference voltage V1 becomes zero. When the open gain of the error amplifier 2 is sufficiently high, the reference voltage V1 and the feedback voltage V2 are equal to each other, so that the bias current I2 flowing through the output voltage adjusting resistors R1 and R2 is represented by the following equation (5). ..

Further, the drain-source current I1 of the output transistor 3 is the sum of the output current I3 and the bias current I2, and is therefore expressed by the following equation (6).

The regulator circuit according to the first embodiment further includes a current detection transistor 4 for detecting the output current I3, a current sink 5, and an output terminal T2 as an output current detection circuit for detecting the output current I3. Be prepared.

The current detection transistor 4 is electrically connected between the power supply line PL and the current sink 5. The current sink 5 is electrically connected between the current detection transistor 4 and the ground wire NL. The current I5 flows into the current sink 5. The node between the current detection transistor 4 and the current sink 5 is connected to the output terminal T2. A current immertor (hereinafter, also referred to as “detection current”) for detecting the output current I3 is output to the output terminal T2.

The current detection transistor 4 is, for example, a p-type MOSFET. The power supply voltage VDD is supplied to the source of the current detection transistor 4, and the current sink 5 is connected to the drain. The gate of the current detection transistor 4 is connected to the output terminal of the error amplifier 2 and the gate of the output transistor 3.

Since the output transistor 3 and the current detection transistor 4 have the same gate-source voltage, the ratio of the drain-source current I1 of the output transistor 3 to the drain-source current I4 of the current detection transistor 4 is It is determined by the size ratio of the two transistors 3 and 4. Assuming that the size ratio of the current detection transistor 4 and the output transistor 3 is 1: N, the drain-source current I4 of the current detection transistor 4 can be expressed by the following equation (7).

In the output current detection circuit, the detection current Indicator output to the output terminal T2 is obtained by subtracting the current I5 flowing through the current sink 5 from the drain / source current I4 of the current detection transistor 4 as shown in the following equation (8). It becomes an electric current.

By controlling the current sink 5 so that the current I5 flowing through the current sink 5 satisfies the following equation (9), the equation (8) can be transformed as in the following equation (10). That is, the detected current Indicator is a current obtained by multiplying the output current I3 by 1 / N.

As described above, the output current detection circuit according to the first embodiment detects the current I4 obtained by multiplying the drain-source current I1 of the output transistor 3 by 1 / N by the current detection transistor 4, and biases it by the current sink 5. It is configured to generate a current I5 obtained by multiplying the current I2 by 1 / N, and output a detected current transistor obtained by subtracting the current I5 from the current I4 to the output terminal T2. The current detection transistor 4 corresponds to an embodiment of the "first current detection circuit", the current sink 5 corresponds to an embodiment of the "second current detection circuit", and the output terminal T2 corresponds to the "output circuit". Corresponds to one embodiment.

According to this, since the output current detection circuit can detect the current indicator proportional to the output current I3, it is possible to detect the pure output current I3 from which the bias current I2 is removed based on the detection current indicator. ..

Embodiment 2.
In the second embodiment, a specific circuit configuration example of the output current detection circuit according to the first embodiment will be described.

FIG. 2 is a circuit diagram showing the configuration of the regulator circuit according to the second embodiment.
With reference to FIG. 2, the output current detection circuit according to the second embodiment includes a current detection transistor 4, a current sink 5, and an output terminal T2. The current sink 5 has current mirrors 7 and 8, a current sink 6, and a resistor R4.

The current mirror 7 is configured to amplify the input current Iin to a current gain of J times and output it as an output current Iout1, and to amplify the input current Iin to a current gain of K times and output it as an output current Iout2. The current I0 flowing through the current sink 6 is input to the input terminal Iin of the current mirror 7. The current mirror 7 outputs a current I6 obtained by amplifying the input current I0 by J times to the first output terminal Iout1, and outputs a current I7 obtained by amplifying the input current I0 by K times to the second output terminal Iout2. That is, the current I6 is a current obtained by multiplying the current I0 by K, and the current I7 is a current obtained by multiplying the current I0 by K.

The resistor R4 is connected between the first output terminal Iout1 of the current mirror 7 and the ground wire NL. The node between the first output terminal Iout1 and the resistor R4 is connected to the inverting input terminal (− terminal) of the error amplifier 2. Assuming that the resistance value of the resistor R4 is R4, the reference voltage V1 input to the inverting input terminal of the error amplifier 2 is the product of the current I6 and the resistance value R4 of the resistor R4 (= I6, R4 = J, I0, R4). It is represented by. That is, the resistor R4 functions as a reference voltage adjusting resistor.

The second output terminal Iout2 of the current mirror 7 is connected to the input terminal Iin of the current mirror 8. The output terminal Iout of the current mirror 8 is connected to the drain of the current detection transistor 4 and the output terminal T2. The current mirror 8 is configured to amplify the input current M times the current gain and output it. The input current of the current mirror 8 is the output current I7 of the current mirror 7, and the output current of the current mirror 8 is the current I5. That is, the current I5 is a current obtained by multiplying the current I7 by M.

According to the first embodiment described above, by adjusting the current I5 flowing through the current sink 5 in FIG. 2 so as to satisfy the above equation (9), the detection current Importor obtained by multiplying the output current I3 by 1 / N is detected. can do.

In the second embodiment, since the reference voltage V1 = I6, R4 = j, I0, R4, the equation (9) can be transformed into the following equation (11).

The ratio of the left side I5 and the right side I0 of the equation (11) corresponds to the product (= KM) of the current gains K and M of the current mirrors 7 and 8. Therefore, if the current gains J, K, and M of the current mirrors 7 and 8 are adjusted so as to satisfy the relationship of the following equation (12), it is possible to detect the pure output current I3 of the regulator circuit from the detected current Indicator. Become.

As shown in FIG. 2, by connecting the detection resistor Rsense between the output terminal T2 and the ground wire NL, the detection current Image is detected as the detection voltage Vunitor by using the voltage drop generated by the detection resistor Rsense. be able to. However, it is desirable to use a high-precision resistor for the detection resistor Rsense.

Embodiment 3.
FIG. 3 is a circuit diagram showing the configuration of the regulator circuit according to the third embodiment.

With reference to FIG. 3, the regulator circuit according to the third embodiment includes an error amplifier 2, an output transistor 3, output voltage adjusting resistors R1 and R2, and an output terminal T1. Since the connection relationship between the error amplifier 2, the output transistor 3, and the output voltage adjusting resistors R1 and R2 is the same as the general regulator circuit shown in FIG. 7, the description will not be repeated.

The regulator circuit according to the third embodiment includes a current detection transistor 4 and a voltage / current conversion circuit 9 as an output current detection circuit for detecting the output current I3. The current detection transistor 4 is, for example, a p-type MOSFET. The power supply voltage VDD is supplied to the source of the current detection transistor 4, and the voltage / current conversion circuit 9 and the output terminal T2 are connected to the drain. The gate of the current detection transistor 4 is connected to the output terminal of the error amplifier 2 and the gate of the output transistor 3. The voltage / current conversion circuit 9 is electrically connected between the node between the resistors R1 and R2 and the output terminal T2. The detection current Importor is output to the output terminal T2.

In the regulator circuit according to the third embodiment, as in the regulator circuit according to the first embodiment shown in FIG. 1, the output transistor 3 and the current detection transistor 4 have the same gate-source voltage, so that current detection is performed. The drain-source current I4 of the transistor 4 can be expressed by the equation (7).

As a result, the detection current Indicator output to the output terminal T2 is also represented by the equation (8), and is the current obtained by subtracting the current I5 flowing through the voltage / current conversion circuit 9 from the drain / source current I4 of the current detection transistor 4. Become.

Therefore, by designing the voltage / current conversion circuit 9 so that the current I5 flowing through the voltage / current conversion circuit 9 satisfies the equation (9), the pure output current I3 of the regulator circuit can be detected from the detection current Indicator. Can be done.

Specifically, the voltage / current conversion circuit 9 is configured to convert the feedback voltage V2 output from the output voltage adjusting resistors R1 and R2 into the current I5. Since the reference voltage V1 and the feedback voltage V2 are equal to each other in the error amplifier 2, the voltage / current conversion circuit 9 may be designed to have the voltage / current conversion characteristics represented by the following equation (13).

As described above, the output current detection circuit of the regulator circuit according to the third embodiment detects the current I4 obtained by multiplying the drain-source current I1 of the output transistor 3 by 1 / N by the current detection transistor 4, and also detects the voltage / current. The conversion circuit 9 is configured to detect the current I5 obtained by multiplying the bias current I2 by 1 / N, and output the detected current Importor obtained by subtracting the current I5 from the current I4 to the output terminal T2. The current detection transistor 4 corresponds to an embodiment of the "first current detection circuit", the voltage / current conversion circuit 9 corresponds to an embodiment of the "second current detection circuit", and the output terminal T2 corresponds to the "second current detection circuit". Corresponds to one embodiment of "output circuit".

According to this, since the output current detection circuit can detect the current unitor obtained by multiplying the output current I3 by 1 / N, the pure output current I3 from which the bias current I2 is removed is detected based on the detected current unitor. be able to.

Embodiment 4.
In the fourth embodiment, a specific circuit configuration example of the output current detection circuit according to the third embodiment will be described.

FIG. 4 is a circuit diagram showing the configuration of the regulator circuit according to the fourth embodiment.
With reference to FIG. 4, the output current detection circuit according to the fourth embodiment includes a current detection transistor 4, a voltage / current conversion circuit 9, and an output terminal T2. The voltage / current conversion circuit 9 includes an operational amplifier 10, a resistor R5, a transistor 11, and current mirrors 12 and 13.

The current mirrors 12 and 13 are configured to amplify the input current by a current gain of M times and output the output current. A transistor 11 and a resistor R5 are electrically connected in series between the input terminal Iin of the current mirror 12 and the ground wire NL. As the transistor 11, a MOSFET, a bipolar transistor, or the like is used. In the example of FIG. 4, the transistor 11 is an n-type MOSFET. The drain of the transistor 11 is connected to the input terminal Iin of the current mirror 12, and the source of the transistor 11 is connected to the resistor R5. The gate of the transistor 11 is connected to the output terminal of the operational amplifier 10.

The operational amplifier 10 receives the feedback voltage V2 at the inverting input terminal (− terminal) and the voltage V4 of the node between the transistor 11 and the resistor R5 at the non-inverting input terminal (+ terminal). When the open gain of the operational amplifier 10 is sufficiently high, the voltage V4 becomes equal to the feedback voltage V2 due to virtual grounding. Similarly, since the reference voltage V1 and the feedback voltage V2 are equal to each other in the error amplifier 2, the current I7 flowing through the transistor 11 and the resistor R5 can be expressed by the following equation (14).

The current mirrors 12 and 13 output a current I5 obtained by amplifying the input current I7 M times.
As described in the third embodiment, the voltage / current conversion circuit 9 is designed so that the current I5 flowing through the voltage / current conversion circuit 9 satisfies the above equation (9), so that the detection current Image can be changed to the regulator circuit. A pure output current I3 can be detected. According to the above equations (9) and (14), the relationship shown in the following equation (15) is established between the input current I7 of the current mirror 12 and the output current I5 of the current mirror 13.

In other words, the current I5 output from the voltage / current conversion circuit 9 satisfies the equation (9) by adjusting the current gains M of the current mirrors 12 and 13 so as to satisfy the relationship shown in the equation (15). Can be done.

As shown in FIG. 4, by connecting the detection resistor Rsense between the output terminal T2 and the ground wire NL, the detection current Image can be detected as the detection voltage Vmotor by the voltage drop generated by the detection resistor Rsense. it can. However, it is desirable to use a high-precision resistor for the detection resistor Rsense.

Embodiment 5.
FIG. 5 is a circuit diagram showing the configuration of the regulator circuit according to the fifth embodiment.

With reference to FIG. 5, the regulator circuit according to the fifth embodiment includes an error amplifier 2, an output transistor 3, output voltage adjusting resistors R1 and R2, and an output terminal T1. Since the connection relationship between the error amplifier 2, the output transistor 3, and the output voltage adjusting resistors R1 and R2 is the same as the general regulator circuit shown in FIG. 7, the description will not be repeated.

The regulator circuit according to the fifth embodiment has detection resistors Rsense1 and Rsense2, an addition circuit 14, a subtraction circuit 15, and an output terminal T2 as output current detection circuits for detecting the output current I3.

The detection resistors Rsense1 and Rsense2 are electrically connected in series between the drain of the output transistor 3 and the resistor R2. The node between the detection resistor Rsense1 and the detection resistor Rsense2 is electrically connected to the output terminal T1. Hereinafter, the resistance values of the detection resistors Rsense1 and Rsense2 will be referred to as Rsense1 and Rsense2.

The error amplifier 2 receives a reference voltage V1 at the inverting input terminal (− terminal) and a feedback voltage V2 at the non-inverting input terminal (+ terminal). The output terminal of the error amplifier 2 is connected to the gate of the output transistor 3. The error amplifier 2 compares the reference voltage V1 and the feedback voltage V2, and controls the voltage V3 applied to the gate of the output transistor 3 so that the deviation of the feedback voltage V2 with respect to the reference voltage V1 becomes zero. When the open gain of the error amplifier 2 is sufficiently high, the reference voltage V1 and the feedback voltage V2 are equal to each other. Therefore, the bias current I2 flowing through the detection resistor Rsense2 and the output voltage adjustment resistors R1 and R2 is expressed by the following equation (16). ).

Further, the output voltage VOUT is represented by the product of the bias current I2 and the sum of the resistance values of the detection resistor Rsense2 and the output voltage adjustment resistors R1 and R2 (= Rsense2 + R1 + R2) as shown in the following equation (17). ..

By making the sum of the resistance values (= Rsense2 + R2) in the right side of the equation (17) equal to the resistance value R2 in the right side of the equation (2), that is, the resistance value of the resistor R2 in FIG. 5 is set to FIG. By setting the value to be smaller by Rsense2 than the resistance value of the resistor R2, the operation of the regulator circuit according to the fifth embodiment is the same as the operation of the general regulator circuit shown in FIG.

The voltage V6 of the node between the detection resistor Rsense2 and the output voltage adjusting resistor R2 is the voltage obtained by subtracting the voltage drop in the detection resistor Rsense2 from the output voltage VOUT, and is represented by the following equation (18).

Further, the drain-source current I1 of the output transistor 3 is the sum of the bias current I2 and the output current I3 as shown in the following equation (19).

Therefore, the voltage V5 of the node between the output transistor 3 and the detection resistor Rsense1 is the voltage obtained by adding the voltage drop in the detection resistor Rsense1 to the output voltage VOUT. Using the equation (19), the following equation (20) is used. expressed.

In the present embodiment, it is desirable that the input impedances of the adder circuit 14 and the subtractor circuit 15 are high. When the input impedance of the adder circuit 14 is low, the bias current I2 flowing through the regulator circuit increases. This can be corrected by the output current detection circuit. On the other hand, if the input impedance of the subtraction circuit 15 is low, the output current I3 of the regulator circuit increases. This causes an offset error in the output current detection circuit. Therefore, in order to detect the output current with high accuracy, it is necessary to set the input impedance of the subtraction circuit 15 high. In the present embodiment, for simplification of the description, it is assumed that the input impedances of the adder circuit 14 and the subtractor circuit 15 are high.

The addition circuit 14 adds the voltage obtained by multiplying the voltage V5 by a and the voltage obtained by multiplying the voltage V6 by b, and outputs the voltage V7 which is the addition result. The coefficients a and b can be arbitrary values. The voltage V7 is given by the following equation (21).

The right side of the equation (21) has a term of output voltage VOUT, a term of output current I3, and a term of bias current I2. Here, if the values of the coefficients a and b and the resistance values of the detection resistors Rsense1 and Rsense2 are set so as to satisfy the relationship of the following equation (22), the term of the bias current I2 is eliminated from the right side of the equation (21). can do.

According to this, the equation (21) can be rewritten as the following equation (23).

The subtraction circuit 15 subtracts the voltage obtained by multiplying the output voltage VOUT by d from the voltage obtained by multiplying the output voltage V7 of the addition circuit 14 by c, and outputs the detection voltage Vunitor as the subtraction result. The coefficients c and d can be arbitrary values. Using equation (23), the detection voltage Vunitor is given by equation (24):

The right side of the equation (24) has a term of output voltage VOUT and a term of output current I3. Here, if the values of the coefficients c and d are set so as to satisfy the relationship of the following equation (25), the term of the output voltage VOUT can be eliminated from the right side of the equation (24).

According to this, the equation (24) can be rewritten as the following equation (26). According to the equation (26), the pure output current I3 can be detected from the detection voltage Vunitor.

As described above, in the output current detection circuit according to the fifth embodiment, the coefficients a and b of the addition circuit 14 and the coefficients c and d of the subtraction circuit 15 satisfy the relationship of the equations (22) and (25). By setting to, the detection voltage Vunitor proportional to the output voltage I3 can be output to the output terminal T2, so that the pure output current I3 can be detected. The detection resistor Rsense1 corresponds to an embodiment of the "first current detection circuit", and the detection resistor Rsense2 corresponds to an embodiment of the "second current detection circuit", and the adder circuit 14, the subtractor circuit 15, and the output terminal T2 corresponds to one embodiment of the "output circuit".

Embodiment 6.
In the sixth embodiment, a specific circuit configuration example of the output current detection circuit according to the fifth embodiment will be described.

FIG. 6 is a circuit diagram showing the configuration of the regulator circuit according to the sixth embodiment.
With reference to FIG. 6, the output current detection circuit according to the sixth embodiment includes operational amplifiers 16 to 18, resistors R6 to R8, and detection resistors Rsense1 and Rsense2. The operational amplifier 16 and the resistor R6 form the adder circuit 14 shown in FIG. The operational amplifiers 17 and 18 and the resistors R7 and R8 form the subtraction circuit 15 shown in FIG.

The input voltages V5 and V6 of the adder circuit 14 are represented by the above equations (18) and (20). In the example of FIG. 6, the adder circuit 14 is configured to add a voltage obtained by multiplying the voltage V5 by 1 and a voltage obtained by multiplying the voltage V6 by 1. That is, since a = b = 1, if the resistance values of the detection resistors Rsense1 and Rsense2 are set to Rsense1 = Rsense2, the relationship shown in the equation (22) can be satisfied. In the following description, the resistance values of the detection resistors Rsense1 and Rsense2 are defined as Rsense.

A voltage V9 is input to the inverting input terminal (− terminal) of the operational amplifier 16. An arbitrary voltage V8 is input to the non-inverting input terminal (+ terminal) of the operational amplifier 16. Assuming that V9 = V8 is established by virtual grounding in the operational amplifier 16, the output voltage V7 of the adder circuit 14 (corresponding to the output voltage of the operational amplifier 16) can be expressed by the following equation (27).

The subtraction circuit 15 is configured to subtract the voltage obtained by multiplying the output voltage VOUT by the voltage obtained by multiplying the voltage V7 by 1. That is, in equation (24), c = 1 and d = 2. The relationship of Eq. (25) is established between the coefficients a, b, c, and d.

In the configuration example of FIG. 6, the amplification factor of the output voltage VOUT can be doubled by setting the resistance value of the resistor R8 to 1/2 of the resistance value of the resistor R7.

The voltage V10 is input to the inverting input terminal (− terminal) of the operational amplifier 17. An arbitrary voltage V8 is input to the non-inverting input terminal (+ terminal) of the operational amplifier 17. Assuming that V10 = V8 holds in the operational amplifier 17, the output voltage of the subtraction circuit 15 (corresponding to the detected voltage Vunitor) can be expressed by the equation (28).

As shown in the formula (28), the detection voltage Vunitor is a voltage obtained by adding an arbitrary voltage V8 to the product of the output current I3 and the resistance values Rsense of the detection resistors Rsense1 and Rsense2. According to this, the pure output current I3 can be detected from the detection voltage Vunitor with reference to an arbitrary voltage V8.

In the present invention, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the invention.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The present invention is shown by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

1 Current source, 2 Error amplifier, 3 Output transistor, 4 Current detection transistor, 5, 6 Current sink, 7, 8, 12, 13 Current mirror, 9 Voltage / current conversion circuit, 10, 16-18 operational amplifier, 14 Addition Circuit, 15 subtraction circuit, PL power supply line, NL ground line, Rsense, Rsense1, Rsense2 detection resistor, R1, R2 output voltage adjustment resistor, R3, R4 reference voltage adjustment resistor, R5 to R8 resistor, T1, T2 output terminal ..

Claims (4)

A regulator circuit that generates a constant voltage based on the reference voltage and outputs it to the output terminal.
A voltage divider circuit that divides the voltage of the output terminal to generate a feedback voltage,
An error amplifier that outputs a voltage corresponding to the deviation of the feedback voltage with respect to the reference voltage,
An output transistor that outputs the constant voltage to the output terminal by outputting a current corresponding to the output voltage of the error amplifier.
It is equipped with an output current detection circuit that detects the output current flowing through the output terminal.
The output current detection circuit
A first current detection circuit configured to detect the current flowing through the output transistor, and
A second current detection circuit configured to detect the current flowing through the voltage divider circuit, and
A regulator circuit including an output circuit configured to output a current or voltage corresponding to a difference between a current detected by the first current detection circuit and a current detected by the second current detection circuit. The first current detection circuit includes a first transistor that outputs a current proportional to the current flowing through the output transistor according to the output voltage of the error amplifier.
The second current detection circuit includes a current sink configured to suck in a current proportional to the current flowing through the voltage dividing circuit.
The first transistor and the current sink are electrically connected in series and
The regulator circuit according to claim 1, wherein the output circuit is connected to a node between the first transistor and the current sink. The first current detection circuit includes a first transistor that outputs a current proportional to the current flowing through the output transistor according to the output voltage of the error amplifier.
The second current detection circuit includes a voltage-current conversion circuit that converts the feedback voltage into a current proportional to the current flowing through the voltage dividing circuit.
The regulator circuit according to claim 1, wherein the output circuit outputs a current or a voltage corresponding to a difference between a current flowing through the first transistor and a current flowing through the voltage-current conversion circuit. The first current detection circuit includes a first resistor connected between the output transistor and the output terminal.
The second current detection circuit includes a second resistor connected between the output terminal and the voltage divider circuit.
The output circuit includes an addition / subtraction circuit that adds / subtracts a voltage drop caused in the first resistor by a current flowing through the output transistor and a voltage drop caused in the second resistor by a current flowing through the voltage dividing circuit. The regulator circuit described in.

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