JP2020159797A - Circuit verification device and circuit verification method - Google Patents

Abstract

To provide a circuit verification device with which it is possible to verify a circuit composed by connecting two or more function circuits selected from a plurality of function circuits included in a verification target circuit.SOLUTION: A circuit verification device connects to a verification target circuit having a plurality of function circuits and a verification counter circuit having a counter circuit corresponding to each of the function circuits and having functionality opposite input and output relation of said function circuits, compares the output of the verification target circuit with the output of the counter circuit that ideally produces the same output as said output and determines whether or not the function circuits included in the verification target circuit are normal, compares the output of the plurality of n-1 or less function circuits connected in series which are selected from among a total number n of function circuits included in the verification target circuit with the output of a circuit composed of the respective counter circuits to these function circuits that are connected in series and determines whether or not the series circuit consisting of the selected function circuits is normal.SELECTED DRAWING: Figure 1

Description

The present invention relates to a circuit verification device and a circuit verification method.

FIG. 9 shows a verification environment 10 using the verification counter circuit 120. In the verification environment 10, the function verification data generation circuit 110 generates function verification data. The verification opposed circuit 120 is a circuit provided for verifying the verified circuit 20, and when the verified circuit 20 is a circuit that outputs a value b when the value a is input, the verification opposed circuit 120 is a value. This is a circuit that outputs a value a when b is input.

Now, suppose that the function verification data generation circuit 110 generates the value a and outputs it to the verification counter circuit 120. In this case, the verification counter circuit 120 inputs the value a and outputs the value b to the verified circuit 20 and the analysis circuit 130. The circuit to be verified 20 inputs the value b and outputs the value a. The analysis circuit 130 determines whether the relationship between the value b input from the verification counter circuit 120 and the value a input from the verified circuit 20 is correct, and if it is correct, determines that the operation of the verified circuit 20 is correct. .. The display device 30 outputs the determination result of the analysis circuit 130. In the case of such a verification environment 10, only analysis (determination) of whether or not the relationship between the value input to the verified circuit 20 and the value output by the verified circuit 20 is correct can be performed. Therefore, when verifying a circuit having a large circuit scale and incorporating a plurality of functions, it takes time to identify a functional error portion in the circuit to be verified 20.

Patent Document 1 describes a function verification method for verifying the function of each functional circuit of the verified circuit by using the opposite functional circuits of each of the plurality of functional circuits of the verified circuit whose function is to be verified. ing.
Further, Patent Document 2 describes a diagnostic circuit capable of detecting an interface failure of the circuit to be verified.

JP-A-2003-044539 Japanese Unexamined Patent Publication No. 11-064465

Here, the technique described in Patent Document 1 can verify each of a plurality of functional circuits in the circuit to be verified, but is composed of a plurality of circuits selected from the plurality of functional circuits included in the circuit to be verified. It is not possible to verify a group of circuits at once. That is, it is not possible to connect a plurality of selected functional circuits and regard them as one circuit, and verify the circuits at once. Therefore, it is not possible to confirm the correctness of the relationship between the input and the output by linking any plurality of connected functional circuits among the plurality of circuits of the circuit to be verified at once.

Therefore, an object of the present invention is to provide a circuit verification device and a circuit verification method that solve the above-mentioned problems.

According to the first aspect of the present invention, the circuit verification device includes a circuit to be verified having a plurality of functional circuits and the functional circuit having a function in which the input and output of the functional circuit have an opposite relationship. The verified opposed circuit having the corresponding opposed circuit, the connection portion connected to, the output of the verified circuit, and the output of the opposed circuit which ideally outputs the same output as the said output are compared with each other. The analysis circuit includes an analysis circuit for determining whether or not the functional circuit included in the circuit is normal, and the analysis circuit is the number of n-1 selected from the total number n of the functional circuits included in the circuit to be verified. Comparing the outputs of the plurality of functional circuits connected in series below with the outputs of the circuits in which the opposite circuits of the functional circuits are connected in series, the series circuit by the selected functional circuit is normal. It is characterized in that it is determined whether or not.

According to the second aspect of the present invention, the circuit verification method is applied to each of the verified circuit having a plurality of functional circuits and the functional circuit having a function in which the input and output relationships of the functional circuits are opposite to each other. The output of the circuit to be verified is included in the circuit to be verified by connecting to a verification facing circuit having a corresponding counter circuit and comparing the output of the circuit to be verified with the output of the counter circuit which ideally outputs the same output as the output. It is determined whether or not the functional circuit is normal, and the output of the plurality of functional circuits connected in series equal to or less than the number of selected n-1 among the total number n of the functional circuits included in the verified circuit. The present invention is characterized in that it is determined whether or not the series circuit by the selected functional circuit is normal or not by comparing the output of the circuit in which each opposite circuit of the functional circuits is connected in series.

According to the present invention, it is possible to verify a circuit in which a plurality of selected functional circuits included in the circuit to be verified are connected.

It is a block diagram which shows the structure of the circuit verification system provided with the circuit verification apparatus by one Embodiment of this invention. It is the first figure which shows the processing flow of the circuit verification apparatus by one Embodiment of this invention. It is the first figure which shows an example of the output data of each functional circuit and each opposite circuit by one Embodiment of this invention. It is a 2nd figure which shows the processing flow of the circuit verification apparatus by one Embodiment of this invention. It is a second figure which shows an example of the output data of each functional circuit and each opposite circuit by one Embodiment of this invention. It is a third figure which shows the processing flow of the circuit verification apparatus by one Embodiment of this invention. It is a third figure which shows an example of the output data of each functional circuit and each opposite circuit by one Embodiment of this invention. It is a figure which shows the minimum structure of the circuit verification apparatus by one Embodiment of this invention. It is a figure which shows the related verification environment.

Hereinafter, a circuit verification device according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a circuit verification system including a circuit verification device according to the same embodiment.
As shown in FIG. 1, the circuit verification system 100 includes, for example, a circuit verification device 1, a circuit to be verified 2, a first display device 3, and a second display device 4.

The circuit to be verified 2 is an example of a circuit to be verified for function, which is a target for verifying the function. The circuit to be verified 2 includes a plurality of functional circuits of a function A circuit 21A that executes a function A, a function B circuit 21B that executes a function B, and a function C circuit 21C that executes a function C, a first selector 24, and a first selector 24. It has a second selector 25. Further, the circuit to be verified 2 constitutes a first series circuit in which the function A circuit 21A, the function B circuit 21B, and the function C circuit 21C are connected in series in that order. Hereinafter, for convenience of explanation, the function A circuit 21A, the function B circuit 21B, and the function C circuit 21C may be collectively referred to as the function circuit 21.

The function circuit 21 (function A circuit 21A, function B circuit 21B, and function C circuit 21C) has a conversion function for converting an input value into an output value which is another value, and a conversion function and an input value of the conversion function. When the output value among the output values is input, it further has a function of converting the output value and outputting the input value (hereinafter, referred to as "opposite function"). That is, when the conversion function of the functional circuit 21 inputs the value a at the first input unit, converts the value a and outputs the value b from the first output unit, the functional circuit 21 outputs the value b at the second input unit. It has an opposite function to input and output the value a from the second output unit. In the present embodiment, the functional circuit 21 (functional A circuit 21A, functional B circuit 21B, and functional C circuit 21C) is described in the circuit diagram from the circuit verification device side (left side in the figure) to the first input unit (A11, B11, When the value input in C11) is output from the first output unit (A12, B12, C12) on the other side (right side in the figure), the data is converted by the conversion function, and the data is converted from the analysis circuit 13 side (right side in the figure). When the value input in the two input units (A21, B21, C21) is output from the second output unit (A22, B22, C22) on the circuit verification device 1 side (left side in the figure), the data is converted by the opposite function. ..

The first selector 24 is a selector circuit that selects data to be input back to the second input unit A21 of the function A circuit 21A. The data selected by the first selector 24 can be switched by switch control. In the present embodiment, as an example, either the data converted by the function A circuit 21A by the conversion function and output from the first output unit A12, or the data converted by the function B circuit 21B by the opposite function and output from the second output unit B22. Select. When the function A circuit 21A converts the data by the conversion function and selects the data output from the first output unit A12, the first selector 24 outputs the data to the second input unit A21 of the function A circuit 21A. Further, when the function B circuit 21B converts the data by the opposite function and selects the data output from the second output unit B22, the first selector 24 outputs the data to the second input unit A21 to the function A circuit 21A. The data selected by the first selector 24 is also output to the first analysis circuit 131.

The second selector 25 is a selector circuit that selects data to be input back to the second input unit B21 of the function B circuit 21B. The data selected by the second selector 25 can be switched by switch control. In the present embodiment, as an example, the second selector 25 is converted by the function B circuit 21B by the conversion function and output from the first output unit B12, or the function C circuit 21C is converted by the opposite function and is converted from the second output unit C22. Select one of the output data. When the function B circuit 21B converts the data by the conversion function and selects the data output from the first output unit B12, the second selector 25 outputs the data to the second input unit B21 of the function B circuit 21B. Further, when the function C circuit 21C converts the data by the opposite function and selects the data output from the second output unit C22, the second selector 25 outputs the data to the second input unit B21 of the function B circuit 21B. The data selected by the second selector 25 is also output to the first analysis circuit 131.

The circuit verification device 1 verifies the function of the circuit to be verified 2 having the plurality of functional circuits 21. The circuit verification device 1 includes a function verification data generation circuit 11, a verification counter circuit 12, an analysis circuit 13, and a connection portion 14.

The function verification data generation circuit 11 generates function verification data for verifying the circuit to be verified 2. The functional verification data may be, for example, a test pattern such as a simple number string. The function verification data generation circuit 11 outputs the generated function verification data to the verification counter circuit 12 and the first analysis circuit 131.

The verification counter circuit 12 has a function c (opposite function of function C) having a function c (opposite function of function C) of converting the input value of the function C circuit 21C of the circuit to be verified 2 and performing inverse conversion when the output value is output. The input value of the function b facing circuit 121b having the function b (opposing function of the function B) and the input value of the function A circuit 21A for performing the inverse conversion when the input value of the function B circuit 21B is converted and the output value is output. It has a function a facing circuit 121a having a function a (opposing function of function A) for performing inverse conversion when converting and outputting an output value. Hereinafter, for convenience of explanation, the function c opposed circuit 121c, the function b opposed circuit 121b, and the function a opposed circuit 121a may be generically referred to as an opposed circuit 121. Further, the verification opposite circuit 12 is a series of the functional circuits 21 in the first series circuit of the circuit to be verified 2, and the opposite circuit 121 corresponding to the functional circuits 21 of the corresponding functional circuit 21 in the first series circuit. A second series circuit connected in series in the reverse order is configured. That is, the verification facing circuit 12 constitutes a second series circuit in which the function c facing circuit 121c, the function b facing circuit 121b, and the function a facing circuit 121a are connected in series in that order.

The functional verification data input to the verification counter circuit 12 is input to the function c counter circuit 121c. The function c facing circuit 121c executes the facing function of the function C with respect to the function verification data, and outputs the execution result to the function b facing circuit 121b and the first analysis circuit 131.
The function b facing circuit 121b executes the facing function of the function B with respect to the data input from the function c facing circuit 121c, and outputs the execution result to the function a facing circuit 121a and the first analysis circuit 131.
The function a facing circuit 121a executes the facing function of the function A with respect to the data input from the function b facing circuit 121b, and outputs the execution result to the verified circuit 2, the first analysis circuit 131, and the second analysis circuit 132. To do.

The analysis circuit 13 includes a first analysis circuit 131 and a second analysis circuit 132.
The first analysis circuit 131 compares the output of each functional circuit 21 of the verified circuit 2 with the output of the counter circuit 121 which ideally outputs the same output as the output, and includes the functional circuit included in the verified circuit 2. It is determined whether or not 21 is normal. Further, the first analysis circuit 131 includes the outputs of a plurality of functional circuits 21 connected in series equal to or less than the number of selected n-1s out of the total number n of the functional circuits 21 included in the verified circuit 2, and their functions. It is determined whether or not the series circuit by the selected functional circuit 21 is normal by comparing with the output of the circuit in which each opposite circuit 121 of the circuit 21 is connected in series. Further, the first analysis circuit 131 compares the output when the output of the verified circuit 2 is input back to the verified circuit 2 with the output of the verification opposed circuit 12, and is a functional circuit included in the verified circuit 2. It is determined whether or not 21 is normal. Further, the first analysis circuit 131 compares the output when the output of the functional circuit 21 is folded back into the functional circuit 21 and the output of the counter circuit 121 corresponding to the functional circuit 21 to be verified. It is determined whether or not the functional circuit 21 included in 2 is normal. Further, the first analysis circuit 131 outputs a plurality of outputs of a plurality of functional circuits 21 connected in series equal to or less than the number of selected n-1s out of the total number n of the functional circuits 21 included in the circuit to be verified 2. The output when the second input is made to the series circuit by the function circuit 21 is compared with the output of the circuit in which each of the opposite circuits 121 of the function circuit 21 is connected in series, and the series by the selected function circuit 21 is compared. Determine if the circuit is normal.

The second analysis circuit 132 compares the output of the verified circuit 2 with the output of the verified opposed circuit 12 to determine whether or not the functional circuit 21 included in the verified circuit 2 is normal.

The first display device 3 is a liquid crystal display, an organic EL (Electro-Luminescence) display, or the like, and displays the verification result (OK or NG) in the first analysis circuit 131.
The second display device 4 is a liquid crystal display, an organic EL display, or the like, and displays a verification result (OK or NG) in the second analysis circuit 132.

FIG. 2 is a first diagram showing a processing flow of the circuit verification device.
FIG. 3 is a first diagram showing an example of output data of each functional circuit and each opposite circuit.
Next, the processing by the circuit verification device 1 will be described.
First, a case where each functional circuit 21 of the circuit to be verified 2 is individually verified will be described. Here, the switch of the first selector 24 selects the data output from the first output unit A21 of the function A circuit 21A, and the switch of the second selector 25 is output from the first output unit B12 of the function B circuit 21B. Data is selected.

First, the function verification data generation circuit 11 generates the function verification data D0 (step S101). Subsequently, the function verification data generation circuit 11 inputs the function verification data D0 to the function c opposite circuit 121c of the verification opposed circuit 12 (step S102). Further, the function verification data generation circuit 11 outputs the function verification data D0 to the first analysis circuit 131.

The function c facing circuit 121c executes the facing function of the function C with respect to the function verification data D0, and outputs the output data D1 which is the execution result to the function b facing circuit 121b and the first analysis circuit 131. The function b facing circuit 121b executes the facing function of the function B with respect to the input data D1, and outputs the output data D2 which is the execution result to the function a facing circuit 121a and the first analysis circuit 131. The function a opposite circuit 121a executes the opposite function of the function A with respect to the input data D2, and outputs the output data D3, which is the execution result, to the verified circuit 2, the first analysis circuit 131, and the second analysis circuit 132. That is, the verification counter circuit 12 inputs the output data D3 having the function verification data D0 as an input to the verified circuit 2 (step S103).

The output data D3 of the verification counter circuit 12 is input to the function A circuit 21A of the verification circuit 2. The function A circuit 21A executes the function A with respect to the input data D3, and outputs the output data D10 which is the execution result to the function B circuit 21B and the first selector 24. The first selector 24 outputs the output data D10 of the function A circuit 21A to the first analysis circuit 131. Further, the first selector 24 returns the output data D10 of the function A circuit 21A to the function A circuit 21A. The function A circuit 21A executes the opposite function of the function A on the return input data D10, and outputs the output data D11 which is the execution result to the first analysis circuit 131.

The function B circuit 21B executes the function B with respect to the output data D10 of the function A circuit 21A, and outputs the output data D20 which is the execution result to the function C circuit 21C and the second selector 25. The second selector 25 outputs the output data D20 of the function B circuit 21B to the first analysis circuit 131. Further, the second selector 25 returns the output data D20 of the function B circuit 21B to the function B circuit 21B. The function B circuit 21B executes the opposite function of the function B with respect to the return input data D20, and outputs the output data D21 which is the execution result to the first selector 24. The first selector 24 outputs the data D21 input from the function B circuit 21B to the first analysis circuit 131.

The function C circuit 21C executes the function C on the output data D20 of the function B circuit 21B, and outputs the output data D30 which is the execution result to the second analysis circuit 132. The second analysis circuit 132 outputs the output data D30 of the function C circuit 21C to the first analysis circuit 131.

Further, the second analysis circuit 132 returns and inputs the output data D30 of the verified circuit 2 to the verified circuit 2 (step S104). The function C circuit 21C of the circuit to be verified 2 executes the opposite function of the function C with respect to the data D30 input in return, and outputs the output data D31 which is the execution result to the second selector 25. The second selector 25 outputs the data D31 input from the function C circuit 21C to the first analysis circuit 131.

The first analysis circuit 131 compares the output data of each functional circuit 21 with the input data to the corresponding opposite circuits 121, and notifies the result by displaying the result on the first display device 3 (step S105). .. More specifically, the first analysis circuit 131 compares the output data D10 of the function A circuit 21A with the input data D2 to the function a counter circuit 121a (output data D2 of the function b counter circuit 121b) and matches. If this is the case, the verification of the function A circuit 21A is OK, and if they do not match, the verification of the function A circuit 21A is NG. Further, the first analysis circuit 131 compares the output data D20 of the function B circuit 21B with the input data D1 to the function b facing circuit 121b (output data D1 of the function c facing circuit 121c), and functions when they match. The verification of the B circuit 21B is OK, and if they do not match, the verification of the function B circuit 21B is NG. Further, the first analysis circuit 131 compares the output data D30 of the function C circuit 21C with the input data D0 (function verification data D0) to the function c opposite circuit 121c, and if they match, the function C circuit 21C is verified. If it is OK and does not match, the verification of the function C circuit 21C is NG.

Further, the first analysis circuit 131 includes the output data when the output data of each functional circuit 21 is input back to the functional circuit 21 (hereinafter referred to as “folded output data”) and the output of each corresponding opposite circuit 121. The data is compared with the data, and the result is displayed on the first display device 3 to notify the data (step S106). More specifically, the first analysis circuit 131 compares the folded output data D11 of the function A circuit 21A with the output data D3 of the function a counter circuit 121a, and if they match, the verification of the function A circuit 21A is OK. If they do not match, the verification of the function A circuit 21A is NG. Further, the first analysis circuit 131 compares the folded output data D21 of the function B circuit 21B with the output data D2 of the function b opposite circuit 121b, and if they match, the verification of the function B circuit 21B is OK, and if they do not match. The verification of the function B circuit 21B is NG. Further, the first analysis circuit 131 compares the folded output data D31 of the function C circuit 21C with the output data D1 of the function c opposite circuit 121c, and if they match, the verification of the function C circuit 21C is OK, and if they do not match. The verification of the function C circuit 21C is NG.

Further, the second analysis circuit 132 compares the output data D3 (input data to the verified circuit 2) of the verification opposed circuit 12 with the output data D30 of the verified circuit 2, and displays the result on the second display device 4. Notify by displaying (step S107). For example, the second analysis circuit 132 is preset with output data for input data to the circuit to be verified 2. The second analysis circuit 132 performs verification based on the set information. Then the process ends.

By the above processing, the first analysis circuit 131 has the output of the function A circuit 21A, the function B circuit 21B, and the function C circuit 21C included in the verified circuit 2, and the function c that ideally outputs the same output as the output. By comparing the outputs of the counter circuit 121c, the function b counter circuit 121b, and the function a counter circuit 121a, the function A circuit 21A, the function B circuit 21B, and the function C circuit 21C included in the verified circuit 2 are individually analyzed. Judge whether it is normal or not. That is, the operation can be determined for each functional circuit 21 constituting the verified circuit 2. This makes it easy to identify an error portion (functional circuit 21) of the function constituting the circuit to be verified 2. Further, since the analysis circuit 13 automatically verifies the output data, it is not necessary for a person to analyze the output data of the circuit to be verified 2.

Further, since the outputs of the circuits constituting the verification opposed circuit 12 and the circuit to be verified 2 can be applied as data for functional verification (analysis), each functional circuit 21 included in the circuit to be verified 2 is verified. There is no need to create new data for each.

FIG. 4 is a second diagram showing a processing flow of the circuit verification device.
FIG. 5 is a second diagram showing an example of output data of each functional circuit and each opposite circuit.
Subsequently, out of the total of 3 of the function A circuit 21A, the function B circuit 21B, and the function C circuit 21C included in the verified circuit 2, is the series circuit by the function circuit 21 connected in series of the selected 2 normal? A case of verifying whether or not it is verified will be described. Hereinafter, a case of verifying a series circuit by the function A circuit 21A and the function B circuit 21B will be described as an example. Here, in the verified circuit 2, the switch of the first selector 24 selects the data output from the second output unit B22 of the function B circuit 21B, and the switch of the second selector 25 is the first output unit of the function B circuit 21B. Controls to select the data output from B12.

Since the processes from step S201 to step S203 are the same as the processes from steps S101 to S103 described above, the description thereof will be omitted.

The output data D3 of the verification counter circuit 12 is input to the function A circuit 21A of the verification circuit 2. The function A circuit 21A executes the function A with respect to the input data D3, and outputs the output data D10 which is the execution result from the first output unit A12.

The function B circuit 21B executes the function B with respect to the output data D10 of the function A circuit 21A, and outputs the output data D20 which is the execution result to the function C circuit 21C and the second selector 25. The second selector 25 outputs the output data D20 of the function B circuit 21B to the first analysis circuit 131. Further, the second selector 25 returns the output data D20 of the function B circuit 21B to the second input unit B21 of the function B circuit 21B. The function B circuit 21B executes the opposite function of the function B with respect to the return input data D20, and outputs the output data D21 which is the execution result to the first selector 24. The first selector 24 returns the data D21 input from the function B circuit 21B to the second input unit A21 of the function A circuit 21A. The function A circuit 21A executes the opposite function of the function A on the return input data D21, and outputs the output data D22 which is the execution result from the second output unit A22 to the first analysis circuit 131.

The function C circuit 21C executes the function C on the output data D20 of the function B circuit 21B, and outputs the output data D30 which is the execution result to the second analysis circuit 132. The second analysis circuit 132 outputs the output data D30 of the function C circuit 21C to the first analysis circuit 131.

Further, the second analysis circuit 132 returns and inputs the output data D30 of the verified circuit 2 to the verified circuit 2 (step S204). The function C circuit 21C of the circuit to be verified 2 executes the opposite function of the function C with respect to the data D30 which is input back in the second input unit C21, and outputs the output data D31 which is the execution result from the second output unit C22. Output to 2 selector 25. Since the switch of the second selector 25 selects the data D20 output from the first output unit B12 of the function B circuit 21B, the data D31 input from the function C circuit 21C is not input.

The first analysis circuit 131 compares the output data of the series circuit by the function A circuit 21A and the function B circuit 21B with the input data to the series circuit by the corresponding function b opposite circuit 121b and the function a opposite circuit 121a. , The result is notified by displaying it on the first display device 3 (step S205). More specifically, the first analysis circuit 131 compares the output data D20 of the function B circuit 21B with the input data D1 to the function b opposite circuit 121b (output data D1 of the function c opposite circuit 121c) and matches. If so, the verification of the series circuit by the function A circuit 21A and the function B circuit 21B is OK, and if they do not match, the verification of the series circuit by the function A circuit 21A and the function B circuit 21B is NG. Further, the first analysis circuit 131 compares the output data D30 of the function C circuit 21C with the input data D0 (function verification data D0) to the function c opposite circuit 121c, and if they match, the function C circuit 21C is verified. If it is OK and does not match, the verification of the function C circuit 21C is NG.

Further, the first analysis circuit 131 compares the folded output data of the series circuit by the function A circuit 21A and the function B circuit 21B with the output data of the series circuit by the corresponding function b opposite circuit 121b and the function a opposite circuit 121a. Then, the result is notified by displaying it on the first display device 3 (step S206). More specifically, the first analysis circuit 131 includes the folded output data D22 of the series circuit by the function A circuit 21A and the function B circuit 21B, and the output of the series circuit by the function b facing circuit 121b and the function a facing circuit 121a. Comparing with the data D3, if they match, the verification of the series circuit by the function A circuit 21A and the function B circuit 21B is OK, and if they do not match, the verification of the series circuit by the function A circuit 21A and the function B circuit 21B is NG. To do. Further, the first analysis circuit 131 compares the folded output data D31 of the function C circuit 21C with the output data D1 of the function c opposite circuit 121c, and if they match, the verification of the function C circuit 21C is OK, and if they do not match. The verification of the function C circuit 21C is NG.

Since the process of step S207 is the same as the process of step S107 described above, the description thereof will be omitted.

In the above-mentioned example, it is verified whether or not the series circuit by the function A circuit 21A and the function B circuit 21B connected in series is normal, but the switch of the first selector 24 is set up and the first selector 24 is set. By setting the switch of the 2 selector 25 downward, it is possible to verify whether or not the series circuit by the function B circuit 21B and the function C circuit 21C is normal by the same processing.

By the above processing, in the first analysis circuit 131, the output of the circuit in which the plurality of functional circuits 21 included in the verified circuit 2 are connected in series and the opposite circuits 121 of the functional circuits 21 are connected in series. By comparing with the output of the circuit, it is determined whether or not the circuit in series by the selected plurality of functional circuits 21 is normal. As a result, the operation can be determined for each circuit in series by the plurality of selected functional circuits 21, so that the cooperation of the plurality of functional circuits 21 can be verified.

FIG. 6 is a third diagram showing a processing flow of the circuit verification device.
FIG. 7 is a third diagram showing an example of output data of each functional circuit and each opposite circuit.
Subsequently, a case of verifying whether or not the entire circuit to be verified 2 is normal will be described. Here, the switch of the first selector 24 selects the data output by the second output unit B22 of the function B circuit 21B, and the switch of the second selector 25 selects the data output by the second output unit C22 of the function C circuit 21C. Is controlled to select.

Since the processes from step S301 to step S303 are the same as the processes from steps S101 to S103 described above, the description thereof will be omitted.

The output data D3 of the verification counter circuit 12 is input to the function A circuit 21A of the verification circuit 2. The function A circuit 21A inputs the input data D3 in the first input unit A11, executes the function A for the gargle input data D3, and outputs the output data D10 which is the execution result from the first output unit A12 to the function B circuit. Output to 21B and the first selector 24.

The function B circuit 21B inputs the output data D10 of the function A circuit 21A to the first input unit B11, executes the function B on the output data D10, and outputs the output data D20 which is the execution result to the first output unit B12. Outputs to the function C circuit 21C and the second selector 25.

The function C circuit 21C inputs the output data D20 of the function B circuit 21B at the first input unit C11, executes the function C on the output data 20, and outputs the output data D30 which is the execution result to the second analysis circuit 132. Output to. The second analysis circuit 132 outputs the output data D30 of the function C circuit 21C to the second input unit C21 and the first analysis circuit 131 of the function C circuit 21C.

The function C circuit 21C of the circuit to be verified 2 inputs the output data D30 of the circuit to be verified 2 back at the second input unit C21 (step S304). The function C circuit 21C of the circuit to be verified 2 executes the opposite function of the function C with respect to the return input data D30, and outputs the output data D31 which is the execution result from the second output unit C22 to the second selector 25. .. The second selector 25 returns the data D31 input from the function C circuit 21C to the function B circuit 21B. Further, the second selector 25 selects the data D31 input from the function C circuit 21C and outputs the data D31 to the first analysis circuit 131. The function B circuit 21B executes the opposite function of the function B with respect to the return input data D31, and outputs the output data D32 which is the execution result to the first selector 24. The first selector 24 returns the data D32 input from the function B circuit 21B to the function A circuit 21A. Further, the first selector 24 selects the data D32 input from the function B circuit 21B and outputs the data D32 to the first analysis circuit 131. The function A circuit 21A executes the opposite function of the function A on the return input data D32, and outputs the output data D33 which is the execution result to the first analysis circuit 131.

The first analysis circuit 131 compares the output data D30 of the circuit to be verified 2 with the input data D0 (function verification data D0) to the verification counter circuit 12 and displays the result on the first display device 3. Notify (step S305). More specifically, the first analysis circuit 131 compares the output data D30 of the circuit to be verified 2 with the function verification data D0, and if they match, the verification of the entire circuit 2 to be verified 2 is OK, and if they do not match, the verification is OK. The verification of the entire circuit to be verified 2 is NG.

Further, the first analysis circuit 131 compares the folded output data D33 of the verified circuit 2 with the output data D3 of the verification counter circuit 12 and notifies the result by displaying the result on the first display device 3 (step S306). ). More specifically, the first analysis circuit 131 compares the folded output data D33 of the verified circuit 2 with the output data D3 of the verification opposed circuit 12, and if they match, the verification of the entire verified circuit 2 is OK. If they do not match, the verification of the entire circuit to be verified 2 is NG.

Since the process of step S307 is the same as the process of step S107 described above, the description thereof will be omitted.

By the above-mentioned processing, the first analysis circuit 131 compares the output of the verified circuit 2 with the output of the verification opposed circuit 12 to determine whether or not the entire verified circuit 2 is normal. This makes it possible to determine the operation of the circuit to be verified 2 as a whole.

The processing of steps S105 to S107, the processing of steps S205 to S207, and the processing of steps S305 to S307 described above do not have to be in this processing order. For example, the processes of the first analysis circuit 131 and the second analysis circuit 132 may be executed in parallel.

In the above-described embodiment, the case where the total number n of the functional circuits 21 included in the verified circuit 2 is 3 has been described as an example, but the present invention is not limited to this, and the number of functional circuits 21 included in the verified circuit 2 may be plural. It may be 2, or it may be 4 or more.

Further, in the above-described embodiment, the first selector 24 and the second selector 25 switch the data to be selected by the switch that can be manually operated, but the present invention is not limited to this, and for example, the signal is the first selector 24 and the second selector 24 and the second selector The data to be selected may be switched by inputting to the selector 25.

FIG. 8 is a diagram showing the minimum configuration of the circuit verification device.
The circuit verification device 1 exhibits at least the functions of the connection unit 14 and the analysis circuit 13.
The connection unit 14 has a verification facing circuit 2 having a plurality of functional circuits 21 and a counter circuit 121 corresponding to each of the functional circuits 21 having a function in which the input and output relationships of the functional circuits 21 are opposite to each other. It is connected to the circuit 12.
The analysis circuit 13 compares the output of the verified circuit 2 with the output of the counter circuit 121 which ideally outputs the same output as the output, and determines whether or not the functional circuit 21 included in the verified circuit 2 is normal. judge. Further, the analysis circuit 13 includes the outputs of a plurality of functional circuits 21 connected in series equal to or less than the number of selected n-1s out of the total number n of the functional circuits 21 included in the verified circuit 2, and the output of the functional circuits 21. It is determined whether or not the series circuit by the selected functional circuit 21 is normal by comparing with the output of the circuit in which each opposite circuit 121 is connected in series.

The circuit verification device 1 described above may have a computer system inside. The process of each process described above is stored in a computer-readable recording medium in the form of a program, and the process is performed by the computer reading and executing this program. Here, the computer-readable recording medium refers to a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Further, this computer program may be distributed to a computer via a communication line, and the computer receiving the distribution may execute the program.

Further, the above program may be for realizing a part of the above-mentioned functions. Further, a so-called difference file (difference program) may be used, which can realize the above-mentioned functions in combination with a program already recorded in the computer system.

100 ... Circuit verification system 1 ... Circuit verification device 11 ... Function verification data generation circuit 12 ... Verification Opposite circuit 121a ... Function a Opposite circuit 121b ... Function b Opposite circuit 121c ... Function c Opposed circuit 13 ... Analysis circuit 131 ... First analysis circuit 132 ... Second analysis circuit 14 ... Connection part 2 ... Tested circuit 21A ... Function A circuit 21B ... Function B circuit 21C ... Function C circuit 24 ... 1st selector 25 ... 2nd selector 3 ... 1st display device 4 ... 2nd display device

According to the first aspect of the present invention, the circuit verification device is a functional circuit and has a conversion function of converting an input input value into an output value and outputting the output value of the input own circuit into the input value. a circuit to be verified with a plurality of said functional circuitry to perform the opposite function of converting and outputting, opposing circuit relation between the input and output of the functional circuit respectively corresponding to said functional circuit having a function as a reverse relationship The output of the circuit to be verified is included in the circuit to be verified by comparing the output of the circuit to be verified and the output of the counter circuit which ideally outputs the same output as the output. The analysis circuit includes an analysis circuit for determining whether or not the functional circuit is normal, and the analysis circuit is connected in series of n-1 or less selected from the total number n of the functional circuits included in the verified circuit. When the output values of a plurality of connected functional circuits are input to the functional circuit, the output converted by using the opposite function is compared with the output of the circuit in which the opposite circuits of the functional circuits are connected in series. Then, it is characterized in that it is determined whether or not the circuit in series by the selected functional circuit is normal.

According to the second aspect of the present invention, the circuit verification method is a functional circuit having a conversion function of converting an input input value into an output value and outputting the output value of the input own circuit into the input value. a circuit to be verified with a plurality of said functional circuitry to perform the opposite function of converting and outputting, opposing circuit relation between the input and output of the functional circuit respectively corresponding to said functional circuit having a function as a reverse relationship The functional circuit included in the verified circuit is included in the verified circuit by comparing the output of the tested circuit with the output of the counter circuit that ideally outputs the same output as the output. Is normal or not, and among the total number n of the functional circuits included in the verified circuit, the output values of a plurality of the functional circuits connected in series equal to or less than the number of selected n-1s are used as the function. The output converted by using the opposite function when input to the circuit is compared with the output of the circuit in which each opposite circuit of those functional circuits is connected in series, and the series circuit by the selected functional circuit is obtained. It is characterized by determining whether or not it is normal.

Claims (7)

A connection unit connected to a circuit to be verified having a plurality of functional circuits and a verification counter circuit having a counter circuit corresponding to each of the functional circuits having a function in which the input and output of the functional circuit have a reverse relationship. When,
An analysis circuit that compares the output of the circuit to be verified with the output of the counter circuit that ideally outputs the same output as the output to determine whether or not the functional circuit included in the circuit to be verified is normal. ,
With
In the analysis circuit, the outputs of a plurality of the functional circuits connected in series equal to or less than the number of selected n-1 among the total number n of the functional circuits included in the verified circuit, and each of the functional circuits facing each other. A circuit verification device that compares the output of a circuit in which circuits are connected in series with the output of a circuit in which the circuits are connected in series to determine whether or not the circuit in series by the selected functional circuit is normal. The connection part
The circuit to be verified, which constitutes the first series circuit in which the functional circuits are connected in series,
A second series in which the order of the functional circuits in the first series circuit and the opposite circuits corresponding to those functional circuits are connected in series in the reverse order of the order of the corresponding functional circuits in the first series circuit. The verification opposed circuit constituting the series circuit and
The circuit verification device according to claim 1, which is connected to. Claim 1 or claim 2 that the analysis circuit compares the output of the verified circuit with the output of the verified opposed circuit to determine whether or not the functional circuit included in the verified circuit is normal. The circuit verification device described in 1. The functional circuit further has an opposite function in which the relationship between the input and the output of the functional circuit is opposite, and has a conversion function of converting the input input value into an output value and outputting the input value, and the input output value. Execute the opposite function that converts to the input value and outputs it,
The analysis circuit compares the output of the verified circuit with the output converted by using the opposite function when the output value is input to the verified circuit, and compares the output of the verified circuit with the output of the verified circuit. The circuit verification device according to any one of claims 1 to 3, which determines whether or not the functional circuit included in the verification circuit is normal. When the output of the functional circuit is input to the functional circuit, the analysis circuit compares the output of the opposite function with the output of the opposite circuit corresponding to the functional circuit, and includes the said circuit to be verified. The circuit verification device according to claim 4, wherein it determines whether or not the functional circuit is normal. In the analysis circuit, out of the total number n of the functional circuits included in the circuit to be verified, the outputs of a plurality of the functional circuits connected in series equal to or less than the number of selected n-1s are serialized by the plurality of functional circuits. The output of the opposite function when input to the circuit of is compared with the output of the circuit in which each opposite circuit of those functional circuits is connected in series, and whether or not the circuit in series by the selected functional circuit is normal or not. The circuit verification device according to claim 4 or 5. It is connected to a verification circuit having a plurality of functional circuits and a verification counter circuit having a counter circuit corresponding to each of the functional circuits having a function in which the input and output of the functional circuit have an opposite relationship.
The output of the circuit to be verified is compared with the output of the opposite circuit that ideally outputs the same output as the output to determine whether or not the functional circuit included in the circuit to be verified is normal.
Of the total number n of the functional circuits included in the circuit to be verified, the outputs of a plurality of the functional circuits connected in series equal to or less than the number of selected n-1, and the opposite circuits of the functional circuits are connected in series. A circuit verification method for determining whether or not a series of circuits based on the selected functional circuit is normal by comparing with the output of the selected circuit.

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