JP2020145502A - Imaging device and control method thereof - Google Patents

Abstract

To provide an imaging device including an imaging element having an AD conversion and a counter, which can acquire a suitable signal with an expanded dynamic range.SOLUTION: An imaging device 700 that acquires a plurality of signals from an imaging element in which a pixel unit includes a plurality of photoelectric conversion units and detects the phase difference includes a plurality of counters that count signals output by the plurality of photoelectric conversion units in a unit pixel of the imaging element, and a system control unit that controls the counting by performing input to the counter or controlling a circuit of the counter. The system control unit controls each of the counters in a first counting mode in which signals output by the plurality of photoelectric conversion units are individually counted, and a second counting mode in which signals output by the plurality of photoelectric conversion units are summed and counted, and a part of the output of the counter in the first counting mode is input to the counter in the second counting mode.SELECTED DRAWING: Figure 7

Description

The present invention relates to an image pickup apparatus and a control method thereof.

A phase difference detection method is known as a method for performing focus detection.
The phase difference detection method divides the luminous flux that has passed through the exit pupil region of the photographing lens, calculates the relative deviation amount by comparing the signals obtained according to the divided luminous flux, and focuses for focusing. The driving amount of the lens is calculated. In recent years, by providing a plurality of photoelectric conversion units (divided pixels) under the microlens of each pixel of the imaging element, it is possible to impart a pupil division function and obtain an imaging signal and a focus detection signal for phase difference detection. Imaging devices are known. Patent Document 1 performs focus detection based on the phase difference of a pair of focus detection signals obtained from an image sensor, and uses an additive signal of a plurality of light receiving units sharing one microlens as an image pickup signal. The device is disclosed.

Patent Document 2 discloses a signal processing circuit that resets the storage capacity each time a certain amount of electric charge is accumulated in a light receiving element in an image sensor having a 1-bit type AD conversion and a counter for each pixel. The amount of light that can be detected by this image sensor is determined by the upper limit of the counter that counts the number of pulses output when the voltage of the storage capacity matches the reference voltage. Further, since the storage capacity is reset every time a constant charge is accumulated in the light receiving element, the photoelectric conversion element does not saturate.

Japanese Unexamined Patent Publication No. 2001-083407 Japanese Unexamined Patent Publication No. 2015-173432

However, in the image sensor of Patent Document 2, when a high-luminance subject is photographed, saturation occurs in the image pickup signal and the focus detection signal, which may lead to deterioration of image quality and focus detection accuracy.

An object of the present invention is to provide an image pickup device including an image pickup device having an AD conversion and a counter, which can acquire a suitable signal with an expanded dynamic range.

In order to solve the above problems, the image pickup apparatus of the present invention is an image pickup apparatus in which a plurality of signals are acquired from an image pickup element having a plurality of photoelectric conversion units in a pixel unit to detect a phase difference, and the plurality of photoelectric devices are detected. A plurality of counting means for counting the signals output by the conversion unit, and a control means for controlling the counting by inputting to the counting means or controlling the circuit of the counting means. The control means sums up the first counting mode in which each of the counting means individually counts the signals output by the plurality of photoelectric conversion units, and the signals output by the plurality of photoelectric conversion units. It is controlled by any of the second counting modes for counting, and a part of the output of the first counting mode is input to the counting means of the second counting mode.

According to the present invention, it is possible to provide an image pickup device including an image pickup device having an AD conversion and a counter, which can acquire a suitable signal with an expanded dynamic range.

It is a figure explaining the structure of a unit pixel. It is a figure explaining the structure of the counter 104A. It is a figure explaining the structure of the counter 104B. It is a figure explaining the wiring between unit pixels. It is a figure which shows the structure of an image sensor. It is a figure explaining an example of the output data of an image sensor. It is a figure which shows the structure of the image pickup apparatus. It is a figure which shows the timing of a signal shaping process. It is a figure which shows the timing of a signal shaping process.

FIG. 1 is a circuit diagram showing a configuration of a unit pixel 100 according to the present embodiment. The unit pixel 100 is one of the pixels included in the image pickup device 500 included in the image pickup apparatus 700 shown in FIG. 7. The image pickup device 500 has, for example, a plurality of unit pixels 100 arranged two-dimensionally in the row direction and the column direction. The unit pixel 100 includes a plurality of photoelectric conversion units, and can adjust the focus of the imaging optical system based on a phase difference detection signal having a phase difference from each photoelectric conversion unit. In this embodiment, an example in which the unit pixel 100 includes two photoelectric conversion units will be described.

The unit pixel 100 includes an avalanche photodiode (hereinafter referred to as APD) 101A, APD101B, a quench resistor 102A, a quench resistor 102B, a waveform shaping circuit 103A, a waveform shaping circuit 103B, a counter 104A, and a counter 104B. The unit pixel 100 further includes an OR circuit 105, a selector 106A, and a selector 106B.

The APD101A and APD101B are photoelectric conversion units that convert the received light into an electric signal. Specifically, the APD101A and APD101B are photoelectric conversion elements using the avalanche effect. When the APD101A and APD101B receive the light transmitted through the same microlens, it is possible to obtain a pair of signals having different regions of the exit pupil. APD101A through the quench resistor 102A is connected to the reverse bias voltage _{V APD,} predetermined voltage is supplied. The APD101B is connected to the reverse bias voltage V _APD via the quench resistor 102B, and a predetermined voltage is supplied. Therefore, when a photon is incident on APD101A and APD101B, an electric charge is generated by avalanche multiplication (avalanche effect), and the generated signals (APD_A, APD_B) are input to the waveform shaping circuit 103A and the waveform shaping circuit 103B.

The waveform shaping circuit 103A and the waveform shaping circuit 103B perform waveform shaping of signals (APD_A, APD_B) from APD101A and APD101B. For example, the waveform shaping circuit 103A and the waveform shaping circuit 103B have a comparison circuit, and output voltage pulses (PLS_A, PLS_B) by comparing the input voltage related to the signal (APD_A, APD_B) with a predetermined threshold voltage. That is, the waveform shaping circuit 103A and the waveform shaping circuit 103B generate voltage pulses (PLS_A, PLS_B), respectively, by performing amplification and edge detection for changes in potential due to generation and discharge of electric charges in response to photon incidents. .. As described above, the APD 101, the quench resistor 102, and the waveform shaping circuit 103 function as a 1-bit type AD conversion unit by converting the incident light into a voltage pulse.

The selector 106A and the selector 106B select voltage pulses to be input to the counter 104A and the counter 104B from the voltage pulses (PLS_A, PLS_B) output by the waveform shaping circuit 103A and the waveform shaping circuit 103B. The selector 106A and the selector 106B operate in response to a selector control signal input from the outside of the unit pixel 100. In the present embodiment, "0" or "1" is set as the selector control signal.

When the selector control signal is '0', control is performed to read out the signals output by the two photoelectric conversion units individually. Hereinafter, the case where the selector control signal is '0' is referred to as the first counting mode. Since the signals output by the two photoelectric conversion units are read out individually, focus detection by the phase difference method becomes possible. It is also possible to generate an imaging signal by synthesizing individually read signals. Therefore, in the first counting mode, the focus detection signal (A image signal and B image signal) and the image pickup signal (A + B image signal) can be acquired. When the selector control signal is '0', the selector 106A selects the voltage pulse PLS_A as the input voltage pulse of the counter 104A, and the selector 106B selects the voltage pulse PLS_B as the input voltage pulse of the counter 104B.

On the other hand, when the selector control signal is '1', control is performed to add up and read out the signals output by the two photoelectric conversion units. Hereinafter, the case where the selector control signal is ‘1’ is referred to as a second counting mode. In the second counting mode, the imaging signal (A + B image signal) can be acquired. When the selector control signal is '1', the selector 106A selects the logical sum of the voltage pulse PLS_A and the voltage pulse PLS_B generated via the OR circuit 105 as the input voltage pulse of the counter 104A. Then, the selector 106B selects the carry signal A of the counter 104A as the input voltage pulse of the counter 104B. The OR circuit 105 is a logic circuit with two inputs and one output, acquires the voltage pulse PLS_A which is the output signal of the waveform shaping circuit 103A and the voltage pulse PLS_B which is the output signal of the waveform shaping circuit 103B, and performs a logical sum operation. The signal is output to the counter 104A.

The counter 104A and the counter 104B are counting units that count the voltage pulses selected by the selector 106A and the selector 106B. The counter 104A and the counter 104B output an output signal indicating a count value (count value) and a carry signal of the most significant bit. The reset and count enablement of the counter 104A and the counter 104B are controlled by the drive signal input to the unit pixel 100. Further, the counter 104B can receive the carry signal and the selector control signal of the counter 104A and the counter 104B configured in another unit pixel 100.

Next, the counter 104A and the counter 104B will be described with reference to FIGS. 2 and 3. In the present embodiment, the case where the counter 104A and the counter 104B are configured as an asynchronous counter having a maximum of 4 bits will be described, but the number of bits of the counter is not limited to 4 bits.

FIG. 2 is a diagram showing a configuration of a circuit of the counter 104A. The counter 104A is composed of a plurality of flip-flops 200 that hold data. In this embodiment, the counter 104A includes four flip-flops 200. The counter 104A can receive a voltage pulse from the selector 106A as an input and a reset signal (RST) included in the drive signal input to the unit pixel 100.

The flip-flop 200 outputs the signal input to the D terminal to the Q terminal at the rising edge of the CLK terminal with positive logic and to the Q ^* terminal paired with the Q terminal with negative logic. The Q ^* terminal is displayed as shown below in the figure.

A voltage pulse is input to the CLK terminal of the first-stage flip-flop 200. The output from the Q ^* terminal of the flip-flop 200 is connected to the CLK terminal of the flip-flop 200 in the subsequent stage. By connecting the CLK terminal of the flip-flop 200 other than the first stage to the Q ^* terminal of the flip-flop 200 of the previous stage, the output of the Q ^* terminal can be used as a carry signal. The 4-bit signal generated by the output of each Q terminal of the flip-flop 200 is output to the outside as the output signal A of the counter 104A. Further, the Q ^* signal, which is the output of the output of the Q ^* terminal of the flip-flop 200 at the final stage, is output to the outside of the counter 104A as a carry signal A.

FIG. 3 is a diagram showing a configuration of a circuit of the counter 104B. The counter 104B is composed of a plurality of flip-flops 200 for holding data and a plurality of selectors. In this embodiment, the counter 104B includes four flip-flops 200, a selector 301, and a selector 302. The counter 104B can receive a voltage pulse from the selector 106B as an input and a reset signal (RST) included in the drive signal input to the unit pixel 100. Further, the counter 104B can receive an external carry signal A, an external carry signal B, and a selector control signal as inputs.

The selector 301 is a selector for the input signal of the third-stage flip-flop 200. When the control signal is '0', the selector 301 selects the Q ^* terminal output of the second-stage flip-flop 200 and outputs it to the third-stage flip-flop 200. On the other hand, when the selector control signal is '1', the selector 301 selects the external carry signal A and outputs it to the third-stage flip-flop 200.

The selector 302 is a selector for the input signal of the fourth-stage flip-flop 200. When the control signal is '0', the selector 302 selects the Q ^* terminal output of the third-stage flip-flop 200 and outputs it to the fourth-stage flip-flop 200. On the other hand, when the selector control signal is '0', the selector 302 selects the external carry signal B and outputs it to the fourth stage flip-flop 200.

The 4-bit signal consisting of the output of the Q terminal of each flip-flop 200 is output to the outside of the counter 104B as the output signal B of the counter. Further, the Q ^* signal, which is the output of the Q ^* terminal of the flip-flop 200 at the final stage, is output to the outside of the counter 104B as a carry signal B.

As described above, when the selector control signal is '0', the counter 104B operates as a 4-bit asynchronous counter that counts voltage pulses. On the other hand, when the selector control signal is '1', the first and second stages are 2-bit counters that count voltage pulses, the third stage is a 1-bit flip-flop that holds the external carry signal A, and the fourth stage. Operates as a 1-bit flip-flop that counts the external carry signal B.

In the output consisting of 8 bits of the unit pixel 100, the lower 4 bits correspond to the output of the counter 104A, and the upper 4 bits correspond to the output of the counter 104B. When the selector control signal is '0', the lower 4 bits correspond to the count value of the voltage pulse PLS_A which is the output of the counter 104A, and the upper 4 bits correspond to the count value of the voltage pulse PLS_B which is the output of the counter B. .. On the other hand, when the selector control signal is '1', the lower 4 bits correspond to the count value of the sum of the voltage pulse PLS_A and the voltage pulse PLS_B which are the outputs of the counter 104A. Then, 2 of the upper 4 bits correspond to the carry signal of the counter 104A input to the counter 104B, and the remaining 2 bits correspond to the external carry signal input to the counter 104B. That is, when the selector control signal is '1', the lower 6 bits correspond to the count value of the sum of the voltage pulse PLS_A and the voltage pulse PLS_B, and the upper 2 bits correspond to the external carry signal.

FIG. 4 is a diagram illustrating wiring between unit pixels. The unit pixel 400 and the unit pixel 410 have the same configuration as the unit pixel 100. The unit pixel 400 is arranged at a certain position on the image sensor, and the unit pixel 410 is arranged adjacent to the unit pixel 400 in the vertical direction. The unit pixel 400 and the unit pixel 410 are a pair of unit pixels 100 that are in a relationship of wiring external carry signals to each other. The carry signal A and carry signal B output from the unit pixel 400 are input to the unit pixel 410 as an external carry signal. The carry signal A and carry signal B output from the unit pixel 410 are input to the unit pixel 400 as an external carry signal. The carry signal A and carry signal B input from the unit pixel 410 to the unit pixel 400 are used by the signal shaping unit 704 when shaping the output signal of the unit pixel 410.

FIG. 5 is a block diagram showing the configuration of the image sensor 500. The image sensor 500 includes a pixel unit 501, an output control circuit 502, a timing control circuit 503, and a selector control circuit 504. The pixel unit 501 has a plurality of unit pixels 100 arranged in a matrix. Specifically, in the pixel unit 501, a large number of combinations of the unit pixel 400 shown in white and the unit pixel 410 shown in diagonal lines adjacent to the unit pixel 400 in the vertical direction are arranged. In this embodiment, an example in which the unit pixels 400 and the unit pixels 410 are alternately arranged in the vertical direction will be described, but the present invention is not limited to this. For example, the unit pixels 400 and the unit pixels 410 may be arranged alternately in the horizontal direction, or may be arranged alternately in the horizontal direction and the vertical direction.

The unit pixel 400 and the output A and the output B of the unit pixel 410 arranged in the pixel unit 501 are input to the output control circuit 502, respectively. The output control circuit 502 selects and controls a unit pixel signal to be output from the input signal. The timing control circuit 503 outputs a drive signal to the pixel unit 501 and also controls the drive timing of the output control circuit 502. The selector control circuit 504 controls the selector control signal input to the unit pixel 400 and the unit pixel 410 of the pixel unit 501. The selector control circuit 504 and the unit pixel 400 are connected by a selector control signal line 505. Further, the selector control circuit 504 and the unit pixel 410 are connected by the selector control signal line 506. The timing control circuit 503 and the selector control circuit 504 are controlled by the system control unit 707, which will be described later.

FIG. 6 is a diagram illustrating an example of output data of the image sensor 500. The image sensor 500 connects the output A and the output B of the unit pixel 100 selected by the output control circuit 502, and sequentially outputs them as an 8-bit signal to the outside. In the present embodiment, for example, as shown in FIG. 6, the lower 4 bits of the 8 bits are assigned to the output A of the unit pixel 100, and the upper 4 bits are assigned to the output B of the unit pixel 100.

FIG. 7 is a diagram showing the configuration of the image pickup apparatus 700. The image pickup device 700 includes an image pickup optical system 701, an image pickup element 500, a signal shaping section 704, an image processing section 705, a focus detection section 706, an optical drive section 702, an image pickup element drive section 703, and a system control section 707. The image pickup optical system 701 is an optical system for forming an optical image of a subject on the image pickup element 500, and includes a plurality of lenses such as a shift lens and a zoom lens, and an aperture. The optical drive unit 702 controls the image pickup optical system 701 according to the focus information output from the focus detection unit 706 and the optical system drive information of the system control unit 707. In the present embodiment, an image pickup device in which a lens and a camera body are integrated will be described as an example, but the present invention is not limited to this, and an image pickup device with a removable lens may be used. ..

The image sensor 500 converts an optical image of a subject imaged via the image pickup optical system 701 into an electrical signal. The details of the image sensor 500 have been described with reference to FIG. The image sensor 500 determines the selector control signal by the selector control circuit 504 based on the instruction from the image sensor drive unit 703. The image sensor drive unit 703 controls the image sensor 500 in response to drive instruction information of the image sensor from the system control unit 707.

The signal shaping unit 704 shapes the 8-bit output signal output from the image sensor 500 according to a predetermined procedure, and generates an image pickup signal and a focus detection signal. The signal shaping unit 704 includes a line memory for waiting for the output signal of the line composed of the unit pixel 400 and the output signal of the line composed of the unit pixel 410. Details of the signal shaping process by the signal shaping unit 704 will be described later. In the present embodiment, the unit pixels arranged in the horizontal direction are treated as one line, and the line composed of the unit pixel 400, the output signal, and the line composed of the unit pixel 410 are alternately arranged in the vertical direction. However, it is not limited to this. The unit pixels arranged in the vertical direction may be treated as one line, and the line composed of the unit pixel 400, the output signal, and the line composed of the unit pixel 410 may be alternately arranged in the horizontal direction. Further, the unit pixels 400 and the unit pixels 410 may be arranged alternately in the horizontal and vertical directions.

The image processing unit 705 performs image processing such as white balance on the image signal generated by the signal shaping unit 704. The image signal subjected to various image processing by the image processing unit 705 is compressed and coded by a compression unit (not shown) and recorded on a recording medium. The recording medium may be detachable from the image pickup device or may be built in the image pickup device.

The focus detection unit 706 calculates a phase difference evaluation value for performing phase difference ranging from the two pupil division images obtained from the signal shaping unit 704, and focus information for controlling the focus position of the imaging optical system 701. Is calculated. The system control unit 707 is a CPU (Central Processing Unit) that performs various calculations and controls the entire image pickup apparatus 700. The system control unit 707 sends drive information of the optical system such as zoom and aperture to the optical drive unit 702 based on the shooting information obtained from the shooting scene, the imaging mode, and the like. Further, the system control unit 707 sends drive information of the image sensor such as an exposure time and a setting instruction of the selector control circuit to the image sensor drive unit 703.

Next, the setting of the selector control signal and the signal shaping process by the signal shaping unit 704 will be described with reference to FIGS. 8 and 9. The image pickup apparatus 700 of the present embodiment can set a first image pickup mode and a second image pickup mode. The first image pickup mode is a mode in which an image pickup signal and a focus detection signal are acquired from all lines of the pixel unit 501 of the image pickup element 500. The second image pickup mode is a mode in which lines for acquiring only the image pickup signal and lines for acquiring both the image pickup signal and the focus detection signal are alternately arranged in the pixel portion 501 of the image pickup device 500.

In the second mode, a line for acquiring only the imaging signal and a line for acquiring both the imaging signal and the focus detection signal are mixed. When acquiring both the imaging signal and the focus detection signal, if the output signal corresponding to the count value of the voltage pulse PLS_A in the lower 4 bits and the count value of the voltage pulse PLS_B in the upper 4 bits is shaped, the 4-bit focus is obtained. The detection signal and the 5-bit imaging signal are acquired. When only the imaging signal is acquired, it is also possible to acquire the 8-bit imaging signal from the 8-bit output signal which is the sum of the voltage pulse PLS_A and the voltage pulse PLS_B. However, if there is a difference of 2 bits or more between the number of bits of the image pickup signal when both the image pickup signal and the focus detection signal are acquired and the number of bits of the image pickup signal when only the image pickup signal is acquired, they are combined. When an image is generated, the image becomes unnatural. Therefore, in order to obtain a publicly captured image, it is desirable that the number of bits of the imaging signal when only the imaging signal is acquired be set to +1 the number of bits when both the imaging signal and the focus detection signal are acquired. .. Therefore, in the present embodiment, the number of bits of the image pickup signal when only the image signal is acquired is controlled to be 5 + 1 = 6 bits. Therefore, when only the imaging signal is acquired, 6 bits of the 8-bit output signal are used as the count value of the sum of the voltage pulse PLS_A and the voltage pulse PLS_B of each unit pixel corresponding to the imaging signal. Then, the remaining 2 bits are used for an external carry signal used to extend the dynamic range of the imaging signal and the focus detection signal. Therefore, the second imaging mode is a mode in which the dynamic range of the imaging signal and the focus detection signal can be expanded.

The system control unit 707 switches the driving method of the image sensor driving unit 703 and the signal shaping unit 704 according to the set imaging mode. When the first image pickup mode is set, the system control unit 707 controls the selector so as to set both the selector control signal line 505 and the selector control signal line 506 to '0' via the image sensor drive unit 703. A drive instruction is issued to the circuit 504. The selector control circuit 504 sets '0' to the selector control signal line 505 and the selector control signal line 506 based on the instruction of the system control unit 707.

As described above, when the selector control signal is '0', the selector 106A selects the voltage pulse PLS_A as the input voltage pulse of the counter 104A, and the selector 106B selects the voltage pulse PLS_B as the input voltage pulse of the counter 104B. .. Therefore, in the first imaging mode, the counter 104A and the counter 104B configured in each unit pixel operate as 4-bit counters, respectively. Therefore, in the first imaging mode, the output signal of the imaging element 500 is such that the lower 4 bits of the 8 bits are the count value of the voltage pulse PLS_A of each unit pixel, and the upper 4 bits are the count value of the voltage pulse PLS_B of each unit pixel. Become.

On the other hand, when the second image pickup mode is set, the system control unit 707 sets the selector control signal line 505 to '1' and the selector control signal line 506 to '0' via the image sensor drive unit 703. As a result, a drive instruction is issued to the selector control circuit 504. The selector control circuit 504 sets "1" for the selector control signal line 505 and "0" for the selector control signal line 506 based on the instruction of the system control unit 707.

First, the unit pixel 400 in which "1" is input as a selector control signal in the second imaging mode will be described. As described above, when the selector control signal is '1', the selector 106A selects the logical sum of the voltage pulse PLS_A and the voltage pulse PLS_B generated via the OR circuit 105 as the input voltage pulse of the counter 104A. Then, the selector 106B selects the carry signal A of the counter 104A as the input voltage pulse of the counter 104B. Therefore, the unit pixel 400 whose selector control signal is set to '1' in the second imaging mode connects the counter 104A and the counter 104B in series. Then, the third bit and the fourth bit of the counter 104B operate so as to count the carry signals of the corresponding unit pixels 410, respectively. In the line composed of the unit pixels 400 in the second image pickup mode, the lower 6 bits of the 8 bits of the output signal of the image pickup element 500 are the count value of the sum of the voltage pulse PLS_A and the voltage pulse PLS_B of each unit pixel. Then, the upper 2 bits of the 8 bits of the output signal of the image sensor 500 become the carry signal A and the carry signal B of the corresponding unit pixel 410.

Next, the unit pixel 410 in which “0” is input as the selector control signal in the second imaging mode will be described. As described above, when the selector control signal is '0', the selector 106A selects the voltage pulse PLS_A as the input voltage pulse of the counter 104A, and the selector 106B selects the voltage pulse PLS_B as the input voltage pulse of the counter 104B. To do. Therefore, in the line composed of the unit pixel 410, the lower 4 bits of the 8 bits of the output signal are the count value of the voltage pulse PLS_A of the unit pixel 410, and the upper 4 bits are the count value of the voltage pulse PLS_B of the unit pixel 410. ..

8 and 9 are timing charts showing the transition of each signal of the signal shaping unit 704 for each imaging mode. The signal shaping unit 704 shapes the output signal output from the image pickup device 500 and generates a shaping signal. The timings t801 and t901 represent the transfer start timing of the output signal of the line composed of the unit pixel 400. The timings t802 and t902 represent the transfer end timing of the output signal of the line composed of the unit pixel 400 and the transfer start timing of the output signal of the line composed of the unit pixel 410. The timings t803 and t903 represent the transfer end timings of the output signals of the line composed of the unit pixels 410. After the timing t803, it is assumed that the transition of the signal shown in the timing t801 to the timing t803 is repeated until the final line of the image sensor 500. Similarly, after the timing t903, it is assumed that the signal transition from the timing t901 to the timing t903 is repeated until the final line of the image sensor 500.

The output signal indicates 8-bit data output from the image sensor 500. The delay signal is a delay signal that is output via a line memory that can hold an output signal for one line built in the signal shaping unit 704. The A shaping signal, the B shaping signal, and the A + B shaping signal are output signals of the signal shaping unit 704 generated by signal shaping processing based on the output signal from the image sensor 500. The effective signal A, the effective signal B, and the effective signal A + B are output signals for control indicating that the data sections are valid for the shaped signal A, the shaped signal B, and the shaped signal A + B. In the valid signal A, the valid signal B, and the valid signal A + B, the period during which the data is valid indicates "H" (High), and the period during which the data is invalid indicates "L" (Low).

First, with reference to FIG. 8, the signal shaping process of the signal shaping unit 704 and the transition of each signal in the first imaging mode will be described. The signal shaping unit 704 in the first imaging mode separates the output signal into lower 4 bits and upper 4 bits, and sets the values of the shaping signal A and the shaping signal B, respectively. Further, the value obtained by adding the shaping signal A and the shaping signal B is taken as the value of the shaping signal A + B.

As an example, signal shaping processing at the timing of timing t804 will be described. At the timing t804, the output signal of the image sensor 500 is 0xBC. At this time, if the signal is separated into the upper 4 bits and the lower 4 bits of the output signal, the upper 4 bits of the output signal are 0x0B and the lower 4 bits are 0x0C. The lower 4 bits of the output signal, 0x0C, are treated as the shaping signal A, and the upper 4 bits, 0xB, are treated as the shaping signal B. Further, the addition signal of the shaping signal A and the shaping signal B is 0x17, and is treated as the value of the shaping signal A + B.

Similarly, in the period from the timing t802 to the timing t803, the lower 4 bits are the shaping signal A, the upper 4 bits are the shaping signal B, and the addition signal of the shaping signal A and the shaping signal B is the shaping signal A + B with respect to the output signal. In the first imaging mode, the shaping signal A, the shaping signal B, the valid signal A corresponding to the shaping signal A + B, the valid signal B, and the valid signal A + B are set to'H'in all lines. Therefore, the shaping signal A, the shaping signal B, and the shaping signal A + B, which have been shaped for the output signals in all the lines, are output in parallel to the subsequent stage. In this way, in the first imaging mode, a 4-bit shaping signal A, a 4-bit shaping signal B, and a 5-bit shaping signal A + B are generated for each unit pixel of the entire line by the signal shaping process, and the process proceeds to the subsequent stage. It is output.

Next, with reference to FIG. 9, the signal shaping process of the signal shaping unit 704 and the transition of each signal in the second imaging mode will be described. The signal shaping unit 704 in the second imaging mode switches the signal shaping processing method between a line composed of the unit pixels 400 and a line composed of the unit pixels 410.

First, the signal shaping process of the line composed of the unit pixels 400 will be described. In the signal output period of the unit pixel 400 shown in the timing t901 to the timing t902, the lower 6 bits of the output signal are the count values of the logical sums of PLS_A and PLS_B. Then, the upper two bits of the output signal are the count values of the carry signals of the counter 104A and the counter 104B of the corresponding unit pixel 410.

During the period from timing t901 to timing t902, the signal shaping unit 704 handles the lower 6 bits of the output signal as shaping signals A + B, and inputs the output signal to a line memory (not shown). In the period from timing t901 to timing t902, the valid signal A + B corresponding to the shaping signal A + B is set to "H", and the valid signal A and valid signal B corresponding to the shaping signal A and the shaping signal B are set to "L".

In the signal output period of the unit pixel 410 shown from the timing t902 to the timing t903, the breakdown of the output signal is that the lower 4 bits are the count value of PLS_A of the unit pixel 410 and the upper 4 bits are the count value of PLS_B of the unit pixel 410. Further, by a line memory (not shown), the output signal one line before, that is, the output signal of the line composed of the unit pixel 400 is output as a delay signal in synchronization with the corresponding unit pixel 410.

During the period from timing t902 to timing t903, the signal shaping unit 704 combines the lower 4 bits of the output signal with the 7th bit of the delay signal, generates a 5-bit signal, and handles it as the shaping signal A. That is, the signal shaping unit 704 combines the output bits of the flip-flop to which the carry signal A of the counter 104A configured in the unit pixel 410 is connected, generates a 5-bit signal, and handles it as the shaping signal A.

Further, the signal shaping unit 704 combines the upper 4 bits of the output signal and the 8th bit of the delay signal, generates a 5-bit signal, and handles it as the shaping signal B. That is, the signal shaping unit 704 combines the output bits of the flip-flop to which the carry signal B of the counter 104B configured in the unit pixel 410 is connected, generates a 5-bit signal, and handles it as the shaping signal B. Further, the signal shaping unit 704 handles the value obtained by adding the shaping signal A and the shaping signal B as a 6-bit shaping signal A + B.

In the period from the timing t902 to the timing t903, the shaping signal A, the shaping signal B, and the valid signal A, the valid signal B, and the valid signal A + B corresponding to the shaping signal A + B become ‘H’. Therefore, the shaping signal A, the shaping signal B, and the shaping signal A + B, which have been shaped with respect to the output signal, are output in parallel to the subsequent stage.

As an example, the signal shaping process at the timings t905 and t906 will be described. At the timing t905, the output signal is 0xE4. At this time, the lower 6 bits of the output signal are 0x24. The upper 2 bits of the output signal are 0x3. The lower 6-bit value 0x24 of the output signal is treated as the value of the shaping signal A + B.

At the timing t906, the output signal is 0x22. At this time, if the signal is separated into the upper 4 bits and the lower 4 bits of the output signal, the upper 4 bits of the output signal are 0x2 and the lower 4 bits are 0x2. Further, the output signal 0xEA of the corresponding unit pixel 400 is input to the delay signal in synchronization with each other.

The value obtained by combining the value 0x2 of the lower 4 bits of the output signal and the value '1' of the 7th bit of the delay signal with the most significant bit of the lower 4 bits of the output signal is treated as the value of the shaping signal A. That is, the shaping signal A is 0x12. Further, the value obtained by combining the value 0x2 of the upper 4 bits of the output signal and the value ‘1’ of the 8th bit of the delay signal with the most significant bit of the upper 4 bits of the output signal is treated as the value of the shaping signal B. That is, the shaping signal B is 0x12. The addition signal of the shaping signals A and B is 0x24, and is treated as the value of the shaping signals A + B.

As described above, in the second imaging mode, the 6-bit shaping signal A + B is generated in the line composed of the unit pixels 400 and output to the subsequent stage. Further, in the line composed of the unit pixels 410, a 5-bit A-shaped signal, a 5-bit B-shaped signal, and a 6-bit A + B-shaped signal are generated and output to the subsequent stage. According to the present embodiment, for each shaping signal in the first imaging mode, each shaping signal in the second imaging mode can be counted in a state where the data range for one bit is expanded, and a high-brightness subject can be counted. It is possible to suppress the occurrence of saturation even when shooting.

In the present embodiment, the unit pixel 400 can acquire only the imaging signal, and the unit pixel 410 can acquire both the imaging signal and the focus detection signal, but the present invention is not limited to this. For example, it can be applied to the case where both the image pickup signal and the focus detection signal are acquired by the unit pixel 400 and only the image pickup signal is received by the unit pixel 410. In this case, the system control unit 707 issues a drive instruction via the image sensor drive unit 703 to set the selector control signal of the unit pixel 400 to '0' and the selector control signal of the unit pixel 410 to '1', and signals. The shaping method in the shaping section 704 may be changed to an appropriate shape.

Further, in the present embodiment, an example in which adjacent unit pixels in the vertical direction are handled as a pair is shown, but the present invention is not limited to this, and some bits of counters connected in series are operated in parallel connection. It may be configured so that it can be used as an extension bit of the counter. For example, a pair may be formed by adjacent unit pixels in the horizontal direction, or wiring may be performed between non-adjacent unit pixels. Further, in the present embodiment, an example in which the unit pixel 100 includes the counter 104A and the counter 104B which are counting means has been described, but the counting means does not necessarily have to be provided in the unit pixel 100 and corresponds to the unit pixel 100. It suffices if it is arranged like this.

(Other Examples)
The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and modifications can be made within the scope of the gist thereof.

100 Unit pixel 104A Counter 104B Counter 500 Image sensor 504 Selector control circuit 707 System control unit 704 Signal shaping unit

Claims (10)

An image pickup device in which a plurality of signals are acquired from an image pickup device having a plurality of photoelectric conversion units in a pixel unit to detect a phase difference.
A plurality of counting means for counting the signals output by the plurality of photoelectric conversion units, respectively.
A control means for controlling the counting by inputting to the counting means or controlling a circuit of the counting means is provided.
The control means sums up the first counting mode in which each of the counting means individually counts the signals output by the plurality of photoelectric conversion units, and the signals output by the plurality of photoelectric conversion units. An imaging feature is controlled in any of the second counting modes for counting, and a part of the output of the counting means in the first counting mode is input to the counting means in the second counting mode. apparatus. In the first counting mode,
Among the plurality of photoelectric conversion units, a first counting means for counting the first signal output by the first photoelectric conversion unit, and
The imaging device according to claim 1, further comprising a second counting means for counting a second signal output by the second photoelectric conversion unit among the plurality of photoelectric conversion units. In the second counting mode,
The first counting means counts the logical sum of the first signal and the second signal.
The second counting means is one of a part of the output of the first counting means paired with the output of the first counting means and the output of the second counting means operating in the first counting mode. The imaging device according to claim 2, wherein the number of units is counted. A shaping means that performs signal shaping processing based on the output of the counting means, and
The imaging device according to claim 3, further comprising a focus detecting means for detecting the phase difference based on a signal for detecting the phase difference output by the shaping means. In the first counting mode,
The shaping means includes a first shaping signal which is a signal for detecting a phase difference corresponding to the counting value of the first counting means and a signal for detecting a phase difference corresponding to the counting value of the second counting means. The imaging according to claim 4, wherein the second shaping signal, and the third shaping signal, which is an imaging signal obtained by adding the first shaping signal and the second shaping signal, are shaped. apparatus. When the first imaging mode for acquiring the phase difference detection signal and the imaging signal from all the pixels is set, the control means controls all the counting means in the first counting mode, and a part of them. When a second imaging mode is set in which a signal for phase difference detection and an imaging signal are acquired from the pixels of the above and the imaging signal is acquired from the other pixels, the control means corresponds to the part of the pixels. The imaging device according to claim 5, wherein the counting means is controlled in the first counting mode, and the counting means corresponding to the other pixels is controlled in the second counting mode. In the second imaging mode,
The first counting means controlled in the first counting mode is a first counter, the second counting means is a second counter, and the first counting means controlled in the second counting mode. Is a third counter, and the second counting means into which a part of the output of the first counter to the third counter is input is a fourth counter.
The shaping means shapes the first shaping signal based on the count value of the first counter and the count value corresponding to the output of the first counter among the count values of the fourth counter. A claim characterized in that the second shaping signal is shaped based on the count value of the second counter and the count value corresponding to the output of the second counter among the count values of the fourth counter. Item 6. The imaging device according to item 6. The image pickup apparatus according to any one of claims 1 to 7, wherein the control means controls the first counting mode and the second counting mode for each line of the image pickup device. Claims 1 to 1, wherein the photoelectric conversion unit has a photoelectric conversion element using an avalanche effect, and counts pulses generated from output signals of the plurality of photoelectric conversion elements by the plurality of counting means. 8. The imaging device according to any one of 8. It is a control method of an image pickup device that acquires a plurality of signals from an image pickup device having a plurality of photoelectric conversion units in a pixel unit to detect a phase difference.
A counting process in which signals output by the plurality of photoelectric conversion units are counted by a plurality of counters, and
A control step of controlling the count by inputting to the counter or controlling the circuit of the counter is provided.
In the control step, each of the counters is counted by adding up the first counting mode in which the signals output by the plurality of photoelectric conversion units are individually counted and the signals output by the plurality of photoelectric conversion units. A control method characterized in that control is performed in any of the second counting modes, and a part of the output of the counting means in the first counting mode is input to the counter in the second counting mode.

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