JP2020144089A - Abnormality detection circuit - Google Patents

Abstract

To discriminate and detect a short-circuit and load opening in an output terminal at low current consumption when a load drive circuit is in a non-action state.SOLUTION: In an abnormality detection circuit 101, a constant-current source 10 with a switch controllable in operation by a switch 10a is connected between a power source terminal 25 and an output terminal 26, and an anode of a first diode 11 is connected to the output terminal 26. A drain of a depletion type detection circuit first transistor 1 put in a diode connection state is connected to a cathode, and a gate and a source of the detection circuit first transistor 1 are connected to a drain of a detection circuit second transistor 2 consisting of an input side of a first current mirror circuit. A detection current in accordance with a result of abnormality detection is output to a drain of a detection circuit third transistor 3 consisting of an output side of the first current mirror circuit.SELECTED DRAWING: Figure 1

Description

The present invention relates to an abnormality detection circuit that is provided in a load drive circuit or the like that supplies power to a load and performs load release detection, ceiling fault detection, and ground fault detection, and particularly reduces power consumption and reliability in crown fault detection. It is related to the one that aims to improve the sex.

Conventionally, a load drive circuit that supplies a power supply voltage to a load is provided with a function of detecting an abnormality such as a disconnection of the load or a short circuit of an output terminal in order to manage the state of the system in which the circuit is incorporated. In particular, in automobile systems and the like where safety is a priority, abnormality detection is always carried out to ensure that the system functions when necessary.
Therefore, in the load drive circuit used for these, it is necessary to detect load release and short circuit of the output terminal even when the load drive circuit is not operating.

In particular, in the case of a load drive circuit that uses a battery as the main power source, load release detection can be performed before the start of load drive or by monitoring at regular intervals, but when the output terminal is short-circuited to the power supply, it is sufficient to perform a load release detection. If the tentacle protection function is not immediately activated, significant battery consumption will occur. Therefore, it is necessary to constantly monitor the tentacle, and an abnormality detection circuit that reliably detects the tentacle and operates with low current consumption is required.

As a circuit that performs load release detection and ceiling fault detection in a state where load drive is not performed at the output terminal of a conventional load drive circuit, for example, a circuit having a configuration as shown in FIG. 7 is known. There is.
Hereinafter, load release detection and sky fault detection in the conventional circuit will be described with reference to the figure.
In the circuit shown in FIG. 7, the resistor RA is located between the power supply terminal 25A and the output terminal 26A, the resistor RB is located between the output terminal 26A and the ground, and the load resistor RL is located between the output terminal 26A and the ground. It is provided.

Further, assuming that the effective series resistance when the output terminal 26A and the power supply are short-circuited is the short-circuit resistor RS, the resistance between the power supply and the ground via the output terminal 26A is as described below.
That is, the resistance between the power supply and the ground via the output terminal 26A is the parallel resistance of the resistor RB and the load resistor RL between the output terminal 26A and the ground, and the resistor RA and the short-circuit resistor RS between the power supply and the output terminal 26A. The parallel resistance of is connected in series.

As a result, the voltage divided by the resistor RB, the load resistor RL, the resistor RA, and the short-circuit resistor RS appears on the output terminal 26A.
The voltage of the output terminal 26A is compared with the first reference voltage VR1 for load release determination in the first comparison circuit COMP1 and the second reference voltage VR2 for celestial junction determination in the second comparison circuit COMP2. Therefore, the load release of the output terminal 26A and the presence / absence of a tentacle are detected.

Here, the first reference voltage VR1 and the second reference voltage VR2 are set as VR1 <VR2. Under this premise, if the voltage VOUT of the output terminal 26A is VOUT <VR1 <(<VR2), both the first comparison circuit COMP1 and the second comparison circuit COMP2 are judged to be normal, and the load is not released and the sky is not open. The result is a judgment that the state is normal and not entangled.

Next, when VR1 <VOUT <VR2, the first comparison circuit COMP1 is determined to be abnormal, the second comparison circuit COMP2 is determined to be normal, and as a result, the determination result is that the load is released.
Further, in the case of (VR1 <) VR2 <VOUT, both the first comparison circuit COMP1 and the second comparison circuit COMP2 are determined to be abnormal, and as a result, a determination result of a heavenly entanglement is obtained.

Further, as a conventional circuit for performing load release detection and ceiling fault detection, for example, there is one using a constant current element as shown in Patent Document 1 and the like.
At first glance, the circuit shown in FIG. 2 of Patent Document 1 seems to have a completely different configuration from the conventional circuit shown in FIG. 7, but the resistor RA in FIG. 7 is used as a low current element. Only the replaced points are different. That is, the determination method for performing load release and crown detection by comparing the voltage of the output terminal with the reference voltage for each of load release and crown is basically the same as that of the conventional circuit shown in FIG.

It is considered that the main differences between the circuit shown in Patent Document 1 and the circuit shown in FIG. 7 are two points: the correlation between the load resistor and the output voltage, and the correlation between the power supply voltage and the current consumption.
However, the principle of the determination method is the same except that the correlation changes, and in the circuit shown in FIG. 7, the determination sensitivity setting can be adjusted by the resistance ratio of the resistor RA and the resistor RB. On the other hand, in the circuit disclosed in Patent Document 1, there is only a difference that it can be adjusted by the current value of the constant current element (27) and the resistance value of the resistor (33) in FIG. 2 of the same document. is there.

Republished patent WO2013 / 047005

Toshiba TPD1055FA data sheet, November 28, 2018

As described above, in the conventional detection circuit, the current flowing from the power supply to the ground terminal via the output terminal is determined by the resistance values of the resistors RA and RB, the load resistor RL, and the crown resistor RS. Generally, the resistance values of the resistors RA and RB need to be set to a value sufficiently higher than the resistance value of the load resistor RL so that the current flowing through these resistors is not wasted. is there.
Therefore, it is usually set in the relationship of RA >> RL and RB >> RL.
It should be noted that RA, RL, RB, and RL are the resistance values of the above-mentioned resistors for convenience.

Therefore, the current consumption in the conventional detection circuit shown in FIG. 7 is as described below.
First, let us consider a state in which a load resistor is properly connected to the output terminal, not a load release or a ceiling.
The resistance between the output terminal 26A and the ground is the parallel resistance of the resistor RB and the load resistor RL, but since it is RB >> RL, it can be approximated as RL.

The resistance between the power supply and the ground via the output terminal 26A can be approximated to RA + RL, but further can be approximated to RA because RA >> RL.
Therefore, the current flowing from the power supply to the ground via the output terminal 26A in a state where the load is properly connected and the load drive circuit is not operating can be approximated to VCS / RA.

In the circuit example shown in Non-Patent Document 1, RA = 100 kΩ. For example, when VCS = 12 V, a current of 120 μA is constantly generated regardless of whether the detection circuit is operating or not in the state where the load is not driven. It will be consumed.
This current consumption can be reduced by increasing the resistance RA, but in order for the circuit to operate normally even at low voltage, the output terminal potential is not affected by the input impedance on the comparison circuit side. It is necessary to pass a current through the resistor RA.

Further, regarding load release, the ratio of RA and RL is also a factor that determines the detection sensitivity, so the resistance value of RA must be determined in consideration of the requirement for the threshold value of the load resistance that is determined to be load release, and the current consumption. It cannot be made significantly higher for the purpose of reducing. Therefore, if the power supply voltage is increased and used, the problem that the current consumption increases is caused.

The actual load release detection is not only when the load is completely disconnected, but also when the series resistance on the load side becomes significantly high due to destruction or failure of the load itself or poor connection with the terminal. You need to judge. However, in the conventional circuit, the output voltage VOUT in the non-heavenly state is VOUT = VCS × RB × RL / {RA × (RB + RL) + RB × RL}, and the load is released when VOUT> VR1. Therefore, the threshold value of the load resistance determined to be the load release can be expressed as RL> VR1 × RA × RB / {VCC × RB-VR1 × (RA + RB)}.

Since this equation includes the term of the power supply voltage VCS in the denominator, it means that the threshold value of the load resistance for determining that the load is open changes in inverse proportion to the power supply voltage VCS.
That is, there is a problem that the resistance value for determining that the load is open cannot be set to a constant value regardless of the power supply voltage.

Next, a case where the output terminal is short-circuited to the power supply while the load resistor is properly connected will be described.
First, even in a short-circuited state, the resistance value does not actually become 0Ω but a finite value. Therefore, assuming that the resistance is a short-circuit resistance RS, the voltage VOUT of the output terminal 26A is VOUT = VCS × RB. It is expressed as × RL × (RA + RS) / {RA × RS × (RB + RL) + RB × RL × (RA + RS)}.

As described above, the resistors RA and RB need to be set to high resistance in order to suppress the current consumption, and since RA >> RS and RB >> RL, they are represented by the above equation. The output voltage VOUT to be generated can be approximated as VOUT = VCS × RL / (RS + RL). As a result, the voltage VOUT of the output terminal is determined by the ratio of the short-circuit resistor RS and the load resistor RL.
Then, if this output voltage VOUT is higher than the second reference voltage VR2 for detecting the crown, it is determined to be a crown.

By the way, the second reference voltage VR2 for detecting the crown and the first reference voltage VR1 for detecting the load release have restrictions related to the resistors RA and RB.
That is, in the state where the load drive circuit is not operating, the load resistor is not connected, and the output terminal 26A is not short-circuited, the output voltage VOUT is VOUT = VCS × {RB / (RA + RB / RB / (RA + RB). )}, But this value is the maximum value of the voltage determined to open the load.

If the first reference voltage VR1 is set higher than the above-mentioned VOUT, the load release detection will not function as a matter of course, while if the second reference voltage VR2 is set lower than the above-mentioned VOUT, the load release will be erroneously detected as a ceiling. It will be.
Therefore, the first reference voltage VR1 and the second reference voltage VR2 need to be set in the relationship of VR1 <VCC × {RB / (RA + RB)} <VR2.

If the second reference voltage VR2 is set low, even a higher short-circuit resistance can be detected and the detection sensitivity can be increased. Therefore, the VR2 is temporarily set to the limit value VCS × {RB / (RA + RB)}. If so, the detectable short-circuit resistor RS is RS = RA / RB × RL.

The ratio of RA and RB is generally set near the midpoint of the power supply voltage so as not to narrow the set voltage range of VR1 and VR2. Therefore, if RA: RB = 1: 1, RS = RL, that is, if the resistance value between the output terminal 26A and the power supply is about the same as or smaller than that of the load resistor RL, it will be detected as a ceiling. There is also a problem that the load cannot be released and the load is determined to be in a normal state.

The present invention has been made in view of the above-mentioned actual conditions, and when the load drive circuit is in a non-operating state, it is possible to distinguish between the ceiling entanglement at the output terminal and the load release with low current consumption, and it is possible to detect it as compared with the conventional invention. It provides a highly reliable abnormality detection circuit.

In order to achieve the above object of the present invention, the abnormality detection circuit according to the present invention is
An abnormality detection circuit that has an output transistor and a gate drive circuit that controls the drive of the output transistor, and detects an abnormality in the output terminal of a load drive circuit that is configured to be able to drive a load connected to the output terminal. And
In the abnormality detection circuit, a constant current source with a switch is connected between a power supply terminal to which the power supply voltage of the load drive circuit is applied and an output terminal, and the constant current source with a switch controls the presence or absence of a constant current output. Configured with a switch that enables
The anode of the first diode is connected to the output terminal, the drain of the first transistor for the depletion type detection circuit is connected to the cathode of the first diode, and the drain of the first transistor for the detection circuit is connected. The gate and source are connected to each other and are connected to the input side of the first current mirror circuit, and the detection current according to the result of abnormality detection can be output to the output side of the first current mirror circuit. It is something that has been done.

According to the present invention, when the load drive circuit is not load-driven, it is possible to reliably detect an abnormality due to a tentacle of the output terminal with extremely low current consumption without erroneous detection, in distinction from load release. It is effective.
In addition, by using a constant current source with a switch and alternately switching the operating state between the ON state and the OFF state in chronological order, it is possible to clearly distinguish between the crown and the load release. In comparison, a more reliable abnormality detection circuit can be provided.
Furthermore, a ground fault can be detected during load drive, and a ceiling fault and load release are determined immediately before the start of load drive, and then a load drive is performed to distinguish between a sky fault, load release, and ground fault. be able to.

It is a circuit diagram which shows the 1st circuit structure example of the abnormality detection circuit in embodiment of this invention. It is a circuit diagram which shows the 2nd circuit structure example of the abnormality detection circuit in embodiment of this invention. It is a circuit diagram which shows the 3rd circuit configuration example of the abnormality detection circuit in embodiment of this invention. It is a circuit diagram which shows the 4th circuit structure example of the abnormality detection circuit in embodiment of this invention. It is a circuit diagram which shows the 5th circuit structure example of the abnormality detection circuit in embodiment of this invention. It is a truth table of the abnormality detection circuit in the embodiment of the present invention. It is a circuit diagram which shows the circuit structure example of the conventional abnormality detection circuit.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 6.
The members, arrangements, etc. described below are not limited to the present invention, and can be variously modified within the scope of the gist of the present invention.
First, a first circuit configuration example of the abnormality detection circuit according to the embodiment of the present invention will be described with reference to FIG.
The abnormality detection circuit 101 according to the embodiment of the present invention is configured so that the load release, the ground fault, and the natural fault at the output terminal 26 of the load drive circuit 102 can be detected separately.

First, the load drive circuit 102 will be described.
The load drive circuit 102 according to the embodiment of the present invention basically has the same circuit configuration as the conventional one.
That is, the load drive circuit 102 is configured to include an output transistor (denoted as "Q1" in FIG. 1) 21 and a gate drive circuit (denoted as "G-DRV" in FIG. 1) 22. It has become.

The gate drive circuit 22 is configured to control the operation of the output transistor 21 using an N-channel MOSFET.
The gate and source of the output transistor 21 are connected to the output stage of the gate drive circuit 22, and the conduction and non-conduction of the output transistor 21 are controlled by controlling the gate-source voltage by the gate drive circuit 22. It has become a thing.

Further, the drain of the output transistor 21 is connected to the power supply terminal 25, while the source is connected to the output terminal 26.
A load 30 is connected between the output terminal 26 and the ground.

The abnormality detection circuit 101 includes first to third transistors for the detection circuit (denoted as "Qdet1", "Qdet2", and "Qdet3" in FIG. 1) 1 to 3 and a first diode (in FIG. 1). Is described as "D1") 11 and a constant current source 10 with a switch.

In the embodiment of the present invention, a compression type N-channel MOSFET is used for the first transistor 1 for the detection circuit.
N-channel MOSFETs are used for the second and third transistors 2 and 3 for the detection circuit.
A constant current source 10 with a switch is connected between the power supply terminal 25 and the output terminal 26, and the anode of the first diode 11 is connected to the output terminal 26.

The constant current source 10 with a switch outputs a constant current when the switch 10a is turned on (closed), while the constant current source 10 is in a high impedance state and the current output is output when the switch 10a is turned off (open). It is configured to be stopped.

The cathode of the first diode 11 is connected to the drain of the first transistor 1 for the detection circuit, and the source of the first transistor 1 for the detection circuit is connected to the drain of the second transistor 2 for the detection circuit together with the gate. ing. Here, the first transistor 1 for the detection circuit is provided in a so-called diode connected state.
The first diode 11 is a backflow prevention diode for preventing the generation of a reverse current when the output terminal 26 becomes a negative voltage.

The second and third transistors 2 and 3 for the detection circuit constitute the first current mirror circuit.
That is, first, the drain and the gate of the second transistor 2 for the detection circuit are connected to each other, and are also connected to the gate of the third transistor 3 for the detection circuit.

Further, the sources of the second and third transistors 2 and 3 for the detection circuit are both connected to the ground.
The drain of the third transistor 3 for the detection circuit, which is the output side of the current mirror circuit, is connected to the detection terminal 27 for taking out the detection current that is the result of the abnormality detection.

The second transistor 2 for the detection circuit functions as a constant current element that limits the inflow of current into the abnormality detection circuit 101. The current of the second transistor 2 for the detection circuit needs to be determined in consideration of the size of the output transistor 21 and the influence of the circuit configuration of the gate drive circuit 22, but it is generally a constant current element of about 10 μA to 100 μA. It is preferable to do so.

Next, the operation in the above configuration will be described.
The following description of the circuit operation includes a state in which the load drive circuit 102 is load-driven (ON), a state in which the load is not driven (OFF), and a case where the constant current source 10 with a switch is ON (operation). The circuit operation according to the state of the output terminal 26 will be described for each of the cases of OFF (non-operation).

First, a case where the load drive circuit 102 is OFF (the load drive is stopped), the constant current source 10 with a switch is ON, and the load 30 is normally connected will be described.
In this case, the output transistor 21 is in the OFF state by being controlled by the gate drive circuit 22 so that the gate-source voltage becomes lower than the threshold voltage.
Therefore, no current flows from the power supply terminal 25 to the output terminal 26 via the output transistor 21, but since the constant current source 10 with a switch is ON, the power supply terminal 25 passes through the constant current source 10 with a switch. A constant current flows into the output terminal 26.

In the circuit shown in FIG. 1, there are three routes 1) to 3) as follows from the output terminal 26 to the ground.
1) Path to ground via load 30 2) Path to ground via first diode 11, first transistor 1 for detection circuit and second transistor 2 for detection circuit 3) Output transistor 21 Route from the source to the ground via the gate drive circuit 22

Of these, in the third path 3), the output terminal 26 fluctuates from a negative voltage to a positive power supply voltage according to the operating state of the load drive, and the source potential and gate potential of the output transistor 21 follow this fluctuation. Also fluctuates. Therefore, the impedance of the output transistor 21 with respect to the source and the ground of the gate is high resistance, and in general, this path can be regarded as a resistance of several hundred kΩ.

Further, in the first path 1), the path via the load 30 has a much lower resistance than the other paths, and most of the current flows into this path.
For example, if the resistance value of the load 30 is 10Ω and the output current IC1 of the constant current source 10 with a switch is 50 μA, the voltage of the output terminal 26 is 0.5 mV, which can be regarded as substantially the same potential as the ground potential.

In this situation, no current flows into the anomaly detection circuit 101 via the first diode 11, and therefore a third detection circuit for the detection circuit that constitutes the first current mirror circuit and serves as its output stage. No detection current flows through the detection terminal 27 to which the drain of the transistor 3 of the above is connected.

Next, a case where the load drive circuit 102 is OFF, the constant current source 10 with a switch is ON, and the load is released will be described.
In this case, the output transistor 21 is in the OFF state when the gate-source voltage is controlled to be lower than the threshold voltage by the gate drive circuit 22.
Therefore, no current flows from the power supply terminal 25 to the output terminal 26 via the output transistor 21, but since the constant current source 10 with a switch is ON, the constant current source 10 with a switch is connected from the power supply terminal 25. A constant current flows into the output terminal 26 via the output terminal 26.

When the load 30 is disconnected, no current flows from the output terminal 26 to the load 30, and a current flows from the output terminal 26 to the ground via the gate drive circuit 22 or the abnormality detection circuit 101 to output. The voltage at the terminal 26 rises.
At this time, in order for the current to flow through the abnormality detection circuit 101 and the detection current to be output from the detection terminal 27, the voltage of the output terminal 26 is the forward voltage (VD1) of the first diode 11 and the detection circuit first. It needs to be higher than the sum of the saturation voltage (VE1) of the transistor 1 of 1, the threshold voltage (Vt2) of the second transistor 2 for the detection circuit, and the saturation voltage (VE2) of the second transistor 2 for the detection circuit. That is, the voltage VOUT of the output terminal 26 needs to satisfy the following equation 1.

VOUT> VD1 + VE1 + Vt2 + VE2 ... Equation 1

When this equation 1 is satisfied, a current flows from the output terminal 26 to the first diode 11, and the first transistor 2 and 3 for the detection circuit pass through the first transistor 1 for the detection circuit. The detection current is output from the detection terminal 27 by the current mirror circuit of.

For example, if VD1 = 0.7V, VE1 = 0.2V, Vt2 = 0.6V, and VE2 = 0.2V, the detection current will be output when the voltage of the output terminal 26 exceeds 1.7V.

Next, a case where the load drive circuit 102 is OFF, the constant current source 10 with a switch is ON, and the output terminal 26 is entwined will be described.
In this case, the potential of the output terminal 26 becomes a voltage substantially equal to the power supply voltage VCS, and the abnormality detection circuit 101 corresponds to the saturation current when the gate source voltage Vgs = 0V of the first transistor 1 for the detection circuit. A current flows from the output terminal 26 into the first diode 11. This current is currently mirrored by the first current mirror circuit by the second and third transistors 2 and 3 for the detection circuit, and as a result, the detection current is transmitted from the drain of the third transistor 3 for the detection circuit to the detection terminal 27. It will be output.

Next, a case where the load drive circuit 102 is OFF, the constant current source 10 with a switch is ON, and the output terminal 26 has a ground fault will be described.
In this case, the potential of the output terminal 26 becomes the ground potential, and the constant current from the constant current source 10 with a switch flows to the ground. Therefore, no current flows through the abnormality detection circuit 101, and the detection current is not output from the detection terminal 27.

The description of each operating state when the load drive circuit 102 described above is not load driven can be summarized as follows.
First, in a state where the load drive circuit 102 is not load-driven and the constant current source 10 with a switch is ON and a constant current is flowing, the abnormality detection circuit 101 detects the load release and the crown and detects the current. Is output.
On the other hand, in the state where the load drive circuit 102 is not load-driven, the abnormality detection circuit 101 does not output the detection current when the load 30 is normally connected and when the output terminal 26 has a ground fault.

Next, a case where the load drive circuit 102 is OFF, the constant current source 10 with a switch is OFF, and the load 30 is normally connected will be described.
In this case, the output transistor 21 is in the OFF state when the gate-source voltage is controlled to be lower than the threshold voltage by the gate drive circuit 22.
Therefore, no current flows from the power supply terminal 25 to the output terminal 26 via the output transistor 21.

Further, since the constant current source 10 with a switch is also turned off, the constant current does not flow from the power supply terminal 25 to the output terminal 26 via the constant current source 10 with a switch. Therefore, no current flows into the abnormality detection circuit 101, and no detection current flows.
In this case, since the output terminal 26 is connected to the ground with a low resistance load 30, the potential is substantially equal to the ground potential.

Next, a case where the load drive circuit 102 is OFF, the constant current source 10 with a switch is OFF, and the load is released will be described.
In this case, the output transistor 21 is in the OFF state when the gate-source voltage is controlled to be lower than the threshold voltage by the gate drive circuit 22. Therefore, no current flows from the power supply terminal 25 to the output terminal 26 via the output transistor 21.

Further, since the constant current source 10 with a switch is also turned off, the constant current does not flow from the power supply terminal 25 to the output terminal 26 via the constant current source 10 with a switch.
Therefore, no current flows into the abnormality detection circuit 101, and no detection current flows.
In this case, the output terminal 26 is connected to the ground with a load of high resistance via the gate drive circuit 22, so that the potential is substantially equal to the ground potential.

Next, a case where the load drive circuit 102 is OFF, the constant current source 10 with a switch is OFF, and the output terminal 26 is entwined will be described.
In this case, the potential of the output terminal 26 becomes a voltage substantially equal to the power supply voltage VCS.
In the abnormality detection circuit 101, a current corresponding to the saturation current when the gate source voltage Vgs = 0V of the first transistor 1 for the detection circuit flows into the first diode 11 from the output terminal 26.
This current is currently mirrored by the first current mirror circuit by the second and third transistors 2 and 3 for the detection circuit, and as a result, the detection current is transmitted from the drain of the third transistor 3 for the detection circuit to the detection terminal 27. It will be output.

Next, a case where the load drive circuit 102 is OFF, the constant current source 10 with a switch is OFF, and the output terminal 26 has a ground fault will be described.
In this case, the potential of the output terminal 26 becomes the ground potential, and since no current flows through either the first transistor 1 for the detection circuit or the constant current source 10 with a switch, no current flows through the abnormality detection circuit 101 for detection. No detection current is output from the terminal 27.

The operation of the abnormality detection circuit 101 described above can be summarized as described below.
That is, when the load drive circuit 102 is not load-driven and the constant current source 10 with a switch is OFF and the constant current is not flowing, the abnormality detection circuit 101 detects only the ceiling fault. The detection current is output, but the detection current is not output when the load 30 is normally connected and when the load is released and the ground fault occurs.

Next, the case where the load drive circuit 102 is load-driven will be described below.
In the following description, when the load drive circuit 102 is load driven, the output transistor 21 has a low impedance between the power supply terminal 25 and the output terminal 26, and the constant current source 10 with a switch outputs the output. Since the constant current has almost no effect on the state of the output terminal 26, the operation of the constant current source 10 with a switch when the load drive circuit 102 is load-driven is described without specifying either ON or OFF. I decided to.

First, a case where the load drive circuit 102 is ON (load drive execution state), the constant current source 10 with a switch is ON or OFF, and the load 30 is normally connected will be described.
In this case, since the output transistor 21 is turned on and the impedance between the power supply terminal 25 and the output terminal 26 becomes low, a current due to the application of the power supply voltage VCS flows to the load 30.

Then, the output terminal 26 has a potential lower than the power supply voltage VCS by the amount of the voltage drop which is the product of the ON resistance of the output ranger 21.
In the abnormality detection circuit 101, a current corresponding to the saturation current when the gate-source voltage Vgs = 0V of the first transistor 1 for the detection circuit flows into the first diode 11 from the output terminal 26. This current is current mirrored by the first current mirror circuit by the second and third transistors 2 and 3 for the detection circuit, and as a result, the detection current is output from the drain of the third transistor 3 for the detection circuit to the detection terminal 27. Will be done.

Next, a case where the load drive circuit 102 is ON, the constant current source 10 with a switch is ON or OFF, and the load is released will be described.
In this case, the output transistor 21 is turned on and the impedance between the power supply terminal 25 and the output terminal 26 becomes low, but since the load is open, no current flows to the ground via the load 30.
Further, since the gate potential of the output transistor 21 is higher than the source potential when it is turned ON, no current flows from the output terminal 26 via the gate drive circuit 22.

Therefore, only in the abnormality detection circuit 101, a current corresponding to the saturation current when the gate-source voltage Vgs = 0V of the first transistor 1 for the detection circuit flows into the first diode 11 from the output terminal 26. This current is currently mirrored by the first current mirror circuit by the second and third transistors 2 and 3 for the detection circuit, and as a result, the detection current is output from the drain of the third transistor 3 for the detection circuit to the detection terminal 27. Will be done.

Next, a case where the load drive circuit 102 is ON, the constant current source 10 with a switch is ON or OFF, and the output terminal 26 is entwined will be described.
In this case, the potential of the output terminal 26 becomes substantially equal to the power supply voltage VCS, and the abnormality detection circuit 101 corresponds to the saturation current when the gate-source voltage Vgs = 0V of the first transistor 1 for the detection circuit. The current flows from the output terminal 26 to the first diode 11. This current is currently mirrored by the first current mirror circuit by the second and third transistors 2 and 3 for the detection circuit, and as a result, the detection current is output from the drain of the third transistor 3 for the detection circuit to the detection terminal 27. Will be done.

Next, a case where the load drive circuit 102 is ON, the constant current source 10 with a switch is ON or OFF, and the output terminal 26 has a ground fault will be described.
In this case, the output terminal 26 becomes the ground potential.
Further, since the output transistor 21 is ON and the voltage between the power supply voltage VCC and the ground is applied between the drain and the source, the output transistor 21 operates in the saturation region.
However, since the current of the output transistor 21 flows directly to the ground, no current flows into the abnormality detection circuit 101, and no detection current flows.

FIG. 6 shows a truth table for each of the above-mentioned operating states, and the contents thereof will be described below with reference to the same figure.
First, when the load drive circuit 102 is OFF and the constant current source 10 with a switch is OFF, the detection current flows only when the output terminal 26 is entangled. That is, when the load drive circuit 102 is in the OFF state, the ceiling of the output terminal 26 can be monitored and detected without constantly passing a current (see the line of FIG. 6 (1)).

Further, when the load drive circuit 102 is OFF and the constant current source 10 with a switch is ON, a detection current flows when the output terminal 26 has a crown or the load is released, and the top fault of the output terminal 26 and the load release are monitored. , Detection is possible (see line in FIG. 6 (2)).
That is, when the load drive circuit 102 is in the OFF state and the constant current source 10 with a switch is alternately switched between the ON state and the OFF state in chronological order, abnormality detection that distinguishes between the ceiling of the output terminal 26 and the load release can be detected. It is possible.

Further, when the load drive circuit 102 is ON, the detection current does not flow only when the output terminal 26 has a ground fault regardless of whether the constant current source 10 with a switch is ON or OFF. Therefore, based on this event. It is possible to detect a ground fault at the output terminal 26 (see the line in FIG. 6 (3)).
Further, before the load drive by the load drive circuit 102 is started, the constant current source 10 with a switch is alternately switched between the ON state and the OFF state in chronological order to determine the tentacle and the load release (FIG. 6 (1)). (Refer to the line of (2) and (2)), and then, by starting the load drive, it is possible to distinguish between the ceiling fault, the load release, and the ground fault.

Next, a second circuit configuration example of the abnormality detection circuit according to the embodiment of the present invention will be described with reference to FIG.
The same components as those in the circuit configuration example shown in FIG. 1 are designated by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
The abnormality detection circuit 101A in the second circuit configuration example has a second circuit between the first diode 11 and the first transistor 1 for the detection circuit in the first circuit configuration example shown in FIG. A diode (denoted as "D2" in FIG. 2) 12 is inserted, and a third diode (denoted as "D3" in FIG. 2) is inserted between the first and second transistors 1 and 2 for the detection circuit. ) 13 has an inserted configuration.

That is, the anode of the second diode 12 is connected to the cathode of the first diode 11, and the cathode of the second diode 12 is connected to the drain of the first transistor 1 for the detection circuit.
Further, the anode of the third diode 13 is connected to the source of the first transistor 1 for the detection circuit, and the cathode of the third diode 13 is connected to the drain of the second transistor 2 for the detection circuit. ..

In such a configuration, the voltage of the output terminal 26 when the detection current starts to flow through the detection terminal 27 can be increased.
In the case of the first circuit configuration example shown in FIG. 1, the relationship between the voltage of the output terminal 26 when the detection current starts to flow and the voltage of the main element of the abnormality detection circuit 101 is as described above. It is represented by Equation 1, but in this second circuit configuration example, the relationship is represented by Equation 2 below.

VOUT> VD1 + VD2 + VE1 + VD3 + Vt2 + VE2 ... Equation 2

Here, VD2 is the forward voltage of the second diode 12, and VD3 is the forward voltage of the third diode 13.
That is, in the case of the second circuit configuration example, the threshold value of the voltage of the output terminal 26 when the abnormality detection circuit 101A detects the load release or the crown is the diode 2 as compared with the first circuit configuration example. The forward voltage of the element increases.

As shown in FIG. 2, the position where the diode is inserted is between the first diode 11 and the first transistor 1 for the detection circuit, or between the first transistor 1 for the detection circuit and the detection circuit. Between the second transistors 2, the number of diodes to be inserted may be one in total, or may be plural or any.
The circuit operation of the second circuit configuration example is basically the same as that of the first circuit configuration example except that the voltage threshold value of the output terminal 26 when detecting load release or ceiling fault is different. The detailed description here will be omitted again.

Next, a third circuit configuration example of the abnormality detection circuit according to the embodiment of the present invention will be described with reference to FIG.
The components that are the same as the components in the circuit configuration examples shown in FIGS. 1 and 2 are designated by the same reference numerals, detailed description thereof will be omitted, and the differences will be mainly described below. ..
The abnormality detection circuit 101B in the third circuit configuration example is located between the first transistor 1 for the detection circuit and the second transistor 2 for the detection circuit in the first circuit configuration example shown in FIG. , A resistor (denoted as "R1" in FIG. 3) 15 is provided.

That is, one end of the resistor 15 is connected to the source of the first transistor 1 for the detection circuit, and the other end of the resistor 15 is connected to the drain of the second transistor 2 for the detection circuit.
By inserting the resistor 15 in this way, it is possible to increase the voltage of the output terminal 26 when the detection current starts to flow in the detection terminal 27 of the abnormality detection circuit 101B.
In the case of the first circuit configuration example shown in FIG. 1, the relationship between the voltage of the output terminal 26 when the detection current starts to flow and the voltage of the main element of the abnormality detection circuit 101 is as described above. Although it is represented by Equation 1, in this third circuit configuration example, the relationship is represented by Equation 3 below.

VOUT> VD1 + VE1 + R1 x ID1 + Vt2 + VE2 ... Equation 3

Here, ID1 is a current flowing from the output terminal 26 into the first diode 11.
After all, in this third circuit configuration example, the threshold value of the voltage of the output terminal 26 in which the abnormality detection circuit 101B detects the load release or the ceiling is the voltage generated by the resistor 15 as compared with the first circuit configuration example. It will be higher by the amount of descent.

The position where the resistor 15 is inserted does not have to be limited to the example shown in FIG. 3, for example, between the output terminal 26 and the first diode 11, the first diode 11 and the first diode 11 for the detection circuit. It may be any one between the transistor 1 of 1 and the first transistor 1 for the detection circuit and the second transistor 2 for the detection circuit.

The circuit operation of the third circuit configuration example is basically the same as that of the first circuit configuration example except that the voltage threshold value of the output terminal 26 when detecting load release or ceiling fault is different. The detailed description here will be omitted again.

Next, a fourth circuit configuration example of the abnormality detection circuit according to the embodiment of the present invention will be described with reference to FIG.
The components that are the same as the components in any of the circuit components of FIGS. 1 to 3 are designated by the same reference numerals, detailed description thereof will be omitted, and the differences will be mainly described below. ..
The abnormality detection circuit 101C in the fourth circuit configuration example is a constant current source 10A with a switch configured as described later in place of the constant current source 10 with a switch in the first circuit configuration example shown in FIG. It is configured to use.

The constant current source 10A with a switch uses the first to fourth transistors for the constant current source (indicated as "Qcc1", "Qcc2", "Qcc3", and "Qcc4" in FIG. 4, respectively) 5 to 8. It is configured.
In the embodiment of the present invention, the first and second transistors 5 and 6 for the constant current source are equipped with P-channel MOSFETs, and the third transistor 7 for the constant current source is provided with a compression type N-channel MOSFET. N-channel MOSFETs are used for the fourth transistor 8 for the constant current source.

Hereinafter, a specific configuration of the constant current source 10A with a switch will be described.
First, the first and second transistors 5 and 6 for the constant current source form a second current mirror circuit, and the second transistor 6 for the constant current source is the input stage and the first transistor for the constant current source. 5 is connected and configured as described below so as to be an output stage.

The sources of the first transistor 5 for the constant current source and the second transistor 6 for the constant current source are connected to each other and connected to the power supply terminal 25, while the drain of the first transistor 5 for the constant current source is The drain of the second transistor 6 for the constant current source is connected to the anode of the first diode 11 to the drain of the third transistor 7 for the constant current source.

Further, the gates of the first transistor 5 for the constant current source and the second transistor 6 for the constant current source are connected to each other, and are also connected to the drain of the second transistor 6 for the constant current source. Here, the second transistor 6 for the constant current source is in a so-called diode-connected state.

The gate and the source of the third transistor 7 for the constant current source are connected to each other and are connected to the drain of the fourth transistor 8 for the constant current source, so that the source of the fourth transistor 8 for the constant current source is connected. Is connected to the ground.
Further, the gate of the fourth transistor 8 for the constant current source is connected to the control signal application terminal (denoted as “EN” in FIG. 4) 28.

In such a configuration, when a voltage corresponding to the logical value High is input to the control signal application terminal 28 as a control signal from the outside, the fourth transistor 8 for the constant current source is turned on, and the third transistor 8 for the constant current source is turned on. The transistor 7 functions as a constant current source, and a saturation current corresponding to a gate-source voltage of 0 V flows through the transistor 7.
The saturation current flowing through the third transistor 7 for the constant current source is transferred to the first transistor 5 for the constant current source by the second current mirror circuit composed of the first and second transistors 5 and 6 for the constant current source. Current mirrored. As a result, a current proportional to the saturation current of the third transistor 7 for a constant current source flows through the output terminal 26.

On the other hand, when a voltage corresponding to the logical value Low is input to the control signal application terminal 28 as a control signal, the fourth transistor 8 for the constant current source is turned off and the third transistor 7 for the constant current source is turned off. Since no current flows through the current, no current flows from the first transistor 5 for the constant current source to the output terminal 26.
As described above, the constant current source 10A with a switch in the fourth circuit configuration example is a constant current source with a switch that supplies a current from the power supply voltage VCS to the output terminal 26 by controlling the voltage of the control signal application terminal 28. Functions as.

The circuit operation of the fourth circuit configuration example is basically the same as that of the first circuit configuration example, except that the constant current source 10A with a switch composed of semiconductor elements is used as described above. Therefore, the detailed description here will be omitted again.

Next, a fifth circuit configuration example of the abnormality detection circuit according to the embodiment of the present invention will be described with reference to FIG.
The components that are the same as the components in any of the circuit components of FIGS. 1 to 4 are designated by the same reference numerals, detailed description thereof will be omitted, and the differences will be mainly described below. ..
The abnormality detection circuit 101D in the fifth circuit configuration example is the second transistor 2 for the detection circuit and the detection circuit for forming the first current mirror circuit in the abnormality detection circuit 101 of the circuit configuration example shown in FIG. A fourth transistor 4 for the detection circuit is provided between the gate and the ground of the third transistor 3, and the operation of the current mirror circuit composed of the second and third transistors 2 and 3 for the detection circuit is externally operated. It has a configuration that can be turned on and off according to a control signal from.

Hereinafter, a specific circuit configuration will be described.
In the embodiment of the present invention, an N-channel MOSFET is used for the fourth transistor 4 for the detection circuit.
The drain of the fourth transistor 4 for the detection circuit is connected to the gates of the second and third transistors 2 and 3 for the detection circuit, while the source is connected to the ground.
Further, the gate of the fourth transistor 4 for the detection circuit is applied to the control signal application terminal 28.

In such a configuration, when the load drive circuit 102 is not load-driven, a control signal corresponding to the logical value Low is constantly applied to the control signal application terminal 28, and the fourth transistor 4 for the detection circuit is inserted. By turning it off, the current mirror circuit composed of the second and third transistors 2 and 3 for the detection circuit is set to the same circuit state as the current mirror circuit in the first circuit configuration example. You can get the operation of.

Further, even when the control signal corresponding to the logical value Low is constantly applied to the control signal application terminal 28 in the state where the load drive circuit 102 is load-driven, the second and third detection circuits are used as described above. The same operation can be obtained by setting the first current mirror circuit composed of the transistors 2 and 3 in the same circuit state as the current mirror circuit in the first circuit configuration example.
That is, in this fifth circuit configuration example, when the load drive circuit 102 is OFF, the control signal of the logical value Low is constantly applied to the control signal application terminal 28 and used, which is the same as the first circuit configuration example. The function can be realized.

On the other hand, when the load drive circuit 102 is load-driven and a control signal corresponding to the logical value High is constantly applied to the control signal application terminal 28, the fourth transistor 4 for the detection circuit is turned on and detected. The gates of the second and third transistors 2 and 3 for the circuit are short-circuited to the ground. Therefore, even if a current flows from the output terminal 26 to the first diode 11, the current flows to the ground via the first transistor 1 for the detection circuit and the fourth transistor 4 for the detection circuit, so that the detection terminal 27 The current from the drain of the third transistor 3 for the detection circuit is not output via.
That is, in this fifth circuit configuration example, the abnormality detection circuit 101D is invalidated by constantly applying the control signal of the logical value High to the control signal application terminal 28 while the load drive circuit 102 is load-driven. It becomes the state of.

As described above, the abnormality detection circuit 101D in the fifth circuit configuration example uses the function of the abnormality detection circuit 101D and is load-driven when the load is not driven by the voltage control of the control signal application terminal 28. Then, the abnormality detection circuit 101D can be appropriately disabled to allow, for example, a separately prepared abnormality detection circuit (not shown) to function.

The present invention is not limited to the above-described circuit configuration examples. For example, in the embodiment of the present invention, the N-channel MOSFET is used for the output transistor 21, but the load is driven by using the P-channel MOSFET. A circuit may be configured.
Further, in the embodiment of the present invention, the second and third transistors 2 and 3 for the detection circuit constituting the first current mirror circuit and the first and third transistors for the constant current source constituting the second current mirror circuit Although MOSFETs are used for the second transistors 5 and 6, bipolar transistors may be used.

It can be applied to an abnormality detection circuit in which highly reliable detection is desired with low current consumption of the output terminal and the load release when the load drive circuit is not operating.

1 to 4 ... 1st to 4th transistors for detection circuit 5 to 8 ... 1st to 4th transistors for constant current source 11 to 13 ... 1st to 3rd diodes 10, 10A ... Constant current source with switch

Claims (8)

An abnormality detection circuit that has an output transistor and a gate drive circuit that controls the drive of the output transistor, and detects an abnormality in the output terminal of a load drive circuit that is configured to be able to drive a load connected to the output terminal. And
In the abnormality detection circuit, a constant current source with a switch is connected between a power supply terminal to which the power supply voltage of the load drive circuit is applied and an output terminal, and the constant current source with a switch controls the presence or absence of a constant current output. Configured with a switch that enables
The anode of the first diode is connected to the output terminal, and the drain of the first transistor for the compression type detection circuit is connected to the cathode of the first diode, so that the first transistor for the detection circuit is connected. The gate and source are connected to each other and connected to the input side of the first current mirror circuit, and the detection current according to the result of abnormality detection can be output to the output side of the first current mirror circuit. An abnormality detection circuit characterized by being made. The abnormality detection circuit according to claim 1, wherein one or a plurality of diodes are provided in the path from the first diode to the input side of the first current mirror circuit. The abnormality detection circuit according to claim 1 or 2, wherein a resistor is provided in a path from the output terminal to the input side of the first current mirror circuit. The constant current source with a switch has a second current mirror circuit composed of first and second transistors for the constant current source, and the output side of the second current mirror circuit is the power supply terminal and the output terminal. On the input side of the second current mirror circuit, there is a third transistor for a constant current source, which is a compression type MOS transistor that is connected to a diode and functions as a constant current element. A fourth current source transistor is provided in series, and the constant current source fourth transistor is turned on and off by a control signal applied from the outside, and the second current is controlled. The abnormality detection circuit according to any one of claims 1 to 3, wherein the output of the current on the output side of the mirror circuit can be controlled. A fourth transistor for a detection circuit is provided so that the gate and ground of the two transistors constituting the first current mirror circuit can be short-circuited according to a control signal applied from the outside. The abnormality detection circuit according to any one of claims 1 to 4, wherein the abnormality detection circuit is characterized. In a state where the load drive circuit is in the off state and the load drive is stopped, by turning off the constant current source with a switch, the presence / absence of a ceiling fault of the output terminal is determined, and immediately after the determination is completed, By turning on the constant current source with a switch, the load of the output terminal is released or the presence or absence of a tentacle is determined.
When the load drive circuit is on and the load drive is being executed, it is determined that the output terminal has a ground fault regardless of whether the constant current source with a switch is on or off. The abnormality detection circuit according to any one of claims 1 to 5, which is characterized. In a state where the load drive circuit is in the off state and the load drive is stopped, by turning off the constant current source with a switch, the presence or absence of a ceiling fault of the output terminal is determined, and immediately after the determination is completed, By turning on the constant current source with a switch, the load of the output terminal is released or the presence or absence of a tentacle is determined, and the result of the determination of the load release or the presence or absence of a tentacle can distinguish between the load release and the load release. The abnormality detection circuit according to any one of claims 1 to 5, wherein the abnormality detection circuit is configured according to any one of claims 1 to 5. In a state where the load drive circuit is in the off state and the load drive is stopped, by turning off the constant current source with a switch, the presence or absence of a ceiling fault of the output terminal is determined, and immediately after the determination is completed, By turning on the constant current source with a switch, the load of the output terminal is released or the presence or absence of a tentacle is determined, and after the load release or the presence or absence of a tentacle is determined, the load drive circuit is turned on. By setting the load drive execution state, the presence / absence of a ground fault at the output terminal is determined, and the result of the determination of the presence / absence of the ground fault makes it possible to distinguish between a ceiling fault, a load release, and a ground fault. The abnormality detection circuit according to any one of claims 1 to 5.

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