JP2020140621A - Information processing device and information processing method - Google Patents

Abstract

To provide an information processing device capable of efficiently writing firmware to multiple processors.SOLUTION: An information processing device includes a first board having a first processor to which the first rank is assigned in a hierarchical structure and a first memory, and a second board having a second processor to which the second rank is assigned in the hierarchical structure and a second memory. In response to acquisition of first write execution data including second write execution data that causes the second processor to write second firmware to the second memory, the first processor outputs the second write execution data included in the first write execution data to the second processor, and writes first firmware to the first memory based on the first write execution data that causes the first processor to write the first firmware to the first memory. In data structure, the second write execution data is the same as the first write execution data.SELECTED DRAWING: Figure 6

Description

The present invention relates to an information processing apparatus and an information processing method.

Research and development are being conducted on a technology for efficiently writing firmware to a processor provided on each of a plurality of boards provided in an information processing device. In the present specification, writing a certain firmware to a certain processor means installing the firmware in a memory for storing data read by the processor, or updating the firmware in the memory.

In this regard, Patent Document 1 describes, in an information processing apparatus having a plurality of different boards having each of a plurality of processors to which each rank is assigned in a predetermined hierarchical structure, firmware for each of the plurality of processors. Is described (see Patent Document 1).

Japanese Unexamined Patent Publication No. 2008-204290

Here, in the method described in Patent Document 1, it is necessary to independently create write execution data for writing firmware to the processor for each of the processors of each substrate. The write execution data is, for example, an installer or the like. Therefore, with this method, it may be difficult to reduce the time and effort required to write the firmware for each processor. That is, in this method, it may be difficult to efficiently write the firmware to the processors of the plurality of boards.

In order to solve the above problems, one aspect of the present invention has a first processor to which a first rank is assigned in a determined hierarchical structure, and a first memory for storing data read by the first processor. A second substrate having a substrate, a second processor to which a second rank one rank lower than the first rank is assigned in the hierarchical structure, and a second memory for storing data read by the second processor. When the first processor acquires the first write execution data including the second write execution data for causing the second processor to write the second firmware to the second memory, the first processor The first write execution that outputs the second write execution data included in the first write execution data to the second processor and causes the first processor to write the first firmware to the first memory. An information processing apparatus that writes the first firmware to the first memory based on the data, and the data structure of the second write execution data is the same data structure as the data structure of the first write execution data. ..

Further, in one aspect of the present invention, in the information processing apparatus, the first output destination data indicating one or more output destinations capable of outputting data from the first processor is further stored in the first memory. The first write execution data includes second output destination data indicating the second processor as an output destination of the second write execution data, and the first processor executes the first write. When the data is acquired, and when one or more output destinations indicated by the first output destination data include the second processor indicated by the second output destination data, the first write execution data includes the second processor. A configuration may be used in which the included second write execution data is output to the second processor.

Further, one aspect of the present invention is that in the information processing device, when the first processor acquires the first write execution data, and to one or more output destinations indicated by the first output destination data. If the second processor indicated by the second output destination data is not included, a configuration that outputs an error may be used.

Further, in one aspect of the present invention, in the information processing unit, when the second firmware included in the second write execution data is empty data, the second processor sends the second memory to the second memory. 2 A configuration may be used in which data indicating that the second firmware has been successfully written to the second memory is output to the first processor without writing the firmware.

Further, in one aspect of the present invention, in the information processing device, the first processor outputs the second write execution data included in the first write execution data to the second processor, and then the second processor. When data indicating that the writing of the second firmware to the memory is successful is acquired from the second processor, the first data is written to the first memory based on the first writing execution data. It may be used.

Further, in one aspect of the present invention, in the information processing unit, the first processor outputs the second write execution data included in the first write execution data to the second processor, and then the second processor. When data indicating that the writing of the second firmware to the memory has failed is acquired from the second processor, a configuration may be used in which the writing of the first firmware to the first memory is not performed.

Further, in one aspect of the present invention, in the information processing apparatus, a third processor to which a third rank, which is one rank lower than the second rank in the hierarchical structure, is assigned, and data read by the third processor are assigned. A third board having a third memory for storing is further provided, and the second write execution data includes third write execution data that causes the third processor to write the third firmware to the third memory. Including, the data structure of the third write execution data is the same data structure as the data structure of the second write execution data, and when the second processor acquires the second write execution data, the said The configuration is used in which the third write execution data included in the second write execution data is output to the third processor, and the second firmware is written to the second memory based on the second write execution data. May be done.

Further, one aspect of the present invention includes a first substrate having a first processor to which a first rank is assigned in a determined hierarchical structure and a first memory for storing data read by the first processor, and the hierarchical structure. An information processing apparatus including a second processor to which a second rank, which is one rank lower than the first rank, is assigned, and a second substrate having a second memory for storing data read by the second processor. When the first processor acquires the first write execution data including the second write execution data for causing the second processor to write the second firmware to the second memory. The first processor outputs the second write execution data included in the first write execution data to the second processor, and writes the first firmware to the first memory to the first processor. The first processor writes the first firmware to the first memory based on the first write execution data, and the data structure of the second write execution data is the data structure of the first write execution data. It is an information processing method that has the same data structure as.

It is a figure which shows an example of the structure of the information processing apparatus 1 which concerns on embodiment. It is a figure which shows an example of the data structure of the write execution data corresponding to a certain 1st processor. It is a figure which shows an example of the data structure of the component C1 shown in FIG. It is a figure which shows an example of the data structure of the writing block W1 shown in FIG. It is a figure which shows an example of the flow of the process performed by the target 1st processor when the write execution data corresponding to the target 1st processor is acquired. It is a figure which shows an example of the flow in which each processor P acquires the write execution data when the write execution data corresponding to the processor P01 is output to the processor P01 from an information processing apparatus 12.

<Embodiment>
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Configuration of information processing system>
First, the configuration of the information processing system 1 according to the embodiment will be described. FIG. 1 is a diagram showing an example of the configuration of the information processing system 1 according to the embodiment.

The information processing system 1 includes an information processing device 11 and an information processing device 12.

The information processing device 11 is, for example, a printer. The information processing device 11 may be another electronic device such as a scanner, a robot, a medical device, or a communication device instead of the printer.

The information processing device 11 includes a plurality of substrates. In the example shown in FIG. 1, the information processing apparatus 11 includes nine substrates, which are a substrate L01, a substrate L11, a substrate L12, a substrate L13, a substrate L21, a substrate L22, a substrate L23, a substrate L31, and a substrate L32. In the following, for convenience of explanation, the nine substrates of the information processing apparatus 11 including the substrate L01, the substrate L11, the substrate L12, the substrate L13, the substrate L21, the substrate L22, the substrate L23, the substrate L31, and the substrate L32 are simply referred to as 9 substrates. It will be described as a single substrate. Some or all of the nine substrates may have the same configuration or different configurations from each other. However, each of the nine boards has a processor and a memory for storing data read by the processor. Further, in each of the nine substrates, the processor and the memory included in the substrate may be integrally configured as one chip, or may be separately configured as separate chips.

In FIG. 1, the processor included in the substrate L01 is shown as the processor P01, and the memory included in the substrate L01 is shown as the memory M01. Further, in FIG. 1, the processor included in the substrate L11 is shown as the processor P11, and the memory included in the substrate L11 is shown as the memory M11. Further, in FIG. 1, the processor included in the substrate L12 is shown as the processor P12, and the memory included in the substrate L12 is shown as the memory M12. Further, in FIG. 1, the processor included in the substrate L13 is shown as the processor P13, and the memory included in the substrate L13 is shown as the memory M13. Further, in FIG. 1, the processor included in the substrate L21 is shown as the processor P21, and the memory included in the substrate L21 is shown as the memory M21. Further, in FIG. 1, the processor included in the substrate L22 is shown as the processor P22, and the memory included in the substrate L22 is shown as the memory M22. Further, in FIG. 1, the processor included in the substrate L23 is shown as the processor P23, and the memory included in the substrate L23 is shown as the memory M23. Further, in FIG. 1, the processor included in the substrate L31 is shown as the processor P31, and the memory included in the substrate L31 is shown as the memory M31. Further, in FIG. 1, the processor included in the substrate L32 is shown as the processor P32, and the memory included in the substrate L32 is shown as the memory M32.

In the following, for convenience of explanation, the nine processors of the processor P01, the processor P11, the processor P12, the processor P13, the processor P21, the processor P22, the processor P23, the processor P31, and the processor P32 included in the information processing device 11 are simply referred to as 9 processors. It will be referred to as a single processor. Further, in the following, for convenience of explanation, unless it is necessary to distinguish each of the nine processors, they will be collectively referred to as a processor P.

Further, in the following, for convenience of explanation, nine memories of the information processing device 11 including the memory M01, the memory M11, the memory M12, the memory M13, the memory M21, the memory M22, the memory M23, the memory M31, and the memory M32 are referred to. It will be described simply as 9 memories. Further, in the following, for convenience of explanation, unless it is necessary to distinguish each of the nine memories, they will be collectively referred to as memory M.

The processor P is, for example, a CPU (Central Processing Unit). The processor P reads the data stored in the memory M and performs processing based on the read data. Further, when some data is acquired from another information processing device, the processor P performs processing based on the acquired data. Note that some or all of the nine processors may be other processors such as FPGA (Field Programmable Gate Array) instead of the CPU. That is, some or all of the nine processors may have different configurations or may have the same configuration.

Each of the nine processors cooperates with each other to cause the information processing device 11 to perform various operations. When the information processing device 11 is a printer as in the present embodiment, the nine processors cooperate with each other to print the image data received from the user on a medium such as roll paper. However, this is only an example, and some or all of the nine processors may be processors that process independently of each other. The role of each of the nine processors is determined by the designer of the device, depending on the device to which the nine processors are applied. Therefore, the specific roles of each of the nine processors in the information processing device 11 will not be described.

The memory M is, for example, a flash memory. In the memory M, various data are written by the processor P. Further, the memory M reads the data stored in the memory M by the processor P. In addition, a part or all of the nine memories may be another storage medium such as a ROM (Read Only Memory) instead of the flash memory. That is, a part or all of the nine memories may have different configurations or the same configurations.

Further, the board L01 has an external connection port such as a USB (Universal Serial Bus) port. As a result, the processor P01 can communicate with other devices via the external connection port. In the example shown in FIG. 1, the information processing device 12 is connected to the processor P01 via the external connection port. Further, in this example, eight of the nine boards other than the board L01 do not have the external connection port. In addition, a part or all of the eight boards may be configured to have the external connection port. Further, the substrate L01 may have a configuration that does not have the connection port.

In addition, each of the nine boards has a port for serial communication. As a result, each of the nine boards can communicate with other devices via the port. In addition, a part of the nine boards may be configured not to have the port.

The information processing device 12 is, for example, a notebook PC, a tablet PC, a desktop PC, a multifunctional mobile phone terminal, a PDA (Personal Digital Assistant), or the like. Here, the multifunctional mobile phone terminal is, that is, a smartphone. The information processing device 12 may be another information processing device instead of these.

The information processing device 12 outputs data desired by the user to the processor P of the board to which the information processing device 12 is connected according to the operation received from the user. In the example shown in FIG. 1, the processor P is the processor P01. That is, in this example, the information processing device 12 is communicably connected to the processor P01. Therefore, in the example, the information processing device 12 outputs the data desired by the user to the processor P01 in response to the operation.

<Connection mode and hierarchical structure between processors>
Next, the connection mode and the hierarchical structure between the nine processors in the information processing device 11 will be described.

In the example shown in FIG. 1, the processor P01 is communicably connected to each of the processors P11 to P13. Further, in this example, the processor P11 is communicably connected to each of the processor P21 and the processor P22. Further, in this example, the processor P13 is communicably connected to the processor P23. Further, in this example, the processor P23 is communicably connected to each of the processor P31 and the processor P32. The connection relationship of the nine processors may be another connection relationship instead of the connection relationship shown in FIG.

Further, each of the nine processors is assigned a rank in a predetermined hierarchical structure in the information processing apparatus 11. The predetermined hierarchical structure is determined by, for example, the physical communication path of each of the nine processors and the processor to which the highest rank is assigned by the designer of the information processing device 11 among the nine processors. It is a hierarchical structure. In the example shown in FIG. 1, the processor to which the highest rank is assigned by the designer among the nine processors is the processor P01.

When the rank assigned to the processor P01 is the highest in the hierarchical structure for each of the nine processors, the three processors through which the processor P01 can flow data, that is, each of the processors P11 to P13, A rank one rank lower than the processor P01 is assigned. Further, in this case, among the processors P to which the processor P11 can flow data, the processors P to which the rank one lower than the processor P11 is assigned in the hierarchical structure are the processor P21 and the processor P22, respectively. This is because the processor P01 is the processor P to which the rank one higher than the processor P11 is assigned in the hierarchical structure. Further, in this case, among the processors P to which the processor P12 can flow data, there is no processor P to which the rank one lower than the processor P12 is assigned in the hierarchical structure. This is because the processor P01 is the processor P to which the rank one higher than the processor P12 is assigned in the hierarchical structure. Further, in this case, among the processors P to which the processor P13 can flow data, the processor P to which the rank one lower than the processor P13 is assigned in the hierarchical structure is the processor P23. This is because the processor P01 is the processor P to which the rank one higher than the processor P13 is assigned in the hierarchical structure. Further, in this case, among the processors P to which the processor P21 can flow data, there is no processor P to which the rank one lower than the processor P21 is assigned in the hierarchical structure. This is because the processor P11 is the processor P to which the rank one higher than the processor P21 is assigned in the hierarchical structure. Further, in this case, among the processors P to which the processor P22 can flow data, there is no processor P to which the rank one lower than the processor P22 is assigned in the hierarchical structure. This is because the processor P11 is the processor P to which the rank one higher than the processor P22 is assigned in the hierarchical structure. Further, in this case, among the processors P to which the processor P23 can flow data, the processors P to which the rank one lower than the processor P23 is assigned in the hierarchical structure are the processor P31 and the processor P32, respectively. This is because the processor P13 is the processor P to which the rank one higher than the processor P23 is assigned in the hierarchical structure. Further, in this case, among the processors P to which the processor P31 can flow data, there is no processor P to which the rank one lower than the processor P31 is assigned in the hierarchical structure. This is because the processor P23 is a processor to which a higher rank than the processor P31 is assigned in the hierarchical structure. Further, in this case, among the processors P to which the processor P32 can flow data, there is no processor P to which the rank one lower than the processor P32 is assigned in the hierarchical structure. This is because the processor P23 is a processor to which a higher rank than the processor P32 is assigned in the hierarchical structure.

That is, in the example shown in FIG. 1, the processor P01 is assigned the highest rank in the hierarchical structure as described above. Further, each of the processors P11 to P13 is assigned a second rank in the hierarchical structure. Further, each of the processors P21 to P23 is assigned a third rank in the hierarchical structure. Further, each of the processor P31 and the processor P32 is assigned the lowest rank in the hierarchical structure.

As described above, the hierarchical structure for each of the nine processors is determined by the physical communication path of each of the nine processors and the processor P to which the highest rank is assigned by the designer of the information processing unit 11. In the following, for convenience of explanation, the hierarchical structure for each of the nine processors will be described simply as a hierarchical structure. In the information processing device 11, when two processors having the same rank assigned in the hierarchical structure among the nine processors are connected to each other so as to be able to communicate with each other, the higher rank is ranked among the two processors. Is assigned, for example, may be determined by the designer of the information processing unit 11, or may be determined by another method.

<Processing process for processor to write firmware>
Hereinafter, the process in which the processor P writes the firmware in the information processing device 11 will be described. In the following, for convenience of explanation, when it is referred to as writing firmware to a certain processor P, it means writing firmware corresponding to the processor P to the processor P.

In the information processing unit 11, when a certain processor P acquires the write execution data corresponding to the processor P, the processor P writes the firmware corresponding to the processor P to the memory M based on the acquired write execution data. Here, the firmware is included in the write execution data. That is, in this case, the processor P writes the firmware included in the acquired write execution data to the memory M.

Here, the data structure of the write execution data will be described. The write execution data corresponding to each of the nine processors to which each rank is assigned in the hierarchical structure is configured as one data by the recursive data structure. In order to explain that the data structure of the write execution data is a recursive data structure, in the following, for convenience of explanation, the processor P to which the first rank is assigned in the hierarchical structure is referred to as the first processor, and the first processor. A processor P to which a second rank, which is one rank lower than the first rank, is assigned among the processors P communicably connected to the second processor will be referred to as a second processor. The first rank may be any rank as long as the rank is one rank higher than the second rank in the hierarchical structure. Further, the second rank may be any rank as long as it is a rank other than the highest rank among the ranks in the hierarchical structure. For example, when the first processor is the processor P01, the second processor is the processor P11. Further, for example, when the first processor is the processor P23, the second processor is the processor P31.

When the write execution data has a recursive data structure, the first write execution data includes the second write execution data. The first write execution data is the write execution data corresponding to the first processor. The second write execution data is the write execution data corresponding to the second processor. The data structure of the second write execution data is the same as the data structure of the first write execution data.

Specifically, in the present embodiment, the write execution data corresponding to the processor P01 to which the highest rank is assigned in the hierarchical structure includes three processors P communicably connected to the processor P01. Moreover, the write execution data corresponding to each of the three processors P to which the second rank is assigned in the hierarchical structure is included. The three processors P are, that is, processors P11 to P13. The data structures of the write execution data corresponding to each of the processor P01, the processor P11, the processor P12, and the processor P13 are the same as each other.

In the present embodiment, the data structure of a certain target data indicates how a plurality of types of data included in the target data are arranged in the target data. For example, the fact that the data structure of one data X1 and the data structure of another data X2 are the same as each other means that the data X1 includes only three types of data: type S1, data of type S2, and data of type S3. If so, the data X2 also contains only three types of data, that is, type S1, data of type S2, and data of type S3, and the order of the three types of data in the data X1. , Means that the order of the three types of data in the data X2 is the same. However, even in this case, the fact that the data structure of the data X1 and the data structure of the data X2 are the same is that the contents indicated by the data of the type S1 included in the data X1 and the type S1 included in the data X2. It does not mean that the contents shown by the data are the same as each other. Further, even in this case, the fact that the data structure of the data X1 and the data structure of the data X2 are the same is that the contents indicated by the data of the type S2 included in the data X1 and the type S2 included in the data X2. It does not mean that the contents shown by the data are the same as each other. Further, even in this case, the fact that the data structure of the data X1 and the data structure of the data X2 are the same is that the contents indicated by the data of the type S3 included in the data X1 and the data structure of the type S3 included in the data X2. It does not mean that the contents shown by the data are the same as each other.

Further, in the present embodiment, the write execution data corresponding to the processor P11 to which the second rank is assigned in the hierarchical structure is the two processors P communicably connected to the processor P11, and the hierarchy. The write execution data corresponding to each of the two processors P to which the third rank is assigned in the structure is included. The two processors P are, that is, the processor P21 and the processor P22. The data structures of the write execution data corresponding to each of the processor P11, the processor P21, and the processor P22 are the same as each other.

Further, in the present embodiment, the write execution data corresponding to the processor P12 to which the second rank is assigned in the hierarchical structure is the processor P communicably connected to the processor P12, and 3 in the hierarchical structure. Since the processor P to which the second rank is assigned is not connected to the processor P12, empty data is included as the write execution data corresponding to the processor P. The empty data included in the write execution data corresponding to the processor P12 is any data indicating that the processor P to which the third rank is assigned in the hierarchical structure is not connected to the processor P12 in the present embodiment. It may be data, for example, null data or the like.

Further, in the present embodiment, the write execution data corresponding to the processor P13 to which the second rank is assigned in the hierarchical structure is the processor P communicably connected to the processor P13, and 3 in the hierarchical structure. The write execution data corresponding to the processor P to which the second rank is assigned is included. The processor P is, that is, the processor P23. The data structures of the write execution data corresponding to each of the processor P13 and the processor P23 are the same as each other.

Further, in the present embodiment, the write execution data corresponding to the processor P23 to which the third rank is assigned in the hierarchical structure is the two processors P communicably connected to the processor P23, and the hierarchy. The write execution data corresponding to each of the two processors P to which the lowest rank is assigned in the structure is included. The two processors P are, that is, the processor P31 and the processor P32. The data structures of the write execution data corresponding to each of the processor P23, the processor P31, and the processor P32 are the same as each other.

Further, in the present embodiment, the write execution data corresponding to the processor P31 to which the lowest rank is assigned in the hierarchical structure is the processor P communicably connected to the processor P31, and is the highest in the hierarchical structure. Since the processor P to which the rank lower than the lower rank is assigned is not connected to the processor P31, empty data is included as the write execution data corresponding to the processor P. The empty data included in the write execution data corresponding to the processor P31 is data indicating that the processor P to which the lower rank than the lowest rank is assigned in the hierarchical structure is not connected to the processor P31 in the present embodiment. Any data can be used as long as it is available, for example, null data or the like.

Further, in the present embodiment, the write execution data corresponding to the processor P32 to which the lowest rank is assigned in the hierarchical structure is the processor P communicably connected to the processor P32, and is the highest in the hierarchical structure. Since the processor P to which the rank lower than the lower rank is assigned is not connected to the processor P32, empty data is included as the write execution data corresponding to the processor P. The empty data included in the write execution data corresponding to the processor P32 is data indicating that the processor P to which the lower rank than the lowest rank is assigned in the hierarchical structure is not connected to the processor P32 in the present embodiment. Any data can be used as long as it is available, for example, null data or the like.

Here, FIG. 2 is a diagram showing an example of a data structure of write execution data corresponding to a certain first processor. In the following, for convenience of explanation, the first processor will be referred to as a target first processor. Further, each of one or more second processors communicably connected to the target first processor will be referred to as a target second processor. In the example shown in FIG. 2, the write execution data corresponding to the target first processor includes two types of data, that is, the header of the write execution data and the body of the write execution data. Further, in the example, in the header, data indicating the size of the header, data indicating the size of the body, data indicating the number of components contained in the body, and n data DX1 to DXn of different types from each other. It contains (n + 3) types of data. n is an integer greater than or equal to 0. That is, the header may not include the n pieces of data. Further, each of the data DX1 to the data DXn may be any kind of data. The number of components is the number of components contained in the body. Further, the component included in the body is data including firmware corresponding to the target first processor or write execution data output from the target first processor to each of one or more target second processors. is there.

Further, in the example shown in FIG. 2, the body of the write execution data corresponding to the target first processor includes m components of components C1 to Cm. m is an integer of 1 or more. The component C1 is an example of data including firmware corresponding to the target first processor. The component C1 contains two types of data, a header of the component C1 and a body of the component C1. The header includes data indicating the size of the header, data indicating the size of the body, and output destination data indicating the output destination of the body. The header may be configured to include other data. In the example shown in FIG. 2, the component C1 is the data including the firmware corresponding to the target first processor as described above. Therefore, the output destination data indicates the target first processor as the output destination. When the output destination data indicates the target first processor, the body contains various data necessary for writing the firmware corresponding to the target first processor to the target first processor. In addition to the various data, the body may include other data.

On the other hand, the component Cm shown in FIG. 2 is an example of data including write execution data corresponding to a certain target second processor among one or more target second processors. The component Cm contains two types of data, a header of the component Cm and a body of the component Cm. The header includes data indicating the size of the header, data indicating the size of the body, and output destination data indicating the output destination of the body. The header may be configured to include other data. In the example shown in FIG. 2, the component Cm is data including write execution data corresponding to the target second processor, as described above. Therefore, the output destination data indicates the target second processor as the output destination. When the output destination data indicates the target second processor, the body includes write execution data corresponding to the target second processor. The data structure of the write execution data is the same as the data structure of the write execution data corresponding to the target first processor shown in FIG.

As described above, the write execution data corresponding to a certain first processor has a recursive data structure. That is, the write execution data includes other write execution data having the same data structure as the data structure of the write execution data. As a result, the creator who creates the write execution data corresponding to each of the nine processors has a common data structure, so that it takes time and effort to create the write execution data corresponding to each of the nine processors. You can save time. In other words, the creator can efficiently create write execution data corresponding to each of the nine processors P. Further, since the write execution data corresponding to each of the nine processors P have the same data structure as each other, even if an error is included in a part of these write execution data, 9 Compared with the case where the write execution data corresponding to each of the processors P has different data structures, the labor and time required for debugging can be reduced.

Of the components included in the write execution data corresponding to the target first processor, the internal data structure of the body of all components other than the component including the output destination data indicating the target first processor is the target first processor. It is hidden from the processing performed by. Therefore, the write execution data corresponding to the target first processor includes one or more target second write execution data having a data structure different from the data structure of the write execution data corresponding to the target first processor. The configuration may be included as write execution data corresponding to each of a part of the processors. The write execution data may be, for example, binary data or the like, or may be data having another data structure. As a result, even if a part of the nine processors P included in the information processing device 11 is a processor having a different standard from the other processors P, the user can use the information processing device 12 as a target. By outputting the write execution data corresponding to the target first processor to one processor, the firmware can be efficiently written to each of the nine processors P.

For example, if the processor P31 and the processor P32 are processors having different standards from the processor P01, the processor P11, the processor P12, the processor P13, the processor P21, the processor P22, and the processor P23, the user can write according to the processor P23. For example, by including the write execution data including the binary data in the body of the component with respect to the built-in execution data, the write execution data corresponding to the target first processor to the target first processor from the information processing device 12 Can be output and the firmware can be efficiently written to each of the nine processors P.

Here, each of the plurality of components included in the body of a certain write execution data also has the same data structure as each other. Therefore, in the following, with reference to FIG. 3, the data structure of the component included in the body of a certain write execution data will be described by taking the data structure of the component C1 shown in FIG. 2 as an example. FIG. 3 is a diagram showing an example of the data structure of the component C1 shown in FIG.

In the following, for convenience of explanation, the body of the component C1 shown in FIG. 2 will be referred to as component data. The component data includes two types of data, a header of the component data and a body of the component data. The header includes three types of data: data indicating the size of the header, data indicating the size of the body, and data indicating the number of write blocks included in the body. The number of write blocks is data indicating the number of write blocks included in the body. Further, each of the plurality of write blocks included in the body is one of the plurality of data in which the firmware to be written to the target first processor is divided. In the example shown in FIG. 3, the firmware is divided into k write blocks W. k may be any integer as long as it is an integer of 1 or more. The write block W1 shown in FIG. 3 indicates the first write block W included in the body. Further, the write block Wk shown in FIG. 3 indicates the kth write block W included in the body.

In addition, the body of the component Cm contains write execution data corresponding to the target second processor indicated by the output destination data of the component Cm instead of the plurality of write blocks. As described above, the data structure of the write execution data has the same data structure as the data structure of the write execution data shown in FIG. 2, and therefore the description by illustration will be omitted.

Here, each of the plurality of write blocks included in the component data body shown in FIG. 3 also has the same data structure as each other. Therefore, in the following, with reference to FIG. 4, the data structure of the write block included in a certain component data will be described by taking the data structure of the write block W1 shown in FIG. 3 as an example. FIG. 4 is a diagram showing an example of the data structure of the write block W1 shown in FIG.

The write block W1 shown in FIG. 3 contains two types of data, a header of the write block W1 and a body of the write block W1. The header includes data indicating the size of the header, data indicating the size of the body, and (s + 2) types of data of s data of different types of data DY1 to DYs. s is an integer greater than or equal to 0. That is, the header may not include the s pieces of data. Further, each of the data DY1 to the data DYs may be any kind of data. In addition, the body contains one of a plurality of data in which the firmware to be written to the target first processor is divided. In addition, in FIG. 4, the details of the data contained in the body are omitted.

Next, with reference to FIG. 5, when the above-mentioned target first processor acquires the write execution data having the above data structure, the process performed by the target first processor will be described. FIG. 5 is a diagram showing an example of the flow of processing performed by the target first processor when the write execution data corresponding to the target first processor is acquired. In the present embodiment, the processor P that can be the target first processor is each of the processor P01, the processor P11, the processor P12, the processor P13, the processor P21, the processor P22, the processor P23, and the processor P32. Further, in the following, for convenience of explanation, the write execution data will be referred to as a target write execution data.

The target first processor refers to the header of the acquired write execution data and specifies the number of components included in the write execution data (step S110).

Next, the target first processor selects the components included in the target write execution data one by one as the target component based on the number of components specified in step S110, and steps S130 to step S130 for each selected target component. The process of S160 is repeatedly executed (step S120).

The target first processor determines whether or not the output destination indicated by the output destination data included in the header of the target component selected in step S120 is the target first processor (step S130).

When the target first processor determines that the output destination indicated by the output destination data included in the header of the target component is the target first processor (step S130-YES), the target first processor transitions to step S120 and is not selected in step S120. Select the next component from the components as the target component. If the target first processor does not have an unselected component in step S120, the target first processor transitions to step S170.

On the other hand, when it is determined that the output destination indicated by the output destination data included in the header of the target component is not the target first processor (step S130-NO), the target first processor is the target second processor. Whether or not it is determined (step S140). In other words, in step S140, the target first processor is a processor P in which the output destination indicated by the output destination data included in the header of the target component is communicably connected to the target first processor and has a hierarchical structure. In, it is determined whether or not the processor P is assigned a rank one lower than that of the target first processor.

When the target first processor determines that the output destination indicated by the output destination data included in the header of the target component is not the target second processor (step S140-NO), the target first processor outputs an error to the information processing device 12 (step S140-NO). Step S160), the process is terminated.

When the target first processor determines that the output destination indicated by the output destination data included in the header of the target component is the target second processor (step S140-YES), the target first processor refers to the target second processor of the output destination. The body of the target component is output (step S150). After that, the target first processor transitions to step S120, and selects the next component as the target component from the unselected components in step S120.

After the iterative processing of steps S120 to S160 is performed, the target first processor refers to the component included in the target write execution data, and there is a component including the output destination data indicating the target second processor as the output destination. It is determined whether or not to do so (step S165).

When the target first processor determines that there is a component including output destination data indicating the target second processor as the output destination (step S165-YES), whether or not the writing of the firmware to all the target second processors is successful. (Step S170). Here, the target first processor obtains information indicating that the firmware has been successfully written from each of the one or more target second processors in step S170, so that the firmware to all the target second processors can be obtained. Judges that the writing was successful. On the other hand, if the target first processor has not acquired information indicating that the firmware has been successfully written from at least one processor P of the one or more target second processors in step S170, all of them. It is determined that the firmware has not been successfully written to the target second processor.

When the target first processor determines that the writing of the firmware to all the target second processors has not been successful (step S170-NO), the target first processor determines whether or not the writing of the target second firmware has failed (step). S200). Here, when the target first processor acquires data indicating that the writing of the firmware has failed from at least one of the one or more target second firmwares in step S170, the target second firmware It is determined that the writing of the firmware has failed. In this case, if the target first processor has not acquired data indicating that the firmware writing has failed from all of one or more target second firmwares in step S170, the target second firmware has failed to write. Judge that it is not done. In step S170, the target first processor also handles a timeout error error even if no response is returned from at least one of the one or more target second firmwares even after a predetermined time has passed. As a result, it may be determined that the writing of the target second firmware has failed.

When the target first processor determines that the writing of the target second firmware has failed (step S200-YES), the target first processor outputs an error to the information processing device 12 (step S210), and ends the process.

On the other hand, when it is determined that the target first processor has not failed to write the target second firmware (step S200-NO), the process proceeds to step S170, and the writing of the firmware to all the target second processors is successful. Determine again whether or not.

On the other hand, in step S170, when the target first processor determines that the firmware has been successfully written to all the target second processors (step S170-YES), it determines whether or not to write the firmware to the target first processor. (Step S180). Here, in step S180, the target first processor includes empty data in the body of the component including the output destination data indicating the target first processor in the header of the component among the components included in the target write execution data. If so, it is determined that the firmware is not written to the target first processor. On the other hand, in step S180, the target first processor determines that the firmware is written to the target first processor when the body does not contain empty data.

When the target first processor determines that the firmware is written to the target first processor (step S180-YES), among the components included in the target write execution data, the output destination data indicating the target first processor in the component header. Based on the body of the component including the above, the firmware corresponding to the target first processor is written to the target first processor (step S190), and the process ends.

On the other hand, when the target first processor determines that the firmware is not written to the target first processor (step S180-NO), the process ends.

On the other hand, in step S165, when the target first processor determines that the component including the output destination data indicating the target second processor does not exist as the output destination (step S165-NO), the target first processor transitions to step S180 and the target first processor. Determines whether to write firmware to the processor.

Through the above processing, the information processing device 11 can write the firmware to the processor P desired by the user. For example, when the development of the processor P01 is incomplete, the user outputs the write execution data corresponding to the processor P11 from the information processing device 12 to the processor P11 without outputting the data to the processor P01. , Processor P11, Processor P21, and Processor P22 can be written with firmware. Further, for example, in the information processing device 11, when the user does not want to write the firmware to the processor P23, the user responds to the processor P23 among the write execution data included in the write execution data corresponding to the processor P01. By making the body of the component of the write execution data empty, each of the processor P01, the processor P11, the processor P12, the processor P13, the processor P21, the processor P22, the processor P31, and the processor P32 without writing the firmware to the processor P23. You can write firmware to. Therefore, for example, the information processing device 11 can efficiently write the firmware to the processor P for which the development has been completed, while developing each of the nine processors P included in the information processing device 11. .. In other words, the information processing device 11 can flexibly select the processor P for updating the firmware according to the convenience of the user.

Here, FIG. 6 is a diagram showing an example of a flow in which each processor P acquires write execution data when the write execution data corresponding to the processor P01 is output from the information processing unit 12 to the processor P01. Is.

As shown in FIG. 6, the processor P01 acquires the write execution data D01 from the information processing device 12. The write execution data D01 is the write execution data corresponding to the processor P01. In this case, the processor P01 operates as the first processor. That is, in this case, the processor P01 outputs the write execution data D11 included in the write execution data D01 to the processor P11, which is one of the second processors with respect to the processor P01, based on the write execution data D01. To do. The write execution data D11 is write execution data corresponding to the processor P11. Further, in this case, the processor P01 outputs the write execution data D12 included in the write execution data D01 to the processor P12, which is one of the second processors with respect to the processor P01, based on the write execution data D01. To do. The write execution data D12 is write execution data corresponding to the processor P12. Further, in this case, the processor P01 outputs the write execution data D13 included in the write execution data D01 to the processor P13, which is one of the second processors with respect to the processor P01, based on the write execution data D01. To do. The write execution data D13 is the write execution data corresponding to the processor P13.

Next, the processor P11 operates as the first processor when the write execution data D11 is acquired from the processor P01. Then, in this case, the processor P11 outputs the write execution data D21 included in the write execution data D11 to the processor P21 which is one of the second processors with respect to the processor P11 based on the write execution data D11. To do. Further, in this case, the processor P11 outputs the write execution data D22 included in the write execution data D11 to the processor P22, which is one of the second processors with respect to the processor P11, based on the write execution data D11. To do.

Further, the processor P13 operates as the first processor when the write execution data D13 is acquired from the processor P01. Then, in this case, the processor P13 outputs the write execution data D23 included in the write execution data D13 to the processor P23, which is the second processor for the processor P13, based on the write execution data D13.

Further, the processor P23 operates as the first processor when the write execution data D23 is acquired from the processor P13. Then, in this case, the processor P23 outputs the write execution data D31 included in the write execution data D23 to the processor P31 which is one of the second processors with respect to the processor P23 based on the write execution data D23. To do. Further, in this case, the processor P23 outputs the write execution data D32 included in the write execution data D23 to the processor P32, which is one of the second processors with respect to the processor P23, based on the write execution data D23. To do.

Here, the processor P01 does not write the firmware to the processor P01 when the body of the component including the output destination data indicating the processor P01 among the components included in the write execution data D01 is empty data.

Further, the processor P11 does not write the firmware to the processor P11 when the body of the component including the output destination data indicating the processor P11 among the components included in the write execution data D11 is empty data.

Further, the processor P12 does not write the firmware to the processor P12 when the body of the component including the output destination data indicating the processor P12 among the components included in the write execution data D12 is empty data.

Further, the processor P13 does not write the firmware to the processor P13 when the body of the component including the output destination data indicating the processor P13 among the components included in the write execution data D13 is empty data.

Further, the processor P21 does not write the firmware to the processor P21 when the body of the component including the output destination data indicating the processor P21 among the components included in the write execution data D21 is empty data.

Further, the processor P22 does not write the firmware to the processor P22 when the body of the component including the output destination data indicating the processor P22 among the components included in the write execution data D22 is empty data.

Further, the processor P23 does not write the firmware to the processor P23 when the body of the component including the output destination data indicating the processor P23 among the components included in the write execution data D23 is empty data.

Further, the processor P31 does not write the firmware to the processor P31 when the body of the component including the output destination data indicating the processor P31 among the components included in the write execution data D31 is empty data.

Further, the processor P32 does not write the firmware to the processor P32 when the body of the component including the output destination data indicating the processor P32 among the components included in the write execution data D32 is empty data.

As described above, in the information processing device 11, the write execution data having a recursive data structure and whether or not the body of the component included in the write execution data is made empty, among all the processors P. Efficient writing of firmware to the processor P desired by the user can be performed. As a result, for example, the information processing device 11 can reduce the labor and time required for updating each processor P. Further, for example, in the information processing device 11, it is not necessary to create write execution data for writing the firmware used only in the development of each processor P to the processor P, and the man-hours required for creating the write execution data can be reduced. it can. Further, in the information processing device 11, it is not necessary to independently create the write execution data to each processor P.

The data structure of the write execution data described above can be easily created by a script program. As a result, the information processing apparatus 11 can reduce the burden required for the user to create the write execution data.

As described above, the information processing apparatus according to the embodiment has a first processor to which the first rank is assigned in a predetermined hierarchical structure, and a first memory for storing data read by the first processor. A board, a second processor to which a second rank one rank lower than the first rank in the hierarchical structure is assigned, and a second board having a second memory for storing data read by the second processor. When the first processor acquires the first write execution data including the second write execution data that causes the second processor to write the second firmware to the second memory, the first processor uses the first write execution data as the first write execution data. The included second write execution data is output to the second processor, and the first firmware is transferred to the first memory based on the first write execution data that causes the first processor to write the first firmware to the first memory. The data structure of the write and second write execution data is the same data structure as the data structure of the first write execution data. As a result, the information processing device can efficiently write the firmware to the plurality of processors.

Further, in the information processing apparatus, the first memory further stores the first output destination data indicating one or more output destinations capable of outputting data from the first processor, and the first write execution data contains the first write execution data. The second output destination data indicating the second processor is included as the output destination of the second write execution data, and when the first processor acquires the first write execution data and the first output destination data is When one or more output destinations shown include the second processor indicated by the second output destination data, the second write execution data included in the first write execution data is output to the second processor. It may be used.

Further, in the information processing device, when the first processor acquires the first write execution data, and the second processor indicated by the second output destination data is assigned to one or more output destinations indicated by the first output destination data. A configuration may be used that outputs an error if it is not included.

Further, in the information processing unit, when the second firmware included in the second write execution data is empty data, the second processor does not write the second firmware to the second memory and goes to the second memory. A configuration may be used in which data indicating that the writing of the second firmware of the above is successful is output to the first processor.

Further, in the information processing device, the first processor outputs the second write execution data included in the first write execution data to the second processor, and then succeeds in writing the second firmware to the second memory. When the data indicating the above is acquired from the second processor, a configuration may be used in which the first data is written to the first memory based on the first write execution data.

Further, in the information processing unit, after the first processor outputs the second write execution data included in the first write execution data to the second processor, the writing of the second firmware to the second memory fails. When the data indicating the above is acquired from the second processor, a configuration may be used in which the first firmware is not written to the first memory.

Further, in the information processing apparatus, a third processor having a third processor to which a third rank, which is one rank lower than the second rank in the hierarchical structure, is assigned, and a third memory for storing data read by the third processor. The second write execution data includes a third write execution data that causes the third processor to write the third firmware to the third memory, and the data structure of the third write execution data is as follows. It has the same data structure as the data structure of the second write execution data, and when the second processor acquires the second write execution data, the second processor transfers the third write execution data included in the second write execution data to the third. A configuration may be used in which the data is output to the processor and the second firmware is written to the second memory based on the second write execution data.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and changes, substitutions, deletions, etc. are made as long as the gist of the present invention is not deviated. May be done.

Further, a program for realizing the function of an arbitrary component in the apparatus described above may be recorded on a computer-readable recording medium, and the program may be read into a computer system and executed. Here, the device is, for example, an information processing device 11, an information processing device 12, a processor P, or the like. The term "computer system" as used herein includes hardware such as an OS (Operating System) and peripheral devices. Further, the "computer-readable recording medium" refers to a portable medium such as a flexible disk, a magneto-optical disk, a ROM, a CD (Compact Disk) -ROM, or a storage device such as a hard disk built in a computer system. .. Furthermore, a "computer-readable recording medium" is a constant, such as the volatile memory inside a computer system that serves as a server or client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. It shall include those holding a time program.

Further, the above program may be transmitted from a computer system in which this program is stored in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the "transmission medium" for transmitting a program refers to a medium having a function of transmitting information, such as a network such as the Internet or a communication line such as a telephone line.
Further, the above program may be for realizing a part of the above-mentioned functions. Further, the above program may be a so-called difference file or a difference program that can realize the above-mentioned functions in combination with a program already recorded in the computer system.

1 ... Information processing system, 11, 12 ... Information processing device, D01, D11, D12, D13, D21, D22, D23, D31, D32 ... Write execution data, L, L01, L11, L12, L13, L21, L22 , L23, L31, L32 ... Substrate, M, M01, M11, M12, M13, M21, M22, M23, M31, M32 ... Memory, P, P01, P11, P12, P13, P21, P22, P23, P31, P32 …processor

Claims (8)

A first substrate having a first processor to which a first rank is assigned in a determined hierarchical structure and a first memory for storing data read by the first processor, and a first substrate.
A second substrate having a second processor to which a second rank one rank lower than the first rank is assigned in the hierarchical structure, and a second memory for storing data read by the second processor, and a second substrate.
With
When the first processor acquires the first write execution data including the second write execution data that causes the second processor to write the second firmware to the second memory, the first write execution is executed. The second write execution data included in the data is output to the second processor, and the first processor is made to write the first firmware to the first memory based on the first write execution data. Write the first firmware to the first memory,
The data structure of the second write execution data is the same data structure as the data structure of the first write execution data.
Information processing device. In the first memory, first output destination data indicating one or more output destinations capable of outputting data from the first processor is further stored.
The first write execution data includes second output destination data indicating the second processor as an output destination of the second write execution data.
When the first write execution data is acquired, the first processor includes the second processor indicated by the second output destination data in one or more output destinations indicated by the first output destination data. If so, the second write execution data included in the first write execution data is output to the second processor.
The information processing device according to claim 1. When the first write execution data is acquired, the first processor includes the second processor indicated by the second output destination data in one or more output destinations indicated by the first output destination data. If not, output an error,
The information processing device according to claim 2. When the second firmware included in the second write execution data is empty data, the second processor does not write the second firmware to the second memory and writes the second firmware to the second memory. Data indicating that the writing of the second firmware was successful is output to the first processor.
The information processing device according to any one of claims 1 to 3. After the first processor outputs the second write execution data included in the first write execution data to the second processor, the writing of the second firmware to the second memory is successful. When the indicated data is acquired from the second processor, the first firmware is written to the first memory based on the first write execution data.
The information processing device according to any one of claims 1 to 4. The first processor outputs the second write execution data included in the first write execution data to the second processor, and then fails to write the second firmware to the second memory. When the indicated data is acquired from the second processor, the first firmware is not written to the first memory.
The information processing device according to any one of claims 1 to 5. Further provided is a third substrate having a third processor to which a third rank, which is one rank lower than the second rank in the hierarchical structure, is assigned, and a third memory for storing data read by the third processor. ,
The second write execution data includes the third write execution data that causes the third processor to write the third firmware to the third memory.
The data structure of the third write execution data is the same data structure as the data structure of the second write execution data.
When the second processor acquires the second write execution data, the second processor outputs the third write execution data included in the second write execution data to the third processor, and executes the second write. Write the second firmware to the second memory based on the data.
The information processing device according to any one of claims 1 to 6. A first board having a first processor to which a first rank is assigned in a determined hierarchical structure and a first memory for storing data read by the first processor, and a rank higher than the first rank in the hierarchical structure. It is an information processing method of an information processing apparatus including a second processor to which a second rank one lower is assigned and a second board having a second memory for storing data read by the second processor.
When the first processor acquires the first write execution data including the second write execution data that causes the second processor to write the second firmware to the second memory, the first write execution data. The first write execution data in which the first processor outputs the second write execution data included in the first memory to the second processor and causes the first processor to write the first firmware to the first memory. The first processor writes the first firmware to the first memory based on
The data structure of the second write execution data is the same data structure as the data structure of the first write execution data.
Information processing method.

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