JP7327076B2 - Information processing device, information processing method, and program - Google Patents

Description

The present invention relates to an information processing device, an information processing method, and a program.

2. Description of the Related Art In an information processing apparatus that executes a plurality of processes, there is known a technique for facilitating fault analysis and the like by acquiring a function call history (hereinafter referred to as history information) by a program that executes each process.

For example, when any function included in an application program is executed, there is a known technique of calling a common process for acquiring history information and requesting an operating system (OS) to store the history information ( For example, see Patent Document 1).

In the conventional technology disclosed in Patent Document 1, a system call is issued each time a program that executes a predetermined process calls a function, which has the problem of greatly affecting the processing performance of the information processing apparatus.

An embodiment of the present invention has been made in view of the above problems, and is an information processing apparatus that executes predetermined processing, while suppressing the influence of the predetermined processing on the performance of the predetermined processing. to be able to obtain history information for programs that run

In order to solve the above problems, an information processing apparatus according to one embodiment of the present invention is an information processing apparatus including a processor having a plurality of CPU cores, executing predetermined processing, and one or more processing execution units that store history information in a first storage unit that temporarily stores the history information; and one or more processing execution units that store the history information stored in the first storage unit a trace execution unit for executing trace processing stored in a second storage unit for accumulating the history information of the process execution unit; causing one of the plurality of CPU cores to execute the trace processing; and an execution control unit that causes one or more CPU cores different from the one CPU core to execute the predetermined process.

According to an information processing apparatus according to an embodiment of the present invention, in an information processing apparatus that executes a predetermined process, history information of a program that executes the predetermined process is suppressed while suppressing the influence of the predetermined process on the processing performance. can be obtained.

1 is a diagram for explaining an overview of an information processing device according to an embodiment; FIG. 1 illustrates an example hardware configuration of an image forming apparatus according to an embodiment; FIG. 1 is a diagram illustrating an example of a software configuration of an image forming apparatus according to one embodiment; FIG. 1 illustrates an example functional configuration of an image forming apparatus according to an embodiment; FIG. FIG. 4 is a diagram for explaining a shared memory according to one embodiment; FIG. FIG. 7 is a sequence diagram illustrating an example of processing at startup according to one embodiment; 6 is a flowchart illustrating an example of history information write processing according to an embodiment; FIG. 7 is a sequence diagram showing an example of processing when calling a function according to one embodiment; FIG. 5 is a sequence diagram showing an example of processing by a processing execution unit according to one embodiment; FIG. 4 is a diagram for explaining embedding of processing by a compiler according to one embodiment; 3 is a diagram illustrating another example of the functional configuration of the image forming apparatus according to one embodiment; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Overview of Information Processing Device>
FIG. 1 is a diagram for explaining an overview of an information processing apparatus according to an embodiment. The information processing apparatus 100 is a computer that includes a processor 110 that includes a plurality of CPU (Central Processing Unit) cores 111a, 111b, 111c, . . . and executes one or more programs 121a, 121b, . In the following description, "CPU core 111" is used when indicating an arbitrary CPU core among the plurality of CPU cores 111a, 111b, 111c, . Also, when indicating an arbitrary program among the one or more programs 121a, 121b, . . . , "program 121" is used.

The processor 110 is a multi-core processor including a plurality of CPU cores 111, which are arithmetic devices that function independently of each other, and is also called a CPU, MPU (Micro Processing Unit), or the like, for example. Note that the number of CPU cores 111 may be two or more. Also, the processor 110 may be composed of a plurality of processors having one or more CPU cores 111 .

The memory 120 is a main storage device (primary storage device) used as a work area or the like of the processor 110, and is realized by, for example, a RAM (Random Access Memory) or the like. The storage 130 is, for example, a nonvolatile large-capacity storage device (secondary storage device) that stores an OS (Operating System), application programs, various data, and the like. (Solid State Drive) or other storage device.

For example, the information processing apparatus 100 is an embedded system using a general-purpose OS or a real-time OS, and the processor 110 executes one or more programs 121a, 121b, . In such an information processing apparatus 100, in general, when a failure occurs, failure analysis tends to be difficult, and information for analysis that remains when a failure occurs is only fragmentary log information. often. Therefore, when a failure occurs in such an information processing apparatus 100, the failure analysis takes a long time, which may lead to an increase in analysis costs and a decrease in customer satisfaction, for example.

In order to reduce such risks, an effective debug function is desired, and one of them is known as a function trace function for acquiring the function call history of each program 121 . However, for example, in the conventional technique disclosed in Patent Document 1, a system call is issued each time the program 121 calls a function.

Therefore, in the information processing apparatus 100 according to the present embodiment, a predetermined specific CPU core 111 (for example, the CPU core 111a) executes the function tracer 123, which is a program that implements the function tracing function. Further, the information processing apparatus 100 executes one or more programs 121 by, for example, CPU cores 111b, 111c, . . . different from the CPU core 111a.

Each program 121 also executes a history information write process, which is a process of writing the history of the called function to the shared memory 122, each time the function is called. This history information writing process performs only the process of writing the history information to the shared memory 122 on the memory 120 such as RAM, and does not write the history information to the secondary storage device such as the storage 130 or the like. This is because the process of storing the history information in the secondary storage generally takes time, and the processing performance of each program 121 is significantly degraded.

Further, the function tracer 123 executes trace processing for storing the history information written in the shared memory 122 by each program 121 in the storage 130 that accumulates the history information 131 of each program 121 . As a result, the function tracer 123 can acquire history information of the one or more programs 121 while reducing the influence of processing executed by the one or more programs 121 on the processing performance.

As described above, according to the present embodiment, in the information processing apparatus 100 that executes a predetermined process, the history information of each program that executes the predetermined process is acquired while reducing the influence of the predetermined process on the processing performance. become able to.

<Hardware configuration>
Here, as an example, the information processing apparatus 100 is assumed to be an image forming apparatus such as an MFP (Multifunction Peripheral) having a scan function, a copy function, a print function, a facsimile function, etc. in one housing. to explain.

However, the information processing apparatus 100 is not limited to this, and is not limited to an image forming apparatus as long as it is an apparatus having a plurality of CPU cores 111 . For example, the information processing apparatus 100 may be a PJ (Projector), an IWB (Interactive White Board), a digital signage, or an output device such as a HUD (Head Up Display) device. It may be a device. Further, the information processing device 100 may be, for example, an industrial machine, an imaging device, a sound collector, a medical device, a network appliance, a connected car, or the like. Further, the information processing apparatus 100 is, for example, an information terminal such as a notebook PC (Personal Computer), a mobile phone, a smartphone, a tablet terminal, a game machine, a PDA (Personal Digital Assistant), a digital camera, a wearable PC, or a desktop PC. can be

FIG. 2 is a diagram illustrating an example of a hardware configuration of an image forming apparatus according to one embodiment; For example, as shown in FIG. 2, the image forming apparatus 200 includes a controller 210, a short-range communication circuit 220, an engine control section 230, an operation panel 240, a network I/F 250, and a fax control unit (hereinafter referred to as FCU). 260 and so on.

Among these, the controller 210 includes a CPU 201, a system memory (MEM-P) 202, a north bridge (NB) 203, a south bridge (SB) 204, an ASIC (Application Specific Integrated Circuit) 205, and a local memory. (MEM-C) 206 , HDD controller 207 , HD 208 , etc., and NB 203 and ASIC 205 are connected by an AGP (Accelerated Graphics Port) bus 211 .

Among them, the CPU 201 is a control unit that performs overall control of the image forming apparatus 200 . Note that the CPU 201 is an example of the processor 110 in FIG. 1 and has a plurality of CPU cores 111a, 111b, 111c, . The NB 203 is a bridge for connecting the CPU 201, the MEM-P 202, the SB 204, and the AGP bus 211, and is a memory controller that controls reading and writing with respect to the MEM-P 202, a PCI (Peripheral Component Interconnect) master, and an AGP target. have

The MEM-P 202 is composed of a ROM 202a, which is a memory for storing programs and data for realizing each function of the controller 210, and a RAM 202b, which is used as a drawing memory for expanding the programs and data and for memory printing. Note that the MEM-P 202 is an example of the memory 120 in FIG. The program stored in the RAM 202b may be configured to be recorded on a computer-readable recording medium and provided.

The SB 204 is a bridge for connecting the NB 203 with PCI devices and peripheral devices. The ASIC 205 is an IC (Integrated Circuit) for image processing that has hardware elements for image processing, and serves as a bridge that connects the AGP bus 211, PCI bus 212, HDD controller 207, and MEM-C 206, respectively. . This ASIC 205 includes a PCI target and AGP master, an arbiter (ARB) that forms the core of the ASIC 205, a memory controller that controls the MEM-C 206, and a plurality of DMACs (Direct Memory Access Controllers) that rotate image data using hardware logic. , and a PCI unit that transfers data between the scanner unit 231 and the printer unit 232 via the PCI bus 212 . Note that the ASIC 205 may be connected to a USB (Universal Serial Bus) interface or an IEEE 1394 (Institute of Electrical and Electronics Engineers 1394) interface.

MEM-C 206 is a local memory used as an image buffer for copying and an encoding buffer. The HD 208 is an example of the storage 130 in FIG. 1, and is a large-capacity storage device that stores various programs, data, image data, font data used for printing, various data such as forms, history information 131, and the like. . The HDD controller 207 controls reading or writing of data to the HD 208 under the control of the CPU 201 . The AGP bus 211 is a bus interface for graphics accelerator cards proposed for speeding up graphics processing, and can speed up the graphics accelerator card by directly accessing the MEM-P 202 with high throughput. .

The short-range communication circuit 220 is a high-frequency circuit, a signal processing circuit, and a communication control circuit that perform communication according to near-field wireless communication standards such as NFC (Near Field Communication) and Bluetooth (registered trademark) using an antenna 220a. etc. The engine control unit 230 is composed of, for example, a scanner unit 231, a printer unit 232, and the like. The scanner unit 231 is a reading device that reads an original or the like. The printer unit 232 is a printing device that prints print data on a print medium. The scanner unit 231 or printer unit 232 includes, for example, image processing such as error diffusion and gamma conversion.

The operation panel 240 includes a panel display unit 240a such as a touch panel for displaying current setting values, a selection screen, and the like, and for receiving input from an operator, and a numeric keypad for receiving setting values of image forming conditions such as density setting conditions. and an operation button 240b such as a start key for accepting a copy start instruction. The controller 210 controls the entire image forming apparatus 200, such as drawing, communication, input from the operation panel 240, and the like.

Note that the image forming apparatus 200 can switch and select the document box function, the copy function, the printer function, and the facsimile function in sequence using the application switching key of the operation panel 240 . The document box mode is set when the document box function is selected, the copy mode is set when the copy function is selected, the printer mode is set when the printer function is selected, and the facsimile mode is set when the facsimile mode is selected.

Network I/F 250 is an interface for data communication using a communication network. The FCU 260 performs transmission and reception of fax data according to the protocol of fax communication. The short-range communication circuit 220, the network I/F 250, the FCU 260, and the like are electrically connected to the ASIC 205 via the PCI bus 212, for example.

<Software configuration>
FIG. 3 is a diagram illustrating an example of a software configuration of an image forming apparatus according to one embodiment; The image forming apparatus 200 includes, for example, a software group 301, an engine 302, hardware resources 303, and the like. Note that the engine 302 corresponds to, for example, the engine control unit 230, scanner unit 231, and printer unit 232 in FIG. Also, the hardware resource 303 corresponds to, for example, the CPU 201, the operation panel 240, the network I/F 250, the MEM-P 202, the HDD controller 207, and the HD 208 shown in FIG.

A software group 301 includes an application layer 304 running on an OS 341 and a platform 305 . The application layer 304 includes application programs (hereinafter referred to as applications) such as a print application 311, a copy application 312, a scanner application 313, and so on. Note that the print application 311, the copy application 312, the scanner application 313, . . . are examples of the one or more programs 121a, 121b, .

The print application 311 is an application for executing print processing. The copy application 312 is an application for executing copy processing. A scanner application 313 is an application for executing a scanning function.

The platform 305 includes a service layer 306 that interprets processing requests from the application layer 304 and generates acquisition requests for hardware resources 303, and an SRM that manages the hardware resources 303 and arbitrates acquisition requests from the service layer 306. System Resource Manager) 331, and IMH (Image Memory Handler) 332 that allocates and manages memory.

The service layer 306 includes, for example, ECS (Engine Control Service) 321, MCS (Memory Control Service) 322, OCS (Operation Control Service) 323, NCS (Network Control Service) 324, LCS (Log Control Service) 325, etc. Contains service modules.

The platform 305 also has an API (Application Programming Interface) 351 that can receive processing requests from the application layer 304 using a predefined function.

The OS 341 executes each software of the application layer 304 and the platform 305 in parallel as processes. Here, the OS 341 is assumed to be Linux (registered trademark), but the OS 341 is not limited to Linux, and may be another OS. The init 342 is a program that is executed first when the OS 341 is activated, and activates the application layer 304, the platform 505, and the like.

The ECS 321 process controls the engine 302, hardware resources 303, and the like. The MCS 322 process controls memory, such as memory acquisition, freeing, and use of the HD 208 . The process of the OCS 323 controls the operation panel 240 and the like, which serve as information transmission means between the user and the main body control. The NCS 324 process provides commonly available network services to applications that send and receive data over a communication network. The LCS 325 process manages and retains log information such as history information 131, for example.

The SRM 331 process controls the system and manages the hardware resources 303 . For example, the process of the SRM 331 arbitrates according to acquisition requests from upper layers that use the printer unit 232, scanner unit 231, etc., hardware resources 303, etc. included in the engine 302, and controls execution. The SRM 331 issues a processing request to the engine 302 using an engine I/F 352 that enables transmission of a processing request to the engine 302 or the like using a predefined function.

<Functional configuration>
FIG. 4 is a diagram showing an example of the functional configuration of the image forming apparatus 200 according to one embodiment. An image forming apparatus (an example of an information processing apparatus) 200 includes, for example, one or more processing execution units 401a, 401b, . It has a control unit 405, an exception handler 406, and the like. In the following description, "processing execution unit 401" is used when indicating an arbitrary processing execution unit among the one or more processing execution units 401a, 401b, . . .

The processing execution unit 401 includes, for example, programs executed by the CPU cores 111b, 111c, . realized by The process execution unit 401 executes a predetermined process and stores history information associated with the execution of the process in the first storage unit 402 that temporarily stores history information. For example, each time a function is called, the process execution unit 401 writes history information, which is the history of the called function, to the shared memory 122 or the like included in the first storage unit 402 .

Note that the program that implements the processing execution unit 401 is not limited to the application of the application layer 304, and may be a service of the platform 305, the SRM 331, the IMH 332, or the like.

The first storage unit (shared memory) 402 is realized by, for example, programs executed by the CPU 201 (for example, the OS 341, etc.), the RAM 202b, and the like. The first storage unit 402 includes, for example, a shared memory 122 that temporarily stores history information that is a history of functions called by the process execution unit 401 .

FIG. 5 is a diagram for explaining a shared memory according to one embodiment. The first storage unit 402 includes, for example, a shared memory 122 as shown in FIGS. 5(A) to 5(C). The shared memory 122 is a RAM area that can be read from and written to (shared) by a plurality of running programs. Used.

The shared memory 122 is composed of a plurality of memory pages (storage areas) 501 as shown in FIG. 5A, for example. In the initial state of the shared memory 122, for example, as shown in FIG. ) has the access attribute set to "read only".

This access attribute can be set for each memory page 501 by the MMU installed in the CPU 201 . Note that a typical size of memory page 501 is 4 kbytes, but other sizes are possible.

In the state of FIG. 5A , the process execution unit 401 can write history information to page 1 . When the processing execution unit 401 uses up the free space of page 1 by writing the history information a plurality of times, the processing execution unit 401 attempts to write the history information to the next page 2 as shown in FIG. 8B. As a result, since page 2, which can only be read, is written, an exception occurs, and it is notified that the memory page 501 has been used up, that is, "history information of a predetermined size has been written to the shared memory 122". detected.

Also, when an exception occurs, the exception handler 406 corresponding to the exception that occurred is activated, and the memory address that caused the exception is passed to the exception handler 406 . In response to this, the exception handler 406 sets the access attribute of page 2 to "read/write enabled" and the access attribute of page 1 to "read only," as shown in FIG. 5C, for example. ”. As a result, the process execution unit 401 can write history information to page 2 of the shared memory 122 .

Here, returning to FIG. 4, the description of the functional configuration of the image forming apparatus 200 is continued.

The trace execution unit (function tracer) 403 is implemented by, for example, a program executed by the CPU core 111a included in the CPU 201 (eg, the function tracer 123 in FIG. 1 or the LCS 325 in FIG. 3, etc.). For example, the trace execution unit 403 executes trace processing to store the history information stored in the first storage unit 402 in the second storage unit 404 that stores the history information of one or more process execution units 401. .

For example, the trace execution unit 403 acquires history information stored in the shared memory (first storage unit) 500 when an exception occurs in the shared memory 122, as described with reference to FIG. 5B. and stores the acquired history information in the second storage unit 404 .

The second storage unit (storage) 404 is implemented by, for example, programs executed by the CPU 201 (eg, the OS 341, etc.) and a storage device (eg, the storage 130 in FIG. 1, or the HD 208 in FIG. 2, etc.). The second storage unit 404 sequentially stores (accumulates) information such as functions called by each of the one or more process execution units 401 and the time of the call as log information. Note that the second storage unit 404 may be an external device (for example, a storage server, a management server, etc.) provided outside the image forming apparatus 200 and capable of communicating with the image forming apparatus 200 .

The execution control unit 405 is realized by, for example, a program (for example, init 342 etc.) executed by the CPU 201 . The execution control unit 405 causes one CPU core 111 (for example, the CPU core 111 a ) among the plurality of CPU cores 111 included in the CPU 201 to execute the trace processing executed by the trace execution unit (function tracer) 403 . Also, the execution control unit 405 causes the other CPU cores 111 (for example, the CPU cores 111b, 111c, . . . ) to execute the processes executed by the process execution units 401a, 401b, .

In addition, in order to specify the CPU core 111 that executes a predetermined process, for example, by setting the affinity (or CPU affinity) of the OS 341, the CPU core 111 that executes the process can be arbitrarily designated or restricted. be able to.

The exception handler 406 is implemented, for example, by a program executed by the CPU 201, and activates the trace execution unit 403 when an exception occurs in the shared memory 122, for example, as described with reference to FIG. 5B.

<Process flow>
Next, the flow of processing of the information processing method according to this embodiment will be described.

<Startup processing>
FIG. 6 is a sequence diagram illustrating an example of processing at startup according to one embodiment. This processing shows an example of processing executed by the image forming apparatus 200 when the image forming apparatus 200 or the OS 341 is activated.

In step S601, when the OS 341 is activated, the OS 341 executes processing processing for initializing the OS 341 itself.

In step S602, the OS 341 causes the CPU 201 to execute a predetermined program (for example, init 342 in FIG. 3) after completing the initialization process. As a result, the execution control unit 405 is implemented by the program executed by the CPU 201 .

In step S603, the execution control unit 405 designates the CPU core 111a to execute a predetermined program (for example, the LCS 325 in FIG. 3). As a result, the program executed by the CPU core 111a realizes the trace execution unit 403 that executes trace processing.

In step S604, the execution control unit 405 designates the CPU cores 111 other than the CPU core 111a (for example, the CPU cores 111b, 111c, . . . ) and executes a predetermined program (for example, the print application 311 in FIG. let it run. Thus, the processing execution unit 401a that executes predetermined processing is realized by the programs executed by the CPU cores 111b, 111c, . . .

In step S605, the execution control unit 405 designates the CPU cores 111 other than the CPU core 111a (eg, the CPU cores 111b, 111c, . . . ) to execute a predetermined program (eg, the copy application 312, etc.). . As a result, the processing execution unit 401b that executes predetermined processing is realized by the programs executed by the CPU cores 111b, 111c, . . .

Through the above processing, the execution control unit 405 causes one CPU core 111a among the plurality of CPU cores 111 included in the CPU 201 to execute the trace processing, and causes the other CPU cores 111b, 111c, . process can be executed.

<Write process of history information>
FIG. 7 is a flowchart illustrating an example of history information write processing according to an embodiment. The processing execution unit 401 according to the present embodiment executes history information writing processing as shown in FIG. 7 each time a function is called.

In step S701, the process execution unit 401 of the image forming apparatus 200 determines whether the function call is the first call. For example, the processing execution unit 401 can determine whether or not the call is the first call by using a flag using a global variable. Specifically, since the initial value of a global variable in C language is "0", if the value is "0", it is determined to be the first call.

If it is the first call, the processing execution unit 401 shifts the processing to step S702. On the other hand, if it is not the first call, the processing execution unit 401 shifts the processing to step S705.

After shifting to step S702, the processing execution unit 401 acquires the shared memory 122 and identification information (hereinafter referred to as ID) for identifying the shared memory 122 as shown in FIG. 5A, for example. For example, when the OS 341 is Linux, the shared memory 122 and the ID of the shared memory 122 can be obtained by using the standard function shmget(). Note that the shared memory 122 acquired here is included in, for example, the first storage unit (shared memory) 402 in FIG.

In step S<b>703 , the processing execution unit 401 notifies the trace execution unit (function tracer) 403 of the acquired ID of the shared memory 122 .

In step S704, the process execution unit 401 records that the first call has been made. For example, the process execution unit 401 changes the value of the above-described global variable from "0" to "1" or the like.

In step S<b>705 , the process execution unit 401 writes history information, which is the history of the called function, to the acquired shared memory 122 .

Through the above process, when the process execution unit 401 calls a function, history information, which is the history of the called function, is written to the first storage unit (shared memory) 402 .

It should be noted that the processing execution unit 401 according to the present embodiment only performs processing for writing history information to the shared memory 122 in the RAM area when calling the function for the second and subsequent times. Do not write to storage devices. Therefore, it is possible to suppress the influence of the predetermined process executed by the process execution unit 401 on the processing performance.

<Processing when calling a function>
FIG. 8 is a sequence diagram illustrating an example of processing when a function is called according to one embodiment. This process shows an example of the process executed by the image forming apparatus 200 when the process execution unit 401 calls the function.

In step S801, when the process execution unit 401 calls a function, in step S802, the process execution unit 401 executes history information writing processing as shown in FIG. As a result, for example, as shown in FIG. 5A, history information is stored in the shared memory 122 when writing is performed to a memory page whose access attribute is “readable/writable”.

On the other hand, as a result, as shown in FIG. 5B, when writing is performed to a memory page whose access attribute is "read only", processing 800 shown in steps S811 to S818 in FIG. 8 is executed. .

In step S811, for example, as shown in FIG. 5B, an exception is generated by writing to a memory page whose access attribute is "read only". In response, the exception handler 406 is activated in step S812.

At step S813, the exception handler 406 changes the access attribute of the shared memory 122. FIG. For example, as shown in FIG. 5B, if an exception occurs when page 2 is written, the exception handler 406 sets the access attribute of page 2 to " Read/Write" and change the access attribute of page 1 to "Read Only". As a result, the process execution unit 401 can write history information to page 2 .

In step S814, the exception handler 406 requests the trace execution unit (function tracer) 403 to execute processing. As a result, in step S815, the trace execution unit 403 reads the history information stored in the shared memory 122. FIG.

In step S<b>816 , the trace execution unit 403 stores history information read from the shared memory 122 in the second storage unit (storage) 404 . Also, in step S817, the trace execution unit 403 notifies the exception handler 406 of a completion notification indicating that the processing has been completed.

In step S818, when returning from the exception, in step S819, the process execution unit 401 executes the process of writing history information to the shared memory 122 whose access attribute has become "readable/writable".

As a result of the above processing, when one memory page of the shared memory 122 runs out of free space, the trace execution unit (function tracer) 403 acquires the history information stored in the memory page and stores it in the second storage unit (storage ) 404 .

<Processing of processing execution part>
FIG. 9 is a sequence diagram illustrating an example of processing by a processing execution unit according to an embodiment; This processing shows an example of processing executed by the image forming apparatus 200 from when the processing execution unit 401 is activated by the execution control unit 405 until the processing ends.

In step S901, the execution control unit 405 activates the process execution unit 401. In step S902, the process execution unit 401 performs processing (environment setup) for preparing an environment for executing the program before executing the main( ) function. ).

In step S903, the processing execution unit 401 calls the main( ) function and starts executing predetermined processing. As a result, for example, the processes of steps S904 to S910 are executed.

In step S904, the processing execution unit 401 calls and executes the first function (for example, function A). In response to this, the process execution unit 401 executes the history information writing process described with reference to FIG. Here, since the function A corresponds to the first function call, the processing of steps S702 to S705 in FIG. 7 is executed.

In step S<b>905 , the process execution unit 401 acquires the shared memory 122 and the ID of the shared memory 122 from the first storage unit 402 . This process corresponds to the process of step S702 in FIG.

In step S<b>906 , the process execution unit 401 notifies the trace execution unit (function tracer) 403 of the acquired ID of the shared memory 122 . This process corresponds to the process of step S703 in FIG.

In step S<b>907 , the process execution unit 401 writes history information indicating that the function A has been called into the shared memory 122 included in the first storage unit 402 . As a result, the history information is stored in the shared memory 122 as shown in FIG. 5A, for example. Note that this process corresponds to the process of step S705 in FIG.

In step S<b>908 , the process execution unit 401 calls and executes the second and subsequent functions (for example, function B). In response to this, the process execution unit 401 executes the history information writing process described with reference to FIG. Here, function B does not correspond to the first function call, so the process of step S705 in FIG. 7 is executed.

In step S<b>909 , the process execution unit 401 writes history information indicating that the function B has been called into the shared memory 122 included in the first storage unit 402 . As a result, the history information is added to the shared memory 122 as shown in FIG. 5A, for example.

As in steps S908 and S909, the process execution unit 401 writes history information to the shared memory 122 each time a function is called, and in step S910, terminates execution of the main() function or terminates execution of the exit() function. Then, the processing after step S911 is executed.

In step S911, the processing execution unit 401 notifies the trace execution unit 403 that writing of the history information has ended. This notification includes, for example, the ID of the shared memory 122 .

In step S912, the trace execution unit 403 acquires the history information stored in the shared memory 122 for which writing has ended. In step S<b>913 , the trace execution unit 403 notifies the process execution unit 401 of completion notification indicating that acquisition of the history information stored in the shared memory 122 has been completed. Furthermore, in step S<b>914 , the trace execution unit (function tracer) 403 stores the acquired history information in the second storage unit (storage) 404 .

In step S915, the process execution unit 401, upon receiving the completion notification, releases the shared memory 122, and in step S916, notifies the execution control unit 405 of an end notification indicating that the process has ended.

Through the above process, the process execution unit 401 can store the history information, which is the history of the function called, in the shared memory 122 included in the first storage unit 402 when executing the process.

Further, when the processing execution unit 401 finishes predetermined processing, the trace execution unit 403 acquires the history information stored in the shared memory 122 before the shared memory is released, and stores the history information in the second storage unit 404 . can be stored in

<Embedding processing by compiler>
As described above, the process execution unit 401 executes the history information write process as shown in FIG. 7 each time the function is called. As an example, the process execution unit 401 may explicitly call a function that executes the history information writing process each time the function is called.

Further, as a preferred example, processing may be embedded in a program so that a function for executing history information writing processing is automatically called when the program is compiled.

FIG. 10 is a diagram for explaining embedding of processing by a compiler according to one embodiment. For example, in GCC (GNU Compiler Collection), which is an open-source compiler, by specifying a specific compile option, it is possible to specify to call specific functions at the beginning and end of each function.

As a result, for example, when the caller function calls the read destination function in step S1001 of FIG. 10, the function "_cyg_profile_func_enter( )" is automatically called in step S1002. At this time, for example, the address of the "callee function" is passed as the first argument, and the address of the "caller function" is passed as the second argument.

Also, in step S1003 of FIG. 10, the function "_cyg_profile_func_exit()" is automatically called before the callee function is terminated. is notified.

For example, the processes of steps S1002 and S1003 are automatically added by designating the aforementioned specific option (for example, "-finstrument-functions"). However, functions such as "_cyg_profile_func_exit()" and "_cyg_profile_func_exit()" must be implemented by the developer.

<Another example of functional configuration>
The functional configuration of the image forming apparatus 200 described with reference to FIG. 4 is an example. For example, in the example of FIG. 4, the image forming apparatus 200 includes the second storage unit 404. The second storage unit 404 is connected to the image forming apparatus via the communication network 1103 as shown in FIG. An external device 1102 or the like that can communicate with 200 may be used.

In FIG. 11, a communication unit 1101 is implemented by, for example, a program executed by the CPU 201 in FIG. I do.

An external device (another example of the second storage unit) 1102 is a general computer or a system including a plurality of computers, is connected to the communication network 1103, and stores history information transmitted from the image forming apparatus 200. It functions as a second storage unit that stores data. The external device 1102 may be, for example, a general storage server or the like, or may be a management server or the like that manages history information of a plurality of image forming apparatuses 200 .

As described above, according to each embodiment of the present invention, in the image forming apparatus 200 that executes predetermined processing, the history information of the program that executes the predetermined processing is acquired while reducing the influence of the processing performance of the predetermined processing. become able to.

Note that, as described above, the image forming apparatus 200 is an example of the information processing apparatus 100 including a CPU having multiple cores. The information processing apparatus 100 may be another electronic device, an information terminal, or the like that includes a CPU having multiple cores.

<Supplement>
Each function of each embodiment described above can be realized by one or more processing circuits. Here, the "processing circuit" in this specification means a processor programmed by software to perform each function, such as a processor implemented by an electronic circuit, or a processor designed to perform each function described above. ASICs (Application Specific Integrated Circuits), DSPs (digital signal processors), FPGAs (field programmable gate arrays) and devices such as conventional circuit modules.

100 information processing device 110 processor 111a, 111b, 111c CPU core 130 storage (storage device)
200 image forming apparatus (an example of an information processing apparatus)
201 CPU (an example of a processor)
208 HD (an example of a storage device)
401a, 401b process execution unit 402 first storage unit 403 trace execution unit 404 second storage unit 405 execution control unit 500 shared memory 501 memory page (storage area)
1102 external device

JP 2014-41419 A

Claims (10)

An information processing device comprising a processor having a plurality of CPU cores,
one or more processing execution units that execute predetermined processing and store history information associated with execution of the processing in a first storage unit that temporarily stores the history information;
a trace execution unit that executes trace processing for storing the history information stored in the first storage unit in a second storage unit that accumulates the history information of the one or more process execution units;
an execution control unit that causes one CPU core among the plurality of CPU cores to execute the trace processing, and causes one or more other CPU cores different from the one CPU core to execute the predetermined processing;
An information processing device. 2. The information processing apparatus according to claim 1, wherein said first storage unit includes a shared memory that can be shared by a plurality of processes executed by said information processing apparatus. The processing execution unit
Acquiring the shared memory and identification information of the shared memory when starting the predetermined process;
notifying the trace execution unit of the acquired identification information of the shared memory;
storing the history information in the acquired shared memory;
The information processing apparatus according to claim 2. The processing execution unit notifies the trace execution unit that the predetermined processing is to be completed when the predetermined processing is completed;
the trace execution unit acquires the history information from the shared memory corresponding to the identification information of the shared memory notified from the processing execution unit when the processing execution unit finishes the predetermined processing; storing in the second storage unit;
The information processing apparatus according to claim 3. The shared memory includes a plurality of storage areas,
The trace execution unit acquires the history information stored in the one storage area when one of the plurality of storage areas runs out of free space, and stores the history information in the second storage unit. Remember,
The information processing apparatus according to any one of claims 2 to 4. 6. The information processing apparatus according to claim 1, wherein said history information includes a function call history by said process execution unit. 7. The information processing apparatus according to claim 1, wherein said trace execution unit sequentially stores said history information of said process execution unit in said second storage unit. The information processing apparatus according to any one of claims 1 to 7, wherein said second storage unit includes a storage device included in said information processing apparatus, or an external device capable of communicating with said information processing apparatus. An information processing device equipped with a processor having a plurality of CPU cores,
one or more predetermined processes;
A process of storing history information associated with execution of the predetermined process in a first storage unit that temporarily stores the history information;
a tracing process of storing the history information stored in the first storage unit in a second storage unit that stores the history information of the one or more process execution units;
a process of causing one CPU core among the plurality of CPU cores to execute the trace process and causing one or more other CPU cores different from the one CPU core to execute the predetermined process;
A method of processing information that performs an information processing device comprising a processor having a plurality of CPU cores,
one or more processing execution units that execute predetermined processing and store history information associated with the execution of the processing in a first storage unit that temporarily stores the history information;
a trace execution unit for executing trace processing for storing the history information stored in the first storage unit in a second storage unit for accumulating the history information of the one or more process execution units; and an execution control unit that causes one CPU core among the CPU cores to execute the trace processing and causes one or more other CPU cores different from the one CPU core to execute the predetermined processing;
A program that functions as

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