JP2020129930A - Unit parallel inverter - Google Patents

Abstract

To generate a gate command in a unit parallel inverter that performs interleaved drive in which two chopper circuits are connected in parallel.SOLUTION: A carrier signal generation unit 6 generates a carrier signal common to first and second units. An inverting unit 5 inverts a duty signal of the second unit to a symmetrical value with an intermediate value between an upper limit value and a lower limit value of the carrier signal as a reference, and outputs the value as a corrected duty signal. A first PWM calculation unit 7 performs PWM control by comparing the duty signal of the first unit and the carrier signal, and outputs a gate command of the first unit. A second PWM operation unit 8 performs PWM control by comparing the corrected duty signal of the second unit and the carrier signal. A logic inversion unit 9 logically inverts the output of the second PWM operation unit 8 and outputs the output as a gate command for the second unit.SELECTED DRAWING: Figure 1

Description

The present invention relates to a unit parallel inverter in which two chopper circuits are connected in parallel, and particularly to a gate command generation method for interleaving.

There is a method called an interleave method in which a plurality of chopper circuits are connected in parallel to reduce the size and weight of the buck-boost chopper. FIG. 5 is a diagram showing a unit parallel inverter in which two chopper circuits are connected in parallel. In the interleave method, the switching cycle of the two chopper circuits connected in parallel is shifted, and the two chopper circuits are operated in opposite phases to reduce the ripple current of the capacitors, and the capacitors can be miniaturized.

Also, Non-Patent Document 1 discloses a method of integrating two cores into one by combining two reactors for a chopper circuit. With such a configuration, the number of parts is reduced, and the current ripple is reduced by mutual induction, thereby reducing the size of the reactor.

As a method of generating the gate command for the two chopper circuits connected in parallel, as shown in FIGS. 6 and 7, a method of generating a carrier signal for each chopper circuit and shifting the phase of each carrier signal by 180° Is common. By comparing this carrier signal with the duty signal of the A-phase first unit and the duty signal of the B-phase second unit, the gate commands S _A1 and S _B1 are generated. As a method for generating the gate commands S _A1 and S _B1 , Patent Documents 1 and 2 describe that the phase difference between carrier signals of n parallel chopper circuits may be 360°/n.

JP, 2011-061901, A JP, 2013-220028, A

"Characteristics Analysis and Design of Boost Chopper Circuit for Vehicles Using Coupled Inductors," Journal of Power Electronics Society, Vol. 39 (2014.3)

However, the method of generating this carrier signal for each chopper circuit and setting the phase difference of each carrier signal may not be implemented depending on the configuration of the control circuit. For example, when the existing control circuit is diverted and the PWM function of the microcomputer is used, the function of generating two carrier signals and inverting the sign of one of the carrier signals is not installed, and the carrier generation unit uses an ASIC ( In some cases, the logic circuit cannot be changed because it is composed of an Application Specific Integrated Circuit.

Because of the above problems, Patent Documents 1 and 2 describe a gate command generation method when three or more chopper circuits are connected in parallel, but a gate command when two chopper circuits are connected in parallel. The generation method is not described.

From the above, it is an object to propose a gate command generation method in a unit parallel inverter that performs interleave drive in which two chopper circuits are connected in parallel.

The present invention has been devised in view of the above-mentioned conventional problems, and one aspect thereof includes a first unit having two switching elements connected in series and two switching elements connected in series, A second unit connected in parallel with the first unit, a first reactor having one end connected to a connection point of two switching elements of the first unit, and a connection point of two switching elements of the second unit. A unit parallel inverter having one end connected to the other end of the first reactor and the other end connected to the other end of the first reactor, the unit parallel inverter performing interleave drive, the common carrier signal for the first and second units. A carrier signal generating unit for generating and an inverting unit for inverting the duty signal of the second unit to a symmetric value based on an intermediate value between the upper limit value and the lower limit value of the carrier signal and outputting the corrected duty signal as a corrected duty signal. And a first PWM operation unit that performs PWM control by comparing the duty signal of the first unit with the carrier signal and outputs a gate command of the first unit, the corrected duty signal of the second unit, and the carrier. It is characterized by further comprising: a second PWM operation unit that performs PWM control by comparing with a signal; and a logic inversion unit that logically inverts the output of the second PWM operation unit and outputs it as a gate command of the second unit. ..

Further, as one aspect thereof, when the upper limit value and the lower limit value of the carrier signal are values of positive and negative symmetry, the inverting unit uses a value obtained by inverting the sign of the duty signal of the second unit as the correction duty signal. It is characterized by outputting.

Further, as another aspect, when the upper limit value and the lower limit value of the carrier signal are not values of positive and negative symmetry, the inverting unit calculates a duty signal of the second unit from a value obtained by adding the upper limit value and the lower limit value of the carrier signal. Is output as the corrected duty signal.

According to the present invention, it is possible to generate a gate command in a unit parallel inverter that performs interleave drive in which two chopper circuits are connected in parallel.

3 is a control block diagram of the unit parallel inverter in the first embodiment. FIG. 3 is a time chart showing each signal in the first embodiment. 6 is a control block diagram of a unit parallel inverter in Embodiment 2. FIG. 9 is a time chart showing each signal in the second embodiment. The figure which shows the unit parallel inverter which connected two chopper circuits in parallel. The control block diagram of the conventional unit parallel inverter. The time chart which shows each signal of the conventional unit parallel inverter.

Hereinafter, Embodiments 1 and 2 of the unit parallel inverter in the present invention will be described in detail with reference to FIGS.

[Embodiment 1]
First, the main circuit of the unit parallel inverter according to the first embodiment will be described with reference to FIG. The first and second embodiments assume a unit parallel inverter in which two chopper circuits are connected in parallel, and do not assume a configuration in which three or more chopper circuits are connected in parallel.

As shown in FIG. 5, in the unit parallel inverter according to the first embodiment, two first and second units A and B of A phase and B phase are connected in parallel. In the first unit A, the first switching element A1 and the second switching element A2 are connected in series. Similarly, in the second unit B, the first switching element B1 and the second switching element B2 are connected in series.

One end of the first reactor L ₁ is connected to the connection point between the A-phase first switching element A1 and the second switching element A2, and the first connection point between the B-phase first switching element B1 and the second switching element B2 is One end of the two reactors L ₂ is connected. The other ends of the first and second reactors L ₁ and L ₂ are connected to each other.

The voltage between the connection point of the first and second reactors L ₁ and L _{2 and} the connection point of the second switching elements A 2 and B 2 is the low voltage side detection value V _low . Further, the voltage between the connection point of the first switching elements A1 and B1 and the connection point of the second switching elements A2 and B2 is the high voltage detection value V _high .

The current on the _low voltage side V _low side of the connection point of the first and second reactors L ₁ and L ₂ is I _L , the current flowing to the first reactor L ₁ is I _L1, and the current flowing to the second reactor L _{2. Is} I _L2 . The gate commands for the switching elements A1, A2, B1, B2 are S _A1 , S _A2 , S _B1 , and S _B2 .

FIG. 1 shows a control block configuration of a unit parallel inverter according to the first embodiment. In the first embodiment, the case where the upper limit value and the lower limit value of the carrier signal are positive and negative symmetrical values such as 1 and -1 will be described.

The DC voltage control unit 1 performs voltage control so that the high-voltage-side voltage detection value V _high follows the DC voltage command value, and outputs the current command value I _{L_ref} . The current command value I _{L_ref} is the current command value of the current I _L that is _passed to the low voltage side voltage detection value V _low side. The multiplying unit 2 _outputs a half value of the current command value I _{L_ref as} a first reactor current command value and a second reactor current command value that flow through the first and second reactors L ₁ and L ₂ of each phase.

The first current control unit 3 inputs the detected value of the current I _L1 and the first reactor current command value, performs current control, and outputs the duty signal of the first unit. The second current control unit 4 inputs the detected value of the current I _L2 and the second reactor current command value, performs current control, and outputs the duty signal of the second unit. The carrier signal generation unit 6 generates a carrier signal common to the A-phase and B-phase first and second units.

The inverting unit 5 inverts the duty signal of the second unit to a symmetrical value with the intermediate value between the upper limit value and the lower limit value of the carrier signal as a reference, and outputs it as a corrected duty signal. In the first embodiment, a value obtained by inverting the sign of the duty signal of the second unit is used as the corrected duty signal.

When the upper limit value and the lower limit value of the carrier signal are positive and negative symmetric values, the intermediate value is 0, so the value inverted to a symmetric value with 0 as a reference is the value with the sign inverted. Therefore, in the first embodiment, the inverting unit 5 uses a value obtained by inverting the sign of the duty signal of the second unit as the corrected duty signal.

The first PWM calculator 7 performs PWM control by comparing the duty signal of the first unit with the carrier signal, and outputs the gate commands S _A1 and S _A2 . The second PWM calculator 8 performs PWM control by comparing the corrected duty signal and the carrier signal. The logic inversion unit 9 logically inverts the output of the second PWM operation unit 8 and outputs it as gate commands S _B1 and S _B2 .

As described above, in the first embodiment, the outputs of the first and second current control units 3 and 4 are input to the first and second PWM calculation units 7 and 8. At that time, the A phase and the B phase (the first , Second unit), and the sign of the duty signal of either one is inverted and input to the first and second PWM operation units 7 and 8. Then, the PWM operation output of which the sign is inverted is logically inverted to generate a final gate command. In FIG. 1, the sign of the duty signal of the second unit is inverted.

FIG. 2 is a time chart showing each signal of the unit parallel inverter in the first embodiment. As shown in FIG. 2, in the first embodiment, the carrier signal is common to the first and second units. PWM control is performed by comparing the duty signal of the first unit (A phase) and the carrier signal, and the gate command S _A1 is output.

Further, the duty signal of the second unit (Phase B) is set by the inverting unit 5 with reference to an intermediate value (0.0) between the upper limit value (1.0) and the lower limit value (-1.0) of the carrier signal. Inverted to a symmetric value. When the duty signal of the second unit (Phase B) is set to 0.6 and inverted to a symmetrical value with the intermediate value 0.0 as a reference, the corrected duty signal becomes -0.6. In the first embodiment, when the duty signal of the second unit (phase B) is set to 0.6, the sign is inverted to output -0.6 as the corrected duty signal.

The second PWM operation unit 8 performs PWM control by comparing the corrected duty signal and the carrier signal, and logically inverts the output of the second PWM operation unit 8 to generate the gate command S _B1 .

As described above, according to the first embodiment, it is possible to generate a gate command in a unit parallel inverter that performs interleave drive in which two chopper circuits are connected in parallel.

Depending on the hardware configuration, it may not be possible to generate two carrier signals having a 180° phase difference when generating a gate command for two-phase interleaving. For example, if the existing control circuit is diverted and the PWM function of the microcomputer is used, the function of generating two carrier signals and inverting the sign of one carrier signal is not installed, and the carrier generation unit is an ASIC. Being configured, it may not be possible to change the logic circuit.

In the first embodiment, it is possible to generate the gate command for two-phase interleaving by adding the process of inverting the duty signal used for the PWM calculation and the process of inverting the gate command after the PWM calculation.

Compared to the case of generating two carrier signals with 180° phase difference, the hardware configuration can be simplified and the restrictions are reduced, so that it becomes easier to realize the gate command generation for interleaving, and the existing control circuit can be realized. Is also easy to divert.

For example, since the duty signal input to the PWM calculation is the calculation result of the CPU or the like, the correction of the sign inversion or the like can be easily realized without depending on the hardware, and the sign inversion function of the PWM operation output is better than the inversion function of the carrier signal. Is often installed as a standard function.

[Embodiment 2]
In the second embodiment, a case where the upper limit value and the lower limit value of the carrier signal are not positive and negative symmetrical values such as 1 and 0 will be described.

FIG. 3 shows a control block configuration of the unit parallel inverter in the second embodiment. As shown in FIG. 3, similarly to the first embodiment, the second embodiment also performs voltage control so that the _high voltage detection value V _high follows the DC voltage command value, and outputs the current command value I _{L_ref} . The multiplying unit 2 _outputs a half value of the current command value I _{L_ref as} a first reactor current command value and a second reactor current command value to be _passed through the first and second reactors L ₁ and L ₂ of each phase.

The first current control unit 3 inputs the detected value of the current I _L1 and the first reactor current command value, performs current control, and outputs the duty signal of the first unit. The second current control unit 4 inputs the detected value of the current I _L2 and the second reactor current command value, performs current control, and outputs the duty signal of the second unit.

The inverting section 5 inverts the duty signal of the second unit to a symmetrical value with the intermediate value between the upper limit value and the lower limit value of the carrier signal as a reference, and outputs it as a corrected duty signal. In the second embodiment, it is assumed that the upper limit value and the lower limit value of the carrier signal are not symmetrical in positive and negative.

The inverting unit 5 of the second exemplary embodiment includes an adding unit 10 and a subtracting unit 11. The addition unit 10 adds the upper limit value and the lower limit value of the carrier signal. The subtractor 11 subtracts the output of the second current controller 4 (duty signal of the second unit) from the output of the adder 10. Subsequent operations of the first and second PWM operation units 7 and 8 and the logic inversion unit 9 are the same as those in the first embodiment.

As an example, FIG. 4 shows a case where the upper limit value of the carrier signal is 1, the lower limit value is 0, and the output of the second current control unit 4 (duty signal of the second unit) is 0.8. When the carrier signal has an upper limit value of 1 and a lower limit value of 0, the intermediate value is 0.5. When the duty signal 0.8 of the second unit is inverted to a symmetrical value with the intermediate value 0.5 as a reference, the corrected duty signal becomes 0.2.

In the second embodiment, the corrected duty signal of the second unit is calculated by the following formula.
Corrected duty signal=carrier signal upper limit value+carrier signal lower limit value−duty signal of second unit
=1.0+0.0-0.8
= 0.2
As described above, according to the second embodiment, the same operational effect as that of the first embodiment can be obtained. Further, even when the configuration of the carrier signal is not positive/negative symmetrical about 0, the corrected duty signal can be generated, and the gate command can be generated by using the carrier signals of the two chopper circuits in common.

When the carrier signal is symmetrical with respect to zero as in the first embodiment, it can be dealt with by inverting the sign of the carrier signal. However, there is a case where the carrier signal is not positive/negative symmetrical, and in that case, the gate command of the unit parallel inverter in which two chopper circuits are connected in parallel cannot be generated by the sign inversion of the carrier signal. It is necessary to prepare carrier signals whose phases are shifted by 180° while synchronizing carrier signals for two phases, which further complicates the configuration.

On the other hand, in the second embodiment, the hardware configuration can be simplified and the number of restrictions is reduced as compared with the case where two carrier signals having a 180° phase difference are generated. Therefore, generation of a gate command for interleaving is not possible. Easier to do. In addition, it is easy to use in existing control circuits.

In the above, the present invention has been described in detail only for the specific examples described, but it is obvious to those skilled in the art that various variations and modifications are possible within the scope of the technical idea of the present invention, Of course, such variations and modifications are within the scope of the claims.

In the specification, the method of generating the duty signal of the first unit and the duty signal of the second unit by using the DC voltage control unit 1 and the first and second current control units 3 and 4 is described. The unit duty signal and the second unit duty signal may be generated by other methods.

1: DC voltage control unit 2: Multiplication unit 3: First current control unit 4: Second current control unit 5: Inversion unit 6: Carrier signal generation unit 7: First PWM calculation unit 8: Second PWM calculation unit 9: Logic inversion Part 10: Adder 11: Subtractor

Claims (3)

A first unit having two switching elements connected in series;
A second unit having two switching elements connected in series and connected in parallel with the first unit;
A first reactor having one end connected to a connection point of the two switching elements of the first unit;
And a second reactor having one end connected to a connection point of two switching elements of the second unit and the other end connected to the other end of the first reactor, the unit parallel inverter performing interleave drive, ,
A carrier signal generator for generating a carrier signal common to the first and second units,
An inversion unit that inverts the duty signal of the second unit to a symmetrical value based on an intermediate value between the upper limit value and the lower limit value of the carrier signal and outputs the corrected duty signal;
A first PWM calculation unit that performs PWM control by comparing the duty signal of the first unit with the carrier signal and outputs a gate command of the first unit;
A second PWM calculation unit that performs PWM control by comparing the corrected duty signal of the second unit with the carrier signal;
A logic inversion unit that logically inverts the output of the second PWM operation unit and outputs it as a gate command of the second unit;
A unit parallel inverter characterized by having. When the upper limit value and the lower limit value of the carrier signal are values of positive and negative symmetry,
The unit parallel inverter according to claim 1, wherein the inverting unit outputs a value obtained by inverting the sign of the duty signal of the second unit as the corrected duty signal. When the upper limit value and the lower limit value of the carrier signal are not positive and negative symmetrical values,
2. The unit parallel according to claim 1, wherein the inverting unit outputs a value obtained by subtracting a duty signal of the second unit from a value obtained by adding an upper limit value and a lower limit value of the carrier signal as the correction duty signal. Inverter.

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