JP2020118790A - Display - Google Patents

Abstract

To provide a display that can prevent a reduction in display quality.SOLUTION: A display comprises: a first substrate that includes a first principal surface and a first concave part; a second substrate that includes a second principal surface opposite to the first principal surface, a main spacer provided on the second principal surface and in contact with the first principal surface, and a sub spacer provided on the second principal surface and separated from the first substrate; and a liquid crystal layer that is located between the first substrate and the second substrate. The sub spacer has an end that is located inside the first concave part; the main spacer has a first height and the sub spacer has a second height, and the second height is larger than the first height.SELECTED DRAWING: Figure 1

Description

Embodiments of the present invention relate to a display device.

In one example, a liquid crystal display device is disclosed that includes a first spacer that defines a distance between the first substrate and the second substrate, and a second spacer that is provided at a position facing the recess of the first substrate. .. The second spacer has substantially the same height as the first spacer. When a pressing force is applied from the outside, the first spacer functions to maintain the space between the substrates in the vicinity thereof, while the second spacer fits in the recess.

JP, 2007-316329, A

An object of the present embodiment is to provide a display device capable of suppressing deterioration of display quality.

According to this embodiment,
A first substrate having a first main surface and a first recess, a second main surface facing the first main surface, and a main spacer provided on the second main surface and in contact with the first main surface. A second substrate having a sub-spacer provided on the second main surface and separated from the first substrate, and a liquid crystal layer located between the first substrate and the second substrate. The sub-spacer has an end located inside the first recess, the main spacer has a first height, the sub-spacer has a second height, and the second spacer has a second height. A display device having a height greater than the first height is provided.

FIG. 1 is a cross-sectional view showing a display device DSP of this embodiment. FIG. 2 is a cross-sectional view showing a comparative example of the display device DSP. FIG. 3 is a cross-sectional view of an experimental device LD for evaluating the bright spot generation load. FIG. 4 is a plan view showing a configuration example of the display panel PNL of this embodiment. FIG. 5 is a diagram showing a configuration example of the display device DSP of the present embodiment. FIG. 6 is a plan view showing an example of a pixel layout. FIG. 7 is a plan view showing the light shielding layer BM corresponding to the pixel layout shown in FIG. FIG. 8 is a sectional view of the display device DSP taken along the line AB shown in FIG. 7. FIG. 9 is a cross-sectional view of the display device DSP taken along the line C-D shown in FIG. 7. FIG. 10 is a cross-sectional view showing a modified example of the first substrate SUB1 shown in FIG.

Hereinafter, the present embodiment will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and a person having ordinary skill in the art can easily think of appropriate modifications while keeping the gist of the invention, and are naturally included in the scope of the invention. Further, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part as compared with the actual mode, but this is merely an example, and It does not limit the interpretation. Further, in the present specification and the drawings, constituent elements that exhibit the same or similar functions as those described above with respect to the already-existing drawings are designated by the same reference numerals, and redundant detailed description may be appropriately omitted. ..

FIG. 1 is a cross-sectional view showing a display device DSP of this embodiment. In one example, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees. The first direction X and the second direction Y correspond to the directions parallel to the main surface of the substrate forming the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP. In this specification, the direction toward the tip of the arrow indicating the third direction Z is referred to as upward (or simply upward), and the direction opposite from the tip of the arrow is referred to as downward (or simply downward). Further, it is assumed that there is an observation position for observing the display device DSP on the tip side of the arrow indicating the third direction Z, and from this observation position, the observation position is directed to the XY plane defined by the first direction X and the second direction Y. Seeing is called planar view.

In the present embodiment, a liquid crystal display device will be described as an example of the display device DSP.

FIG. 1 schematically shows a cross section of the display device DSP in the YZ plane defined by the second direction Y and the third direction Z. The display device DSP includes a display panel PNL. The display panel PNL includes a first substrate SUB1, a second substrate SUB2, a seal SE, and a liquid crystal layer LC. The seal SE bonds the first substrate SUB1 and the second substrate SUB2 together with the cell gap formed. The liquid crystal layer LC is held between the first substrate SUB1 and the second substrate SUB2.

The first substrate SUB1 includes a main surface 1A, a main surface 1B, and a recess CC1. Further, although not shown, an alignment film is formed on the upper surface of the main surface 1A of the first substrate SUB1 and the lower surface of the main surface 2B of the second substrate SUB2. The main surface 1A and the recess CC1 are in contact with the liquid crystal layer LC. The main surface 1A is a flat surface that is substantially parallel to the XY plane. The main surface 1B is located on the opposite side of the main surface 1A and is not in contact with the liquid crystal layer LC. The recess CC1 is recessed with respect to the main surface 1A. The recess CC1 has a bottom CB. The bottom portion CB corresponds to a portion of the recess CC1 that is farthest from the second substrate SUB2 or a portion that is closest to the main surface 1B. The recess CC1 has a depth DP from the main surface 1A to the bottom CB. As will be described later, such a recess CC1 is formed by a through hole penetrating the organic insulating film or a recess of the organic insulating film. The depth DP is, for example, 1 μm to 5 μm, and is larger than the film thickness of the inorganic insulating film provided on the first substrate SUB1. When the recess CC1 is formed by the through hole of the organic insulating film, the depth DP is almost equal to the film thickness of the organic insulating film. Further, the recess CC1 may be formed by through holes of a plurality of organic insulating films stacked in the third direction Z.

The second substrate SUB2 includes a main surface 2A, a main surface 2B, a main spacer MSP, and a sub spacer SSP. The main surface 2B is a flat surface that faces the main surface 1A with the liquid crystal layer LC interposed therebetween and is substantially parallel to the XY plane. In the illustrated example, the main surface 2B is in contact with the liquid crystal layer LC, but may not be in contact with the liquid crystal layer LC. The main surface 2A is located on the opposite side to the main surface 2B and is not in contact with the liquid crystal layer LC. Both the main spacer MSP and the sub spacer SSP are provided on the main surface 2B. However, the main spacer MSP and the sub spacer SSP may be in contact with the main surface 2B, or an insulating layer or a conductive layer may be interposed between the main spacer MSP and the sub spacer SSP and the main surface 2B.

The main spacer MSP forms a cell gap for holding the liquid crystal layer LC in a steady state in which a pressing force is not applied to the display panel PNL from the outside. The main spacer MSP has an end portion MSPE in contact with the main surface 1A. The main spacer MSP has a height H1 from the main surface 2B to the end MSPE.
The sub-spacer SSP is separated from the first substrate SUB1 in the steady state and does not contribute to the formation of the cell gap. The sub spacer SSP is formed at a position overlapping the recess CC1. The sub spacer SSP has an end portion SSPE located inside the recess CC1. The sub spacer SSP has a height H2 from the main surface 2B to the end portion SSPE. The height H2 is larger than the height H1. That is, the end portion SSPE of the sub spacer SSP is closer to the main surface 1B of the first substrate SUB1 than the end portion MSPE of the main spacer MSP. Regarding the thickness along the third direction Z between the main surface 2A and the main surface 2B of the second substrate SUB2, the thickness T21 at the position where the main spacer MSP contacts is the thickness at the position where the sub spacer SSP contacts. It is equivalent to the thickness T22. Therefore, the height H1 of the main spacer MSP and the height H2 of the sub spacer SSP are measured with reference to the same plane parallel to the XY plane. In addition, the end portion MSPE and the end portion SSPE correspond to a portion farthest from the main surface 2B or a portion closest to the main surface 1B in each of the main spacer MSP and the sub spacer SSP.

The sub-spacer SSP in the steady state will be described in more detail. The end portion SSPE is separated from the bottom portion CB. The position of the end portion SSPE along the third direction Z is between the bottom portion CB and the main surface 1A. The distance D10 between the bottom portion CB and the end portion SSPE is smaller than the depth DP of the recess CC1. Further, the sub spacer SSP is not in contact with any part of the recess CC1. Therefore, the liquid crystal layer LC is located between the recess CC1 and the sub spacer SP. As a matter of course, the liquid crystal layer LC is also located between the bottom portion CB of the recess CC1 and the end portion SSPE of the sub spacer SP.

The distance D11 between the bottom portion CB and the main surface 2B is larger than the height H2 of the sub spacer SSP. The distance D12 between the main surface 1A and the main surface 2B is equal to the height H1 of the main spacer MSP and smaller than the height H2 of the sub spacer SSP. The distance D11 is equal to the sum of the distance D10 and the height H2. The difference between the height H2 and the height H1 is smaller than the depth DP. Regarding the thickness along the third direction Z between the main surface 1A and the main surface 1B of the first substrate SUB1, the thickness T11 at the position where the end portion MSPE of the main spacer MSP is in contact is the thickness of the sub spacer SSP. The depth DP is greater than the thickness T12 at the position where the end portion SSPE contacts, and the depth DP corresponds to the difference between the thickness T11 and the thickness T12.

In this specification, the depth DP, the heights H1 and H2, the thicknesses T11 and T12, the thicknesses T21 and T22, the distance D10, and the distances D11 and D12 correspond to the length along the third direction Z. ..

A detailed configuration of the display panel PNL will be omitted here, but the display panel PNL is a display mode using a vertical electric field along the third direction Z, and an inclination inclined in an oblique direction with respect to the XY plane. Any of a display mode using an electric field, a display mode using a horizontal electric field along the XY plane, and a display mode using a combination of the above vertical electric field, horizontal electric field, and gradient electric field as appropriate You may have a structure.
The display panel PNL of the present embodiment has a transmissive display function of displaying an image by selectively transmitting light from the back side of the first substrate SUB1, but the present invention is not limited to this. For example, the display panel PNL may have a reflective display function of displaying an image by selectively reflecting light from the front surface side of the second substrate SUB2, or may have both a transmissive display function and a reflective display function. You may have it.

FIG. 2 is a cross-sectional view showing a comparative example of the display device DSP. In the illustrated comparative example, the end portion SSPE of the sub-spacer SSP is separated from the main surface 1A, and the height H2 of the sub-spacer SSP is smaller than the height H1 of the main spacer MSP, as compared with the configuration example illustrated in FIG. They differ in points.

FIG. 3 is a cross-sectional view of an experimental device LD for evaluating the bright spot generation load. Here, the illustration of the sub spacer SSP is omitted. The experimental apparatus LD includes a support portion ST that supports the display panel PNL that is an experiment target, and a load portion PL that presses the display panel PNL. The support portion ST partially (linearly or dot-likely) supports the main surface 1B of the first substrate SUB1. The load part PL applies a load from the main surface 2A of the second substrate SUB2 toward the first substrate SUB1. The display panel PNL under load is deformed, and along with the deformation, one of the first direction X and the second direction Y, or along both the first direction X and the second direction Y, the first substrate SUB1. And the second substrate SUB2 is displaced. Such misalignment between the substrates is caused by the main spacer MSP provided on the second substrate SUB2 rubbing the alignment film of the first substrate SUB1 and damaging the alignment film, resulting in light leakage (bright spots caused by misalignment of liquid crystal molecules). ) May occur. In the above experimental device LD, the relationship between the load with which the load part PL presses the display panel PNL and the presence or absence of a bright spot was measured. The bright spot generation load is a load when bright spots are generated. The inventors have confirmed that when the bright spot generating load in the comparative example shown in FIG. 2 is 1, the bright spot generating load in the configuration example of the present embodiment shown in FIG. 1 is about 1. It was double. Therefore, as shown in FIG. 1, by forming the sub-spacer SSP, the lateral displacement of the first substrate SUB1 and the second substrate SUB2 in the XY plane is prevented even when a load is applied from the outside, and the brightness is reduced. It has a certain effect on the reduction of spot generation.

The description will be continued with reference to FIG. 1 again. When a pressing force is applied to the display panel PNL from the outside, the end portion SSPE of the sub spacer SSP is in contact with the bottom portion CB of the recess CC1 without contacting the side surface of the recess CC1, and excessive deformation of the display panel PNL is suppressed. To be done. That is, since the sub-spacer SSP stays inside the recess CC1, the displacement between the first substrate SUB1 and the second substrate SUB2 is suppressed. Therefore, the movable amount of the main spacer MSP can be limited. As a result, damage to the alignment film due to the movement of the main spacer MSP can be suppressed, and deterioration in display quality due to poor alignment of liquid crystal molecules can be suppressed.

In the configuration example of the present embodiment shown in FIG. 1, the main surface 1A corresponds to the first main surface, the recess CC1 corresponds to the first recess, the main surface 2B corresponds to the second main surface, and the height H1. Corresponds to the first height, the height H2 corresponds to the second height, the distance D11 corresponds to the first distance, and the distance D12 corresponds to the second distance.

FIG. 4 is a plan view showing a configuration example of the display panel PNL of this embodiment. The seal SE that attaches the first substrate SUB1 and the second substrate SUB2 is formed in a loop shape and does not include a liquid crystal injection port. The display panel PNL includes a display area DA for displaying an image and a frame-shaped non-display area NDA surrounding the display area DA. The display area DA is located inside surrounded by the seal SE.

The IC chip 1 and the flexible printed circuit board 2 are located in the non-display area NDA and are connected to the first substrate SUB1. The IC chip 1 may be mounted on the flexible printed circuit board 2. The IC chip 1 has, for example, a built-in display driver that outputs a signal necessary for displaying an image. The display driver here includes at least a part of a signal line driving circuit SD, a scanning line driving circuit GD, and a common electrode driving circuit CD which will be described later.

Such a display panel PNL is manufactured by the following process, for example. That is, after preparing the first substrate SUB1 and the second substrate SUB2 respectively, the height H1 of the main spacer MSP is measured and the volume of the liquid crystal layer LC is calculated. After that, the seal SE is formed in a loop shape, and a liquid crystal material having a calculated volume is dropped inside the seal SE while the seal SE is in an uncured state. After that, the first substrate SUB1 and the second substrate SUB2 are attached to each other, and the seal SE is cured.

FIG. 5 is a diagram showing a configuration example of the display device DSP of the present embodiment. The display device DSP includes a plurality of pixels PX in the display area DA. The plurality of pixels PX are arranged in a matrix. Further, the display device DSP includes a plurality of scanning lines G (G1 to Gn), a plurality of signal lines S (S1 to Sm), a common electrode CE, and the like in the display area DA. The scanning lines G are each connected to the scanning line drive circuit GD. The signal lines S are each connected to the signal line drive circuit SD. The common electrode CE is arranged over the plurality of pixels PX and is connected to the common electrode drive circuit CD.
Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, etc., and is provided on the first substrate SUB1 shown in FIG. The switching element SW is composed of, for example, a thin film transistor (TFT), and is electrically connected to the scanning line G and the signal line S. The pixel electrode PE is electrically connected to the switching element SW. Each of the pixel electrodes PE faces the common electrode CE and drives the liquid crystal layer LC by an electric field generated between the pixel electrode PE and the common electrode CE. The storage capacitor CS is formed, for example, between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE.

FIG. 6 is a plan view showing an example of a pixel layout. In FIG. 6, a direction that intersects the second direction Y at an acute angle in the counterclockwise direction is defined as a direction E1, and a direction that intersects the second direction Y at an acute angle in the clockwise direction is defined as a direction E2. The angle θ1 formed by the second direction Y and the direction E1 is substantially the same as the angle θ2 formed by the second direction Y and the direction E2. The scanning lines G11 to G13 extend along the first direction X and are arranged in the second direction Y at intervals. The signal lines S11 to S15 extend substantially along the second direction Y and are arranged in the first direction X at intervals.

The pixel electrodes PE11 to PE14 are arranged between the scanning lines G11 and G12. The pixel electrodes PE11 to PE14 are arranged side by side along the first direction X. The pixel electrodes PE21 to PE24 are arranged between the scanning lines G12 and G13. The pixel electrodes PE21 to PE24 are arranged in the first direction X. The pixel electrodes PE11 and PE21 are arranged between the signal lines S11 and S12, the pixel electrodes PE12 and PE22 are arranged between the signal lines S12 and S13, and the pixel electrodes PE13 and PE23 are arranged between the signal lines S13 and S14. The pixel electrodes PE14 and PE24 are arranged between the signal lines S14 and S15.

Each of the pixel electrodes PE11 to PE14 has a strip electrode Pa1 extending along the direction E1. The pixel electrodes PE21 to PE24 each have a strip electrode Pa2 extending along the direction E2. In the illustrated example, the number of the band electrodes Pa1 and Pa2 is two, but it may be one or three or more. The shape of the pixel electrode PE is not limited to this, and may be rectangular or square.

The common electrodes CE11 and CE12 are superimposed on the signal lines S11 to S15. The pixel electrodes PE11 to PE14 overlap the common electrode CE11. The pixel electrodes PE21 to PE24 overlap with the common electrode CE12. In the illustrated example, the scanning line G12 is located between the common electrodes CE11 and CE12.

FIG. 7 is a plan view showing the light shielding layer BM corresponding to the pixel layout shown in FIG. The light shielding layer BM is provided on the second substrate SUB2 shown in FIG. The light-shielding layer BM is formed in a lattice shape in the illustrated example, and includes light-shielding portions BMX and BMY. The opening OP surrounded by the light shielding layer BM corresponds to a region that contributes to display in the pixel PX. The light shielding portions BMX are arranged in the second direction Y at intervals and extend along the first direction X, respectively. The light shielding portion BMX is overlapped with each of the scanning lines G11 to G13 in a plan view. The light shielding portion BMX is formed in a strip shape having a substantially constant width WX along the second direction Y. The light shielding portions BMY are arranged in the first direction X at intervals and extend along the second direction Y, respectively. The light blocking portion BMY overlaps with each of the signal lines S11 to S15 in a plan view. The light blocking portion BMY is formed in a band shape having a substantially constant width along the first direction X.

Here, an example of the positional relationship between the recesses CC1 to CC3 provided in the first substrate SUB1 and the main spacers MSP and the sub spacers SSP provided in the second substrate SUB2 will be described. The light-shielding portion BMX2 corresponds to a light-shielding portion of the light-shielding portion BMX that overlaps the scanning line G12.

The recesses CC1 to CC3 are arranged in the first direction X at intervals and overlap the light shield BMX2. Each of the recesses CC1 to CC3 is located between the adjacent signal lines.

The sub spacer SSP and the main spacer MSP are arranged in the first direction X and overlap the light shield BMX2. The main spacer MSP is located between the recesses CC2 and CC3, and is also located at the intersection of the scanning line G12 and the signal line S13. The sub spacer SSP overlaps the recess CC1 and is located between the signal lines S11 and S12.

The sub-spacer SSP has a length LX1 along the first direction X and a length LY1 along the second direction Y. The length LX1 is greater than the length LY1. That is, the sub-spacer SSP has a laterally elongated shape expanded in the first direction X in a plan view. In the illustrated example, the sub spacer SSP is formed in an oval shape, but may be formed in another shape such as a rectangular shape. The sub-spacers SSP in the figure have the same shape.

The recess CC1 has a length LX11 along the first direction X and a length LY11 along the second direction Y. The length LX11 is greater than the length LY11. Further, the length LX11 is larger than the length LX1 of the sub spacer SSP. The length LY11 is larger than the length LY1 of the sub spacer SSP. That is, the recess CC1 has a size sufficient for the sub spacer SSP to enter. Note that the difference between the length LX1 and the length LX11 is determined according to the allowable amount of displacement between the substrates along the first direction X, and similarly, the difference between the length LY1 and the length LY11 is It is determined according to the allowable amount of displacement between the substrates along the two directions Y.

The recesses CC2 and CC3 do not overlap any of the sub spacers. Therefore, the recesses CC2 and CC3 may have a different shape from the recess CC1. For example, in order to flatten the region where the main spacer MSP contacts between the recesses CC2 and CC3, the lengths of the recesses CC2 and CC3 along the first direction X are made smaller than the length LX11 of the recess CC1. Good. Alternatively, the distance D2 between the concave portions CC2 and CC3 may be larger than the distance D1 between the concave portions CC1 and CC2. As a result, when the main spacer MSP comes into contact between the recesses CC2 and CC3, it is less likely to be affected by the recesses CC2 and CC3, and the cell gap can be made uniform. It should be noted that the intervals D1 and D2 here are both lengths along the first direction X.

The main spacer MSP has a length LX2 along the first direction X and a length LY2 along the second direction Y. The length LX2 is equal to the length LY2. In the illustrated example, the main spacer MSP is formed in a substantially circular shape in plan view, but may be formed in another shape such as a square shape. The length LY2 is larger than the length LY1 of the sub spacer SSP.

As described above, the main spacer MSP is located at the intersection of the scanning line G12 and the signal line S13, and overlaps with the intersection of the light blocking portion BMX2 and the light blocking portion BMY. Therefore, the periphery of the main spacer MSP is shielded by the light shield BMX2 and the light shield BMY. Moreover, since the movable amount of the main spacer MSP is limited when the pressing force is applied to the display panel PNL, the light shielding area around the main spacer MSP can be reduced. As a result, the area of the opening OP per pixel PX can be increased.

On the other hand, the sub-spacer SSP is located between the signal lines S11 and S12 and overlaps the light shield BMX2, but does not overlap the light shield BMY. Therefore, when the sub-spacer SSP has the same length LY2 as the main spacer MSP, it is necessary to extend the width of the light-shielding portion BMX2 along the second direction Y to shield the periphery of the sub-spacer SSP. is there. In the illustrated example, since the length LY1 of the sub spacer SSP is smaller than the length LY2 of the main spacer MSP, it is possible to shield the surroundings of the sub spacer SSP without expanding the light shielding portion BMX2. For example, in the light shield BMX2, the width W11 at the position overlapping the sub spacer SSP is equal to the width W12 at the position overlapping the recess CC2. Each of the widths W11 and W12 here is a length along the second direction Y.

In the configuration example shown in FIG. 7, the recesses CC1 to CC3 correspond to the first recess to the third recess, the length LX1 corresponds to the first length, and the length LY1 corresponds to the second length. The length LY2 corresponds to the third length, the width W11 corresponds to the first width, and the width W12 corresponds to the second width.

FIG. 8 is a sectional view of the display device DSP taken along the line AB shown in FIG. 7. The display device DSP includes a display panel PNL, optical elements OD1 and OD2, and an illumination device IL. The illumination device IL, the optical element OD1, the display panel PNL, and the optical element OD2 are arranged in this order along the third direction Z.

The first substrate SUB1 includes an insulating substrate 10, insulating films 11 to 14, a scanning line G12, a semiconductor layer SC, a signal line S13, common electrodes CE11 and CE12, an alignment film AL1 and the like. The insulating substrate 10 is a light transmissive substrate such as a glass substrate or a flexible resin substrate. The semiconductor layer SC is located between the insulating substrate 10 and the insulating film 11. The semiconductor layer SC is included in the switching element SW shown in FIG. The semiconductor layer SC is formed of, for example, polycrystalline silicon (for example, low temperature polysilicon), but may be formed of amorphous silicon or an oxide semiconductor. The scanning line G12 is located between the insulating films 11 and 12. The signal line S13 is located between the insulating films 12 and 13. The signal line S13 is in contact with the semiconductor layer SC in the through hole CH1 penetrating the insulating films 11 and 12. The scanning line G12 and the signal line S13 are metal materials such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo), tungsten (W), copper (Cu), and chromium (Cr), and these. It is formed of an alloy or the like that is a combination of the above metal materials, and may have a single layer structure or a multilayer structure.

The common electrodes CE11 and CE12 are located between the insulating films 13 and 14. The common electrodes CE11 and CE12 are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The alignment film AL1 is located on the insulating film 14.

The insulating films 11, 12, and 14 are inorganic insulating films formed of an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer structure or a multi-layer structure. Good. The insulating film 13 is, for example, an organic insulating film formed of an organic material such as acrylic resin. The insulating film 13 may be an inorganic insulating film.

The second substrate SUB2 includes an insulating substrate 20, a light shielding layer BM, a color filter layer CF, an overcoat layer OC, an alignment film AL2, a main spacer MSP, and the like. Like the insulating substrate 10, the insulating substrate 20 is a light-transmissive substrate such as a glass substrate or a resin substrate. The light blocking layer BM and the color filter layer CF are located on the side of the insulating substrate 20 that faces the first substrate SUB1. The light blocking layer BM includes the light blocking portions BMX and BMY shown in FIG. 7. The color filter layer CF includes, for example, red, green, and blue color filters. The overcoat layer OC covers the color filter layer CF. The overcoat layer OC is formed of a transparent resin. The alignment film AL2 covers the lower surface OCB of the overcoat layer OC. The alignment films AL1 and AL2 are formed of, for example, a material exhibiting horizontal alignment. The first substrate SUB1 and the second substrate SUB2 described above are arranged so that the alignment films AL1 and AL2 face each other.

The main spacer MSP is provided in contact with the lower surface OCB of the overcoat layer OC. In the illustrated example, a part of the main spacer MSP is covered with the alignment film AL2, but the end portion MSPE is exposed from the alignment film AL2. The end portion MSPE is in contact with the upper surface ALA of the alignment film AL1 between the common electrode CE11 and the common electrode CE12. The entire main spacer MSP may be covered with the alignment film AL2. In this case, the alignment films AL1 and AL2 are interposed between the insulating film 14 and the main spacer MSP. Immediately below the main spacer, the scanning line G12 and the signal line S13 intersect.
In such an example, the upper surface ALA corresponds to the main surface 1A or the first main surface shown in FIG. 1, the lower surface OCB corresponds to the main surface 2B or the second main surface, and the lower surface 10B of the insulating substrate 10 is used. Corresponds to the main surface 1B, and the upper surface 20A of the insulating substrate 20 corresponds to the main surface 2A. Further, the lower surface 20B of the insulating substrate 20 may correspond to the main surface 2B or the second main surface.

The liquid crystal layer LC is located between the first substrate SUB1 and the second substrate SUB2, and is held between the alignment films AL1 and AL2. The liquid crystal layer LC includes liquid crystal molecules LM. The liquid crystal layer LC is made of a positive type (dielectric anisotropy is positive) liquid crystal material or a negative type (dielectric anisotropy is negative) liquid crystal material.

The optical element OD1 including the polarizing plate PL1 is adhered to the lower surface 10B of the insulating substrate 10. The optical element OD2 including the polarizing plate PL2 is adhered to the upper surface 20A of the insulating substrate 20. In addition, the optical element OD1 and the optical element OD2 may include a retardation plate, a scattering layer, an antireflection layer, or the like, if necessary.

In such a display panel PNL, the liquid crystal molecules LM are initially in a predetermined direction between the alignment films AL1 and AL2 in an off state where an electric field is not formed between the pixel electrode PE and the common electrode CE. It is oriented. In such an off state, the light emitted from the illumination device IL toward the display panel PNL is absorbed by the optical element OD1 and the optical element OD2, resulting in a dark display. On the other hand, in the ON state in which the electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecules LM are aligned in a direction different from the initial alignment direction by the electric field, and the alignment direction is controlled by the electric field. .. In such an ON state, part of the light from the illumination device IL is transmitted through the optical element OD1 and the optical element OD2, resulting in bright display.

FIG. 9 is a cross-sectional view of the display device DSP taken along the line C-D shown in FIG. 7. Here, illustration of layers between the insulating substrate 10 and the insulating film 12 is omitted. The first substrate SUB1 further includes signal lines S11 to S14, drain electrodes DE11 to DE13, pixel electrodes PE11 to PE13, and the like. Each of the drain electrodes DE11 to DE13 is an electrode included in the switching element SW shown in FIG. For example, the drain electrode DE12 is electrically connected to the signal line S13 via the semiconductor layer SC shown in FIG.

The signal lines S11 to S14 are all covered with the insulating film 13. The drain electrodes DE11 to DE13 are located on the insulating film 12. The drain electrode DE11 is located between the signal line S11 and the signal line S12, the drain electrode DE12 is located between the signal line S12 and the signal line S13, and the drain electrode DE13 is located between the signal line S13 and the signal line S14. Is located in.

The position P1 indicates the edge of the insulating film 13 on the drain electrode DE11. Positions P2 and P3 indicate the edges of the insulating film 13 on the drain electrode DE12. The position P4 indicates the edge of the insulating film 13 on the drain electrode DE13. The positions P1 and P2 are adjacent to the signal line S12, and the distance between the position P1 and the signal line S12 is smaller than the distance between the signal line S12 and the position P2. The positions P3 and P4 are adjacent to the signal line 13, and the distance between the position P3 and the signal line S13 is equal to the distance between the signal line S13 and the position P4. The length from the position P1 to the position P2 along the first direction X corresponds to the distance D1 shown in FIG. 7. The length from the position P3 to the position P4 along the first direction X corresponds to the distance D2. The distance D1 is smaller than the distance D2.

The insulating film 13 has through holes CH11 to CH13. The through holes CH11 to CH13 penetrate to the drain electrodes DE11 to DE13, respectively. The recesses CC1 to CC3 are formed by through holes CH11 to CH13, respectively. For example, the through hole CH11 is located between the signal lines S11 and S12 and has a width W21. The width W21 here corresponds to the length along the first direction X of the drain electrode DE11 exposed from the insulating film 13. Further, the drain electrode DE11 has a width W22 along the first direction X. The widths W21 and W22 are smaller than the distance D21 along the first direction X between the signal lines S11 and S12. In the illustrated example, the width W21 is smaller than the width W22, but the width W21 may be larger than the width W22. In the through hole CH11, neither of the signal lines S11 and S12 is exposed.

The pixel electrodes PE11 to PE13 are located on the insulating film 14 and covered with the alignment film AL1. The pixel electrodes PE11 to PE13 are formed of the transparent conductive material such as ITO or IZO described above. The pixel electrodes PE11 to PE13 are electrically connected to the drain electrodes DE11 to DE13, respectively. For example, the pixel electrode PE11 is in contact with the drain electrode DE11 in the through hole CH11. Between the drain electrode DE11 and the pixel electrode PE11, another transparent electrode (for example, an electrode formed in the same step as the common electrode CE) or another metal electrode (for example, for reducing the resistance of the common electrode CE) is used. Electrodes formed in the same step as the metal wiring) may be interposed.

In the second substrate SUB2, the sub spacer SSP is provided in contact with the lower surface OCB of the overcoat layer OC, similarly to the main spacer MSP. The sub spacer SSP and the main spacer MSP are formed by using the same material in the same process. Similar to the example shown in FIG. 1, the main spacer MSP has a height H1, the sub spacer SSP has a height H2, and the height H2 is higher than the height H1. The heights H1 and H2 here are defined as lengths along the third direction Z with the lower surface OCB as a reference, with the lower surface OCB of the overcoat layer OC corresponding to the second main surface 2B. is there. As described above, the lower surface 20B of the insulating substrate 20 may correspond to the second main surface 2B. In this case, the height H11 of the main spacer MSP and the height H12 of the sub spacer SSP can be defined as the length along the third direction Z with respect to the lower surface 20B. Even in such a case, the height H12 is higher than the height H11. However, when the height H11 of the main spacer MSP based on the lower surface 20B is compared with the height H2 of the sub spacer SSP based on the lower surface OCB, the height H11 may be higher than the height H2. sell.
A part of the sub spacer SSP is covered with the alignment film AL2. The sub spacer SSP overlaps the recess CC1. The end portion SSPE of the sub spacer SSP is located inside the recess CC1. The edge portion SSPE is separated from the alignment film AL1. That is, the edge portion SSPE is not in contact with the first substrate SUB1. The edge part SSPE is closer to the insulating substrate 10 than the edge part MSPE.

Attention is paid to the positional relationship between the color filter layer CF and the main spacer MSP and the sub spacer SSP. The color filter layer CF includes color filters CF1 to CF3 having different colors. In one example, the color filter CF1 is a green color filter, the color filter CF2 is a red color filter, and the color filter CF3 is a blue color filter. The number of color filters overlapping the sub spacer SSP is smaller than the number of color filters overlapping the main spacer MSP. In the illustrated example, only the single color filter CF1 overlaps the sub spacer SSP, while the multiple color filters CF2 and CF3 overlap the main spacer MSP.

In the configuration example shown in FIG. 9, the insulating substrate 10 corresponds to the first insulating substrate, the insulating substrate 20 corresponds to the second insulating substrate, and the signal lines S11 and S12 correspond to the first signal line and the second signal line. However, the insulating film 13 corresponds to the first organic insulating film, and the overcoat layer OC corresponds to the second organic insulating film.

FIG. 10 is a cross-sectional view showing a modified example of the first substrate SUB1 shown in FIG. As compared with the configuration example shown in FIG. 9, the first substrate SUB1 is different in that the first substrate SUB1 includes metal wirings ML11 and ML12 and an insulating film 15. In the recess CC1, the connection electrodes BE and RE are arranged between the pixel electrode PE11 and the drain electrode DE11. Note that either of the connection electrodes BE and RE may be omitted. The metal wirings ML11 and ML12 are located between the insulating films 13 and 15. The connection electrode BE and the metal wirings ML1 and ML2 are formed of the same metal material. The common electrode CE11 shown in FIG. 8 is located between the insulating films 15 and 14. The connection electrode RE is formed of the same transparent conductive material as the common electrode CE11. In one example, the insulating films 13 and 15 are organic insulating films, but the insulating film 15 may be an inorganic insulating film.

In such a modified example, the recess CC1 is formed by a through hole in the insulating films 13 and 15. When the insulating films 13 and 15 are organic insulating films, a deeper recess CC1 can be formed as compared with the configuration example shown in FIG. Therefore, when a pressing force is applied from the outside, the sub spacer SSP is less likely to be separated from the recess CC1, and the displacement between the first substrate SUB1 and the second substrate SUB2 can be suppressed.

As described above, according to this embodiment, it is possible to provide the display device capable of suppressing the deterioration of the display quality.

Although some embodiments of the present invention have been described, these embodiments are presented as examples, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

DSP...Display device PNL...Display panel MSP...Main spacer SSP...Sub spacer CC...Recessed portion CH...Through hole AL...Alignment film S...Signal line G...Scanning line

Claims (14)

A first substrate having a first main surface and a first recess;
A second main surface facing the first main surface, a main spacer provided on the second main surface and in contact with the first main surface, and a sub-spacer provided on the second main surface and separated from the first substrate. And a second substrate including
A liquid crystal layer located between the first substrate and the second substrate,
The sub-spacer has an end located inside the first recess,
The main spacer has a first height,
The sub spacer has a second height,
The display device, wherein the second height is larger than the first height. The display device according to claim 1, wherein the liquid crystal layer is located between the first recess and the sub spacer. The first recess has a bottom,
The display device according to claim 2, wherein a first distance between the bottom portion and the second main surface is larger than the second height. The display device according to claim 3, wherein a second distance between the first main surface and the second main surface is equal to the first height and smaller than the second height. The main spacer and the sub spacer are arranged in the first direction,
The sub spacer has a first length along the first direction and a second length along a second direction intersecting the first direction,
The display device according to claim 1, wherein the first length is greater than the second length. The main spacer has a third length along the second direction,
The display device according to claim 5, wherein the third length is larger than the second length. The first substrate includes a second recess located between the sub spacer and the main spacer,
The second substrate includes a light shielding portion extending along the first direction,
In a plan view, the light shielding portion overlaps the sub spacer, the second recess, and the main spacer,
The light-shielding portion has a first width at a position overlapping with the sub spacer and a second width at a position overlapping with the second recess,
The display device according to claim 6, wherein the first width is equal to the second width. The first substrate includes a third recess,
The main spacer is located between the second recess and the third recess,
The display device according to claim 7, wherein a distance between the second concave portion and the third concave portion is larger than a distance between the first concave portion and the second concave portion. The first substrate includes a first insulating substrate, and a first organic insulating film located between the first insulating substrate and the liquid crystal layer,
The first organic insulating film has a through hole,
The display device according to claim 1, wherein the first recess is formed by the through hole. The first substrate includes a first signal line, a second signal line, and a drain electrode located between the first signal line and the second signal line,
The first organic insulating film covers the first signal line and the second signal line,
The display device according to claim 9, wherein the through hole penetrates to the drain electrode. The first signal line and the second signal line are arranged at intervals along the first direction,
The through hole is located between the first signal line and the second signal line, and has a width along the first direction,
The display device according to claim 10, wherein the width is smaller than the interval. The second substrate includes a second insulating substrate, a second organic insulating film, and a color filter layer located between the second insulating substrate and the second organic insulating film,
The display device according to claim 1, wherein the color filter layer includes a color filter of a single color that overlaps with the sub spacer and a color filter of a plurality of colors that overlaps with the main spacer. The second substrate includes a second insulating substrate and a second organic insulating film having the second main surface,
The display device according to claim 1, wherein each of the main spacer and the sub spacer has the first height and the second height with respect to the second main surface. The second substrate includes a second insulating substrate having the second main surface,
The display device according to claim 1, wherein each of the main spacer and the sub spacer has the first height and the second height with respect to the second main surface.

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