JP2020096408A - Power source control device - Google Patents

Abstract

To prevent sounding of a switching power source.SOLUTION: A power source control device 200 is a main control part for a switching power source 100 that generates a desired output voltage OUT from an input voltage IN by driving a switch output stage 110, and supplies the output voltage OUT to a load Z. The power source control device includes a load resistance circuit 130 that is connected to the switch output stage 110 separately from the load Z, and a control circuit 140 that, during a light load, repeatedly halts and restarts driving of the switch output stage 110 within a range in which the output voltage OUT does not become less than a target value, and adjusts a load resistance value of the load resistance circuit 130 so as to prevent a switching frequency from becoming less than a lower limit value.SELECTED DRAWING: Figure 1

Description

The invention disclosed in this specification relates to a power supply control device.

2. Description of the Related Art Conventional switching power supplies include a model having an operation mode (so-called light load mode) in which switching pulses are thinned out at a light load to reduce switching loss. In such a light load mode, the switching frequency fluctuates according to the load current, so that depending on the amount of the load current, the switching frequency drops to the human audible band (generally 20 kHz or less), and the input capacitor and the output capacitor. There is a possibility that an unpleasant sound (a so-called noise of a switching power supply) may be generated.

As an example of the related art related to the above, Patent Document 1 can be cited.

JP, 2005-177722, A

As a method for preventing the ringing of the switching power supply, for example, when the ringing prevention function is turned on, the load resistance provided inside the power supply control IC is connected to the switch output stage to constantly increase the load current. It may be possible to intentionally increase the switching frequency. However, in such a conventional method, the load current constantly increases even when it is not necessary to connect the load resistance (=when the switching frequency does not fall within the human audible band even if the load resistance is not connected). Therefore, the efficiency is unnecessarily reduced. Moreover, since the required load current changes depending on the constant of the external element, the degree of freedom in setting the constant of the external element is impaired.

In addition, in the switching power supply of the hysteresis control system, when the noise suppression function is turned on, the lower transistor of the switch output stage is turned on when a certain time has elapsed from the previous switching timing, and the charge stored in the output capacitor is turned on. It is possible to suppress the decrease of the switching frequency by forcibly discharging the. However, such a conventional method is intended only for the switching power supply of the hysteresis control system, and can be directly applied to the switching power supply of the voltage mode control system or the current mode control system having the light load mode. There wasn't.

SUMMARY OF THE INVENTION In view of the above problems found by the inventor of the present application, the invention disclosed in the present specification has as its main object to provide a power supply control device capable of preventing noise of a switching power supply.

The power supply control device disclosed in the present specification is a control body of a switching power supply that drives a switch output stage to generate a desired output voltage from an input voltage and supplies the output voltage to a load. Separately from the load resistance circuit connected to the switch output stage, and in the range where the output voltage does not fall below the target value when the load is light, the drive output of the switch output stage is repeatedly stopped and restored and the switching frequency does not fall below the lower limit. And a control circuit for adjusting the load resistance value of the load resistance circuit (first configuration).

In the power supply control device having the first configuration, the control circuit lowers the load resistance value when the switching frequency is lower than the lower limit value, and when the switching frequency is higher than the lower limit value. A configuration (second configuration) for increasing the load resistance value is preferable.

Further, in the power supply control device having the second configuration, the control circuit measures an interval of switching pulses supplied to the switch output stage, and determines that the interval of the switching pulses is larger than an upper limit value in a current cycle. For example, the load resistance value may be lowered in the next cycle, and if the interval between the switching pulses is smaller than the upper limit value in the current cycle, the load resistance value may be raised in the next cycle (third configuration).

In the power supply control device having the third configuration, the control circuit is configured to adjust the load resistance value using an m-bit (m≧2) load resistance control signal (fourth configuration). Good to do.

In the power supply control device having the fourth configuration, the load resistance circuit is connected in parallel to the switch output stage in m columns, and each of the first to mth bits of the load resistance control signal is connected. The switches are connected between the switches in the first column to the m-th column and the switches in the first column to the m-th column and the ground terminal, which are turned on/off in accordance with the logical value of each bit, and are respectively 2 ^{m−. It is} preferable to have a configuration (fifth configuration) including the resistors in the first column to the m-th column having a resistance value of ^k R (where k=1, 2,..., M).

Further, in the power supply control device having the fourth or fifth configuration, the control circuit increments the load resistance control signal by x (where x≧1) when lowering the load resistance value, and the load resistance value is increased. It is preferable that the load resistance control signal be decremented by 1 when the voltage is pulled up (sixth configuration).

Further, in the power supply control device having the sixth configuration, the control circuit outputs the switching pulse of y generation (where 1<y≦x) when the switch output stage is returned to the drive state (seventh configuration). ) Is recommended.

Further, in the power supply control device having any one of the above first to seventh configurations, the control circuit determines whether to perform the load resistance value adjusting operation based on an enable signal stored in a storage unit. The configuration (8th configuration) is preferable.

Further, the power supply control device having any one of the first to eighth configurations may be integrated in a semiconductor device (ninth configuration).

Further, the switching power supply disclosed in this specification is configured to have a power supply control device having any one of the above first to ninth configurations (tenth configuration).

According to the invention disclosed in this specification, it is possible to provide a power supply control device capable of preventing the switching power supply from ringing.

The figure which shows 1st Embodiment of a switching power supply. The figure which shows one structural example of the control circuit The figure which shows one structural example of a load resistance circuit. The figure which shows the relationship between a load resistance control signal, a switch state, and a load resistance value. Diagram showing the relationship between the load resistance control signal and the load resistance value Diagram showing an example of the configuration of a logic circuit The figure which shows the 1st example of load resistance adjustment operation The figure which shows the 2nd example of load resistance adjustment operation. The figure which shows 2nd Embodiment of switching power supply.

<Switching power supply (first embodiment)>
FIG. 1 is a diagram showing a first embodiment of a switching power supply. The switching power supply 100 of this embodiment is a DC/DC converter that generates a desired output voltage OUT from an input voltage IN and supplies it to a load Z, and includes a switch output stage 110, a feedback voltage generation circuit 120, and a load resistance circuit. It has 130 and a control circuit 140.

The above-described constituent elements are the semiconductor device 200 (so-called power supply control IC) that is the main controlling body of the switching power supply 100, except for some constituent elements (the inductor 113 and the capacitors 114 and 115 in this figure) included in the switch output stage 110. Should be integrated into. In addition to the components described above, the semiconductor device 200 may include any constituent element (such as various protection circuits) as appropriate.

Further, the semiconductor device 200 includes a plurality of external terminals T1 to T3 as means for establishing an electrical connection with the outside of the device.

The switch output stage 110 is a step-down type that drives an inductor current IL by turning on/off an upper switch and a lower switch that are connected so as to form a half bridge to generate a desired output voltage OUT from an input voltage IN. The switch output stage includes an output transistor 111, a synchronous rectification transistor 112, an inductor 113, and capacitors 114 and 115.

The output transistor 111 is an NMOSFET [N-channel type metal oxide semiconductor field effect transistor] that functions as an upper switch of the switch output stage 110. Inside the semiconductor device 200, the drain of the output transistor 111 is connected to the external terminal T1 (=application terminal of the input voltage IN). The source of the output transistor 111 is connected to the external terminal T2 (=application end of the switch voltage SW). The gate of the output transistor 111 is connected to the application terminal of the upper gate signal G1. The output transistor 111 is turned on when the upper gate signal G1 is at high level, and is turned off when the upper gate signal G1 is at low level. When an NMOSFET is used as the output transistor 111, a bootstrap circuit or a charge pump circuit (not shown in the figure) for raising the high level of the upper gate signal G1 to a voltage value higher than the input voltage IN is required.

The synchronous rectification transistor 112 is an NMOSFET that functions as a lower switch of the switch output stage 110. Inside the semiconductor device 200, the drain of the synchronous rectification transistor 112 is connected to the external terminal T2 (=application end of the switch voltage SW). The source of the synchronous rectification transistor 112 is connected to the ground terminal (=application terminal of the ground voltage GND). The gate of the synchronous rectification transistor 112 is connected to the application end of the lower gate signal G2. The synchronous rectification transistor 112 turns on when the lower gate signal G2 is at a high level, and turns off when the lower gate signal G2 is at a low level.

The inductor 113 and the capacitors 114 and 115 are discrete components externally attached to the semiconductor device 200. The first end of the capacitor 114 is connected to the external terminal T1 of the semiconductor device 200. The second end of the capacitor 114 is connected to the ground end. The first end of the inductor 113 is connected to the external terminal T2 of the semiconductor device 200. The second end of the inductor 113 and the first end of the capacitor 115 are connected to the application end of the output voltage OUT and the external terminal T3 of the semiconductor device 200. The second end of the capacitor 115 is connected to the ground end. The capacitor 114 functions as an input capacitor for smoothing the input voltage IN. Further, the inductor 113 and the capacitor 115 function as an LC filter that rectifies and smoothes the switch voltage SW to generate the output voltage OUT.

The output transistor 111 and the synchronous rectification transistor 112 are basically turned on/off complementarily according to the upper gate signal G1 and the lower gate signal G2. By such an on/off operation, a rectangular wave switch voltage SW pulse-driven between the input voltage IN and the ground voltage GND is generated at the first end of the inductor 113. The word "complementary" described above is provided not only when the on/off states of the output transistor 111 and the synchronous rectification transistor 112 are completely reversed, but also when the both transistors are simultaneously turned off (dead time). It should be understood as including cases. Further, when the load is light, both the output transistor 111 and the synchronous rectification transistor 112 may be turned off, and the driving of the switch output stage 110 may be temporarily stopped (details will be described later).

The output format of the switch output stage 110 is not limited to the step-down type described above, but may be a step-up type, a step-up/down type, or an inversion type. Also, the rectification method of the switch output stage 110 is not limited to the synchronous rectification method described above, and a diode rectification method using a rectification diode as the lower switch may be adopted.

Further, the output transistor 111 can be replaced with a PMOSFET. In that case, the above-mentioned bootstrap circuit and charge pump circuit are unnecessary.

Further, the output transistor 111 and the synchronous rectification transistor 112 can be externally attached to the semiconductor device 200. In that case, instead of the external terminal T2, an external terminal for outputting the upper gate signal G1 and the lower gate signal G2 to the outside of the device is required.

When a high voltage is applied to the switch output stage 110, a high withstand voltage element such as a power MOSFET, an IGBT [insulated gate bipolar transistor], or a SiC transistor is used as the output transistor 111 and the synchronous rectification transistor 112. Good.

The feedback voltage generation circuit 120 includes resistors 121 and 122 connected in series between an external terminal T3 (=application end of the output voltage OUT) and a ground end, and responds to the output voltage OUT from a connection node between the both resistors. The feedback voltage FB (=the divided voltage of the output voltage OUT) is output.

If the output voltage OUT is within the input dynamic range of the control circuit 140, the feedback voltage generation circuit 120 may be omitted and the output voltage OUT itself may be directly input to the control circuit 140 as the feedback voltage FB.

The load resistance circuit 130 is a circuit block introduced to realize a quiet light load mode (QLLM [quiet light load mode], details will be described later), and is connected to the switch output stage 110 separately from the load Z. .. Specifically, the load resistance circuit 130 is connected between the external terminal T3 and the ground terminal inside the semiconductor device 200. The load resistance value Rtotal of the load resistance circuit 130 is adjusted according to the m-bit (where m≧2) load resistance control signal QLLM. Since the discharge current ID of the capacitor 115 increases as the load resistance value Rtotal decreases, the output voltage OUT drops sharply. On the contrary, since the discharge current ID decreases as the load resistance value Rtotal increases, the output voltage OUT slows down.

As a basic output feedback control, the control circuit 140 performs pulse width modulation control of the upper gate signal G1 and the lower gate signal G2 so that the feedback voltage FB matches a predetermined target value (reference voltage REF described later). (PWM [pulse width modulation] control) is performed.

In addition, the control circuit 140 repeats driving stoppage and driving recovery of the switch output stage 110 within a range in which the output voltage OUT does not fall below the target value during light load, thereby reducing switching loss in a light load mode (PFM [pulse frequency]. modulation] mode).

Further, in order to realize the silent light load mode described above, the control circuit 140 sets the switching frequency Fsw to the lower limit value FswL (=the frequency at which the switching power supply 100 does not make a noise even in the light load mode, for example, human audible). It has a function of dynamically adjusting the load resistance value Rtotal of the load resistance circuit 130 by using the load resistance control signal QLLM so as not to fall below 21 to 25 kHz (higher than the band) (details will be described later).

<Control circuit>
FIG. 2 is a diagram showing a configuration example of the control circuit 140. The control circuit 140 of this configuration example includes a reference voltage generation circuit 141, an error amplifier 142, a ramp signal generation circuit 143, an oscillator 144, a comparator 145, a logic circuit 146, and a drive circuit 147.

The reference voltage generation circuit 141 generates a reference voltage REF for setting the target value of the output voltage OUT. As the reference voltage generation circuit 141, a DAC [digital-to-analog converter] that converts a digital reference voltage setting signal into an analog reference voltage REF may be used. With such a configuration, it is possible to realize the soft start operation at the time of startup and adjust the output voltage OUT by using the reference voltage setting signal.

The error amplifier 142 generates an error signal ERR according to the difference between the feedback voltage FB applied to the inverting input terminal (−) and the reference voltage REF applied to the non-inverting input terminal (+). The error signal ERR increases when the feedback voltage FB is lower than the reference voltage REF, and decreases when the feedback voltage FB is higher than the reference voltage REF.

The ramp signal generation circuit 143 generates a ramp signal RAMP having a triangular waveform, a sawtooth waveform, or an nth-order slope waveform (for example, n=2) that rises during the ON period Ton of the output transistor 111. The ramp signal RAMP starts rising from a zero value when the output transistor 111 turns on, and is reset to a zero value when the output transistor 111 turns off. Further, by adding the current sense signal corresponding to the inductor current IL to the ramp signal RAMP, output feedback control of the current mode control method can be performed.

The oscillator 144 generates an ON signal ON (=clock signal) which is pulse-driven at a predetermined frequency.

The comparator 145 compares the error signal ERR applied to the non-inverting input terminal (+) with the ramp signal RAMP applied to the inverting input terminal (-) to generate an off signal OFF. The off signal OFF has a high level when the ramp signal RAMP is lower than the error signal ERR, and has a low level when the ramp signal RAMP is higher than the error signal ERR. That is, the pulse generation timing of the OFF signal OFF becomes slower as the error signal ERR becomes higher, and becomes earlier as the error signal ERR becomes lower.

The logic circuit 146 basically generates the upper control signal S1 and the lower control signal S2 according to the ON signal ON and the OFF signal OFF. More specifically, the logic circuit 146 raises the upper control signal S1 to the high level and lowers the lower control signal S2 to the low level when a pulse is generated in the ON signal ON. As a result, the output transistor 111 is turned on and the synchronous rectification transistor 112 is turned off, so that the switch voltage SW rises to a high level (≈VIN). On the other hand, the logic circuit 146 lowers the upper control signal S1 to the low level and raises the lower control signal S2 to the high level when a pulse is generated in the off signal OFF. As a result, the output transistor 111 is turned off and the synchronous rectification transistor 112 is turned on, so that the switch voltage SW falls to a low level (≈GND).

Therefore, the ON control period Ton (=high level period of the switch voltage SW) of the output transistor 111 becomes longer as the OFF signal OFF pulse generation timing becomes longer, and becomes shorter as the OFF signal OFF pulse generation timing becomes shorter. To be done. That is, the on-duty D of the output transistor 111 (=the ratio of the on-period Ton in one cycle) increases as the error signal ERR increases, and decreases as the error signal ERR decreases.

In the light load mode (PFM mode) described above, the logic circuit 146 prevents the switching frequency Fsw from falling below the lower limit value FswL (for example, 21 to 25 kHz) when the drive output of the switch output stage 110 is repeatedly stopped and restored. In addition, it has a function of generating the load resistance control signal QLLM.

More specifically, the logic circuit 146 lowers the load resistance value Rtotal when the switching frequency Fsw is lower than the lower limit value FswL, and raises the load resistance value Rtotal when the switching frequency Fsw is higher than the lower limit value FswL. First, the digital signal value of the load resistance control signal QLLM is determined (details will be described later).

The drive circuit 147 includes an upper driver 147a that receives an input of the upper control signal S1 and generates an upper gate signal G1, and a lower driver 147b that receives an input of the lower control signal S2 and generates a lower gate signal G2. .. A buffer or an inverter can be used as each of the upper driver 147a and the lower driver 147b.

<Load resistance circuit>
FIG. 3 is a diagram showing a configuration example of the load resistance circuit 130. The load circuit 130 in this figure includes switches 131(1) to 131(m) and resistors 132(1) to 132(m).

The first ends of the switches 131(1) to 131(m) are all connected to the external terminal T3. The second ends of the switches 131(1) to 131(m) are connected to the first ends of the resistors 132(1) to 132(m), respectively. The second ends of the resistors 132(1) to 132(m) are all connected to the ground end.

The switches 131(1) to 131(m) are connected in parallel to the external terminal T3 (and by extension, the output end of the switch output stage 110) in m columns, and each of them is connected to the load resistance control signal QLLM. The switches correspond to the switches in the first column to the m-th column that are turned on/off according to the respective logical values of 1 bit (LSB [least significant bit]) to m-th bit (MSB [most significant bit]).

Further, the resistors 132(1) to 132(m) are connected between the switches 131(1) to 131(m) and the ground terminal, and are respectively 2 ^m−k R (where k=1 and 2). ,..., M) corresponding to the resistances of the first column to the m-th column. For example, when the resistors 132(1) to 132(4) are provided corresponding to the 4-bit load resistance control signal QLLM[3:0], the respective resistance values are 8R (=2 ^4-1 R). 4R(=2 ⁴⁻² R), 2R(=2 ⁴⁻³ R), and R(2 ⁴⁻⁴ R).

FIG. 4 shows the relationship between the digital signal values (0d to 15d) of the load resistance control signal QLLM [3:0], the on/off states of the switches 131(1) to (4), and the load resistance value Rtotal. It is a figure.

When QLLM=0d (0000b), all the switches 131(1) to 131(4) are turned off. Therefore, the connection between the external terminal T3 and the ground terminal is cut off. As a result, Rtotal=∞.

When QLLM=1d (0001b), the switch 131(1) is turned on and all the switches 131(2), 131(3) and 131(4) are turned off. Therefore, only the resistor 132(1) is connected between the external terminal T3 and the ground terminal. As a result, Rtotal=8R.

When QLLM=2d (0010b), the switch 131(2) is turned on and all the switches 131(1), 131(3) and 131(4) are turned off. Therefore, only the resistor 132(2) is connected between the external terminal T3 and the ground terminal. As a result, Rtotal=4R.

When QLLM=3d (0011b), the switches 131(1) and 131(2) are turned on and the switches 131(3) and 131(4) are turned off. Therefore, the resistors 132(1) and 132(2) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=8R/3 (≈2.7R).

When QLLM=4d (0100b), the switch 131(3) is turned on and all the switches 131(1), 131(2) and 131(4) are turned off. Therefore, only the resistor 132(3) is connected between the external terminal T3 and the ground terminal. As a result, Rtotal=2R.

When QLLM=5d (0101b), the switches 131(1) and 131(3) are turned on and the switches 131(2) and 131(4) are turned off. Therefore, the resistors 132(1) and 132(3) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=8R/5 (≈1.6R).

When QLLM=6d (0110b), the switches 131(2) and 131(3) are turned on and the switches 131(1) and 131(4) are turned off. Therefore, the resistors 132(2) and 132(3) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=4R/3 (≈1.3R).

When QLLM=7d (0111b), the switches 131(1), 131(2) and 131(3) are turned on and the switch 131(4) is turned off. Therefore, the resistors 132(1), 132(2) and 132(3) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=8R/7 (≈1.1R).

When QLLM=8d (1000b), the switch 131(4) is turned on and all the switches 131(1), 131(2) and 131(3) are turned off. Therefore, only the resistor 132(4) is connected between the external terminal T3 and the ground terminal. As a result, Rtotal=R.

When QLLM=9d (1001b), the switches 131(1) and 131(4) are turned on and the switches 131(2) and 131(3) are turned off. Therefore, the resistors 132(1) and 132(4) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=8R/9 (≈0.9R).

When QLLM=10d (1010b), the switches 131(2) and 131(4) are turned on and the switches 131(1) and 131(3) are turned off. Therefore, the resistors 132(2) and 132(4) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=4R/5 (≈0.8R).

When QLLM=11d (1011b), the switches 131(1), 131(2) and 131(4) are turned on and the switch 131(3) is turned off. Therefore, the resistors 132(1), 132(2), and 132(4) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=8R/11 (≈0.7R).

When QLLM=12d (1100b), the switches 131(3) and 131(4) are turned on and the switches 131(1) and 131(2) are turned off. Therefore, the resistors 132(3) and 132(4) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=2R/3 (≈0.67R).

When QLLM=13d (1101b), the switches 131(1), 131(3) and 131(4) are turned on and the switch 131(2) is turned off. Therefore, the resistors 132(1), 132(3), and 132(4) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=8R/13 (≈0.61R).

When QLLM=14d (1110b), the switches 131(2), 131(3) and 131(4) are turned on and the switch 131(1) is turned off. Therefore, the resistors 132(2), 132(3), and 132(4) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=4R/7 (≈0.57R).

When QLLM=15d (1111b), the switches 131(1) to 131(4) are turned on. Therefore, the resistors 132(1) to 132(4) are connected in parallel between the external terminal T3 and the ground terminal. As a result, Rtotal=8R/15 (≈0.53R).

FIG. 5 is a diagram showing the relationship between the digital signal value (0d to 15d) of the load resistance control signal QLLM [3:0] and the load resistance value Rtotal. As shown in the figure, the load resistance value Rtotal is in inverse proportion to the digital signal value of the load resistance control signal QLLM (Rtotal=8R/QLLM). That is, when the load resistance control signal QLLM is incremented, the load resistance value Rtotal becomes smaller, and conversely, when the load resistance control signal QLLM is decremented, the load resistance value Rtotal becomes larger.

<Logic circuit>
FIG. 6 is a diagram showing a configuration example of the logic circuit 146. The logic circuit 146 of this configuration example includes a pulse generation unit 146a, a counter 146b, and a load resistance adjustment unit 146c.

The pulse generator 146a basically generates the upper control signal S1 and the lower control signal S2 in response to the ON signal ON and the OFF signal OFF, thereby complementarily turning on/off the output transistor 111 and the synchronous rectification transistor 112. Turn off.

However, when the switching power supply 100 shifts to the light load mode, the pulse generation unit 146a may set both the upper control signal S1 and the lower control signal S2 to the low level. In this case, since both the output transistor 111 and the synchronous rectification transistor 112 are turned off, the switch output stage 110 is in the drive stopped state (=the state in which the external terminal T2 is in high impedance).

Regarding the transition to the light load mode, for example, when the output voltage OUT becomes higher than the target value and the feedback voltage FB exceeds the light load transition voltage (=α×VREF, where α>1), It is advisable to shift from the mode (PWM mode) to the light load mode (PFM mode).

In addition, as for the recovery from the light load mode, for example, when the output voltage OUT drops near the target value and the feedback voltage FB falls below the light load release voltage (=β×VREF, where 1<β<α). Moreover, it is good to return from the light load mode to the normal mode.

Of course, the transition condition/return condition of the light load mode is not limited to the above. For example, it may be detected whether the error signal ERR is below the DC offset value of the ramp signal RAMP, or Alternatively, it may be detected whether or not the off signal OFF is fixed to the low level for a predetermined period.

The counter 146b measures the pulse interval of the upper control signal S1 (=corresponding to the switching pulse supplied to the switch output stage 110) and outputs the measurement result as the count output value CNTO. More specifically, the count output value CNTO is incremented by the pulse of the logic clock signal CLK and reset by the pulse of the upper control signal S1.

The load resistance adjusting unit 146c compares the count output value CNTO with a predetermined threshold value TH each time a pulse of the upper control signal S1 is generated, and determines the digital signal value of the load resistance control signal QLLM according to the result.

More specifically, the load resistance adjusting unit 146c increments the load resistance control signal QLLM so as to lower the load resistance value Rtotal if CNTO>TH, and conversely, if CNTO<TH, the load resistance control signal QLLM is increased. The load resistance control signal QLLM is decremented so as to increase the resistance value Rtotal (details will be described later).

In addition, the logic circuit 146 (in particular, the counter 146b and the load resistance adjusting unit 146c) uses the enable signal EN (=a flag signal for switching enable/disable of the silent light load mode) stored in the storage unit 150, It is determined whether or not the adjusting operation of the load resistance value Rtotal is performed at the time of load.

When the silent light load mode is valid (for example, EN=H), the logic clock signal CLK is generated, the switching pulse interval is measured by the counter 146b, and the load resistance control signal QLLM is generated by the load resistance adjusting unit 146c. Is done.

On the other hand, when the silent light load mode is disabled (for example, EN=L), the generation of the logic clock signal CLK is stopped, and the power supply to the counter 146b and the load resistance adjustment unit 146c is cut off. At this time, the digital signal value of the load resistance control signal QLLM becomes 0d, and the load resistance circuit 130 is disconnected from the switch output stage 110.

With such a configuration, it is possible to switch between enabling and disabling of the silent light load mode depending on whether to prioritize noise reduction or efficiency improvement.

As the storage unit 150, it is desirable to use a non-volatile memory such as an OTPROM [one time programmable ROM].

<Load resistance adjustment operation>
FIG. 7 is a diagram showing a first example of the load resistance adjusting operation in the silent light load mode. The output voltage OUT, the upper control signal S1, the count output value CNTO, and the load resistance control signal QLLM[7: 0] and the load resistance value Rtotal are depicted.

When the silent light load mode is valid, the drive stop and drive recovery of the switch output stage 110 are repeated within a range in which the output voltage OUT does not fall below the target value, as in the normal light load mode (PFM mode). On the other hand, the adjustment operation of the load resistance Rtotal using the load resistance control signal QLLM is performed so that the switching frequency Fsw does not fall below the predetermined lower limit value FswL (for example, 21 to 25 kHz). Hereinafter, a specific description will be given with reference to this figure.

At time t1, a pulse is generated in the upper control signal S1 as the output voltage OUT decreases to a predetermined lower limit value OUTL (>target value). As a result, the output voltage OUT once rises and then starts to fall again due to the drive stop of the switch output stage 110. Since QLLM=0d and Rtotal=∞ at this point, the output voltage OUT gradually decreases with a slope according to the load current flowing through the load Z. Further, the count output value CNTO is reset to a zero value by the pulse of the upper control signal S1 and then incremented by the pulse of the logic clock signal CLK.

After that, at time t2, a pulse is generated in the upper control signal S1 as the output voltage OUT is lowered again to the lower limit value OUTL. At this time, the count output value CNTO immediately before the reset exceeds the threshold value TH. This is equivalent to the pulse interval T of the upper control signal S1 being larger than the upper limit value Tmax (=1/Fsw, for example, 40 to 48 μs), and the switching frequency Fsw being lower than the lower limit value FswL. .. In response to this comparison result, the load resistance control signal QLLM is incremented by x (where x≧1 and, for example, x=5). Therefore, QLLM=5d and Rtotal=128R/5.

Thus, if the pulse interval T of the upper control signal S1 is greater than the upper limit value Tmax in the current cycle (=time t1 to t2), the load resistance value Rtotal is lowered in the next cycle (=time t2 to t3). As a result, the output voltage OUT decreases more rapidly than in the current cycle, and the switching frequency Fsw in the next cycle can be increased.

After that, at time t3, CNTO>TH is still satisfied, so QLLM is further incremented by 5. As a result, QLLM=10d and Rtotal=128R/10, so that the output voltage OUT drops more sharply.

On the other hand, at time t4, the count output value CNTO immediately before the reset does not exceed the threshold value TH. This is equivalent to the pulse interval T of the upper control signal S1 being smaller than the upper limit value Tmax, and further, the switching frequency Fsw being higher than the lower limit value FswL. In response to this comparison result, load resistance control signal QLLM is decremented by 1. Therefore, QLLM=9d and Rtotal=128R/9.

Thus, if the pulse interval T of the upper control signal S1 is smaller than the upper limit value Tmax in the current cycle (=time t3 to t4), the load resistance value Rtotal is increased in the next cycle (=time t4 to t5). As a result, the output voltage OUT decreases more slowly than in the current cycle, so that the switching frequency Fsw in the next cycle can be decreased.

Even after time t5, by performing the same load resistance adjusting operation as described above, the reduction of the switching frequency Fsw is appropriately suppressed without impairing the effect of reducing the switching loss in the light load mode (PFM mode) as much as possible, It is possible to prevent noise of the switching power supply 100.

In this figure, the load resistance control signal QLLM is incremented by +5 and decremented by -1. For the reason, refer to the second operation example (FIG. 8) below. The details will be described.

FIG. 8 is a diagram showing a second example of the load resistance adjusting operation in the silent light load mode. The output voltage OUT, the upper control signal S1, the load resistance control signal QLLM[7:0], and The load resistance value Rtotal is depicted.

In the operation example of this figure, when the output voltage OUT decreases to the lower limit value OUTL and the drive of the switch output stage 110 is restored, y is output to the upper control signal S1 (where 1<y≦x, for example y=x. =5) pulses are continuously generated (see time t11 to t12 or time t13 to t14).

Therefore, if it is determined that T>Tmax at the timing when the first pulse is generated in the upper control signal S1, the load resistance control signal QLLM is incremented by x in response to the determination, but thereafter, it is short. When the second pulse to the yth pulse are further generated at the pulse interval (T<Tmax), the load resistance control signal QLLM is decremented by (y-1). As a result, finally QLLM=(x-(y-1))d.

Here, if x<y, even if the load resistance control signal QLLM is incremented by x, it is always returned to a zero value (0d) by the continuous pulse of the upper control signal S1, so that the load resistance value Rtotal is lowered. It becomes impossible to promote the decrease of the output voltage OUT.

On the other hand, if x≧y, the load resistance control signal QLLM can be reliably incremented even if y consecutive pulses are generated in the upper control signal S1. Therefore, it is possible to reduce the load resistance value Rtotal to promote a decrease in the output voltage OUT, and thus it is possible to suppress a decrease in the switching frequency Fsw and prevent the switching power supply 100 from ringing.

The increment amount x of the load resistance control signal QLLM is not limited to x=+5, and it is desirable that the increment value x can be adjusted to an arbitrary value x using the storage unit 150 described above. For example, when the skip mode (y=1) is adopted in the switching power supply 100, x=+1 may be set. On the other hand, the decrement amount of the load resistance control signal QLLM may be fixed at -1 at all times.

<Switching power supply (second embodiment)>
FIG. 9 is a diagram showing a second embodiment of the switching power supply. The switching power supply 100 of the present embodiment is based on the first embodiment (FIG. 1) and has some modifications.

First, as a first modification, the feedback voltage generation circuit 120 is externally attached to the semiconductor device 200. With this change, the external terminal T3 that receives the input of the output voltage OUT is abolished, and the external terminal T4 that receives the input of the feedback voltage FB is newly provided.

Next, as a second modification, the load resistance circuit 130 is provided between the external terminal T2 (=application end of the switch voltage SW) and the ground end with the elimination of the external terminal T3. By changing the connection position as described above, it is possible to obtain the same effect as that of the first embodiment (FIG. 1).

<Other modifications>
Various technical features disclosed in the present specification can be modified in various ways in addition to the above-described embodiment without departing from the spirit of the technical creation. For example, the mutual replacement of the bipolar transistor and the MOS field effect transistor and the logical level inversion of various signals are arbitrary. That is, the above-described embodiments are exemplifications in all respects and should be considered not to be restrictive, and the technical scope of the present invention is not limited to the above-described embodiments, It is to be understood that the meaning equivalent to the range of and the range of all changes included in the range are included.

The power supply control device disclosed in this specification can be used as a control body of a switching power supply mounted in various applications.

100 Switching Power Supply 110 Switch Output Stage 111 Output Transistor 112 Synchronous Rectification Transistor 113 Inductors 114, 115 Capacitor 120 Feedback Voltage Generation Circuit 130 Load Resistor Circuit 131(1) to 131(m) Switch 132(1) to 132(m) Resistor 140 Control circuit 141 Reference voltage generation circuit 142 Error amplifier 143 Lamp signal generation circuit 144 Oscillator 145 Comparator 146 Logic circuit 146a Pulse generation unit 146b Counter 146c Load resistance adjustment unit 147 Drive circuit 147a Upper driver 147b Lower driver 150 Storage unit 200 Semiconductor device ( Power control IC)
T1, T2, T3, T4 External terminal Z load

Claims (10)

A power supply control device that is a main control unit of a switching power supply that generates a desired output voltage from an input voltage by driving a switch output stage and supplies the output to a load,
A load resistance circuit connected to the switch output stage separately from the load,
A control circuit that repeats drive stop and drive recovery of the switch output stage within a range where the output voltage does not fall below a target value at light load and adjusts the load resistance value of the load resistance circuit so that the switching frequency does not fall below a lower limit value. When,
A power supply control device comprising: The control circuit lowers the load resistance value when the switching frequency is lower than the lower limit value, and raises the load resistance value when the switching frequency is higher than the lower limit value. The power supply control device according to. The control circuit measures the interval of the switching pulses supplied to the switch output stage, and if the interval of the switching pulses is greater than the upper limit value in the current cycle, the load resistance value is reduced in the next cycle, and in the current cycle. The power supply control device according to claim 2, wherein the load resistance value is increased in the next cycle if the interval between the switching pulses is smaller than the upper limit value. The power supply control device according to claim 3, wherein the control circuit adjusts the load resistance value using an m-bit (where m≧2) load resistance control signal. The load resistance circuit is
The first column to the m-th column, which are connected in parallel to the switch output stage in m columns and are turned on/off in accordance with the respective logical values of the first bit to the m-th bit of the load resistance control signal. Switch of
The first column to the m-th column, which are connected between the switches in the first column to the m-th column and the ground terminal, and have resistance values of 2 ^m−k R (where k=1, 2,..., M), respectively. resistance of m rows,
The power supply control device according to claim 4, further comprising: The control circuit increments the load resistance control signal by x (where x≧1) when decreasing the load resistance value, and decrements the load resistance control signal by 1 when increasing the load resistance value. The power supply control device according to claim 4 or 5. 7. The power supply control device according to claim 6, wherein the control circuit outputs the switching pulse of y emission (where 1<y≦x) when the switch output stage is returned to the driving state. The control circuit determines whether to perform an adjustment operation of the load resistance value based on an enable signal stored in a storage unit. Power controller. 9. The power supply control device according to claim 1, wherein the power supply control device is integrated in a semiconductor device. A switching power supply comprising the power supply control device according to claim 1.

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