JP2020087053A - Semiconductor device - Google Patents

Abstract

To perform controlling for preventing failure of a system using DRAM access and requiring real-time processing.SOLUTION: A semiconductor device comprises first and second DRAMs, first and second DRAM-PHYs, a temperature sensor, a memory controller, and first and second masters. The first and second masters can access the first and second DRAM-PHYs. The memory controller performs access control to each DRAM-PHY from each master. When a temperature change in the semiconductor device is detected, the memory controller issues a retraining instruction to the first and second DRAMs, and the first master gets priority access to the first DRAM, and the second master do so to the second DRAM. In a period where the first DRAM cannot access, the first master sends access request to the second DRAM. When the first and second masters simultaneously send access request to the second DRAM, the memory controller gives priority to the request from the first master.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device, and particularly to memory access control of the semiconductor device.

A DRAM (Dynamic Random Access Memory), which is a memory generally used in a semiconductor device, has a period in which it cannot be regularly accessed due to its characteristics.

For example, in DRAM, it is necessary to periodically perform an operation of refreshing in order to prevent the stored contents from being gradually lost due to a leak current. DRAM access may not be possible during the refresh period.

Further, when the temperature of the DRAM changes, the operation timing of the DRAM may change due to a change in the characteristics of the transistor, and the DRAM may malfunction. To prevent this, retraining timing must be regularly adjusted. should not. DRAM access may not be possible during this retraining period.

In order to solve this problem, Japanese Patent Laid-Open No. 2004-242242 discloses a technique for monitoring the temperature of DRAM and changing the refresh interval according to the temperature so as not to increase the inaccessible period.

JP, 2016-48592, A

However, the technique described in Patent Document 1 does not consider that real-time processing may not be in time because the period during which the DRAM cannot be accessed is absolutely generated. For example, processing that requires real-time processing, such as moving image recording processing and display processing in an imaging device, may be delayed in time due to a period during which DRAM access is not possible, and the system may fail.

Therefore, it is an object of the present invention to perform memory access control in a system using DRAM access so as not to break down a system that requires real-time processing.

In order to achieve the above object, the semiconductor device according to the present invention,
A semiconductor device comprising a first DRAM, a second DRAM, a first DRAM-PHY, a second DRAM-PHY, a temperature sensor, a memory controller, a first master, and a second master. And the second master are masters capable of accessing the first DRAM-PHY and the second DRAM-PHY, and the memory controller controls access from each master to each DRAM-PHY and uses a temperature sensor. When the temperature change of the semiconductor device is detected, the memory controller issues a retraining instruction to the first DRAM and the second DRAM, and the first master preferentially accesses the first DRAM. The second DRAM requests access to the second DRAM during the period when the first DRAM is inaccessible, and the second master preferentially accesses the second DRAM. If there is an access request from the master of the second DRAM to the second DRAM, its own access processing is delayed, and if there is an access request from the first master and the second master to the second DRAM at the same time, the memory controller The feature is that the request from one master is prioritized.

According to the semiconductor device of the present invention, in a system using DRAM access, it is possible to perform memory access control that does not break down a system that requires real-time processing.

Overall view of a semiconductor device 100 according to a first embodiment of the present invention The figure which showed the temperature change of the semiconductor device 100, and the relationship of the retraining interval. Diagram showing access to each DRAM of the semiconductor device 100

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment FIG. 1 is a diagram of a semiconductor device according to a first embodiment of the present invention.

100 is a semiconductor device in the present invention. The semiconductor device 100 includes a CPU 101, a memory controller 102, a master 103 (first master), a master 104 (second master), a DRAM-PHY 105, a DRAM-PHY 106, and a temperature sensor 107. The semiconductor device 100 is connected to the DRAM 110 and the DRAM 120, which are external memories, and uses them as the main memory on the system.

The CPU 101 is a control device that controls the entire semiconductor device 100. The CPU 101 controls each circuit block by accessing the registers of each circuit block such as the master 103, the master 104, the memory controller 102, and the temperature sensor 107.

The masters 103 and 104 are functional blocks that serve as masters for the DRAMs 110 and 120 that are external memories. The master 103 is a circuit such as a moving picture coding circuit, a moving picture recording circuit, and a display circuit that requires real-time processing and requires a lot of processing. The master 104 is a circuit, such as a lens control circuit and a still image developing circuit, which does not require real-time property as compared with the master 103. Although only two masters 103 and 104 are shown here, there are many other masters not shown.

102 is a memory controller. The memory controller 102 accepts memory access requests from many masters such as the masters 103 and 104, and makes a memory access request to the DRAM 110 or 120 via the DRAM-PHY 105 or 106. At this time, the memory controller 102 arbitrates the access request from each master and accesses each DRAM via each DRAM-PHY in accordance with a predetermined priority order.

110 and 120 are external DRAMs. The DRAMs 110 and 120 write or read data according to the access requests from the corresponding DRAM-PHYs 105 and 106, respectively. Although two DRAMs are used here, three or more DRAMs may exist. In that case, it is assumed that a separate independent DRAM-PHY is connected to the memory controller 102.

Note that FIG. 1 is a schematic diagram, and the actual size and positional relationship between each master and each DRAM-PHY do not necessarily match this figure, but the relative positional relationship is that the master 103 and the DRAM-PHY 105 are close to each other. , The master 104 and the DRAM-PHY 106 are arranged in the vicinity. Therefore, when the master 103 accesses the DRAM-PHY 105, it can be accessed with a small latency, but when the master 103 accesses the DRAM-PHY 106, a large latency occurs. Similarly, when the master 104 accesses the DRAM-PHY 106, it can be accessed with a small latency, but when the master 104 accesses the DRAM-PHY 105, a large latency occurs.

107 is a temperature sensor. The temperature sensor 107 periodically measures the temperature of the semiconductor device 100 at certain fixed intervals. The CPU 101 constantly monitors the temperature information obtained by the temperature sensor 107, and instructs the memory controller 102 to perform control such as execution/non-execution of retraining and change of retraining interval according to the temperature change information. ..

FIG. 2 is a diagram showing the relationship between the time change of the temperature of the semiconductor device 100 and the retraining interval.

Until time t100, the semiconductor device 100 is in a steady operation, and the temperature of the semiconductor device 100 hardly changes. After time t100, it is assumed that the operation mode of the semiconductor device 100 is changed and switched to a mode in which a large amount of power is consumed and heat is generated, such as a moving image recording mode. After the operation mode is switched, the temperature change is large until time t200, and the slope is equal to or more than a certain constant value K until time t200. It is also assumed that after time t200, the temperature change also becomes gentle and the slope becomes less than a certain value K. Further, it is assumed that after time t300, the steady state is reached and the temperature change is almost eliminated.

In the section up to time t100, since there is almost no temperature change, the characteristics of the transistor hardly change, and retraining is not necessary. Therefore, the memory controller 102 does not issue a retraining execution instruction to the PHYs 105 and 106, and retraining is not performed in the DRAMs 110 and 120.

In the section from the time t100 to the time t200, the temperature change is the slope K or more, and the retraining is performed at the interval of T1. Since this section is a section in which the temperature change is large, T1 is a relatively small time interval and frequently requires retraining. The memory controller 102 issues a retraining instruction to the PHYs 105 and 106 at intervals of T1 to retrain the DRAMs 110 and 120.

Further, in the section from time t200 to t300 where the inclination is K or less, retraining is performed at intervals of T2 where T2>T1. Since the temperature change is gentle in this section, it is not necessary to perform retraining at intervals of about T1, and retraining is performed at intervals of T2 larger than T1. Furthermore, after time t300, there is almost no change in temperature, and retraining is also stopped.

As described above, the retraining interval becomes appropriate according to the temperature change of the semiconductor device 100, and the period during which the DRAM cannot be accessed does not unnecessarily increase. Further, if the DRAM 110 and the DRAM 120 start retraining at the same time, a period in which the DRAM cannot be accessed occurs. Therefore, the retraining of the DRAM 110 and the DRAM 120 is executed with a timing shift as shown in FIG. For example, in the period from time t100 to t200, the retraining timing of the DRAMs 110 and 120 is shifted by T1/2 time, and in the period from time t200 to t300, the retraining timing of the DRAMs 110 and 120 is shifted by T2/2 time. ..

Even when the number of DRAMs is three or more, the memory controller 102 controls the retraining timings of all the DRAMs to be different. Therefore, when looking at all the DRAMs in total, there is no period during which the DRAMs cannot be accessed.

Next, the access amount of the DRAM 110 and the DRAM 120 will be described with reference to FIG. As the time axis in FIG. 3, for example, the interval between t100 and t200 in FIG. 2 is enlarged.

FIG. 3A is a graph showing the access amount to the DRAM 110 with respect to the time axis. The area indicated by A1 in FIG. 3A indicates access to the DRAM 110 of the master 103. The master 103 constantly requires an access amount of A on the vertical axis of the graph. The master 103 basically accesses the DRAM 110 that can be accessed with low latency.

The blank periods at times t1 to t2 and t7 to t8 in FIG. 3A represent the retraining period of the DRAM 110. During this time, each master cannot access the DRAM 110.

FIG. 3B is a graph showing the access amount to the DRAM 120 with respect to the time axis. Areas B1 to B3 in FIG. 3B indicate access to the DRAM 120 of the master 104. The master 104 constantly requires an access amount of B on the vertical axis of the graph. The master 104 basically accesses the DRAM 120 that can be accessed with low latency.

The area indicated by A2 in FIG. 3B indicates access to the DRAM 120 of the master 103. Originally, the master 103 accesses the DRAM 110 which can be accessed with a small latency, but cannot access the DRAM 110 at times t1 to t2 and t7 to t8, and therefore issues an interrupt access request to the DRAM 120.

When there is an interrupt access request from the master 103 that requires real-time processing to the DRAM 120, the memory controller 102 controls so that the master 103 has priority over the master 104 that originally needed to access the DRAM 120.

At time t1 to t2, the master 104, which originally needed to access the DRAM 120, gives its original access backward from time t2 to t3 by prioritizing the interrupt access of the master 103 (area B2). ).

Further, the blank periods at times t4 to t5 and t10 to t11 in FIG. 3B represent the retraining period of the DRAM 120. During this time, each master cannot access the DRAM 120. During this period, the master 104, which originally needs access to the DRAM 120, delays the access time to t5 to t6 (area B3).

With the above configuration, it is possible to perform memory access control that does not break down a system that requires real-time processing in a configuration including multiple masters and multiple DRAMs.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes can be made within the scope of the gist thereof.

100 semiconductor device, 101 CPU, 102 memory controller,
103 master, 104 master, 105 DRAM-PHY,
106 DRAM-PHY, 107 temperature sensor, 110 DRAM,
120 DRAM

Claims (4)

A semiconductor device comprising: a first DRAM, a second DRAM, a first DRAM-PHY, a second DRAM-PHY, a temperature sensor, a memory controller, a first master, and a second master.
The first master and the second master are masters capable of accessing the first DRAM-PHY and the second DRAM-PHY, and the memory controller controls access from each master to each DRAM-PHY,
When the temperature sensor detects a temperature change in the semiconductor device, the memory controller issues a retraining instruction to the first DRAM and the second DRAM,
The first master preferentially accesses the first DRAM, but requests access to the second DRAM while the first DRAM is inaccessible,
The second master preferentially accesses the second DRAM, but performs its own access processing during the period when the second DRAM is inaccessible and when there is an access request from the first master to the second DRAM. Rearward,
A semiconductor device, wherein the memory controller gives priority to the request from the first master when the first master and the second master request access to the second DRAM at the same time. The semiconductor device according to claim 1, wherein the first master is a circuit that requires real-time processing, and the second memory master is a circuit that does not require real-time processing. The memory controller narrows the retraining interval when the temperature change detected by the temperature sensor is larger than a certain value, and widens the retraining interval when the temperature change detected by the temperature sensor is less than a certain value. Alternatively, the semiconductor device is stopped, or the semiconductor device according to claim 1 or 2. 4. The semiconductor device according to claim 1, wherein the memory controller disperses the retraining time so that the retraining timings of the respective DRAMs do not overlap.