JP2020083671A5 - - Google Patents

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JP2020083671A5
JP2020083671A5 JP2018215724A JP2018215724A JP2020083671A5 JP 2020083671 A5 JP2020083671 A5 JP 2020083671A5 JP 2018215724 A JP2018215724 A JP 2018215724A JP 2018215724 A JP2018215724 A JP 2018215724A JP 2020083671 A5 JP2020083671 A5 JP 2020083671A5
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Prior art keywords
contrast ratio
huge
downfall
defect
removing method
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JP2018215724A
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JP7204436B2 (en
JP2020083671A (en
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Claims (7)

SiCエピタキシャルウェハのヒュージダウンフォールを識別する、識別工程と、前記識別工程で識別したヒュージダウンフォールを除去する、除去工程と、を有し、
前記識別工程は、SiCエピタキシャルウェハ表面の三角形の欠陥を特定する、第1工程と、前記三角形の欠陥のうち、ヒュージダウンフォールを有する欠陥を抽出する、第2工程と、を有し、
前記第2工程は、
前記三角形の欠陥の3辺のそれぞれの基準面に対する第1コントラスト比、第2コントラスト比、及び第3コントラスト比を求める、コントラスト比決定工程と、
前記第1コントラスト比、前記第2コントラスト比、及び前記第3コントラスト比と比較して、前記基準面に対するコントラスト比が大きい又は小さい特定部分をヒュージダウンフォールとして検出する、ヒュージダウンフォール検出工程と、を有し、
前記特定部分は、
コントラスト比が、前記第1コントラスト比、前記第2コントラスト比、及び前記第3コントラスト比のうちの1より大きな値を示すいずれのコントラスト比よりも5%以上大きい、又は、前記第1コントラスト比、前記第2コントラスト比、及び前記第3コントラスト比のうちの1より小さい値を示すいずれのコントラスト比よりも5%以上小さい場合に、ヒュージダウンフォールとして検出する、欠陥除去方法。
It has an identification step of identifying the huge downfall of the SiC epitaxial wafer and a removing step of removing the huge downfall identified in the identification step.
The identification step includes a first step of identifying a triangular defect on the surface of the SiC epitaxial wafer, and a second step of extracting a defect having a huge downfall from the triangular defects.
The second step is
A contrast ratio determination step of obtaining a first contrast ratio, a second contrast ratio, and a third contrast ratio with respect to a reference plane of each of the three sides of the defect of the triangle.
A huge downfall detection step of detecting a specific portion having a large or small contrast ratio with respect to the reference plane as a huge downfall as compared with the first contrast ratio, the second contrast ratio, and the third contrast ratio. Have,
The specific part is
The contrast ratio is 5% or more larger than any of the contrast ratios showing a value larger than 1 of the first contrast ratio, the second contrast ratio, and the third contrast ratio, or the first contrast ratio. the second contrast ratio, and if more than 5% smaller than any of contrast ratio shows a value of less than one of said third contrast ratio is detected as huge Downfall, defect removal method.
前記除去工程は、モース硬度が5以上のプローブを、ヒュージダウンフォールに押し付ける、請求項1に記載の欠陥除去方法。 The defect removing method according to claim 1, wherein the removing step presses a probe having a Mohs hardness of 5 or more against a huge downfall. 前記除去工程は、レーザー又はビームをヒュージダウンフォールに照射する、請求項1に記載の欠陥除去方法。 The defect removing method according to claim 1, wherein the removing step irradiates a huge downfall with a laser or a beam. 前記除去工程は、ヒュージダウンフォールにガス及び液体及び/または固体を同時に噴射する、請求項1に記載の欠陥除去方法。 The defect removing method according to claim 1, wherein the removing step is to simultaneously inject a gas and a liquid and / or a solid into the huge downfall. 前記除去工程は、前記ヒュージダウンフォール付近に対向電極を設置し、放電または電気分解を行う、請求項1に記載の欠陥除去方法。 The defect removing method according to claim 1, wherein in the removing step, a counter electrode is installed in the vicinity of the huge downfall and discharge or electrolysis is performed. 前記除去工程は、ヒュージダウンフォールをウェットエッチングする、請求項1に記載の欠陥除去方法。 The defect removing method according to claim 1, wherein the removing step is wet etching of the huge down fall. SiCウェハ上にエピタキシャル膜を成膜する工程と、
請求項1から6のいずれかに記載の欠陥除去方法を行う工程と、を有する、SiCエピタキシャルウェハの製造方法。
The process of forming an epitaxial film on a SiC wafer and
A method for manufacturing a SiC epitaxial wafer, comprising the step of performing the defect removing method according to any one of claims 1 to 6.
JP2018215724A 2018-11-16 2018-11-16 Defect removal method and SiC epitaxial wafer manufacturing method Active JP7204436B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2018215724A JP7204436B2 (en) 2018-11-16 2018-11-16 Defect removal method and SiC epitaxial wafer manufacturing method

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Application Number Priority Date Filing Date Title
JP2018215724A JP7204436B2 (en) 2018-11-16 2018-11-16 Defect removal method and SiC epitaxial wafer manufacturing method

Publications (3)

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JP2020083671A JP2020083671A (en) 2020-06-04
JP2020083671A5 true JP2020083671A5 (en) 2021-12-23
JP7204436B2 JP7204436B2 (en) 2023-01-16

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JP2018215724A Active JP7204436B2 (en) 2018-11-16 2018-11-16 Defect removal method and SiC epitaxial wafer manufacturing method

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230261057A1 (en) * 2020-07-02 2023-08-17 Sumitomo Electric Industries, Ltd. Silicon carbide epitaxial substrate and method of manufacturing silicon carbide epitaxial substrate
JPWO2022190458A1 (en) * 2021-03-12 2022-09-15

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4716148B1 (en) 2010-03-30 2011-07-06 レーザーテック株式会社 Inspection apparatus, defect classification method, and defect detection method
JP6493690B2 (en) 2016-08-31 2019-04-03 昭和電工株式会社 SiC epitaxial wafer, manufacturing method thereof, large pit defect detection method, defect identification method
JP6459132B2 (en) 2016-08-31 2019-01-30 昭和電工株式会社 SiC epitaxial wafer, manufacturing method thereof, and defect identification method
JP6820191B2 (en) 2016-12-14 2021-01-27 昭和電工株式会社 Evaluation method for semiconductor wafers

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