JP2020081518A - Game machine - Google Patents

Abstract

To provide a game machine capable of performing more improved image performance control.SOLUTION: While first means (ST1, ST2) for securing a pair of two-dimensional spaces having a horizontal size determined based on the number of lateral pixels and a predetermined vertical size of a display device in one of storage areas secured in a memory circuit and for granting a pair of index numbers for identifying the pair of two-dimensional spaces function at the time of initial processing after power is turned on, and second means (ST6) for identifying a two-dimensional space that a display circuit 74 should read from among the pair of two-dimensional spaces and third means (ST7, ST8) for executing creation processing and issuing processing of a display list are configured so as to repeatedly function at the time of steady processing after completion of initial setting processing, execution of the second means and the third means is avoided during an operation period not satisfying a predetermined operation start condition.SELECTED DRAWING: Figure 10

Description

The present invention relates to a gaming machine that performs a lottery process resulting from a game operation and executes an image effect corresponding to the lottery result, and particularly to a gaming machine that can stably perform a powerful image effect.

A ball game machine such as a pachinko machine is equipped with a symbol starting opening provided on the game board, a symbol display section for displaying a series of symbol variation modes by a plurality of display symbols, and a large winning opening for opening/closing the opening/closing plate. Is configured. Then, when the detection switch provided in the symbol starting port detects the passage of the game ball, the winning state is established, and after the game ball is paid out as the prize ball, the display symbol is changed in the symbol display portion for a predetermined time. After that, when the symbols are stopped in a predetermined mode such as 7/7/7, a big hit state occurs, and the special winning opening is repeatedly opened to generate a game state that is advantageous to the player.

Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball is won at the symbol start opening, and the above-mentioned symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is a winning state, a production operation called a reach action or the like is executed for about 20 seconds, and then special symbols are arranged. On the other hand, the same reach action may be executed even in the case of the lost state, and in this case, the player pays close attention to the big hit state and pays close attention to the transition of the effect operation. Then, at the end of the symbol changing operation, if the predetermined symbols are aligned with the stop line, the player is guaranteed to be in the big hit state.

JP, 2017-0933633, A JP, 2017-093632, A JP, 2016-159030, A JP, 2016-159029, A

In this type of gaming machine, there is a high demand for making various effects complicated and abundant, especially for image effects. Therefore, the applicant has made various proposals (Cited Documents 1 to 4), but it is desired to further enhance the image effect and improve the image effect control.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine capable of executing improved image production control.

In order to achieve the above object, a gaming machine according to the present invention has an image control means for issuing a display list for specifying a display screen of a display device, a predetermined image data based on the display list, and a predetermined buffer area ( For example, the image generation means for completing and outputting to the frame buffer FBa) is configured, and the image generation means completes the image data specified by the display list in the buffer area; A display circuit for reading and outputting image data in the buffer area and a memory circuit (for example, a built-in VRAM 71) in which the buffer area is arranged are configured to secure a plurality of storage areas in the memory circuit. A pair of two-dimensional spaces having a horizontal size determined based on the number of pixels in the horizontal direction of the display device and a predetermined vertical size are secured in any of the secured storage areas, and the pair of two-dimensional spaces is specified. The first means for giving a pair of index numbers (for example, ST1 and ST2 in FIG. 10) functions at the time of initial processing after power-on, and identifies the two-dimensional space to be read by the display circuit from the pair of two-dimensional spaces. After the second setting means (for example, ST6 in FIG. 10) and the third means (for example, ST7, ST8 in FIG. 10) for executing the display list creation process and the issuing process are completed, During steady-state processing, it is configured to function repeatedly every predetermined operation cycle, while it is configured to avoid execution of the second means and the third means in operation cycles that do not satisfy the predetermined operation start condition. .

The present invention corresponds to the skip operation of ST5 of FIG. 10 or ST5 of FIG. 15 in the embodiment, for example. Therefore, it is preferable that the internal circuits of the image control means and the image generation means are reset to the initial state when the number of consecutive times when the execution of the third means and the fourth means is avoided exceeds a predetermined value. . Further, it is more preferable that the image effect executed on the display device and the sound effect in which the speaker functions are reset to the initial state in response to the internal circuit being reset to the initial state.

According to the present invention described above, even in the case of advanced image effects, the occurrence of abnormal operation is prevented in advance, so that a smooth and appropriate image control operation can be executed.

It is a perspective view showing a pachinko machine of the present embodiment. It is a front view which shows the game area of the game machine of FIG. It is a block diagram which shows the whole circuit structure of the game machine of FIG. FIG. 2 is a block diagram showing the circuit configuration of an effect control unit in the gaming machine of FIG. 1 in a little more detail. It is drawing explaining the compound chip which comprises an effect control part. 5 is a diagram illustrating a cycle steal transfer operation and a pipeline transfer for the DMAC. It is a figure explaining an index space, an index table, a virtual drawing space, and a drawing area. It is a block diagram which described the internal structure of a data transfer circuit with the related circuit structure. It is the block diagram which described the internal structure of a display circuit with the related circuit structure. It is the flowchart which explains the control operation of production control CPU63 when the preloader is not used. 7 is a diagram illustrating a configuration of a display list. It is a flow chart which shows DL issue processing which issues display list DL. 13 is a flowchart illustrating an operation when the DMAC is involved in the operation of FIG. 12. 14 is a flowchart illustrating an operation following the process of FIG. 13. It is the flowchart which explains the control operation of production control CPU63 when the preloader is used. 16 is a flowchart illustrating a part of FIG. 15. 16 is a flowchart illustrating another part of FIG. 15. 9 is a time chart showing the operation of each part of the VDP for an embodiment that does not use a preloader. 9 is a time chart showing the operation of each unit of the VDP for the embodiment using the preloader. It is a block diagram which shows the whole circuit structure about another Example. FIG. 21 is a block diagram showing a part of FIG. 20 in some detail. It is a flow chart explaining the contents of operation about another example. It is drawing explaining another Example.

Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of this embodiment. The pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably attached to an island structure, and a front frame 3 that is pivotally mounted to be openable and closable via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, a total of three speakers are arranged at the upper left and right positions and the lower side of the glass door 6. The two speakers arranged in the upper part are configured to output the sounds of the left and right channels R and L, respectively, and the lower speaker is configured to output the bass sound.

The upper plate 8 for storing the game balls for firing is mounted on the front plate 7, and the lower plate 9 for storing the game balls overflowing or extracted from the upper plate 8 and the launch handle are mounted on the lower portion of the front frame 3. And 10 are provided. The firing handle 10 is interlocked with a firing motor, and a game ball is fired by a batting mallet that operates according to the rotation angle of the firing handle 10.

A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 is not functioning normally, but when the game state is the button chance state, the built-in lamp is turned on and it can be operated. The button chance state is a game state provided as needed.

In addition, below the chance button 11, a rotary switch type volume switch VLSW is arranged, and when the player operates the volume switch VLSW, from a silent level (=0) to a maximum level (=7), The speaker volume can be adjusted in 8 steps. The volume of the speaker is initially set by a setting switch (not shown) that can be operated only by a staff member, and the initial setting volume is maintained unless the player operates the volume switch VLSW. Further, the abnormality notification sound for notifying that an abnormal situation has occurred is emitted at the maximum volume regardless of the initial volume set by the staff member or the volume set by the player.

On the right side of the upper plate 8, there is provided an operation panel 12 for operation of lending a ball to a card type ball lending machine, a frequency display section for displaying the remaining amount of the card by a three-digit number, and a ball for a predetermined amount of game balls. A ball lending switch for instructing lending and a return switch for instructing the return of the card at the end of the game are provided.

As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 composed of an outer rail and an inner rail made of metal is provided in an annular shape, and a central opening HO is provided substantially at the center thereof. A movable effect body (not shown) is housed under the central opening HO in a concealed state. When the movable notice effect is performed, the movable effect body rises to be in an exposed state, so that a predetermined reliability is obtained. A notice production is realized. Here, the advance notice effect is an effect that informs uncertainly that a big hit state advantageous to the player is coming, and the reliability of the notice effect means a probability that the big hit state is brought.

In the central opening HO, a main display device DS1 including a large-sized (for example, horizontal 1280×vertical 1024 pixels) liquid crystal color display (LCD) is arranged, and on the right side of the main display device DS1, a small (for example, horizontal) A movable sub-display device DS2 composed of a liquid crystal color display of 480×800 pixels) is arranged. The main display device DS1 is a device that variably displays a specific symbol related to the big hit state and also displays a background image and various characters in an animation manner. This display device DS1 has special symbol display portions Da to Dc in the central portion and a normal symbol display portion 19 in the upper right portion. Then, in the special symbol display portions Da to Dc, a reach effect that is expected to invite a big hit state may be executed, and in the special symbol display portions Da to Dc and around it, an appropriate notice effect or the like is executed.

The sub display device DS2 normally displays image information in a stationary state in which its display screen is tilted at an angle that is easy for the player to see. However, at the time of a predetermined notice production, the inclination angle is changed to an angle that is easy for the player to see, while moving to the left side in the figure, a predetermined notice image is displayed.

That is, the sub display device DS2 of the embodiment functions not only as a display device but also as a movable effect body that executes a notice effect. Here, the notice effect by the sub display device DS2 is set to have a high degree of reliability, and the player pays attention to the moving operation of the sub display device DS2 with great expectation.

By the way, in the game area where the game balls fall and move, the first symbol starting opening 15a, the second symbol starting opening 15b, the first big winning opening 16a, the second big winning opening 16b, the normal winning opening 17, and the gate 18 Are arranged. Each of these winning openings 15 to 18 has a detection switch inside, so that the passage of a game ball can be detected.

At the upper part of the first symbol starting port 15a, after the game ball that has entered from the introduction port IN moves in the shape of a seesaw or roulette wheel, the production stage 14 configured to be able to win the first symbol starting port 15 is arranged. There is. Then, when a game ball wins the first symbol starting port 15, the changing operation of the special symbol display portions Da to Dc is started.

The second symbol starting port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws, and when the stop symbol after the change of the normal symbol display unit 19 displays a hit symbol, a predetermined symbol is given. The opening/closing claw is opened only for a time or until a predetermined number of game balls are detected.

In addition, the normal symbol display portion 19 is for displaying a normal symbol, and when a game ball that has passed through the gate 18 is detected, the normal symbol changes for a predetermined time and is extracted at the time when the game ball passes through the gate 18. Display a stop symbol determined by the selected random number for lottery and stop.

The first special winning opening 16a is configured to include a slide board that moves forward and backward, and the second special winning opening 16b is configured to include an opening/closing plate that is pivotally supported at its lower end and opens forward. .. The operations of the first big winning opening 16a and the second big winning opening 16b are not particularly limited, but in this embodiment, the first big winning opening 16a corresponds to the first symbol starting opening 15a, and the second big winning opening. 16b is constituted so as to correspond to the first symbol starting port 15b.

That is, when the game ball wins the first symbol starting port 15a, the variation operation of the special symbol display portions Da to Dc is started, and after that, when the predetermined jackpot symbols are aligned with the special symbol display portions Da to Dc, the first jackpot. The barrel special game is started, and the slide board of the first big winning opening 16a is opened forward to facilitate the winning of the game ball.

On the other hand, as a result of the variation operation started by the winning of the game ball to the second symbol starting port 15b, when the predetermined big hit symbols are aligned with the special symbol display portions Da to Dc, the second big hit special game is started, The opening/closing plate of the two major winning openings 16b is opened to facilitate the winning of game balls. The game value of the special game (big hit state) is variously different according to the big hit symbols to be arranged, but which game value is given is based on the lottery result according to the winning timing of the game ball in advance. It is determined.

In a typical big hit state, after the opening/closing plate of the special winning opening 16 is opened, the opening/closing plate is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls are won. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display portions Da to Dc is a specific symbol among the special symbols, a privilege that the game after the special game is in the high probability state (probability change state) is provided. Granted.

FIG. 3 is a block diagram showing the entire circuit configuration of a pachinko machine GM that realizes each of the above-described operations, and FIG. 4A shows a part of it in detail.

As shown in FIG. 3, the pachinko machine GM has a power supply board 20 which receives various direct current voltages and various power supply abnormal signals ABN1 and ABN2 in response to AC24V, and a main control board 21 which centrally controls a game control operation. , A production interface board 22 on which a circuit element SND for voice production is mounted, and a production control board 23 which integrally executes lamp production, voice production, and image production based on a control command CMD received from the main control board 21. Based on the liquid crystal interface board 24 located between the effect control board 23 and the display devices DS1 and DS2, and the control command CMD' received from the main control board 21, the payout motor M is controlled to pay out the game ball. The payout control board 25 and a launch control board 26 that launches a game ball in response to a player's operation are mainly configured.

In the case of the present embodiment, the production interface board 22, the production control board 23, and the liquid crystal interface board 24 are directly connected to the male connector and the female connector without passing through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire substrate can be minimized, and the noise resistance can be improved by minimizing the connection line.

As illustrated, the control command CMD′ output from the main control board 21 is transmitted to the payout control board 25 via the main board relay board 33. On the other hand, the control command CMD output from the main control board 21 is transmitted to the effect control board 23 via the effect interface board 22. The control commands CMD and CMD' each have a 16-bit length, but are transmitted in parallel every two 8-bit lengths.

A computer circuit including a one-chip microcomputer is mounted on the main control board 21 and the payout control board 25. In addition, the production control board 23 is mounted with a composite chip 50 in which computer circuits such as a VDP circuit (Video Display Processor) 52 and a built-in CPU circuit 51 are built. Therefore, these control boards 21, 25, 23, the circuits mounted on the production interface board 22 and the liquid crystal interface board 24, and the operations realized by the circuits are functionally collectively referred to in this specification. , Main control unit 21, effect control unit 23, and payout control unit 25. In addition, with respect to the main control unit 21, the effect control unit 23 and the payout control unit 25 are sub-control units.

The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back surface of the game board 5. The frame-side member GM1 includes a front frame 3 to which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outer side thereof. Fixedly installed. On the other hand, the board side member GM2 is exchanged in response to a model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. In addition, all except the frame side member 1 are the board side members GM2.

As shown by the broken line frame in FIG. 3, the frame side member GM1 includes a power supply board 20, a payout control board 25, a firing control board 26, and a frame relay board 36, and these circuit boards are The front frame 3 is fixed in place. On the other hand, on the back surface of the game board 5, the main control board 21 and the effect control board 23 are fixed together with the display devices DS1 and DS2 and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by the connection connectors C1 to C4 centrally arranged at one place.

The power supply board 20 is connected to the main board relay board 33 through the connection connector C2, and is connected to the power supply relay board 34 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors the turning on and off of the AC power supply. When the power supply monitoring unit MNT detects the interruption of the AC power supply, the power supply abnormality signals ABN1 and ABN2 are immediately changed to the L level. It should be noted that the power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

The main board relay board 33 outputs the power supply abnormality signal ABN1 output from the power supply board 20, the backup power supply BAK, and DC5V, DC12V, DC32V as they are to the main control unit 21. Further, the power supply relay board 34 outputs the AC and DC power supply voltages received from the power supply board 20 as they are to the production interface board 22.

As shown in the figure, the production interface board 22 is equipped with a voice circuit SND such as a voice processor 27, and the production control board 23 is provided with a composite chip 50 having a built-in computer circuit such as a VDP circuit 52 and a CPU circuit 51. It is installed.

Further, the production interface board 22 is equipped with a reset circuit RST3 that detects a rise in the power supply voltage and generates a reset signal SYS (CPU reset signal) when the power is turned on. The CPU reset signal SYS is transmitted to the audio circuit SND of the production interface board 22 and the composite chip 50 of the production control board 23 to synchronously reset the power source of each electronic element. As will be described later, when the program processing of the CPU circuit 51 enters an infinite loop state, the watchdog timer 58 (see FIG. 4A) incorporated in the CPU circuit 51 is activated to activate the audio circuit SND and the composite chip. 50 is synchronously reset abnormally.

Next, the payout control board 25, which is the frame-side member GM1, is directly connected to the power supply board 20 without the intermediary of the relay board, and receives the same power supply abnormality signal ABN2 and the backup power supply BAK that the main control section 21 receives. Received along with the power supply voltage. Further, the main control unit 21 and the payout control unit 25 are respectively equipped with reset circuits RST1 and RST2, and are configured so that a power supply reset signal is generated when the power is turned on and each computer circuit is reset. ..

As described above, in the present embodiment, the main controller 21, the payout controller 25, and the effect interface board 22 are provided with the reset circuits RST1 to RST3, respectively, and the CPU reset signal SYS is transmitted between the circuit boards. It will not be transmitted. That is, since there is no wiring cable for transmitting the CPU reset signal SYS, the risk that the computer circuit is abnormally reset due to noise superimposed on the wiring cable is eliminated.

However, each of the reset circuits RST1 and RST2 provided in the main controller 21 and the payout controller 25 has a built-in watchdog timer, and does not receive a regular clear pulse from the CPU of each controller 21 and 25. In this case, each CPU is forcibly reset.

Further, the main controller 21 is provided with an initialization switch SW that can be operated by a staff member so that when the power is turned on, a RAM clear signal CLR indicating whether or not the initialization switch SW has been turned ON is output. It is configured. The RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the payout control unit 25, and determines whether or not to initialize the entire area of the built-in RAM of the one-chip microcomputers of the control units 21 and 25. ing.

Further, the main control unit 21 and the payout control unit 25 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 so as to start necessary end processing prior to power failure or business end. The backup power supply BAK is a DC 5V DC power supply that retains the data in the built-in RAM of the one-chip microcomputers of the main control unit 21 and the payout control unit 25 even after the AC power supply 24V is shut off due to the closing of business or power failure. Therefore, the main control unit 21 and the payout control unit 25 can restart the game operation before power-off after power-on (power-source backup function). This pachinko machine is designed so that the stored contents of the RAM of each one-chip microcomputer are retained for at least several days.

As shown in FIG. 3, the main control unit 21 receives from the payout control unit 25 a prize ball counting signal indicating a payout operation of gaming balls, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN. There is. The status signal CON includes, for example, an out-of-supply signal, an insufficient payout error signal, and a lower plate full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 is completed after the power is turned on.

Further, the main controller 21 is connected to each game component of the game board 5 via the game board relay board 32. Then, while receiving a switch signal of a detection switch built in each of the winning ports 16 to 18 on the game board, it drives solenoids such as an electric tulip. The solenoids and the detection switches are configured to operate with the power supply voltage VB (12V) distributed from the main controller 21. Further, each switch signal indicating a winning state or the like to the symbol starting port 15 is converted into a switch signal of TTL level or CMOS level by an interface IC which operates with a power supply voltage VB (12V) and a power supply voltage Vcc (5V). Then, it is transmitted to the main control unit 21.

As described above, the production interface board 22, the production control board 23, and the liquid crystal interface board 24 are integrated by connector connection, and the production interface board 22 is connected to the power supply via the power relay board 34. DC voltage (5V, 12V, 32V) of each level is received from the substrate 20 (see FIGS. 3 and 4A).

As shown in FIG. 3, the production interface board 22 receives the control command CMD and the strobe signal STB from the main control unit 21 and transfers them to the production control board 23. More specifically, as shown in FIG. 4A, the control command CMD and the strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the effect control board 23 via the input buffer 40. ..

The CPU reset signal SYS generated by the reset circuit RST3 is supplied to the effect control board 23 and the audio circuit SND such as the audio processor 27 via the input buffer 40 and the OR circuit G1. As shown in the figure, the OR circuit G1 is also supplied with the underflow signal UF of the WDT circuit 58, and when either of the two signals SYS, UF becomes an active level, the internal circuit of the composite chip 50 and the audio circuit SND are supplied. Are reset in synchronization (abnormal reset). The internal circuit of the composite chip 50 that is abnormally reset includes a CPU circuit 51 and a VDP circuit 52, and the audio circuit SND that is abnormally reset includes an audio processor 27 and an audio memory 28.

As shown in FIG. 4A, the input buffer 44 of the effect interface board 22 receives the switch signals of the chance button 11 and the volume switch VLSW from the frame relay boards 35 and 36, and sends each switch signal to the CPU of the effect control board 23. It is transmitted to the circuit 51. Specifically, a 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW and a 1-bit length indicating the ON/OFF state of the chance button 11 are transmitted to the CPU circuit 51.

Further, the production interface board 22 is connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay boards 35 and 36. As shown, an output buffer 42 is arranged corresponding to the lamp driving board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp driving board 31. In FIG. 4A, for convenience, the input buffer 43a and the output buffer 43b are collectively referred to as the input/output buffer 43. The input buffer 43a receives the outputs SN0 to SNn of the origin sensor for grasping the current position (rotational positions of the effect motors M1 to Mn) of the accessory which is the movable effect body, and transmits them to the CPU circuit 51 of the effect control board 23. There is.

The same type of driver IC is mounted on the lamp drive board 30, the motor lamp drive board 31, and the lamp drive board 37, and the production interface board 22 receives the serial signal received from the production control board 23 from each driver IC. Have transferred to. Specifically, the serial signal is a lamp (motor) drive signal SDATA and a clock signal CK, and the drive signal SDATA is transmitted to each driver IC in a clock synchronization method, and a lamp effect by a large number of LED lamps and decorative lamps is produced. A character effect is executed by the effect motors M1 to Mn.

In the case of the present embodiment, the lamp effect is executed by the three groups of lamp groups CH0 to CH2, and the lamp drive board 37 clocks the lamp drive signal SDATA0 of CH0 via the frame relay boards 35 and 36. It is received in synchronization with the signal CK0. A series of lamp drive signals SDATA0 transmitted as a serial signal are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, so that the lighting state is updated all at once.

The above points are the same for the lamp driving board 30. The driver IC of the lamp driving board 30 receives the lamp driving signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. The lighting state of the lamp group CH1 is updated all at once at the timing of change to.

On the other hand, the driver IC mounted on the motor lamp drive board 31 drives the lamp group CH2 by receiving the lamp drive signal transmitted in the clock synchronous system, and receives the motor drive signal transmitted in the clock synchronous system, The effect motor groups M1 to Mn configured by a plurality of stepping motors are driven. The lamp drive signal and the motor drive signal are a series of serial signals SDATA2, which are serially transmitted in synchronization with the clock signal CK1, and the driver IC which receives the serial signal SDATA2 receives the timing when the operation control signal ENABLE2 changes to the active level. Then, the driving states of the lamp group CH2 and the motor groups M1 to Mn are updated.

Next, the audio circuit SND will be described. As shown in FIG. 4A, the effect interface board 22 includes a voice processor (voice synthesizer circuit) 27 that reproduces an audio signal based on an instruction received from the CPU circuit 51 (effect control CPU 63) of the effect control board 23. An audio memory 28 for storing compressed audio data, which is the original data of the audio signal to be reproduced, and a digital amplifier 29 for receiving the audio signal output from the audio processor 27 are mounted.

The voice processor 27 accesses the voice memory 28 based on the operation parameter (set value by voice command) received from the effect control CPU 63 in the voice control register which is a built-in register, reproduces and outputs a necessary voice signal. .. As shown in FIG. 4A, the voice processor 27 and the voice memory 28 are connected by a voice address bus having a length of 26 bits and a voice data bus having a length of 16 bits. Therefore, 1 Gbit (=2 ²⁶ *16) of data can be stored in the audio memory 28.

In the case of the present embodiment, the compressed voice data stored in the voice memory 28 is the phrase compressed data specified by the 13-bit long phrase number NUM (000H to 1FFFH), which is equivalent to one song of a series of background music. (BGM), a set of effect sounds (preliminary sounds), etc. are stored in association with a maximum of 8192 types (=213) of the phrase numbers NUM. The phrase number NUM is specified by the set value (operation parameter) of the voice command transmitted from the effect control CPU 63 to the voice control register of the voice processor 27.

As shown in FIG. 4A, the data bus and the address bus of the CPU circuit 51 of the effect control unit 23 are stored in the time circuit (real time clock) 38 and the effect data memory 39 mounted on the liquid crystal interface board 24. Has also reached. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and is configured so that the CPU circuit 51 can arbitrarily access it. The effect data memory 39 is a high-speed accessible memory device SRAM (Static Random Access Memory), which is connected to the 16-bit address bus and the lower 16-bit data bus of the CPU circuit 51, and is stored therein. The game performance information and other information being played can be appropriately R/W accessed from the CPU circuit 51.

The clock circuit 38 and the effect data memory 39 are driven by a secondary battery (not shown), and the secondary battery is appropriately charged by the power supply voltage from the power supply board 20 during the game operation. Therefore, even after the power is cut off, the clocking operation of the clock circuit 38 is continued, and the game performance information stored in the effect data memory 39 is permanently stored (nonvolatile).

As shown on the right side of FIG. 4A, on the effect control board 23, a composite chip 50 having a built-in CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 for storing a control program of the CPU circuit 51, A DRAM (Dynamic Random Access Memory) 54 that can access a large amount of data at high speed and a CGROM 55 that stores a large amount of CG data necessary for effect control are mounted.

FIG. 5A is a circuit block diagram illustrating the composite chip 50 forming the effect control unit 23, including the related circuit elements. As shown in the figure, in the composite chip 50 of the embodiment, a built-in CPU circuit 51 that issues a display list DL at predetermined time intervals, and display devices DS1 and DS2 that generate image data based on the issued display list DL are provided. A VDP circuit 52 for driving is built in. The built-in CPU circuit 51 and the VDP circuit 52 are connected via a CPUIF circuit 56 that relays the transmission/reception data of each other.

Further, the CPUIF circuit 56 is connected to a control memory (PROGRAM_ROM) 53 that stores a control program and necessary control data in a nonvolatile manner, and a work memory (RAM) 57 that has a storage capacity of about 2 Mbytes. It is configured to be accessible from the built-in CPU circuit 51. Then, in the work memory (RAM) 57, a DL buffer BUF that temporarily stores a display list DL in which a series of instruction commands for specifying each frame of the display devices DS1 and DS2 are described is secured.

In the case of the present embodiment, the series of instruction commands includes a texture load type command such as a TXLOAD command for reading and decoding (developing) an image material (texture) from the CGROM 55, and a VRAM area (index Texture setting commands such as the SET INDEX command that has the function of specifying the space) in advance, and primitive drawing commands such as the SPRITE command for placing the decoded (decompressed) image material at a predetermined position in the virtual drawing space. , Environment setting commands such as SETDAVR command and SETDAVF command for specifying the drawing area that is actually drawn on the display device among the images drawn in the virtual drawing space by drawing commands, and the index table IDXTBL that manages the index space. Includes index table control commands (WRIDXTBL) for.

In FIG. 7C, a virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), a drawing area that can be arbitrarily set in the virtual drawing space, and output to the display devices DS1 and DS2. The relationship between the actual drawing areas in the frame buffers FBa and FBb for temporarily storing the image data to be stored is illustrated.

The built-in CPU circuit 51 is a circuit having a performance equivalent to that of a general-purpose one-chip microcomputer. A watchdog timer (WDT) 58 forcibly resetting, a RAM 59 having a storage capacity of about 16 kbytes and used as a work area of the CPU, and a DMAC (Direct Memory Access Controller) for realizing data transfer without going through the CPU. 60, a serial input/output port (SIO) 61 having a plurality of input ports Si and an output port So, and a parallel input/output port (PIO) 62 having a plurality of input ports Pi and an output port Po. Has been done.

For convenience, the expression “input/output port” is used, but in the effect control unit 23, the input/output ports include an input port and an output port that operate independently. Note that this point is the same for the input/output circuit 64p and the input/output circuit 64s described below.

The parallel input/output port 62 is connected to an external device (production interface board 22) through an input/output circuit 64p, and the production control CPU 63, via the input circuit 64p, the encoder output 3bit of the volume switch VLSW and the chance. The switch signal of the button 11, the control command CMD, and the interrupt signal STB are received. The encoder output 3 bits and the switch signal 1 bit are supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p.

Similarly, the received control command CMD is supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p. Further, the strobe signal STB is supplied to the interrupt terminal of the effect control CPU 63 via the input/output circuit 64p to activate the reception interrupt processing. Therefore, the effect control CPU 63 that grasps the control command CMD on the basis of the reception interrupt process controls the sound effect, the lamp effect, the motor effect, and the image effect corresponding to the control command CMD uniformly through the effect lottery and the like. Will be done.

Although not particularly limited, in this embodiment, the SMC unit (Serial Management Controller) 78 of the VDP circuit 52 is used for the lamp effect and the motor effect. The SMC unit 78 is a composite controller that incorporates an LED controller and a Motor controller, and is configured to output a serial signal in a clock synchronization system. Further, the Motor controller is configured to be able to output a latch pulse at an arbitrary timing based on a set value in a predetermined control register 70, and to be able to input a serial signal by a clock synchronization method.

Therefore, in this embodiment, the motor drive signal and the LED drive signal are output from the SMC unit 78 in synchronization with the clock signal, while the latch pulse is output as the operation control signal ENABLE at an appropriate timing. .. Further, the origin sensor signals SN0 to SNn from the effect motor groups M1 to Mn are serially input by the clock synchronization method.

As described with reference to FIG. 4A, the clock signals CK0 to CK2, the drive signals SDATA0 to SDATA2, and the operation control signals ENABLE0 to ENABLE2 are output to the predetermined drive substrates 30, 31, 37 is transmitted. The origin sensor signals SN0 to SNn are serially input from the motor lamp drive board 31 to the SMC section 78 via the input/output buffer 43.

However, in this embodiment, it is not essential to use the SMC unit 78. That is, since the CPU circuit 51 has the built-in general-purpose serial input/output port SIO61, it is possible to execute a lamp effect and a motor effect by using these.

Specifically, as shown by the broken line in FIG. 5A, in the configuration shown by the broken line, clock signals CK0 to CK2, via the input/output circuit 64s internally connected to the serial input/output port SIO61, The drive signals SDATA0 to SDATA2 are output, and the operation control signals ENABLE0 to ENABLE2 are output via the input/output circuit 64p. It should be noted that, for convenience, it is expressed as an input/output port or an input/output circuit, but it is the output port or output circuit that actually functions.

Here, the serial output port SO is configured by incorporating a 16-stage FIFO register. Then, the DMAC circuit 60 is activated upon receiving an operation start instruction (see ST18 in FIG. 10(b)) from the effect control CPU 63, and sequentially selects the necessary drive data from the lamp/motor drive table (see FIG. 10(b)). Read out and DMA-transferred to the FIFO register of the serial output port SO. The drive data accumulated in the FIFO register is serially output from the serial output port SO by the clock synchronization method. The DMAC circuit has a plurality of DMA channels (for example, 4), but is configured so that the first DMA channel DMA-transfers the lamp drive data and the second DMA channel DMA-transfers the motor drive data. ing.

Next, the WDT circuit 58 provided in the built-in CPU circuit 51 has a WDT counter that performs a down-count operation based on the set values in a plurality of control registers (WDT control registers, etc.) accessible from the effect control CPU 63. Is configured. The WDT counter starts from a predetermined initial value and is down-counted toward a zero in a predetermined operation cycle. When the down-count value reaches zero, an internal interrupt (WDT interrupt) is generated and the active level is lowered. Of the underflow signal UF.

As described above with reference to FIG. 4A, the underflow signal UF is transmitted to each unit via the OR circuit G1 and abnormally resets the composite chip 50 and the audio circuit SND in synchronization. Of course, the effect control CPU 63 restores the counter value to the initial value by writing a predetermined 1-bit value in the initialization bit of the WDT control register every predetermined time (for example, 1/30 seconds) (see ST14 in FIG. 10). Therefore, the occurrence of the above-mentioned abnormal reset is avoided. When the counter value of the WDT counter returns to the initial value, the initialization bit also returns to the original value.

As described above, in this embodiment, the effect control CPU 63 only needs to write-access the initialization bit (1 bit) of the WDT control register, and the reset circuits RST1 and RST2, like the CPUs of the main control unit 21 and the payout control unit 25, need. Since it is not necessary to output a clear pulse to, the control load is reduced by this amount. Further, since a WDT interrupt is generated when the underflow is abnormal, it is possible to store the occurrence time of the abnormal reset in the effect data memory 39 in a nonvolatile manner by activating an appropriate WDT interrupt processing program. FIG.4(b) has shown the circuit structure in such a case, and the production|generation control CPU63 will be in a reset state by a software reset process after execution of a WDT interruption process program.

The DMAC circuit 60 performs a predetermined number of times for each predetermined data transfer unit in a predetermined DMA transfer mode from a transfer source (Source) to a transfer destination (Destination) based on a set value in a predetermined operation control register. , A circuit for repeating data transfer.

For example, in the embodiment in which the serial output port SO functions (see the broken line in FIG. 5A), the operation control register of the CPU circuit 51 stores the start address (start value of the transfer source address) of the lamp/motor drive table. , The address of the input register of the serial output port SO (fixed value of the transfer destination address), the data transfer unit (8 bits), and the transfer count are designated. Then, the DMAC circuit 60, which has received the operation start instruction from the predetermined operation control register, updates the transfer source address and DMA-transfers the drive data to the predetermined transfer destination address.

This point is almost the same in the case of the embodiment (FIGS. 13 and 17C) in which the display list DL is issued by the DMAC circuit 60. That is, the effect control CPU 63 stores the start address of the transfer source (DL buffer BUF), the transfer destination (transfer port TR_PORT), the DMA transfer mode, and the data transfer unit in the predetermined operation control register of the CPU circuit 51. , The number of transfers, and other conditions will be set. Note that these points will be described later with reference to FIG. 13.

Generally, the DMA transfer mode includes a cycle steal transfer mode in which the DMA operation does not occupy the memory bus, such as releasing the bus control right during a unit operation (R operation/W operation) of the DMA transfer, and a plurality of R operations and DMA operation during burst transfer (pipeline transfer) mode in which the bus control right is not released until the specified number of transfers is completed, such as continuous W operation, and while a DMA transfer request (demand) received from another device is active. A demand transfer mode or the like for continuing the operation can be considered. However, the DMAC circuit 60 of this embodiment functions in the cycle steal transfer mode in which a memory release period of at least one cycle is provided between the read access activation (R operation) and the write access activation (W operation) at the time of DMA transfer. By doing so, the operation of the effect control CPU 63 is prevented from being hindered.

FIG. 6 is a diagram for explaining the cycle steal transfer operation (a) and the pipeline transfer (b). As shown in FIG. 6A, the DMAC circuit 60 functioning in the cycle steal transfer mode operates at least one cycle between the read access activation (R) and the write access activation (W) of one data transfer. In this idle cycle, the production control CPU 63 can use the bus. As is clear from the comparison between FIGS. 6A and 6B, in the pipeline transfer, the bus is not released to the CPU until one cycle (one operand transfer) is completed, whereas in the cycle steal transfer mode. Since the bus is opened to the CPU for each read access, the operation of the CPU is not significantly delayed.

Then, for example, in the embodiment using the DMAC circuit 60 when the display list DL is issued to the VDP circuit 52, the data transfer unit (1 operand) of one cycle is set to 32×2 bits and the display list DL is stored. While appropriately increasing the source address of the built-in RAM 59 (+8 for each operand transfer), the DMA transfer operation is performed on the transfer port register TR_PORT (see FIG. 8) of the data transfer circuit 72 specified by the fixed address. Is running.

As will be described later, in the embodiment, by adding a necessary number of NOP (no operation) commands to the display list DL, the entire data size is fixed (for example, 4×64=256 bytes, or an integer thereof). By adjusting one operand transfer 32 times×2 times 32 times (or an integral multiple thereof), the issue of the display list DL is completed. Even when the drawing circuit 76 executes the NOP command, virtually no change occurs.

Next, the VDP circuit 52 will be described. The VDP circuit 52 includes a CGROM 55 that stores compressed data that is a constituent element of a still image or a moving image that forms an image effect, and an external DRAM (Dynamic) having a storage capacity of about 4 Gbit. The Random Access Memory) 54, the main display device DS1 and the sub display device DS2 are connected. The DRAM 54 is preferably composed of DDR (Double-Data-Rate SDRAM).

Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of a NAND flash memory having a storage capacity of about 62 Gbit, and compressed data required for serial transmission. Is configured to get. Therefore, the problem of skew (difference in transmission rate for each bit data) that is inevitably generated in parallel transmission is solved, and extremely high-speed transmission operation becomes possible. Although not particularly limited, in this embodiment, the CGROM 55 is accessed at a high speed by the HSS (High Speed Serial) method based on Serial ATA.

Regardless of whether or not the HSS method conforming to Serial ATA is adopted, the NAND flash memory is mechanically stabler than the hard disk and can be accessed at high speed, while it is a sequential access memory. Compared to DRAM and SRAM (Static Random Access Memory), there is a problem in random accessibility. Therefore, in the present embodiment, a preload operation of reading a group of compressed data (CG data) into the DRAM 54 prior to the drawing operation is executed to realize smooth random access of the CG data during the drawing operation. ing. By the way, the access speed becomes slower in the order of internal VRAM>external DRAM>CGROM.

More specifically, the VDP circuit 52 includes a control register group 70 in which various operation parameters that define the operation of a VDP (Video Display Processor) can be set by the effect control CPU 63, and image data to be displayed on the display devices DS1 and DS2. A built-in VRAM (video RAM) 71 of about 48 Mbytes used at the time of generation, a data transfer circuit 72 that executes data transmission/reception between each part inside the chip and data transmission/reception with the outside of the chip, and a source and destination of the built-in VRAM 71. An index table IDXTBL capable of specifying address information, a preloader 73 capable of executing a preload operation for Read access to the CGROM 55 prior to a drawing operation, and a graphics decoder for decoding (decoding/expanding/decompressing) the compressed data read from the CGROM 55. (GDEC) 75, a drawing circuit 76 that appropriately combines the decoded (decompressed) still image data and moving image data to generate image data for each frame of the display devices DS1 and DS2, and the operation of the drawing circuit 76. As a part, the geometry engine 77 that generates a stereoscopic image by appropriate coordinate conversion and the image data of the frame buffers FBa and FBb generated by the drawing circuit 76 are read out, and three systems that can perform appropriate image processing in parallel (A/B/C) display circuits 74A to 74C and an output selection unit 79 that appropriately outputs the outputs of the three-system (A/B/C) display circuits 74, and an image output by the output selection unit 79 An LVDS unit 80 that converts data into an LVDS signal, an SMC unit 78 that can transmit/receive serial data, a CPUIF unit 81 that relays data transmission/reception with the CPUIF circuit 56, and a CG bus IF unit 82 that relays data reception from the CGROM 55. And a DRAMIF section 83 for relaying data transmission/reception with the external DRAM 54, and a VRAMIF section 84 for relaying data transmission/reception with the built-in VRAM 71.

FIG. 5B shows the relationship between the CPUIF unit 81, the CG bus IF unit 82, the DRAMIF unit 83, the VRAMIF unit 84, the control register group 70, the CGROM 55, the DRAM 54, and the built-in VRAM 71. As illustrated, the CG data acquired from the CGROM 55 is transferred to the preload area of the external DRAM 54 as preload data, for example, via the data transfer circuit 72 and the DRAMIF unit 83.

However, the preload operation described above is not an essential operation, and the data transfer destination is not limited to the external DRAM 54 and may be the built-in VRAM 71. Therefore, for example, in the embodiment in which the preload operation is not executed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and the VRAMIF section 84 (FIG. 5B).

By the way, in the present embodiment, the built-in VRAM 71 stores the image data for specifying the expansion area of the compressed data read from the CGROM 55 and each ARGB information (32 bit=8×4) of W×H display pixels of the display device. A frame buffer area for storing data and a Z buffer area for storing depth information of each display pixel are required. In the ARGB information, A means 8-bit α plane data and RGB means 8-bit data of three primary colors.

Here, the above-mentioned areas of the built-in VRAM 71 are indirectly accessed by the effect control CPU 63 based on various instruction commands (texture, SPRITE, etc.) described in the display list DL, but READ/WRITE access thereof. It is troublesome to specify the Destination address and the Source address of the built-in VRAM 71 one by one. Therefore, in this embodiment, in the initial processing after the CPU is reset, a one-dimensional or two-dimensional logical memory space (hereinafter referred to as an index space) necessary for the drawing operation is secured and an index number is assigned to each index space. By doing so, access based on the index number is enabled.

Specifically, after the CPU is reset, the built-in VRAM 71 is roughly divided into three types of memory areas, and a required number of index spaces are secured in each memory area. Then, by constructing an index table IDXTBL (see FIG. 7A) that stores the index space and the index number in association with each other, the subsequent operation based on the index number is realized.

It is necessary to (1) add this index space after initial processing, and conversely (2) open it. Therefore, during the operation of the addition/release effect control CPU 63, it is possible to determine whether or not the timing of the addition/release processing is possible, and whether or not the processing of addition/release is actually completed. The area FG is provided in the index table IDXTBL. The built-in VRAM 71 is roughly divided into three types of memory areas, two AAC areas (a1, a2), a page area (b), and an arbitrary area (c), which will be described below. The index table IDXTBL is divided into three sections corresponding to (a1, a2)(b)(c) (FIG. 7(a)). As shown in the figure, in this embodiment, the first AAC area (a1) and the second AAC area (a2) are secured as the AAC area (a), but it is not particularly limited and only one of them is provided. But good. In the following description, the first and second AAC areas (a1, a2) may be collectively referred to as the AAC area (a).

In the case of this embodiment, the built-in VRAM 71 has (a) an AAC area having an index space and its index number automatically assigned by internal processing and having a memory cache function, and (b) a two-dimensional space of, for example, 4096 bits×128 lines. As a unit space, it is configured such that it can be divided into a page area in which an index space can be secured in the range of an integral multiple thereof, and (c) a start address (space start address) STx and an arbitrary area in which the horizontal size Hx can be arbitrarily set. (See FIG. 7B). However, in order to facilitate the internal operation of the VDP circuit 52, the lower 11 bits of the space start address STx of the index space arbitrarily set in the arbitrary area (c) are 0, and a predetermined bit (2048 bits=256 bytes). Must be in units.

After the CPU is reset, the maximum value of the memory space required for each and the area start address (lower 11 bits=0) are specified, and the AAC area (a1), the second AAC area (a2), and the page area ( b) and are secured, and the remaining memory area becomes an arbitrary area (c). In order to facilitate the internal operation of the VDP circuit 52, the maximum value of the memory space of the AAC area is defined in units of 2048 bits, and the maximum value of the memory space of the page area is an integral multiple of the above unit space of 4096 bits×128 lines. It is said that.

Next, a required number of index spaces are set in each of the areas (a1, a2)(b)(c) thus secured. When the arbitrary area (c) is used, in order to facilitate the internal operation of the VDP circuit 52, the horizontal size Hx of the index space that handles two-dimensional data can be arbitrarily set as a multiple of 256 bits, while The vertical size is a fixed value (for example, 2048 lines).

In any case, since the VDP circuit 52 automatically assigns the index space and the index number to the first and second AAC areas (a1, a2), for example, by the SETINDEX command of the texture setting system command, If the decoding destination is specified in the AAC area (a), the TXLOAD (texture load) command that reads CG data from the CGROM 55 need only specify the source address of the CGROM 55 and the horizontal and vertical sizes after expansion (decoding). It will be. Therefore, in the present embodiment, for a still image (texture) such as a character that appears temporarily during a notice presentation, or an I-stream moving image, the decoding destination is the AAC area (a).

Since the memory cache function is added to all the AAC areas (a), for example, when the same texture of the CGROM 55 is read into the AAC areas (a) a plurality of times, after the second time, The decoded data cached in the AAC area (a) can be utilized, and extra READ access and decoding processing can be suppressed. However, when the AAC area (a) is used up, old data is automatically destroyed. Therefore, in this embodiment, when the AAC area (a) is used, the first AAC area (a1) is basically used. Only the specific texture to be used repeatedly is acquired in the second AAC area (a2).

As the texture that is repeatedly used, for example, a character that repeatedly appears in a predetermined notice effect, a background image when the background screen is constructed with a still image, and the like can be illustrated. In such a case, the SETINDEX command of the texture setting commands sets the decoding destination to the second AAC area (a2), and the TXLOAD command decodes the texture such as characters and background images to the second AAC area (a2). After that, the decoding result is protected by not using the second AAC area (a2).

Then, after specifying the decoding destination in the second AAC area (a2) with the SET INDEX command and executing the same TXLOAD command to reacquire the acquired texture, the acquired texture will hit the cache. , Read access to the CGROM 55 and the time required for the decoding process can be deleted. As will be described later, such a cache hit function is also exerted on the preload data prefetched in the preload area. However, the preload data cache hit in the preload area is the compressed data before decoding, whereas the AAC It is significant that the cache hit in the area is the expanded data after decoding.

By the way, a texture is a concept that generally refers to the texture and texture of the surface of an object, but in this specification, sprite image data that constitutes a still image, image data that constitutes one moving image frame, , And is used as a concept that includes not only image data to be attached to drawing primitives such as triangles and quadrangles but also image data after decoding. Then, when the image data is copied (hereinafter, referred to as a move for convenience) inside the built-in VRAM 71, the image data of the move source is set as a texture by the SETINDEX command of the texture setting command, and then the SPRITE command is set. Will be executed.

By the execution of the SPRITE command, the source image data of the movement source is formally drawn in the virtual drawing space shown in FIG. 7C, but is actually drawn on the display device in the virtual drawing space. If the correspondence between the area and the index space that will be the frame buffer is set in advance by environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), for example, the virtual drawing space by the SPRITE command By the drawing, the source image data of the movement source is drawn in a predetermined index space (frame buffer) (see FIG. 7C).

In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC area (a1, a2), a page area (b) and an arbitrary area (c), and an appropriate number of index spaces are secured in each. Each index space is specified by an independent index number for each area (a)(b)(c). The index number is, for example, 1 byte long, and the page area (b) and the optional area (c) (excluding the AAC area (a) automatically assigned by the internal circuit) are rendered in the range of 0 to 255. The control CPU 63 can freely assign an index number.

Therefore, in the present embodiment, as shown in FIG. 7A, a pair of frame buffers FBa are secured in the arbitrary area (c) for the display device DS1, and the index numbers 255 and 255 are assigned to both of the double buffer structures. 254 is given. That is, as the frame buffer FBa for the main display device DS1, the index space 255 and the index space 254 that are used by switching in a toggle manner are secured. Although not particularly limited, the index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of horizontal pixels of the display device DS1. Since each pixel is specified by 32 bits of ARGB information, the horizontal size 1280 means 32×1280=40960 bits (a multiple of 256 bits).

Further, for the display device DS2, another pair of frame buffers FBb is secured in the arbitrary area (c), and index numbers 252 and 251 are given to both of the double buffer structures. That is, the index space 252 and the index space 251 are secured as the frame buffer FBb for the sub display device DS2. The index spaces 252 and 251 have a horizontal size of 480 corresponding to the number of pixels in the horizontal direction of the display device DS2. Also in this case, since each pixel is specified by the ARGB information 32 bits, the horizontal size 480 means 32×480=15360 bits (a multiple of 256 bits).

The frame buffers FBa and FBb are secured in the arbitrary area (c) by setting an arbitrary horizontal size in the arbitrary area (c) as a multiple of 32 bytes (=256 bits=8 pixels). This is because, as described above, if the number of horizontal pixels of the display devices DS1 and DS2 is matched, no waste occurs in the reserved area. On the other hand, in the page area (b), only the horizontal/vertical size that is an integral multiple of the unit space of 128 pixels×128 lines can be set.

However, the vertical size of the two-dimensional index space secured in the arbitrary area (c) has a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area of horizontal size 1280×vertical size 1024 becomes the effective data area for the main display device DS1. This also applies to the sub display device DS2, and in the frame buffer FBb, only the area of horizontal size 480×drop size 800 becomes the effective data area for the sub display device DS2 (FIG. 7(c), FIG. 10(d)).

In any case, in the frame buffers FBa and FBb, the double buffers (255/254, 252/251) are alternately used as the drawing area for the drawing circuit 76, and the above point will be described later. The double buffers (255/254, 252/251) are alternately used as display areas for the display circuits 74A and 74B. In this embodiment, since the Z buffer that stores the depth information of the display pixel is not used, a missing number (253) occurs. However, when using the Z buffer, the index numbers 253 and 250 of the arbitrary area (c) are used. The index spaces 253 and 250 serve as Z buffers for the display device DS1 and the display device DS2.

Further, in this embodiment, when an additional index space (memory area) is secured in the arbitrary area (c) where the frame buffers FBa and FBb are secured, an index number starting from 0 is given. .. Although not limited in any way, in the present embodiment, the effect image composed of the character and other still images, as a work area for the notice effect to appear in a part of the display screen in an appropriate rotation posture, if necessary, An index space (0) is secured in the arbitrary area (c).

However, use of the work area is not essential, and an index space as a work area may be secured in the page area (b) instead of the arbitrary area (c). If the page area (b) is used, an index space having a multiple size of a square unit space of horizontal size 128 (=4096 bits)×vertical size 128 can be secured, which is suitable for handling a small effect image.

By the way, in the present embodiment, a moving image including a background image is formed, and the image effect is realized by almost only the moving image. In particular, a large number (usually 10 or more) of moving images are drawn at the same time during the variation effect. All of these moving pictures are stored in the CGROM 55 in a compressed state as a series of moving picture frames, but an I stream moving picture composed of only I frames and an IP stream moving picture composed of I frames and P frames. It is divided into and. Here, the I frame (Intra coded frame) means a frame that compresses the input image as it is, independently of other screens. On the other hand, a P frame (Predictive coded frame) means a frame in which forward predictive coding is performed, and an I frame or a P frame that is temporally located in the past is required.

Therefore, in the present embodiment, the IP stream moving image is expanded in the page area (b) instead of the AAC area (a) where the destruction of the old data may occur. That is, a large number of index spaces (IDX _{0 to} IDX _N ) are secured in the page area (b) capable of securing an index space having a multiple of horizontal size 128×vertical size 128, and a series of moving image frames is used for each moving image frame. The same index space IDXi corresponding to MVi is always used for decoding. That is, the moving image MV1 is expanded in the index space IDX1, the moving image MV2 is expanded in the index space IDX2, and so on. Similarly, the moving image MVi is expanded in the index space IDXi.

More specifically, the moving image MVi will be described in more detail by using the SET INDEX command to specify that "the decoding destination of the IP stream moving image MVi is the index space (i) of the index number i in the page area (b)". The TXLOAD command that acquires one frame of the IP stream moving image MVi is executed.

Then, one moving picture frame (one of a series of moving picture frames) on the CGROM 55 specified by the TXLOAD command is first acquired in the AAC area (a), and then automatically activated by the GDEC (graphics decoder) 75. , One frame of the acquired moving image is decoded and expanded in the index space (i) of the page area (b).

On the other hand, in the present embodiment, the I stream moving image is treated the same as the still image, and it is designated by the SET INDEX command that "the decoding destination of the I stream moving image MVj is the first AAC area (a1)". Execute the TXLOAD command. As a result, the moving image frame is acquired in the first AAC area (a1), and thereafter, the automatically activated GDEC 75 expands the decoded data in the first ACC area (a1). As described above, since the index space of the AAC area (a) is automatically generated, it is not necessary to specify the index number. Note that the expansion volume required for the index space, that is, the horizontal and vertical sizes of the decoded texture (video frame) is TXLOAD regardless of whether the expansion destination is the AAC area (a) or the page area (b). Specified by command.

By the way, the IP stream moving image MVi and the I stream moving image MVj are generally composed of N moving image frames (I frames and P frames). Therefore, in the TXLOAD command, for example, the Source address of the CGROM 55 in which the k-th (1≦k≦N) moving image frame is stored, the expanded horizontal/vertical size, and the like are specified. Although not limited in any way, in the embodiment that hardly uses a still image, most of the 48 Mbytes of memory space of the built-in VRAM 71 (about 30 Mbytes) is allocated to the page area (b). In the embodiment that hardly uses still images, only the first AAC area (a1) is secured as the AAC area, the second AAC area (a2) is not secured, and the cache hit function of the AAC area described above is used. Also do not utilize.

Note that a dedicated GDEC (graphics decoder) circuit may be provided in order to speed up the decoding process of the compressed moving image data. If a dedicated GDEC circuit is built in the VDP circuit 52, it is sufficient to indicate the start address of the compressed video data to the GDEC circuit in the decoding process of the compressed video data composed of N compressed video frames. It is not necessary to specify the start address for each of N compressed moving image frames.

However, incorporating a plurality of such dedicated GDEC circuits for each compression algorithm further complicates the internal configuration of the VDP circuit 52. In view of this, in this embodiment, software GDEC is used to implement decoding processing for data such as IP stream moving images, I stream moving images, still images, and other α values by software processing corresponding to each compression algorithm. Note that the processing time difference between the hardware processing and the software processing does not matter so much, and the processing time only concerns the access (READ) time from the CGROM 55.

Subsequently, returning to FIG. 5A and continuing the description, the data transfer circuit 72 uses the resource (storage medium) inside the VDP circuit and the external storage medium as a transfer source port or a transfer destination port and connects them. It is a circuit that executes a data transfer operation by DMA (Direct Memory Access). FIG. 8 is a block diagram showing the internal structure of the data transfer circuit 72 together with the related circuit structure.

As shown in FIG. 8, the data transfer circuit 72 is configured to send and receive data to and from the CGROM 55, the DRAM 54, and the built-in RAM 71 via the integrated connection bus ICM having a router function. The CGROM 55 and the DRAM 54 are accessed via the CG bus IF section 82 and the DMAMIF section 83.

On the other hand, the built-in CPU circuit 51 issues the display list DL to the drawing circuit 76 and the preloader 73 via the transfer port register TR_PORT built in the data transfer circuit 72. Although the built-in CPU circuit 51 and the data transfer circuit 72 are bidirectionally connected, when the display list DL is issued, the transfer port register TR_PORT is a data write port that receives one unit of data that constitutes the display list DL. Function as. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits corresponding to the FIFO structure of the CPU bus controller 72d.

As shown in the figure, the effect control CPU 63 can write-access the transfer port register TR_PORT via the CPUIF section 81, while the DMAC circuit 60 directly uses the transfer port register TR_PORT when utilizing the DMAC circuit 60. You will have Write access. Then, a series of instruction commands written in the transfer port register TR_PORT (that is, an instruction command string forming the display list DL) is in units of 32 bits, and a CPU bus incorporating a FIFO buffer (32 bits×130 stages) of FIFO buffers. It is configured to be automatically accumulated in the control unit 72d.

Further, the data transfer circuit 72 executes data transmission/reception operations on the transmission paths of the three channels ChA to ChC, and has a ChA control circuit 72a (N=130) having a FIFO buffer having a FIFO structure (64 bits×N stages). Stage), a ChB control circuit 72b (N=1026 stages), and a ChC control circuit 72c (N=130 stages).

The instruction command string (display list DL) accumulated in the CPU bus control unit 72d is either the drawing circuit 76 or the drawing circuit 76 based on the setting value in the data transfer register RGij (a kind of various control registers 70) by the effect control CPU 63. It is transferred to the preloader 73. As indicated by the arrow, the display list DL is transferred from the CPU bus control unit 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b and to the preloader 73 via the FIFO buffer of the ChC control circuit 72c. Is configured.

In this embodiment, the ChB control circuit 72b and the ChC control circuit 72b are specialized for the transfer operation of the display list DL, and the data stored in the FIFO buffer of the CPU bus control unit 72d is the ChB control circuit. The data is transferred to the drawing circuit 76 or the display list analyzer of the preloader 73 as a part of the display list DL via 72b or the FIFO buffer of the ChC control circuit 72c.

Then, the drawing circuit 76 starts the drawing operation based on the transferred display list DL. On the other hand, the preloader 73 executes a necessary preload operation based on the transferred display list DL. By the preload operation, the CG data of the CGROM 55 is prefetched in the preload area secured in the DRAM 54, and the display list DL (hereinafter referred to as the rewrite list DL') in which the source address of the texture is changed is secured in the DRAM 54 with respect to the TXLOAD command and the like. Stored in the DL buffer area BUF'.

On the other hand, the ChA control circuit 72a and the connection bus access arbitration circuit 72e function for data transfer between storage media such as the CGROM 55, the DRAM 54, and the built-in RAM 71. Further, the IDXTBL access arbitration circuit 72f functions when accessing the built-in RAM 71 which requires the address information of the index table IDXTBL. When specifically confirmed, the ChA control circuit 72a transfers, for example, (a) the compressed data of the CGROM 55 to the built-in VRAM 71, or (b) preloads the compressed data of the CGROM 55 to the external DRAM 54. In this case, (c) the prefetch data in the preload area is transferred to the built-in VRAM 71.

Here, the ChA control circuit 72a is configured to be operable in parallel with the ChB control circuit 72b and the ChC control circuit 72c, and the operations (a) to (c) described above are the operation of issuing the display list DL ( This can be executed in parallel with ST8 of FIG. 10, PT11 of FIG. 15) and the transfer operation of the rewrite list DL′ (PT10 of FIG. 15). Further, the ChB control circuit 72b and the ChC control circuit 72c can be simultaneously executed. For example, the process of step PT10 in FIG. 15 in which the ChB control circuit 72b functions and the process of step PT11 in which the ChC control circuit 72c functions are parallel. Then it is feasible. However, since the transfer port register TR_PORT is single, at the timing when one (72b/72c) uses the transfer port register TR_PORT, the other (72c/72b) accesses the transfer port register TR_PORT. I can't.

When the ChA control circuit 72a operates, the connection bus access arbitration circuit 72e arbitrates data transmission with each storage element (CGROM 55, DRAM 54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL. In the case where the preloader 73 functions, the rewrite list DL′ stored in the DL buffer area BUF′ of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b. (See FIG. 16B).

As described above, the data transfer circuit 72 according to the present exemplary embodiment includes a data transfer source arbitrarily selected from various storage resources (Resource) and a data transfer destination arbitrarily selected from various storage resources (Resource). In between, high-speed data transfer is realized. As confirmed from FIG. 8, the storage resources in which the data transfer circuit 72 functions include not only the built-in RAM 71 but also external devices passing through the CPUIF unit 56, the CG bus IF unit 82, and the DRAMIF unit 83.

Then, like the amount of data to be acquired at one time from the CGROM 55 (memory sequential read), the data transfer amount with the external device in which the ChA control circuit 72a functions is determined by the display in which the ChB control circuit 72b or the ChC control circuit 72c functions. The list DL is huge compared to the case of the list DL, and the amount of data transfer differs greatly from each other.

Here, for each of these various types of data transfer, it is conceivable that the unit data amount and the total transfer data amount can be finely set, but this makes the control operation inside the VDP complicated and smooth the transfer operation. Be hindered. Therefore, in this embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total transfer data amount is limited to be an integral multiple of the minimum data amount DTmin, so that a high-speed and smooth data transfer operation is performed. Has been realized. Although not particularly limited, in the data transfer circuit 72 of the embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total transfer data amount is limited to this integral multiple.

Therefore, the instruction command sequence of the display list DL stored in the FIFO buffer of the CPU bus control unit 72d every 32 bits is stored in the ChB control circuit 72b and the ChC control circuit 72b at the timing when the total amount reaches the minimum data amount Dmin. It will be transferred and stored in each FIFO buffer.

Although the display list DL is composed of a series of instruction commands, in the present embodiment, the display list DL corresponds to the write unit (32 bits) of the transfer port register TR_PORT and the command length is an integer N times 32 bits. It is composed only of (N>0) instruction commands. Therefore, the drawing circuit 76 and the preloader 73 that receive the instruction command of the display list DL via the data transfer circuit 72 can quickly and smoothly start the command analysis processing (DL analyze). It should be noted that the command length that is an integral multiple of 32 bits is not limited to all significant bits, and includes a non-significant bit (Don't care bit), meaning that it is an integral multiple of 32 bits.

Next, the preloader 73 will be described. As outlined above, the preloader 73 interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72b), and stores the CG data on the CGROM 55 referenced by the TXLOAD command in advance in the DRAM 54. This is a circuit for transferring to the preload area of. Further, the preloader 73 stores, in the DL buffer BUF' of the DRAM 54, a rewriting list DL' in which the reference destination of the CG data is rewritten to the address after transfer regarding the TXLOAD command. The DL buffer BUF' and the preload area are secured in advance during the initial processing after the CPU reset (ST3 in FIG. 10).

Then, the rewrite list DL′ is displayed at the start of the drawing operation of the drawing circuit 76 via the connection bus access arbitration circuit 72e of the data transfer circuit 72 and the ChB control circuit 72b, and is displayed by the display list analyzer (DL Analyzer) of the drawing circuit 76. ) Is transferred to. Then, the drawing circuit 76 executes the drawing operation based on the rewriting list DL'. Therefore, based on the TXLOAD command or the like, the CG data that should originally be acquired from the CGROM 55 is acquired from the preload area of the DRAM 54 as preload data that is preread in the preload area. In this case, the preload data can be repeatedly used unless it is overwritten and erased, and the preload data having a cache hit in the preload area is repeatedly reused.

In this embodiment, since the preload area is set in the external DRAM 54 having a sufficient storage capacity, the above-mentioned cache hit function works effectively. Further, since the storage capacity of the external DRAM 54 is large, for example, multiple preload for preloading CG data for a plurality of frames at a stretch is possible. That is, regarding the operation period of the preloader 73, the operation period of a series of preload operations including the prefetch operation of CG data is appropriately set within the range of an integral multiple of the operation cycle δ during the intermittent operation of the VDP circuit 52. Multiple preload is realized by.

However, in the following description, for the sake of convenience, an embodiment without multiple preload will be described. Therefore, the preloader 73 of the embodiment completes the preload operation for one frame during one operation cycle (δ). As will be described later with reference to FIG. 10, in this embodiment, the operation cycle δ during the intermittent operation of the VDP circuit 52 is 1/30 second which is a double cycle of the vertical synchronizing signal of the display device DS1.

Next, the drawing circuit 76 sequentially analyzes the instruction command sequences of the display list DL and the rewriting list DL′ transferred via the data transfer circuit 72, and cooperates with the graphics decoder 75, the geometry engine 77, and the like. Then, it is a circuit for drawing an image of one frame of each of the display devices DS1 and DS2 in the frame buffer formed in the VRAM 71.

As described above, in the embodiment in which the preloader 73 functions, the reference destination of the CG data in the rewrite list DL' is not the CGROM 55 but the preload area set in the DRAM 54. Therefore, the sequential access to the CG data generated during the drawing by the drawing circuit 76 can be executed quickly, and a high-resolution moving image with a lot of movement can be drawn without any problem. That is, according to the present embodiment, it is possible to execute a complex and sophisticated image effect while utilizing an inexpensive SATA module as the CGROM 55.

As described with reference to FIG. 7, the frame buffer FB secured in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a reading area, and the two areas are used by alternately switching the applications. .. Further, in this embodiment, since the two display devices DS1 and DS2 are connected, as shown in FIG. 7, the two sections of frame buffers FBa/FBb are secured. Therefore, the drawing circuit 76 draws one frame of image data in the drawing area (writing area) of the frame buffer FBa for the display device DS1 and also draws the drawing area (writing area) of the frame buffer FBa for the display device DS2. Then, one frame of image data is drawn. When the image data is written in the drawing area, the display circuit 74 reads the image data in the other reading area (display area) and outputs it to each of the display devices DS1 and DS2.

The display circuit 74 is a circuit that reads out image data from the frame buffers FBa and FBb, performs final image processing, and then outputs the image data (see FIG. 9). The final image processing includes, for example, scaling processing for enlarging/reducing the image, delicate color correction processing, and dithering processing for minimizing the quantization error of the entire image. Then, the digital RGB signals (24 bits in total) that have undergone these image processes are output together with the horizontal synchronizing signal and the vertical synchronizing signal. As shown in FIG. 9, in this embodiment, three systems of display circuits A/B/C that perform the above-described operations in parallel are provided, and each of the display circuits 74A to 74C has a corresponding frame buffer. The image data of FBa/FBb/FBc is read and the final image processing is executed. However, in this embodiment, since there are two display devices, the frame buffer FBc is not secured and the display circuit 74C does not function.

In connection with this operation, the output selection unit 79 of this embodiment transmits the output signal of the display circuit 74A to the LVDS unit 80a and the output signal of the display circuit 74B to the LVDS unit 80b (Fig. 9). Then, the LVDS unit 80a converts the image data (24-bit digital RGB signal in total) into an LVDS signal, adds one pair for transmitting a clock signal, and outputs it to the main display device DS1 as all five pairs of differential signals. ing. The main display device DS1 has a built-in conversion receiving unit RV for LVDS signals, which restores RGB signals from LVDS signals and displays an image corresponding to the output of the display circuit 74A.

In this respect, the LVDS unit 80b is also the same, and for a total of 24 bits of each 8-bit digital RGB signal, a pair for transmitting a clock signal is added, and a total of five pairs of differential signals are output to the conversion receiving unit RV, The display device DS2 realizes image display by a total of 24 bits of RGB signals received from the conversion receiving unit RV. Therefore, the sub display device DS2 and the main display device DS1 have a resolution of 2 ⁸ *2 ⁸ *2 ⁸ .

It is not always necessary to use the LVDS signal. For example, when the transmission distance is short, the digital RGB signal is directly transmitted to the display device via the digital RGB unit 80c, or when the transmission distance is long. Converts the digital RGB signal into a V-By-one (registered trademark) signal in the conversion transmitting unit TR′ and transmits the V-By-one (registered trademark) signal to the conversion receiving unit RV′, and then returns the digital RGB signal in the conversion receiving unit RV′. Is also suitable. It should be noted that the broken line in FIG. 9 shows this operation mode, but the above operation is possible with any output signal of the display circuits 74A to 74C by appropriately setting the operation of the output selection unit 79. Becomes

Next, the SMC unit 78 (Serial Management Controller) is a composite controller incorporating an LED controller and a Motor controller. Then, while the LED drive signal and the motor drive signal are output in synchronization with the clock signal to the LED/Motor driver (driver IC that incorporates the shift register) mounted on the external board, the latch pulse is output at an appropriate timing. It is configured to output.

Regarding the internal circuit of the VDP circuit 52 and the operation thereof, the operation content to be executed by the internal circuit is defined by the operation parameter (setting value) set in the control register group 70 by the effect control CPU 63, and the operation of the VDP circuit 52 is executed. The state can be specified by reading the operation status value of the control register group 70. The control register group 70 means a large number of VDP registers RGij mapped in the memory space (0 to FFFFFH) of about 1 Mbyte on the memory map of the effect control CPU 63, and the effect control CPU 63 passes through the CPUIF section 81. The operation parameter WRITE (setting) operation and the operation status value READ operation are executed (see FIG. 5B).

In the control register group 70 (VDP register RGij), the "system control register" in which initial setting values related to system operation such as interrupt operation are written, and the AAC area (a) and page area (b) are fixed in the built-in VRAM. , "Index table register" for constructing or changing the index table IDXTBL, and "data transfer" in which setting values and the like regarding data transfer processing by the data transfer circuit 72 between the effect control CPU 63 and the internal circuit of the VDP circuit 52 are written. “Register”, “GDEC register” for specifying the execution status of the graphics decoder 75, “drawing register” in which instruction commands and setting values for the drawing circuit 76 are written, and setting values for operation of the preloader 73 are written. A "preloader register", a "display register" in which setting values related to the operation of the display circuit 74 are written, an "LED control register" in which setting values related to the LED controller (SMC unit 78) are written, and a Motor controller (SMC). And a "motor control register" in which the set values for the section 78) are written.

In the following description, one or a plurality of registers RGij included in the control register group 70 may be collectively referred to as the above-mentioned individual name or VDP register RGij, but in any case, the effect control CPU 63 The internal operation of the VDP circuit 52 is controlled by writing an appropriate set value in a predetermined VDP register RGij. Specifically, the effect control CPU 63 realizes a predetermined image effect based on the display list DL that is updated at appropriate time intervals and the set value in the predetermined VDP register RGij. In this embodiment, the effect control CPU 63 handles the lamp effect and the motor effect, so the VDP register RGij also includes an LED control register and a motor control register.

Next, a unified effect control operation of image effect, sound effect, motor effect, and lamp effect, which is realized by the composite chip 50 having the built-in CPU circuit 51 and the VDP circuit 52 built therein, will be described. FIG. 10 is a flowchart for explaining the control operation of the effect control CPU 63 of the built-in CPU circuit 51.

The operation of the effect control CPU 63 includes a main process (a) started after CPU reset, a timer interrupt process (b) started every 1 mS, a reception interrupt process (not shown) started upon receiving the control command CMD, and a display. VBLANK interrupt processing (c) which is activated upon receiving the VBLANK signal generated at the start timing of the V blank (vertical blanking period) of the device DS1.

In the reception interrupt process, the control command CMD received from the main control unit 21 is stored in a predetermined reception buffer so that it can be referred to in the main process (ST13), and the process ends. In the VBLANK interrupt process, the interrupt counter VCNT is incremented for each VBLANK interrupt, and at the start timing of the main process, the operation start timing of 1/30 second is grasped based on the value of the interrupt counter VCNT, and then the interrupt The counter VCNT is cleared to zero (ST4).

On the other hand, in the timer interrupt process, as shown in FIG. 10B, a lamp effect or motor effect progression process (ST18) and a sensor signal acquisition process for acquiring the origin sensor signals SN0 to SNn signals, chance button signals, and the like. (ST19) and are included. The lamp effect and the motor effect are controlled on the basis of an effect scenario that centrally manages all the effect operations, and if the effect start time managed by the effect counter EN is reached, in the effect scenario update process (ST11), the motor drive table or The lamp drive table is specified.

Then, after that, the motor effect proceeds based on the specified motor drive table, and the lamp effect advances based on the specified motor drive table. As described above, in some embodiments, the DMAC circuit (first and second DMA channels) 60 functions during the operation of step ST18. Note that the motor effect proceeds every 1 mS, but the lamp effect proceeds at an appropriate timing longer than 1 mS.

Next, the main process (a) will be described as an embodiment in which the preloader does not function. As shown in FIG. 10A, the main process is divided into an initial process (ST1 to ST3) that is executed after the CPU is reset and a steady process (ST4 to ST14) that is repeatedly executed every 1/30 seconds thereafter. To be done.

Then, the steady process is started at the timing when the interrupt counter VCNT becomes VCNT≧2 (ST4), and therefore the operation cycle δ of the steady process becomes 1/30 seconds. This operation cycle δ is nothing but the actual operation cycle δ of the VDP circuit 52 that intermittently operates under the control of the effect control CPU 63. It should be noted that the reason why the determination condition is VCNT≧2 is to take into consideration the possibility that the steady process (ST4 to ST14) is abnormally lengthened and misses the timing of VCNT=2, but VCNT=3. Is designed to prevent

Continuing the description of the main processing (FIG. 10A) based on the above, in this embodiment, in the initial processing, the built-in VRAM 71 having a storage capacity of 48 Mbytes is stored in the ACC area (a) having an appropriate storage capacity, The page area (b) and the arbitrary area (c) are appropriately separated (ST1). Specifically, with respect to the ACC area (a1, a2) and the page area (b), the area start address of each area and the necessary total data size are set in a predetermined index table register RGij (ST1). Then, the reserved ACC areas (a1, a2) and the remaining area not included in the page area (b) become the arbitrary area (c).

Here, the first 11 bits of the first and second ACC areas (a1, a2) and the area start address of the page area (b) must be 0 for each of the lower 11 bits, but can be arbitrarily selected in units of 2048 bits. Yes (1 address = 1 byte, 256 addresses are selected). Also, the total data size is arbitrarily selected within the range of an integral multiple of the unit size. Although not particularly limited, the unit size of the ACC area (a) is 2048 bits and the unit size of the page area (b) is 512 kbits.

As described above, in the present embodiment, a certain condition is set for the area setting of the ACC area (a1, a2) and the page area (b), but this is as wasteful as possible for the built-in VRAM 71 whose memory capacity is limited. This is because the internal operation of the VDP circuit 52 is smoothed while eliminating the area. That is, if the storage capacity of the built-in VRAM 71 is increased unnecessarily, the manufacturing cost may increase and the chip area may increase. On the other hand, if the free area setting that completely eliminates the waste area is allowed, the internal processing is This is because the processing time for VRAM access cannot be shortened due to complexity. It should be noted that the same reason is provided with a certain constraint for securing the index space described below.

Continuing the description based on the above, following the processing of step ST1, the necessary index space IDXi is secured for the page area (b) and the arbitrary area (c) (ST2). Specifically, by setting necessary information in a predetermined index table register RGij, the index space IDXi of each area (b)(c) is secured.

For example, when the index space IDXi is provided in the page area (b), the multiple number information of the arbitrary horizontal size Hx and the arbitrary vertical size Wx corresponding to the arbitrary index number i (vertical and horizontal multiple information for the unit space) ) Is set in a predetermined index table register RGij (ST2).

As described above, the index space IDXi of the page area (b) has a horizontal size of 128×vertical size of 128 lines as a unit space, and one pixel is specified by the information of 32 bits. Based on the setting of the size Wx, the index space IDXi of data size (bit length)=32×128×Hx×128×Wx is secured. The start address (space start address) of the index space IDXi of the page area (b) is automatically given internally.

Further, when the index space IDXi is provided in the arbitrary area (c), the arbitrary head address (space head address) STx and the multiple information of the arbitrary horizontal size Hx are associated with the predetermined index number i. Is set in the index table register RGij (ST2). Here, the term “arbitrary” is based on a predetermined condition. The horizontal size Hx is arbitrarily determined in 256-bit units, and the lower 11 bits of the start address STx is 0, which is arbitrarily determined in 2048-bit units. As described above, since the vertical size of the arbitrary area is fixed to 2048 lines, based on the setting of the horizontal size Hx, the data size (bit length)=2048×Hx index after the head address STx. The space is secured.

Specifically, as the frame buffer FBa of the main display device DS1, a pair of index spaces having a horizontal size of 1280×vertical lines 2048 are set in one or a plurality of predetermined index table registers RGij by specifying their respective index numbers. As the frame buffer FBb of the sub display device DS2, a pair of index spaces of horizontal size 480×vertical line 2048 are set in one or a plurality of predetermined index table registers RGij by specifying index numbers. If the number of horizontal pixels of the display device does not match an integer multiple of 256 bits/32 bits, the horizontal size of each index space is larger than the number of horizontal pixels of the display device, and 256/32=8. Set to a value that is an integral multiple of to minimize the occurrence of useless memory areas.

As described above, by setting necessary size information and address information in the predetermined index table register RGij for the page area (b) and the arbitrary area (c), the required number of index spaces IDXi are generated. (ST2). Then, corresponding to this setting process (ST2), the index table IDXTBL for specifying the address information and size information of each index space IDXi is automatically constructed. As shown in FIG. 7A, the index table IDXTBL stores the start address of each index space IDXi together with other necessary information, and is used when data is transferred inside the VDP circuit 52 and external storage resources (Resource ) Is referred to at the time of data acquisition (see FIG. 8). The index space IDXi of the AAC area (a) is automatically generated when necessary and automatically disappears, so that the setting process of step ST2 is unnecessary.

As shown in FIGS. 7A and 7B, a pair of frame buffers FBa and FBb are secured in the arbitrary area (c), and index numbers are given to them. In the embodiment that does not use the Z buffer, a pair of index spaces 255 and 254 to which index numbers 255 and 254 are assigned are secured as the frame buffer FBa. Further, as the frame buffer FBb, a pair of index spaces 252 and 251 to which index numbers 252 and 251 are given are secured. In the present embodiment, the work area with index number 0 (index space 0) is also secured in the arbitrary area (c).

Further, in this embodiment, a required number of index spaces IDXi to be the decoding region of the IP stream moving image are secured in the page region (a) and the index number i is given. However, initially, only the index space IDX ₀ for the background moving image (IP stream moving image) is secured. Then, the index space IDXj of the page area (a) is increased based on the setting process to the index table register RGij or the command command of the display list DL according to the necessity in the image effect (variable effect or notice effect), After that, if it becomes unnecessary, the index space IDXj is opened. That is, FIG. 7A shows the index table IDXTBL in the steady operation.

The index space of the ACC area (a) is automatically generated when necessary based on the instruction command described in the display list DL, and the index table IDXTBL has the start address of the automatically generated index space IDXj. And other necessary information are automatically set. In this embodiment, this AAC area (a) is used as a decoding area for still images and other textures.

The above-described operation of securing the index space is realized exclusively by the setting operation to the index table register RGij included in the control register group 70. By executing the necessary setting operation, the steady operation (intermittent operation) of the VDP circuit 52 shown in FIGS. 18 to 19 is enabled.

For example, by writing a predetermined operation parameter (the number of lines and the number of pixels) in a predetermined display register RGij that defines the operation of the display circuit 74, the number of display lines and the number of horizontal pixels are set for each of the display devices DS1 and SD2. (SS30). As a result, in each of the frame buffers FBa and FBb, the vertical and horizontal dimensions of the effective data area (broken line portion in FIG. 10D) to be read-accessed by the display circuit 74 are specified.

Next, a predetermined operation parameter (address value) is written in a predetermined display register RGij to specify the vertical display start position and the horizontal display start position for each frame buffer FBa, FBb (SS31). As a result, the valid data area whose vertical and horizontal dimensions are specified by the processing of step SS30 is settled on the frame buffers FBa and FBb. Here, the vertical display start position and the horizontal display start position are relative address values in each index space, and in the embodiment shown in FIG. 10D, the display start position is (0, 0).

Then, the display register RGij (DSPAINDEX) related to the display circuit 74A driving the main display device DS1 and the display register RGij (DSPBINDEX) related to the display circuit 74B driving the sub display device DS2 are respectively displayed in the "display area (0)". And "display area (1)" are set to define each display area (SS32).

Here, the "display area" means an index space (frame buffers FBa, FBb) from which the display circuits 74A, 74B should read image data in order to drive the display devices DS1, DS2, and each has a double buffer structure. Means one of the double buffers in the frame buffers FBa and FBb. However, the display circuits 74A and 74B actually read the image data only in the "valid data area" specified in steps SS30 to SS31 in the display area (0) or the display area (1).

In the present embodiment, the index space 254 of the index number 254 in the VRAM arbitrary area (c) is defined as “display area (0)” in the frame buffer FBa, and the index number in the VRAM arbitrary area (c) is not limited. The index space 255 of 255 is defined as "display area (1)" (SS32).

In the frame buffer FBb, the index space 251 of the index number 251 in the VRAM arbitrary area (c) is set as “display area (0)”, and the index space 252 of the index number 252 in the VRAM arbitrary area (c) is set as “display area ( 1)” (SS32). Note that the definition of the “display area” in the initial processing (SS3) is not particularly limited, and the index space (display area) to which the display circuit 74 should READ access the image data for each operation cycle δ toggles. You may switch.

In the present embodiment, after the above initial processing (SS30 to SS32) is completed, the first-class prohibition setting is performed so that the set value in the predetermined system control register RGij is not changed by the influence of noise or the like. A predetermined prohibition value is set in the register RGij (first prohibition setting SS33).

Here, the set values for which writing is prohibited in the future include (1) set values related to the display clocks of the display devices DS1 and DS2, (2) set values related to the sampling clock of the LVDS, and (3) selection of the output selection circuit 79. It includes set values related to operation, (4) synchronization relationship between the plurality of display circuits DS1 and DS2 (the display circuit 74B is dependent on the operation cycle of the display circuit 74A), and the like. Although there is software processing for canceling the first prohibition setting, it is not used in this embodiment. However, it is also suitable to use it if necessary.

Next, by setting a predetermined prohibition value in the second type prohibition setting register RGij, the write prohibition setting is made for the VDP register RGij of the initialization system (second prohibition setting SS34). Here, the registers that are set to be prohibited include the VDP register RGij related to steps SS30 to SS32.

On the other hand, by setting a predetermined prohibition value in the third-type prohibition setting register RGij, it is possible to set prohibition to a large number of VDP registers including the VDP register relating to the setting processing of steps ST1 to ST3 (the first prohibition setting). 3 prohibition setting). However, it is not used in principle in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be arbitrarily canceled by writing the cancel value in a predetermined cancel register RGij, and the setting value should be changed during the steady operation. Will also be possible.

Since the initial setting process has been described above, before describing the steady process (ST4 to ST14), the steady operation (intermittent operation) of the VDP circuit 52 controlled by the effect control CPU 63 will be described with reference to FIG. A brief description will be given based on FIG.

The intermittent operation of the VDP circuit 52 is as shown in FIGS. 18 and 19, and in the embodiment in which the preloader 73 is not used, as shown in FIG. 18A, the display list DLi completed by the effect control CPU 63 is: In the operation cycle (T1), it is issued to the drawing circuit 76, and the drawing circuit 76 completes the image data in the frame buffers FBa and FBb by the drawing operation based on the display list DLi. Then, the image data completed in the frame buffers FBa and FBb is output to the display devices DS1 and DS2 by the display circuit 74 in the next operation cycle T1+δ, and based on the subsequent drawing operation of the display devices DS1 and DS2. , A display screen that the player perceives.

On the other hand, in the embodiment using the preloader 73, as shown in FIG. 19A, the display list DLi completed by the effect control CPU 63 is issued to the preloader 73 in its operation cycle (T1), and the preloader 73 , The display list DLi is interpreted, necessary read-ahead operation is executed, and a part of the display list DLi is rewritten to complete the rewrite list DL′. The pre-read CG data and the rewrite list DL' are stored at appropriate places in the DRAM 54.

Next, the drawing circuit 76 acquires the rewriting list DL′ from the DRAM 54 in the next operation cycle (T1+δ), and completes the image data in the frame buffers FBa and FBb by the drawing operation based on the rewriting list DL′. .. Then, the image data completed in the frame buffers FBa and FBb is output to the display devices DS1 and DS2 by the display circuit 74 in the next operation cycle (T1+2δ), so that the subsequent display devices DS1 and DS2 are rendered. Based on the operation, the display screen is sensed by the player.

Although the intermittent operation of the VDP circuit 52 has been schematically described above, in order to realize the above-described operations of FIGS. 18 to 19, the effect control CPU 63 causes the value of the interrupt counter VCNT after the initial processing (ST1 to ST3). Repeatedly waiting for the operation start timing to be reached, and when the operation start timing (one-by-one V blank start timing) is reached, the interrupt counter VCNT is cleared to zero (ST4).

After that, the steady operation is started, but in the present embodiment, first, it is determined whether or not the operation start condition for starting the steady operation is satisfied (ST5). Note that this determination timing is the timing of T1, T1+δ, T1+2δ,... Described in FIGS. 18 to 19, that is, the start timing of the vertical blanking period (VBLANK) of the display device DS1. The display timing of the display device DS2 is set during the initial setting (ST3) so as to be dependent on the display timing of the display device DS1.

Since the operation start condition determined at the start timing of the vertical blanking period (VBLANK) differs depending on whether the preloader 73 is used or not, first, an embodiment (FIG. 10) in which the preloader 73 is not used will be described. In this case, originally, the circuit configuration and the program are designed so that the internal operation of the VDP proceeds as shown in the time chart of FIG. That is, based on the display list DL1 completed in the operation cycle (T1), the drawing circuit 76 should end the drawing operation during the operation cycle (T1 to T1+δ). However, for example, like the display list DL3 completed in the operation cycle (T1+2δ) of FIG. 18A, it cannot be said that the drawing operation may not end during the operation cycle (T1+2δ to T1+3δ).

This situation is taken into consideration in the determination process of step ST5, and the effect control CPU 63 accesses the status register RGij (a kind of control register group 70) indicating the operation state of the drawing circuit 76, and at the timing of step ST5, The drawing circuit 76 determines whether or not the required operation has been completed. In the embodiment in which the preloader 73 is not used, for example, at timing T1+δ in FIG. 18A, the status information of the drawing register regarding the drawing circuit 76 is read-accessed and it is confirmed that the drawing operation based on the display list DL1 is completed. To do.

Then, when the operation start condition is not satisfied (nonconformity), the abnormality flag ER for counting the number of abnormalities is incremented, and the processes of steps ST6 to ST8 are skipped. The abnormality flag ER is determined along with other serious abnormality flags ABN in the processing of steps ST9 and ST10, and if the number of consecutive abnormalities is not large (ER≦2) on the assumption that the serious abnormality flag ABN is in the reset state, The production command analysis processing is executed as in the normal state (ST13).

In the effect command analysis processing (ST13), it is determined whether or not the control command CMD is received from the main control board 21, and when the control command CMD is received, the control command CMD is analyzed and necessary processing is executed. (ST13). Here, the necessary processing includes a start preparation processing for a new variation effect based on a control command CMD that instructs the start of variation effect, and an error notification start processing based on a control command CMD indicating an error occurrence.

Then, in order to return the WDT timer to the initial value, a prescribed 1 bit is written in the initial bit of the WDT control register (ST14), and the process returns to step ST4. The effect control CPU 63 does not need to output the clear pulse to the external device, and the advantage that it is sufficient to simply execute the Write command to the internal register is as described above.

The case where the operation start condition is not satisfied and the abnormality flag ER is ER≦2 has been described above. In such a case, the display area read by the display circuit 74 is toggle-switched in the operation cycle. The process (ST6) and the display list creation process (ST7) are skipped, and the effect scenario does not proceed (see ST8 to ST12). This is because the image data in the incomplete frame buffers FBa and FBb is not output. Therefore, for example, in the operation cycle (T1+3δ) of FIG. 18A, the image effect does not proceed, and a frame drop occurs in which the original screen (the screen based on DL2) is displayed again.

Here, in order to avoid dropped frames, a configuration of waiting until the operation start condition is satisfied can be considered. However, since there are many control processes (ST6 to ST12) to be executed by the effect control CPU 63 and it is necessary to secure the processing time for each, in the present embodiment, frame drop occurs when the operation start condition is not satisfied. There is.

However, even if a frame drop occurs, the progress of the image effect is delayed by about 1/30 to 2/30 seconds as compared with the lamp effect and the motor effect that are advanced by the interrupt process (FIG. 10B). Yes, the player does not notice this. Moreover, when the frame is dropped, the effect scenario processing (ST11) including the update processing of the effect counter EN and the voice progress processing (ST12) are also skipped, so that the reach effect, the notice effect, and the accessory that are started after that are performed. In the effect, there is no fear that the start timing of the image effect, the sound effect, the lamp effect, the motor effect, or the like will be shifted.

That is, in the production scenario, the start timings of the image production, the audio production, the lamp production, and the motor production and the content of the production to be executed thereafter are centrally managed, and the production counter EN updated only in the normal time Since the timing is controlled, the synchronization of various performances will not be lost. For example, if there is a performance operation that combines explosion sound, explosion image, character movement, and lamp flash operation, each performance operation described above will start correctly in synchronization even after a frame drop occurs. It

Although the comparatively slight abnormality has been described above, when the serious abnormality flag ABN is in the set state or when the number of continuous abnormalities is large (ER>2), the state is set to the infinite loop state after the determination in step ST10. There is. As a result, the down count operation of the WDT timer proceeds, the composite chip 50 including the effect control CPU 63 is abnormally reset, and then the initial processing (ST1 to ST3) is re-executed, so that an abnormal situation occurs. It is expected that the root cause will be resolved.

As described with reference to FIG. 4, at the time of this abnormality, the audio circuit SND is also abnormally reset, so that the image effect, the audio effect, the lamp effect, and the motor effect are all returned to the initial state. However, since these reset operations have no effect on the main control unit 21 and the payout control unit 25, there is no possibility that a big hit state disappears or a prize ball disappears.

Although the abnormal situation has been described above, in reality, the above-mentioned abnormalities rarely occur even in the case of a minor case, and after the processing of step ST5, the predetermined display register RGij (DSPACTL/DSPBCTL) is set. Based on this, the "display areas" of the frame buffers FBa and FBb that store the image data to be read by the display circuit 74A and the display circuit 74B are toggled (ST6). As described above, since “display area (0)” and “display area (1)” are defined in advance in the initial processing (ST3), in the processing of step ST6, the frame buffers FBa and FBb are It specifies which of the display area (0) and the display area (1) the "display area" of is.

By executing this step ST6, the display circuit 74A alternately outputs the image data from the index space 254 (display area (0)) and the index space 255 (display area (1)) for each operation cycle δ. The data is read out and the display device DS1 is driven. Similarly, the display circuit 74B alternately reads out the image data from the index space 251 (display area (0)) and the index space 252 (display area (1)) for each operation cycle δ to display the sub display device DS2. Will be driven. Note that the display circuit 74 actually performs READ access is limited to the effective data area in the display area (0)/display area (1) as described above.

In any case, in this embodiment, the "display area" is switched for each operation cycle, so that the display circuits 74A and 74B display the display devices DS1 and DS2 with respect to the image data completed by the drawing circuit 76 in the immediately previous operation cycle. The output processing to will be started. However, since the process of step ST5 is started from the start of the vertical blanking period (V blank) of the main display device DS1, the output process of the image data is actually started after the vertical blanking period is completed. Will be done. In FIG. 18A, the arrow shown in the column of the display circuit indicates the operation cycle of this output processing.

When the processing of step ST6 having the above meaning is completed, the effect control CPU 63 subsequently completes the display list DL specifying the image data to be output to the display device by the display circuit 74 in the next operation cycle. (ST7). Although not particularly limited, in this embodiment, the list buffer area (DL buffer BUF) of the RAM 59 is secured and the display list DL is completed there (see FIG. 8).

The display list DL is configured by listing a series of instruction commands in an appropriate order, and is configured to end by describing an EODL (End Of DL) command. Then, in this embodiment, in order to realize smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all instruction commands including the EODL command are multiplied by an integer N times a command length of 32 bits (N>0). It is limited only to the command command of. As described above, the instruction command configured by an integer N times 32 bits may include an insignificant bit (Don't care bit).

As described above, the display list DL of the embodiment is composed of only instruction commands having a command length of an integer N times 32 bits (N>0). Therefore, the data volume value (total data amount) of the entire display list DL is It is always an integral multiple of the minimum unit of command length (32 bits=4 bytes). Further, in this embodiment, in consideration of the minimum data amount Dmin of the data transfer circuit 72, the data volume value of the display list DL is an integral multiple (1 or more) of the minimum data amount Dmin, and the instruction command It is adjusted to be an integral multiple of the minimum unit (4 bytes). For example, if Dmin=256 bytes, the data volume value of the display list DL is adjusted to any value of 256 bytes, 512 bytes,...

Here, it is also suitable to adjust to 256 bytes or 512 bytes as appropriate according to the complexity of the effect contents, but in this embodiment, there are two display devices and the sub display device DS2 is The data volume value of the display list DL is constantly adjusted to 256 bytes in consideration of not executing a complicated image effect.

However, this method is not limited in any way, and is adjusted to 512 bytes or 768 bytes when there are three or more display devices or in the case of a gaming machine which executes complicated image effects including the sub-display device DS2. To be done. In addition, during a normal effect, the data volume value of the display list DL is adjusted to 256 bytes, and only when a special effect is executed, the data volume value of the display list DL is adjusted to 512 bytes or 768 bytes. Is also suitable.

However, in the case of the present embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) defined in advance in each operation cycle δ. As the adjustment method, a simple method (A) of filling a 32-bit long EODL command with a 32-bit long NOP (No Operation) command for compensating for the shortage area, or after filling the shortage area with a 32-bit long NOP command Finally, the standard method (B) in which a 32-bit EODL command is described can be considered. It should be noted that the data volume value (total data amount) of the display list DL is terminated by the EODL command without any adjustment, and dummy data is additionally transferred during the operation of the data transfer circuit 72 to be an integral multiple of the minimum data amount Dmin. A non-adjustment method (C) that secures the transfer amount of

Here, in the case of adopting the standard method (B), first, the command counter CNT is initialized to a specified value (64-1 corresponding to 256 bytes), and every time a significant instruction command is written to the DL buffer area BUF. In addition, a method is conceivable in which the command counter CNT is appropriately subtracted, and when a series of significant instruction commands have been written, the NOP command is described until the command counter CNT becomes zero, and the EODL command is described last. In the case of the present embodiment, since the command length of the instruction command is limited to an integer N times 32 bits (N>0), the above processing is easy, and the subtraction processing of the command counter CNT is an integer. The subtraction process corresponds to N.

On the other hand, when adopting the simple method (A), it is sufficient to first fill the entire list buffer area (DL buffer BUF) with the NOP command when creating the display list DL. Seems better. From the viewpoint of simplicity, the non-adjustment method (C) also seems to be excellent. However, in this embodiment, the standard method (B) is basically adopted, and the actual data amount from the head of the display list DL to the EODL command, that is, the data amount up to the EODL command is always the data transfer circuit 72. Is adjusted to be an integral multiple of the minimum data amount Dmin.

This is in consideration of the embodiment utilizing the preloader 73. If the simple method (A) or the non-adjustment method (C) is adopted, the actual data amount of the display list DL up to the EODL command is random. This is because the value becomes a value, and a problem occurs when the rewrite list DL′ rewritten by the preloader 73 is transferred to the DRAM 54 or when the rewrite list DL′ is transferred from the DRAM 54 to the drawing circuit 76. The ChA control circuit 72a of the data transfer circuit 72 functions when transferring the rewrite list DL′ to the DRAM 54, and the ChB control circuit 72b functions when transferring the rewrite list DL′ to the drawing circuit 76 (see FIG. 16). In any case, only the rewrite list DL' up to the EODL command is transferred.

The advantages of the standard method (B) of adjusting the data volume value of the display list DL have been described above, but in the embodiment in which the preloader 73 is not used, the issued display list DL is only processed by the drawing circuit 76. Therefore, the use of the simplified method (A) and the non-adjustment method (C) is not prohibited at all.

However, in the following description, the details of the display list DL will be described based on FIG. 11 on the assumption that the standard method (B) is used in principle regardless of whether or not the preloader 73 is used.

Although not particularly limited, in the present embodiment, the display list DL first describes the instruction command string (L11 to L16) related to the main display device DS1, and then the instruction command string (L17 to L20) related to the sub display device DS2. I am trying to describe it. Also, the standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Note that FIG. 11 also shows the procedure in which the effect control CPU 63 writes the instruction command in the list buffer area of the RAM 59 and the operation of the drawing circuit 76 based on the display list DL in effect.

As shown in FIG. 11, at the top of the display list DL, an environment setting instruction command (SETDAVR) is described, and the upper left base point address (X, Y) on the index space IDX is set for the frame buffer FBa of the display device DS1. Specify (L11). As described with reference to FIG. 7A, in this embodiment, a pair of frame buffers FBa are secured in the arbitrary area (c) for the display device DS1. Then, normally, by setting the base point address (X, Y)=(0, 0) corresponding to the effective data area for the display circuit 74, the drawing circuit 76 is utilized from the head position of the frame buffer FBa. ..

In FIG. 7C, the actual drawing area on the lower left side is labeled L11. This means that the actual drawing area on the frame buffer FBa is changed to the base address (0, 0) means that it was specified to start from the position. However, the vertical and horizontal dimensions of the actual drawing area and the index numbers that specifically specify the actual drawing area have not yet been decided, and are decided by an instruction command (SETINDEX) L13 described later. The instruction command L11 also specifies whether or not the Z buffer is used.

Next, set the upper left base point coordinates (Xs, Ys) and the lower right diagonal point coordinates (Xe, Ye) in the virtual drawing space using the environment setting system command (SETDAVF), and set W×H dimensions. The drawing area of is defined (L12). Here, the virtual drawing space is a virtual two-dimensional space of ±8192 in the X direction and ±8192 in the Y direction that can be drawn by a drawing instruction command (SPRITE command or the like) (see FIG. 7C). ..

By this instruction command L12 (SETDAVF), the virtual drawing space is divided into a drawing area where the drawing contents are actually reflected on the display device DS1 and other non-drawing areas. Further, the instruction command L12 (SETDAVF) associates the actual drawing area whose start position (base point address) is specified by the instruction command L11 with the drawing area in the virtual drawing space.

In other words, the instruction command L12 defines a W×H actual drawing area starting from the base point address, which corresponds to the drawing area in the virtual drawing space, in the frame buffer FBa (index space is undecided). It will be. Therefore, the drawing area specified by the instruction command L12 must be equal to or smaller than the horizontal size of the frame buffer FBa. Usually, the drawing area and the actual drawing area are defined to have the same size as the effective data area (FIG. 10D) for the display circuit 74.

After the drawing circuit 76 executes the instruction commands L11 and L12, only the drawing contents included in the drawing area among the drawing contents drawn in the virtual drawing space are reflected in the actual drawing area of the frame buffer FBa. become. Therefore, the drawing contents of the portion protruding from the drawing area and the portion described as the work area in FIG. 7C are not reflected as they are in the frame buffer. When a work area is secured in the virtual drawing space, a non-drawing area in the virtual drawing space is used.

Next, in the current operation cycle, the drawing circuit 76 defines where to draw the drawing content to be drawn based on the display list DL to be completed (L13). Specifically, with respect to the frame buffer FBa of the display device DS1 having the double buffer configuration, the index space IDX that is the "writing area" of the drawing content based on the display list DL this time is specified (L13). Specifically, by the SET INDEX command which is a texture setting type command, (1) the frame buffer FBa is secured in an arbitrary area, and (2) an arbitrary index space IDX _N to be a "writing area" is set. The index number N on the area is specified.

For example, when N=255 is specified by the instruction command L13, the actual drawing area corresponding to the drawing area defined in the virtual drawing space is specifically the frame buffer FBa having the double buffer structure. It is defined as being the index space IDX ₂₅₅ .

In the case of the present embodiment, the index number of the frame buffer FBa is 255 or 254 (FIG. 7(a)), and either of the toggled switching is designated (L13). The index number is the index number of the display area (0)/(1) that is not designated in step ST6 of the main process. For example, in the process of step ST6, when the display area (0) is designated for the display circuit 74, the display area (1) becomes the “writing area” for the drawing circuit 76.

As described above, after the correspondence between the actual drawing area (W×H logical space) and the drawing area (W×H virtual space) is generally defined by the instruction commands L11 and L12, By the instruction command L13 (SET INDEX) that specifically specifies the index space IDX, the W×H virtual space is associated with the W×H logical space in the specific index space IDX.

In other words, in the future, based on a series of instruction commands, the contents virtually drawn in the W×H virtual space are the contents of the VDP internal that defines the correspondence between the virtual space and the real address of the internal VRAM 71. The image data of the built-in VRAM 71 (frame buffer) is obtained based on the conversion table.

Subsequently, as the "writing area", an instruction command for executing the frame buffer clear processing for filling the specified index space IDX with, for example, black is described (ST14, ST15). This is nothing but the erasing process of the image data written in the frame buffer FBa two operation periods ago.

Specifically, for example, black is selected by the SETFCOLOR command, which is one of the environment setting commands, and the rectangular area is defined by the RECTANGLE command, which is a primitive drawing system command. The RECTANGLE command specifies the XY coordinates of the upper left end point and the lower right end point of the drawing area (virtual space corresponding to the frame buffer FBa) set in the virtual drawing space (see FIG. 7C). ..

Since the drawing preparation processing is completed by the above processing, next, an instruction command for drawing an appropriate texture such as a still image or one frame of a moving image in the virtual drawing space is listed. Typically, first, the index space IDX, which is the expansion destination of the texture, is specified by the SETINDEX command of the texture setting system, and then the TXLOAD command that is the instruction command of the texture loading system is described, and the predetermined read from the CGROM 55 The texture is described in the display list DL so as to be expanded in a predetermined index space IDX.

As described above, in this embodiment, the background moving image is composed of the IP stream moving image. So, for example, for the background video, specify the index space IDX that should be expanded as the index space IDX ₀ of the page area (b) with the SETINDEX command of the texture setting system, and then describe the TXLOAD command of the texture loading system. To do. In the TXLOAD command, it is necessary to specify the start address (texture source address) of the CGROM 55 and the expanded data size (horizontal×vertical) for the moving image frame to be loaded this time.

When the above TXLOAD command is executed in the VDP circuit 52, one moving image frame (texture) of the background moving image is first acquired in the AAC area (a), and then the page area (texture) is automatically set by the GDEC 75 which is automatically activated. It is expanded to the index space IDX ₀ of b). Next, this one moving image frame is drawn in the virtual drawing space. In this case, the SET INDEX command (texture setting system) may be used to set that "the index space IDX ₀ of the page area (b) is the texture to be processed thereafter", but it is processed continuously after the TXLOAD command. In this case, the description of this SET INDEX command can be omitted.

In any case, in a state in which "the index space IDX ₀ of the page area (b) is the texture to be processed thereafter" is set, the parameter for the α blending process is set next. Describe an appropriate command command for the inter-drawing calculation system. The α blending process relates to a transparency/translucency process of an image already written in the drawing area (frame buffer FBa) and an image to be overwritten. Therefore, unlike the moving image frame of the background moving image, it is not necessary to use the instruction command of the inter-drawing calculation system in the first drawing operation.

Then, the "texture of index space IDX ₀ of the page area (b) (one moving image frame of the background video)" is set in the virtual drawing space (rectangular Destination area) by the SPRITE command which is an instruction command of the primitive drawing system. Describe the SPRITE command to draw in. In the SPRITE command, it is necessary to specify the upper left end point and the lower right end point of the Destination area in the virtual drawing space.

This Destination area is the whole or a part of the drawing area (the virtual space defined on the virtual drawing space) associated with the actual drawing area (FBa) in advance by the instruction commands L11 and L12. However, since the background moving image is usually drawn on the entire display screen, the Destination area in such a case is the entire drawing area or more. Note that the case where the Destination area is larger than the entire drawing area is, for example, when the background moving image is zoomed up.

With the above processing, the drawing of the video frame of the background video is completed, so next, list the instruction commands such as texture load system, texture setting system, inter-drawing operation system, primitive drawing system command in an appropriate order, The display list DL is configured to draw various textures on the background moving image. As described above, since a large number of moving images are required at the time of changing performance, in that case, the index table control system instruction is issued to increase the index space IDX for the page area (b) of the built-in VRAM 71. The command (NEWPIX) will be described.

For example, regarding the second IP stream moving image, after the additional index space IDX ₁ is secured in the page area (b) by the NEWPIX command, this index space IDX ₁ is specified (SETINDEX), and the second Instruct the development of one frame of the video (TXLOAD), and place the developed texture in the proper place in the drawing area (SPRITE). Normally, the Destination area in this case is a part of the drawing area.

This is the same as the following, and after the index space IDX _k is secured by the NEWPIX command one after another, if a plurality of IP streams are drawn in the drawing area while performing appropriate α blending processing, the drawing content in the drawing area will be The image data is sequentially stored in the frame buffer FBa, which is an actual drawing area. When rendering a plurality of N IP stream moving images, a plurality N of index spaces are functioning in the page area (b).

Then, when a series of variation effects are completed, the DELPIX command is used to release the index space IDX that is considered unnecessary among the many index spaces IDX _{1 to} IDX _k secured in the page area (b). The unnecessary index space IDX may be deleted.

When drawing a still image or an I-stream moving image, the SETINDEX command is used to specify that these textures are to be decoded in the AAC area (a), and then the TXLOAD command is executed. The texture acquired in (a) is then developed in the ACC area (a) by the GDEC 75 which is automatically activated. Then, the developed texture may be drawn at a proper place in the drawing area by the SPRITE command. The first AAC area (a1) or the second AAC area (a2) is used depending on whether or not the cache hit function is used.

In the above description, each texture is directly drawn in the drawing area of the DS1 for the main display device, but the operation is not necessarily limited to this. For example, if an appropriate drawing area is provided without overlapping with the drawing area already reserved for the display device DS1 (FIG. 7C) and this drawing area is associated with the work area of the built-in VRAM 71, it becomes an intermediate value. An appropriate rendering image can be completed by constructing various drawing areas. Here, the reason why the drawing area for the display device DS1 does not overlap is that the subsequent correspondence setting is prioritized for the overlapping area, and the drawing content in that area is not reflected in the frame buffer FBa.

As shown in FIG. 7C, the work area of this embodiment is the index space IDX ₀ in the arbitrary area (c). Then, at an effect timing using this work area, an instruction command for associating the drawing area for the effect image (see FIG. 7C) with the work area (actual drawing area of the index space IDX ₀ ) in advance. List the columns (SETDAVR, SETDAVF, SETINDEX). As shown in FIG. 7C, the drawing area for the effect image is secured in an area not included in the drawing area for the main display device DS1.

Then, after that, an instruction command similar to the instruction command row L16 regarding the frame buffer FBa is listed, and an appropriate effect image may be completed in the index space IDX ₀ . In the case of the present embodiment, since the effect image is composed of a still image, an instruction command (SETINDEX) is described so that the decoded data is expanded in the first AAC area (a1), and then the index space IDX ₀ The primitive drawing command (SPRITE) that uses the destination in the drawing area as the destination will be used. It should be noted that such an operation is repeated once or a plurality of times depending on the effect contents.

Then, after the index space IDX ₀ that has completed the effect image is positioned as a texture (SETINDEX), the effect image (texture) of the index space IDX ₀ is drawn in the drawing area of the DS1 for the main display device by the SPRITE command. Just do it. In such a case, it is conceivable that the effect image of the index space IDX ₀ is decomposed into triangular drawing primitives, rotated at an appropriate angle, and then drawn in the drawing area. The rotation angle of the texture is associated with, for example, the reliability of the notice effect.

Although the instruction command sequence (L11 to L16) for completing one frame of the main display device DS1 has been described above, the instruction command sequence (L17 to L12) for completing one frame of the sub display device DS2 is also described. It is the same. That is, the start XY coordinates of the frame buffer FBb are specified (L17) is defined (usually X=0, Y=0), and the sub display device DS2 for the virtual drawing space shown in FIG. The drawing area is defined (L18).

By the way, in the present embodiment, after the generation of the image data for the main display device DS1 is completed, the process proceeds to the generation process for the sub display device DS2, so the drawing area for the sub display device DS2 is for the main display device DS1. There is no problem even if the drawing area overlaps with the drawing area, and the drawing area can be freely set. Therefore, when developing a program for generating the display list DL, for example, when an appropriate texture is pasted to a newly set drawing area with the SPRITE command, setting of the operation parameter (Destination area) of the SPRITE command, etc. It can be stylized to some extent.

When the definition of such an arbitrary drawing area is completed (L18), next, for the frame buffer FBb of the display device DS2 having the double buffer configuration, an index space to be a "writing area" of the drawing content based on the current display list DL. The IDX is specified (L19). The index number of this index space IDX is the index number of the frame buffer FBb that does not correspond to the display area (0)/(1) designated in step ST6 of the main processing.

Then, thereafter, the instruction command strings L20 to L22 for the sub display device DS2 are listed similarly to the instruction command strings L14 to L16 for the main display device DS1. Also, the effect image completed in the index space IDX ₀ can be used.

As described above, in the present embodiment, all of the instruction commands of L11 to L22 forming the display list DL are limited to those having a command length of an integral multiple of 32 bits. Then, as described above, the data volume value (total data amount) of the display list DL of the present embodiment is adjusted to a fixed length (256 bytes), and the necessary number of NOP commands (L23) that are dummy commands are added. Then, it is terminated by the EODL command (L24). That is, in the embodiment of FIG. 11, the standard method (B) described above is adopted.

However, even if the standard method (B) is adopted, it is not always necessary to fix the total data amount of the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, when the total data amount of the display list DL excluding the NOP command exceeds 256 bytes (for example, a special performance period), the NOP command is added to the total data amount of the display list DL. , 512 bytes or more, adjusted to N×256 bytes. Note that, when the standard method (B) is adopted, the end of N×256 bytes is terminated by the EODL command, as described above.

Although the configuration of the display list DL has been described in detail above, the effect control CPU 63 issues the completed display list DL having a fixed byte length to the VDP circuit (ST7 to ST8). FIG. 12 is a flowchart illustrating a DL issuing process (ST8 in FIG. 10) in which the effect control CPU 63 directly Write-accesses the transfer port register TR_PORT of the transfer circuit 72 to issue the display list DL to the drawing circuit 76. The transfer port register TR_PORT is a kind of the data transfer register RGij that defines the operation content of the data transfer circuit 72.

In order to realize the DL issuing process, first, it is necessary to set necessary setting values in a plurality of data transfer registers RGij that define the operation content of the data transfer circuit 72. Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission via the inside of the data transfer circuit 72 are specified in a predetermined data transfer register RGij. Although the setting contents are not particularly limited, here, when the data transfer operation is executed while checking the remaining amount of the FIFO buffer with respect to the CPUIF controller 56 via the ChB control circuit 72b and the CPU bus controller 72d. Set (ST20). In the following description, the ChB control circuit 72b may be abbreviated as "transfer circuit ChB" for convenience.

Next, the total transfer size is set in a predetermined data transfer register RGij. As described above, in this embodiment, the total amount of data in the display list DL is adjusted to an integral multiple of 256 bytes, so that value is set. The total data amount=256×N is an integer N times the minimum data amount Dmin of the data transfer circuit 72. Normally, the multiple N is 1 or 2, but in the following description, N=1 will be described.

Here, since the transfer port register TR_PORT (hereinafter, may be abbreviated as a transfer port) is a register having a length of 32 bits, the effect control CPU 63 executes a register Write operation to the transfer port TR_PORT every 32 bits. It will be. Therefore, the value of the management counter CN that manages the number of register writes is initialized to 64 (ST21). When the non-adjustment method (C) is adopted, the data transfer amount that is an integral multiple of the minimum data amount Dmin is determined and the management counter CN is set at this timing.

Since the initial setting is completed by the above processing, next, the data transfer operation via the transfer circuit ChB is set to the start state (ST22), and the setting to the predetermined drawing register RGij defining the operation of the drawing circuit 76 is performed. The drawing operation is started based on the value (ST23). As a result, after that, the effect control CPU 63 secures a quick and smooth Analyze process by the drawing circuit 76 (display list analyzer) for the instruction command sequence for performing the register Write operation to the transfer port TR_PORT.

Note that the prompt and smooth Analyze processing effectively contributes to the fact that the command commands listed in the display list DL are limited to command commands having a command length of 32 bits, which is an integral multiple. Timings t1, t2, t3, and t4 in FIG. 18A indicate the operation timing of step ST23. Since the display list DL issuing process (ST8) ends quickly, FIGS. 18 to 19 do not describe the time width required for the issuing process.

Then, it is confirmed whether the setting of step ST22 worked (ST24). This is because the initial setting of each part of the data transfer circuit 72 requires more processing time than the register write operation (setting operation) by the effect control CPU 63, and therefore, the subsequent instruction is given to the data transfer circuit 72 in an incomplete state. Because there is no. If the operation start state is not reached even after waiting for a predetermined time, the serious abnormality flag ABN is set and the DL issuing process is terminated (ST25). As a result, thereafter, the watchdog timer 58 functions and the composite chip 50 is abnormally reset (ST10).

However, normally, the setting in step ST22 is completed quickly, and then, after confirming that the FIFO buffer of the CPU bus control unit 72d (32 bits×130 stages) is not full (ST26). , Instructing commands are written in the transfer port TR_PORT line by line in order from the first line forming the display list DL (ST28).

Then, while decrementing the management counter CN (ST29), the processes of steps ST26 to ST29 are repeated (ST30) until the management counter CN becomes zero. In the case of this embodiment, since the minimum data amount Dmin is defined in the data transfer circuit 72, the data transfer operation is executed at the timing when the minimum data amount Dmin is accumulated in the FIFO buffer, and the intermittent operation is performed. Transfer operation.

In any case, in this embodiment, the DL issuing process (ST28) is completed promptly, but if the setting contents in the VDP register RGij are inconsistent due to the influence of noise or the like, in step ST26. In the determination, the state of the FIFO buffer Full may not be resolved even after waiting for a predetermined time. Then, in such a case, the initialization data is set in a predetermined VDP register RGij to initialize the drawing circuit 76 and the data transfer circuit 72, and then the serious abnormality flag ABN is set to execute the DL issuing process. Finish (ST27).

By the way, at this timing, the data transfer circuit 72 and the drawing circuit 76 have already started their operations and have completed a certain amount of processing, so the contents of the drawing register RGij are set for the initialization processing of the drawing circuit 76. While maintaining the state, (1) set all internal parameters that may be set by the display list DL to initial values, (2) set all internal control circuits to initial states, (3) This includes initializing the GDEC 75 and (4) initializing the cache state of the AAC area. Similarly, the initialization processing of the data transfer circuit 72 includes the initialization processing of the entire data transfer until then, such as clearing the FIFO buffer. As a result, the status information indicating the operation state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

Although the contents of the drawing register RGij are maintained in the initialization process of step ST27 described above, the contents of a predetermined drawing register may be initialized. The predetermined drawing register that is cleared to the initial value includes (a) an execution control register that sets the start of drawing execution (see ST23 in FIG. 12), (b) a status register that indicates the execution status of the drawing circuit 76, and ( c) Contains a status register that identifies the position of the display list currently being processed.

In any case, as a result of setting the serious abnormality flag ABN, the watchdog timer 58 then functions and the composite chip 50 is abnormally reset (ST10), so that the drawing circuit 76 and the data transfer circuit 72 are initialized. Processing is not always essential. On the other hand, when the drawing circuit 76 and the data transfer circuit 72 are initialized, as a result, abnormal recovery can be expected, so the process returns to step ST20 without setting the serious abnormal flag ABN, and the DL issuing process is restarted. It is also suitable to carry out.

This point is the same in the process of step ST25, and it is preferable that the data transfer circuit 72 and the drawing circuit 76 are initialized and then the process returns to step ST20 without setting the serious abnormality flag ABN. However, in such a case, the number of re-executions of the DL issuance process is counted, and if the number of re-executions exceeds the limit value, the serious abnormality flag ABN is set and the DL issuance process is terminated.

FIG. 12B is a diagram for confirming the normal operation state. As illustrated, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and the operation based on each instruction command is executed. This operation is executed in parallel with the issue processing of the display list DL and the data transfer operation (ST26 to ST30) of the data transfer circuit 72.

For example, when the instruction command (TXLOAD) is executed, the required texture is read from the CGROM 55 and acquired in the AAC area (a), and then the GDEC 75 is automatically activated to execute the decoding operation and Later data is expanded in a predetermined index space. Further, depending on the instruction command, the geometry engine 77 or the like functions, but in any case, the image data corresponding to the display list DL is completed in the frame buffers FBa and FBb by the cooperation of the respective units of the drawing circuit 76. Will be.

Next, the case of issuing the display list DL via the DMAC circuit 60 will be described with reference to FIG. Although not limited in any way, of the first to fourth DMA channels built in the DMAC circuit 60, the third DMA channel is used.

In the embodiment of FIG. 13, first, a clear value is set in each of the predetermined data transfer register RGij and the predetermined drawing register RGij, and the data transfer circuit 72 and the drawing circuit 76 are initialized (ST20). This process is the same as the error process of step ST27 of FIG. 12, the internal circuit of the data transfer circuit 72 including the FIFO buffer is initialized, and the status bit of the data transfer register indicating the progress of the data transfer is initialized. Thus, the bit indicating that the entire data transfer is being initialized has a predetermined value.

The same applies to the drawing circuit 76. (1) Setting the internal parameters to the initial values, (2) Setting the internal control circuit to the initial state, (3) Initializing the GDEC 75, (4) ) A process for initializing the cache state of the AAC area is included. Further, also in the initialization processing of the drawing circuit (ST20 in FIG. 13), the above-mentioned predetermined drawing register RGij may be initialized. In the process of FIG. 12, such an initialization process may be executed first.

In the process of FIG. 13, next, it is confirmed that the initialization process is normally completed by reading a predetermined status register RGij that specifies the operation states of the data transfer circuit 72 and the drawing circuit 76 (ST21). If the initialization cannot be performed, the serious abnormality flag ABN is set and the process is terminated (ST22). However, such a situation hardly occurs in reality.

Next, the transfer operation mode of the data transfer circuit 72 and the transmission via the data transfer circuit 72 are set in a predetermined data transfer register RGij. The setting content is not particularly limited, but here, it is set according to the setting in the DMAC circuit 60 regarding the passage from the CPUIF unit 56 through the ChB control circuit 72b and the transfer protocol to the CPU bus control unit 72d (ST23. ).

Next, the total transfer size is set in a predetermined data transfer register RGij. As in the case of FIG. 12, the total amount of data=256. When the non-adjustment method (C) is adopted, the transfer total size that is an integral multiple of the minimum data amount Dmin is determined and set at this timing. Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST25). Timings t1, t2, t3, t4 in FIG. 18A are also operation timings in step ST25. Then, after the operation of the DMAC circuit 60 is started (ST26), the data transfer operation of the data transfer circuit 72 is started (ST27).

The process for starting the operation of the DMAC circuit 60 is as shown in FIG. 13B. First, in the state where the DMAC transfer is prohibited, the completion of the transfer of one cycle of data transfer unit (1 operand) ( ST40). The detailed operation content is the same as the process shown in FIG. 14, and is divided into a process of setting the DMAC transfer to be prohibited (ST53) and a standby process thereafter (ST54).

Such processing is provided (1) In another embodiment, the DMAC circuit 60 (third DMA channel) may be used in the main processing and the timer interrupt processing (FIG. 10), and (2) In another embodiment in which the process of step ST5 of FIG. 10 is not provided, the DMAC circuit 60 that has started issuing the display list DL may not be able to complete the DL issuing operation within its operation cycle (δ). It is to consider what to obtain.

In the exceptional situation as described above, if a new setting value (inconsistent setting value or the like) is additionally set to the operating DMAC circuit 60, normal DMA operation is not guaranteed at all, and serious trouble occurs. Although there is a concern, provision of the process of step ST40 ensures the normal operation based on the subsequent set value. That is, even in the modified embodiment in which this embodiment is partially modified, the normal DMA operation thereafter can be realized regardless of the preceding trouble.

If the process of step ST40 having the above meaning is executed, then the operating condition of the DMAC circuit 60 is set (ST41). Specifically, as shown in FIG. 6, the cycle steal transfer mode is selected, and one operand transfer is 32 bit transfer×2 times. Further, the Source address is an address of the list buffer area (DL buffer BUF) of the RAM 59 and therefore should be recognized as increasing sequentially. On the other hand, the Destination address is a transfer port TR_PORT and should be a fixed value. ..

Next, the head address of the DL buffer BUF of the RAM 59 is set in a predetermined operation control register that defines the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT which is the transfer destination address is set (ST43). .. Further, the total transfer size, that is, the total data amount of the display list DL is set to 256 bytes (ST44), and then the DMA operation of the DMAC circuit 60 is started (ST45).

By the way, the description so far is based on the assumption that the actual bit length of the instruction command is all an integral multiple of 32 bits. However, since the configurations of the display list DL and the instruction command are not necessarily limited, such a case will be described below.

For example, when the total data amount X of the display list DL is an arbitrary value X that is not an integral multiple of 32 bits, including the case where the above-described non-adjustment method (C) is adopted, in the process of step ST44, the arbitrary value X is set. Is adjusted to an appropriate transfer amount MOD, and then a transfer total size setting process is executed. Here, the appropriate transfer amount MOD is defined based on the setting content for one-operand transfer and the minimum data amount Dmin (byte) of the data transfer circuit 72.

Specifically, if the one-operand transfer setting is N bytes×M times, the transfer amount MOD is adjusted to an integer multiple of N×M (bytes) and an integer multiple of Dmin (bytes). To be done. For example, if N×M=8×4 and Dmin=256, the arbitrary value X (=300) bytes is adjusted to the transfer amount MOD (=512) bytes.

As described above, including the general theory, in the DMA operation of the DMAC circuit 60, the cycle steal transfer operation as shown in FIG. 6 is started, and the display list DL of the embodiment does not particularly hinder the operation of the CPU. In this case, the data is transferred to the transfer port TR_PORT every 32 bits. Then, the transferred data is transferred to the drawing circuit 76 via the transfer circuit ChB.

In order to realize such an operation, in this embodiment, following the processing of step ST45, the transfer operation of the data transfer circuit 72 is started and the processing ends (ST27). After that, the data transfer circuit 72 receives the instruction command string of the display list DL from the DMAC circuit 60 with the minimum data amount Dmin as one unit, and transfers this to the drawing circuit 76. Then, the drawing circuit 76 executes the drawing operation based on the instruction command of the display list DL. Therefore, after the processing of step ST27, the effect control CPU 63 can start the processing of step ST11 of FIG. 10, and in parallel with the drawing operation by the VDP circuit 52 (DL issuing processing by the DMAC circuit 60), the audio effect is produced. It is possible to control the lamp effect and the motor effect.

FIG. 13C shows the contents of this operation. Prior to the DMA transfer, the operation of the drawing circuit is started (ST25), and the display list analyzer of the drawing circuit 76 executes the Analyze processing quickly and smoothly, and in addition to the operations of the GDEC 75, the geometry engine 77, etc. Based on this, in the frame buffers FBa and FBb, image data for one frame is generated for each of the display devices DS1 and DS2.

By the way, the configuration of FIG. 13 in which the DL issuing process ends in the process of step ST27 is not necessarily limited. For example, as shown in FIGS. 20 to 21, when the other CPU controls the sound effect, the lamp effect, and the motor effect, the normal operation of the DMAC circuit 60 and the data transfer circuit 72 is performed after the process of step ST27. Is preferably confirmed. FIG. 14 is a flowchart illustrating an operation subsequent to step ST27 in FIG. 13 and for confirming the normal operation.

First, referring to a predetermined status register, it is confirmed that the transfer operation of the DMAC circuit 60 is normally completed (ST50). Also, it is confirmed that the data transfer circuit 72 has completed the transfer operation (ST51). Normally, the DL issuing process of FIG. 13 is completed through such a route.

On the other hand, even after waiting for a predetermined time. When the operation of the DMAC circuit 60 is not completed, or when the data transfer circuit 72 is not completed the transfer operation, a clear value is set in a predetermined VDP register RGij for the drawing circuit 76 and the data transfer circuit 72. Then, the DL issuing process is initialized (ST52). This is an operation based on the fact that the issuing process of the display list DL is not normally completed, and specifically, the same contents as the error process of step ST27 of FIG. 12 and the initial process of step ST20 of FIG. is there.

That is, also in this case, since the drawing circuit 76 has already started its operation and has completed some processing, the initialization processing of the drawing circuit 76 may be set by (1) the display list DL. To set all internal parameters with initial values to (2) to set all internal control circuits to initial state, (3) to initialize GDEC75, (4) to initialize cache state of AAC area It is included to convert.

Next, the new DMA transfer operation is prohibited (ST53), and the completion of the transfer operation of the one operand being executed is waited (ST54). As described above, in the present embodiment, 32 bits transfer×2 times is used as one operand, and this is to avoid sudden initialization of the operating DMAC circuit 60.

When this preparatory work is completed, a clear value is set in a predetermined operation control register that defines the operation of the DMAC circuit 60, and the DMAC circuit 60 is initialized (ST52). Then, the serious abnormality flag ABN is set and the DL issuing process is ended. In this case, since abnormal recovery can be expected by the processing of steps ST52 and ST55, it is also preferable to return to step ST20 of FIG. 13 and re-execute the DL issuing processing without setting the serious abnormal flag ABN. is there. However, it is necessary to count the number of re-executions of the DL issuing process (ST23 to ST27) and, if the number of re-executions exceeds the limit value, set the serious abnormality flag ABN and end the DL issuing process.

Next, main processing when using the preloader 73 will be described with reference to FIG. The process of FIG. 15 is similar to the process of FIG. 10, but first, the contents of the start condition determination (ST5') are different. That is, in the embodiment using the preloader, the status information of the drawing circuit 76 and the preloader 73 is read-accessed at the start of each operation cycle, and the drawing operation based on the display list DL1 is completed, and the display list DL2. It is confirmed that the preload operation based on (3) is completed (ST5').

As shown in the time chart of FIG. 19A, the preloader 76, for example, based on the display list DL1 issued in the operation cycle (T1), performs the prefetch operation (preload operation) during the operation cycle (T1 to T1+δ). Should have finished. Further, the drawing circuit 76 should have completed the drawing operation based on the display list DL1 during the operation cycle (T1+δ to T1+2δ), for example, based on the operation start command instructed in the operation cycle (T1+δ).

Therefore, in (ST5'), the status information of the VDP register RGij relating to the drawing circuit 76 and the preloader 73 is read-accessed to confirm the above normal operation. FIG. 19A shows a state in which the normal operation is confirmed at the determination timings of the operation cycles T1, T1+δ, T1+2δ, and T1+4δ, but the preload operation is not completed at the determination timings of the operation cycle T1+3δ. ..

Then, at the time of such an abnormality, the abnormality flag ER is incremented (ER=ER+1), and the process proceeds to step ST9. Therefore, frame drop occurs as in the case of the embodiment of FIG. That is, since the display area switching process (ST6) is skipped, the same screen is displayed again. The operation period (T1+3δ to T1+4δ) shown in FIG. 18A shows the operation state.

If the start condition is not satisfied in the determination in step ST5′, the drawing circuit 76 is not operated because the drawing operation start instruction (PT10) based on the rewriting list DL′ is not executed. This is the state, and no new display list is generated. Note that in FIG. 19A, timings t0, t2, and t4 indicate the operation timing of the drawing operation start instruction (PT10), more accurately, the timing of step ST26 in FIG.

The case where the determination in step ST5′ is non-conforming has been described above. However, in the normal case, after the display areas of the frame buffers FBa and FBb are toggled (ST6), the rewriting list DL is written to the drawing circuit 76. The drawing operation based on'is started (PT10). The specific content is as shown in FIG. 16, and the drawing circuit 76 is controlled from the DL buffer BUF′ of the external DRAM 54 via the data transfer circuit 72 (transfer circuit ChB) under the control of the effect control CPU 63. The rewriting list DL' is acquired and the drawing operation is executed.

Prior to explaining the flowchart of FIG. 16 that realizes this operation, when the operation of the preloader 73 is confirmed, the preloader 73 determines the prefetch operation (preload) of the CGROM 55 based on the display list DL acquired one operation cycle before. Has been completed, and the prefetched data has already been stored in the preload area secured in the external DRAM 54. In addition, the source address of the texture load command (TXLOAD) described in the display list DL is rewritten to the address of the preload area, and is stored in the DL buffer BUF′ of the external DRAM 54 as the rewriting list DL′. ing.

In this rewriting process, the total amount of data in the display list DL does not change, and the total amount of data in the rewriting list DL' is the same as that in the display list DL. The display list DL is created by the standard method (B), and the end of the rewrite list DL' is the EODL command as in the case of the display list DL.

Referring to FIG. 16 based on the above, the effect control CPU 63 first sets the clear values in the predetermined data transfer register RGij and the predetermined drawing register RGij, and sets the data transfer circuit 72 and the drawing circuit 76. Initialize (ST20). This process has the same contents as the process of ST20 in FIG. Next, it is confirmed that the initialization processing has been normally completed (ST21), and if the initialization is not completed even if a predetermined time elapses, the serious abnormality flag ABN is set and the processing is terminated ( ST22).

Normally, the initialization of the data transfer circuit 72 and the drawing circuit 76 is normally completed, so that the transmission via the inside of the data transfer circuit 72 is set in a predetermined data transfer register RGij (ST23). Specifically, it is set to transfer data from the external DRAM 54 to the drawing circuit 76 via the ChB control circuit 72b (ST23). Next, the start address of the DL buffer BUF' of the external DRAM 54 in which the rewrite list DL' is stored is set in a predetermined data transfer register RGij (ST24).

Further, the total transfer size of this rewrite list DL' is set in a predetermined data transfer register RGij (ST25). As described above, the total amount of data in the rewrite list DL' is the same as the total amount of data in the display list DL, specifically, for example, 256 bytes.

Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST26). Timings t1, t2, t3, t4 in FIG. 18A are also operation timings in step ST26. Then, next, based on the set value in the predetermined data transfer register RGij, the operation of the data transfer circuit 60 is started and the processing is ended (ST27). After that, the effect control CPU 63 shifts to the display list generation process (ST7) that is activated in the next operation cycle without particularly being involved in the operations of the data transfer circuit 72 and the drawing circuit.

On the other hand, the drawing circuit 76, which starts the operation at the timing of step ST26, executes the drawing operation based on the rewriting list DL' to generate the image data based on the rewriting list DL' in the frame buffers FBa and FBb. Note that in this operation, the drawing circuit 76 exclusively performs read access to the preload area without performing read access to the CGROM 55, so that a series of drawing operations can be completed quickly.

Since the processing contents of step PT10 have been described above, returning to FIG. 15, the description will be continued. In the embodiment utilizing the preloader 73 after the processing of step PT11, the display list DL to be activated in the next cycle is It is created based on the standard method (B) (ST7). For example, in the operation cycle (T1) shown in FIG. 19A, the display list DL referred to by the drawing circuit 76 is created in the operation cycle (T1+δ) which is the next cycle.

Next, the production control CPU 63 issues the created display list DL to the preloader 73 instead of the drawing circuit 76 (PT11). The specific operation content is as shown in FIG. First, regarding the embodiment (FIG. 10) in which the preloader 73 is not used, when the effect control CPU 63 directly issues the display list DL to the drawing circuit 76 (FIG. 12) and via the DMAC circuit 60. Although the case of issuing (FIG. 13) is shown, almost the same operation is shown in FIG. 17B and FIG. 17C except that the issue destination is the preloader 73. ..

17A is a flowchart for explaining the operation of FIG. 17B, which is almost the same as the flowchart of FIG. However, the CPUIF unit 56 is set to pass through the ChC control circuit 72c and the CPU bus control unit 72d is set to execute the data transfer operation while checking the remaining amount of the FIFO buffer (ST20). In the following description, the ChC control circuit 72c may be abbreviated as "transfer circuit ChC" for convenience.

Next, the total transfer size (for example, 256 bytes adjusted by the standard method (B)) is set in a predetermined data transfer register RGij, and the management counter CN is initialized to 64 (ST21). Next, the data transfer operation via the transfer circuit ChC is set to the start state (ST22), and the preload operation is started based on the set value in the preload register RGij defining the operation of the preloader 73 (ST23).

As a result, after that, in the preloader 73, when the production control CPU 63 executes the necessary analysis (Analyze) processing for each instruction command to be written in the transfer port TR_PORT, and detects an instruction command (TXLOAD) to read-access the CGROM 55. , The texture is preloaded and stored in the preload area of the DRAM 54. Further, the rewrite list DL' in which the source address of the texture is changed is stored in the DL buffer area BUF' of the DRAM 54.

Note that the timings t1, t3, and t5 in FIG. 19A actually indicate the operation timing of step ST23 in FIG. However, also in this embodiment, if any abnormality occurs in the process of issuing the display list DL, the processes of step ST25 and step ST27 are executed. Specifically, the operations of the data transfer circuit 72 and the preloader 73 are initialized, and the display list DL issuing process (ST20 to ST30) is re-executed within a possible range. The initialization process of the preloader 73 includes erasing the rewrite list DL' in an unfinished state and clearing the preload area in which the preload data is newly stored.

Although the case where the preloader 73 is used and the case where the preloader 73 is not used have been described above in detail, the specific operation content is not particularly limited. FIG. 18B shows an embodiment in which the display list generated by the effect control CPU 63 is issued to the drawing circuit 76 with a delay of one operation cycle δ instead of the generated operation cycle. In the case of such an embodiment, the drawing circuit 76 can use almost all the time of one operation cycle (δ), so that the possibility of dropped frames is reduced.

Further, FIG. 19B shows an embodiment in which the display list generated by the effect control CPU 63 is issued to the preloader 73 with a delay of one operation cycle instead of the generated operation cycle thereof. In this case, the preloader 73 can perform the pre-doing operation using almost the entire time of one operation cycle (δ), and in this case also, the possibility of dropping frames is reduced.

Although the composite chip 50 is used in the description so far, the effect control CPU 63 and the VDP circuit do not necessarily have to be integrated in one element. Furthermore, in the above embodiment, the entire effect control is controlled by a single CPU (effect control CPU 63), but the upstream CPU and the downstream effect control CPU 63 cooperate with each other to effect the effect. The control operation may be executed.

20 to 21 are block diagrams showing such an embodiment. As shown in the figure, in this embodiment, the effect control CPU on the upstream side controls the sound effect, the lamp effect, and the motor effect. On the other hand, the internal CPU 50 on the downstream side controls only the image effect based on the control command CMD' received from the effect control CPU.

When such a configuration is adopted, the built-in CPU 50 does not need to execute the processing of step ST12 of FIG. 10A and the processing of FIG. DL can be generated, and more complex and sophisticated image effects such as 3D (Dimension) can be realized. In such a case, the display list becomes large, but in that case, the total data amount of the display list DL is adjusted to 512 bytes or more N×256 bytes by adding a dummy command. .

Further, since the operation of the built-in CPU 50 on the downstream side is specialized in image effect control, it is possible to confirm that the drawing operation is completed after issuing the display list DL. The lower part of FIG. 12 shows an example of the operation control in this case. When the drawing operation is not completed even after the limit time is exceeded, the serious abnormality flag ABN is set and the processing ends (ST32). Since the processing of the built-in CPU 50 on the downstream side is only for the image effect control, it may be possible to simply wait for the completion of the drawing operation in an endless loop.

When adopting such a configuration, the start condition determination (ST5) of FIG. 10A can be repeated for a predetermined time. Even with such a configuration, if the delay in the completion of the drawing operation is not so long, there is only a problem that the switching between the display area (0) and the display area (1) is delayed. That is, as in the operation cycle T1+3δ shown in FIG. 22A, in one operation cycle in which the display operation is repeated twice, the first half is in the frame drop state, and in the second half, the normal frame is displayed.

This point is the same when the preloader is used, and the start condition determination (ST5') in FIG. 15A can be repeated for a predetermined time. Then, if there is some delay, as in the operation cycle T1+3δ shown in FIG. 22B, only the first half is in the frame drop state, and in the second half, a normal frame is displayed. However, if the completion of the drawing operation is significantly delayed, a complete frame drop occurs as in the operation cycle T1+3δ in FIG. 18A, and if such a situation continues, the watchdog timer 58 Will be started. Therefore, thereafter, all or part of the effect control operation (image effect only) may be abnormally reset based on the underflow signal UF. This point is the same when the preloader is not used.

Further, when the control operation of the built-in CPU 50 is specialized for image effect control, in the embodiment adopting the DMA transfer, as shown in the lower part of FIG. 14, the drawing operation of the drawing circuit 76 is completed and the data transfer circuit 72 is operated. When the operation is completed, it is determined whether the operation of the DMAC circuit 60 is completed (ST50' to ST52'). Then, if any of the operations is not normally completed, the operations of the data transfer circuit 72 and the drawing circuit 76 are initialized, and the same processing (ST55' to ST57') as the processing of steps ST53 to ST55 is executed. It In this case as well, it is preferable to re-execute the DL issuing process a predetermined number of times.

The embodiment has been described above in which, as the frame buffers FBa and FBb of the main display device DS1 and the sub display device DS2, an index space having a horizontal size that completely matches the number of horizontal pixels of each display device is constructed. FIG. 23A is a diagram for confirming this relationship, in which a drawing area (W×H) on the virtual drawing space and an effective data area (actual drawing area W×H) on the index space are shown. , Both show the case where the number of horizontal/vertical pixels of the display device matches.

In such a correspondence relationship, the drawing operation in the virtual drawing space by the display list DL is not necessarily limited to the drawing area (W×H), and therefore, for example, as shown by the left slant line in the upper part of FIG. , A drawing image (W′×H′) that exceeds the drawing area (W×H) is temporally moved, so that the actual drawing area W×H shown by the right slanted line at the bottom of FIG. It is possible to appropriately move the drawing contents to the vertical/horizontal/diagonal.

In order to execute such an effect, for example, as shown in FIG. 23B, an index space having a horizontal size W larger than the number of horizontal pixels of the display device may be provided. In this case, the drawing area W×H in the virtual drawing space defined by the instruction command L12 (SETDAVF) of the display list DL is larger than the actual drawing area w×h corresponding to the number of horizontal/vertical pixels of the display device. Is set. In the lower part of FIG. 23B, the actual drawing area w×h is shown by a right slanted line.

The vertical and horizontal dimensions of the actual drawing area w×h are specified as the number of display lines and the number of horizontal pixels of the display device in the process of step SS30 in FIG. 10, and the upper left end point of the actual drawing area w×h is In step SS31 of 10, the vertical/horizontal display start position is set in a predetermined display register.

On the other hand, the base address (X, Y) in the index space is set in a predetermined drawing register by the instruction command L11 of the display list. As described above, specifically, the upper left base point address on the index space IDX is defined as (0, 0) by the environment setting related instruction command L11 (SETDAVR). Then, if the upper left end point of the actual drawing area w×h is appropriately moved in the steady process, the drawing content of the actual drawing area W×H indicated by the right slanted line in the lower part of FIG. Will be moved accordingly.

As described with reference to FIG. 10, with respect to the VDP register RGij according to steps SS30 to SS32, the write-prohibition setting is made at the initial setting (second prohibition setting SS34), but at the timing of executing the above-mentioned effect, a predetermined value is set. This prohibition setting is released by writing the release value in the VDP register RGij of.

Although various embodiments have been described in detail above, the specific description does not limit the present invention. Although a ball game machine is described for the sake of convenience, the present invention can be suitably applied to other game machines such as a spinning-roller game machine.

GM gaming machine 71 memory circuit FBa, FBb buffer area DL display list 23 image control means 52 image generation means 77 drawing circuit 74 display circuit ST1, ST2 first means ST6 second means ST7, ST8 third means

Claims (3)

Image control means for issuing a display list for specifying the display screen of the display device, and image generation means for completing and outputting predetermined image data based on the display list in a predetermined buffer area are configured. ,
The image generation means includes a drawing circuit that completes image data specified by the display list in the buffer area, a display circuit that reads and outputs image data in the buffer area, and a memory circuit in which the buffer area is arranged. ,, and
A plurality of storage areas are secured in the memory circuit, and a pair of two-dimensional spaces having a horizontal size determined based on the number of horizontal pixels of the display device and a predetermined vertical size in any of the secured storage areas. And a first means for assigning a pair of index numbers for identifying a pair of two-dimensional spaces functions at the time of initial processing after power-on,
After the second means for specifying the two-dimensional space to be read by the display circuit among the pair of two-dimensional spaces and the third means for executing the display list creating process and the issuing process are completed, the initialization process is completed. In the steady process of, while it is configured to function repeatedly every predetermined operation cycle,
A gaming machine configured to avoid execution of the second means and the third means in an operation cycle that does not satisfy a predetermined operation start condition. The internal circuit of the image control means and the image generation means is configured to be reset to an initial state when the number of consecutive times when the execution of the third means and the fourth means is avoided exceeds a predetermined value. The game machine described. The gaming machine according to claim 2, wherein the image effect executed on the display device and the sound effect in which the speaker functions are reset to the initial state in response to the internal circuit being reset to the initial state.