JP2020077743A - Laminate and semiconductor package - Google Patents

Abstract

To form a highly reliable wiring layer on a resin layer.SOLUTION: A laminate according to one aspect of the present invention includes a resin layer 12, a titanium nitride layer 15, and a copper layer 17 in this order. A semiconductor package according to another aspect of the present invention includes a redistribution layer and a semiconductor element, and the redistribution layer includes a resin layer 12, a titanium nitride layer 15, and a copper layer 17 in this order.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a laminated body and a semiconductor package.

  In electronic parts such as semiconductor packages having semiconductor elements mounted thereon, resin compositions are used for various purposes such as adhesion, temporary fixing, insulation, sealing and the like. In such an application, for example, a conductive wiring layer is formed on an insulating resin layer made of a resin composition. As the wiring layer in this case, for example, as described in Patent Document 1, a Ti (titanium) layer / Cu (copper) layer formed by a sputtering method is generally used.

International Publication No. 2008/105535

  In the resin layer and the wiring layer as described above, the two are favorably adhered to each other for a long period of time even under various environments such as a high temperature environment, a low temperature environment, a high temperature and high humidity environment (that is, excellent reliability). Is desirable. However, according to the study by the present inventors, when the above-mentioned wiring layer made of a copper layer and a titanium layer is used, the adhesion between the titanium layer and the resin layer is not always sufficient, and therefore the reliability is excellent. It is hard to say that the wiring layer can be formed on the resin layer.

  Therefore, an object of the present invention is to form a highly reliable wiring layer on a resin layer.

  One aspect of the present invention is a laminate including a resin layer, a titanium nitride layer, and a copper layer in this order. This laminated body is suitably used for a wiring layer in an electronic component such as a semiconductor package, and thereby a wiring layer having excellent reliability can be obtained.

  The laminate may further include a titanium layer between the titanium nitride layer and the copper layer.

  Another aspect of the present invention is a semiconductor package including a redistribution layer and a semiconductor element, and the redistribution layer having a resin layer, a titanium nitride layer, and a copper layer in this order. The redistribution layer in this semiconductor package is excellent in reliability.

  The redistribution layer may further include a titanium layer between the titanium nitride layer and the copper layer.

  According to the present invention, a wiring layer having excellent reliability can be formed on the resin layer.

It is a schematic cross section which shows the electronic component which concerns on one Embodiment. It is a schematic cross section which shows the principal part of a semiconductor package.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view showing an electronic component according to an embodiment. As shown in FIG. 1, an electronic component 1 according to an embodiment includes, for example, a printed circuit board (PCB; Print Circuit Board) 2 and a semiconductor package 3 mounted on the printed circuit board 2.

  The printed board 2 may be a known printed board, and includes, for example, a board 4 and wirings 5 provided on the board 4.

  The semiconductor package 3 may be FOWLP, for example. Specifically, the semiconductor package 3 covers the rewiring layer 6, the semiconductor element 7 provided on the rewiring layer 6, and the rewiring layer 6 and the semiconductor element 7 so as to cover the semiconductor element 7, for example. The sealing layer 8 provided and a plurality of solders 9 provided on the opposite side of the rewiring layer 6 from the semiconductor element 7 are provided.

  The rewiring layer 6 includes, for example, a first resin layer 10 made of a resin composition, a first wiring layer 11, and a second resin layer 12 made of a resin composition from the side close to the printed circuit board 2. It is laminated in this order. Since the first resin layer 10 is provided with a plurality of through holes, and the first wiring layer 11 is also formed in the through holes, the first wiring layer 11 and the plurality of solders 9 are formed. And are electrically connected to each other. The second resin layer 12 is also provided with a plurality of through holes, and the second wiring layer 13 made of, for example, copper is formed in the through holes, so that the first wiring layer 11 and the semiconductor The element 7 is electrically connected to each other via the second wiring layer 13.

  The semiconductor package 3 is mounted so that each of the plurality of solders 9 is in contact with the wiring 5 of the printed board 2. An underfill layer 14 is formed between the printed board 2 and the semiconductor package 3, for example, by filling an underfill material.

  The first resin layer 10 and the second resin layer 12 are each formed of a cured product of resin. The resin may be, for example, polybenzoxazole resin, polyimide resin, epoxy resin, oxetane resin, phenol resin, or the like. The phenol resin may be, for example, at least one selected from novolac resins, resole resins, polyhydroxystyrene resins and modified products thereof. The first resin layer 10 and the second resin layer 12 may each be 0.5 μm or more, 1 μm or more, or 2 μm or more, and may be 500 μm or less.

  FIG. 2 is a schematic cross-sectional view showing a main part of the semiconductor package 3. As shown in FIG. 2, in one embodiment, the first wiring layer 11 includes a titanium nitride layer 15, a titanium layer 16, and a copper layer 17 in this order from the second resin layer 12 side. There is. In other words, the redistribution layer 6 includes a laminated body in which the second resin layer 12, the titanium nitride layer 15, the titanium layer 16, and the copper layer 17 are laminated in this order.

  The titanium nitride layer 15 is formed of titanium nitride (TiN). The thickness of the titanium nitride layer 15 may be, for example, 5 nm or more and may be 500 nm or less, and from the viewpoint of further improving the adhesiveness between the first wiring layer 11 and the second resin layer 12. Is preferably 5 nm to 300 nm, and is preferably 10 nm to 100 nm from the viewpoint that the conductivity of the first wiring layer 11 can be suitably secured.

  The titanium nitride layer 15 can be formed by, for example, a method of sputtering titanium in an atmosphere containing nitrogen gas (also called a reactive method). The atmosphere may be, for example, a mixed gas atmosphere of argon and nitrogen.

  The titanium layer 16 is formed of titanium (Ti). The thickness of the titanium layer 16 may be, for example, 5 nm or more, may be 500 nm or less, may be 10 nm to 300 nm, and can suitably cover the corners of the copper layer 17 and the like, and shorten the etching time. From the viewpoint of achieving the same, the thickness is preferably 20 nm to 100 nm. The titanium layer 16 can be formed by, for example, a method of sputtering titanium in an argon atmosphere.

  The copper layer 17 is formed of copper (Cu). The thickness of the copper layer 17 is, for example, 10 nm to 20 μm, or 1 μm to 200 μm, and is preferably 1 μm to 10 μm from the viewpoint of shortening the electrolytic plating time. The copper layer 17 can be formed, for example, by forming a first copper layer (seed layer) by sputtering and then laminating a second copper layer on the first copper layer by electrolytic plating. The thickness of the first copper layer (seed layer) may be, for example, 5 nm or more, 500 nm or less, and may be 10 nm to 400 nm.

  As described above, since the titanium nitride layer 15 is provided in the first wiring layer 11 so as to be in contact with the second resin layer 12, for example, the first wiring layer includes only the titanium layer and the copper layer. It is possible to improve the adhesion between the first wiring layer 11 and the second resin layer 12 as compared with the case where (the titanium layer is in contact with the second resin layer). Although the reason is not clear, it is presumed that the titanium nitride layer has more points of action on the second resin layer than the titanium layer.

  In the above embodiment, the titanium layer 16 is provided between the titanium nitride layer 15 and the copper layer 17, but in another embodiment, the titanium layer may not be provided. That is, in another embodiment, the first wiring layer has a titanium nitride layer and a copper layer in this order from the second resin layer side. In other words, in another embodiment, the redistribution layer includes a laminated body in which the second resin layer, the titanium nitride layer, and the copper layer are laminated in this order. Even in this case, the adhesion between the first wiring layer 11 and the second resin layer 12 can be improved.

  In the above embodiment, the electronic component 1 including the semiconductor package 3 has been described as an example, but a laminated body including a resin layer, a titanium nitride layer, and a copper layer in this order is a laminate in another embodiment. , May be used for other than the electronic component.

  Hereinafter, the present invention will be described more specifically with reference to Examples, but the present invention is not limited to the following Examples.

<Example 1>
Polybenzoxazole resin (trade name: HD-8940, manufactured by Hitachi Chemical DuPont Micro Systems Co., Ltd.) is applied on a silicon wafer by spin coating using a coating and developing apparatus ACT-8 (manufactured by Tokyo Electron Limited). After prebaking, an inert gas oven CLH-21CD-S (manufactured by Koyo Thermo System Co., Ltd.) was used to raise the temperature to 200 ° C. at a temperature rising rate of 1.5 ° C./min at an oxygen concentration of 20 ppm or less, and then at 200 ° C. Heat treatment was performed for an hour. After that, when the temperature in the oven was lowered to 50 ° C. or lower, a wafer having a resin layer formed on a silicon wafer (hereinafter, also simply referred to as “wafer”) was taken out. The resin layer had a thickness of 7.5 μm.

Next, after heating the above-prepared wafer in vacuum at 120 ° C. for 30 minutes, the resin surface was etched by the ion gun method in the same vacuum. At this time, etching was performed under the condition that the SiO ₂ film was etched by 20 nm. After that, titanium sputtering was performed in a state where nitrogen gas was injected in an argon atmosphere to form a titanium nitride layer having a thickness of 10 nm. Then, under an argon atmosphere, a titanium layer having a thickness of 50 nm and a copper seed layer having a thickness of 200 nm were laminated. Subsequently, a copper layer having a thickness of 20 μm was laminated using an electroplating method to obtain a laminated body.

<Example 2>
A laminated body was obtained in the same manner as in Example 1 except that the atmosphere for forming the titanium nitride layer was changed to a mixed gas atmosphere of argon: nitrogen = 1: 4 (volume ratio).

<Comparative Example 1>
A laminated body was obtained in the same manner as in Example 1 except that the titanium nitride layer was not formed.

[Evaluation of laminate]
About the laminated body obtained by each example, peel strength (kN / when peeling another layer from the resin layer using a tabletop peel tester (brand name: small tabletop tester EZ-S, Shimadzu Corporation) m) was measured and evaluated as the peel strength before the reliability test. The results are shown in Table 1. The conditions were a peel width (initial peel distance) of 10 mm, a peel angle of 90 °, and a peel speed of 10 mm / min.
In addition, each of the laminates was subjected to the following reliability test. First, the laminate was put into a constant temperature and humidity chamber of 85 ° C./85%, taken out 168 hours later, and then reflow treatment was repeated 10 times within 1 hour. The reflow treatment was performed by heating with a temperature profile corresponding to the JEDEC (J-STD-0200) standard in which the maximum temperature was 260 ° C. Subsequently, 200 cycles of repeating a cycle of standing for 15 minutes in an environment of -65 ° C and then standing for 15 minutes in an environment of 150 ° C were repeated. Then, the peel strength (kN / m) of each laminate after the reliability test was measured in the same manner as above. The results are shown in Table 1.

  DESCRIPTION OF SYMBOLS 1 ... Electronic component, 2 ... Printed circuit board, 3 ... Semiconductor package, 4 ... Board, 5 ... Wiring, 6 ... Rewiring layer, 7 ... Semiconductor element, 8 ... Sealing layer, 9 ... Solder, 10 ... First resin Layers, 11 ... First wiring layer, 12 ... Second resin layer, 13 ... Second wiring layer, 14 ... Underfill layer, 15 ... Titanium nitride layer, 16 ... Titanium layer, 17 ... Copper layer.

Claims (4)

  A laminated body including a resin layer, a titanium nitride layer, and a copper layer in this order.   The laminate according to claim 1, further comprising a titanium layer between the titanium nitride layer and the copper layer. A rewiring layer and a semiconductor element,
A semiconductor package in which the redistribution layer has a resin layer, a titanium nitride layer, and a copper layer in this order.   The semiconductor package according to claim 3, wherein the redistribution layer further includes a titanium layer between the titanium nitride layer and the copper layer.

Images