JP2005268810A - Wiring board, semiconductor package, base insulating film, and manufacturing method of wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board, which allows various devices, such as semiconductor devices, to be mounted with high density, the promotion of high-speed wiring and high-density fine wiring to be easy, and reliability to be excellent, a semiconductor package using the same, and a manufacturing method of the same. <P>SOLUTION: A base insulating layer 7 is provided in the wiring substrate 13. The thickness of the base insulating layer 7 is in the range from 3 to 100 μm. Breaking strength when temperature is 23 °C is 80 MPa or more. Elastic modulus when temperature is 150 °C is 2.3 GPa or more. Moreover, a ratio (a/b) is made to be ≤2.5, where a in MPa is the breaking strength when temperature is -65 °C, and b in MPa is the breaking strength when temperature is 150 °C, and the breaking strength a and b, and the elastics modulus c and d are set so as to fill an inequality represented by the absolute value of (c/d-a/b)≤0.8, where c in GPa is the elastic modulus when temperature is -65 °C, and d in GPa is the elastic modulus when temperature is 150 °C. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a wiring board suitably used for a semiconductor package and a module, a semiconductor package using the wiring board, a base insulating film used for the wiring board, and a method for manufacturing the wiring board. The present invention relates to a wiring board, a semiconductor package, a base insulating film, and a method for manufacturing the wiring board, which can mount these various devices at high density, drive these devices at high speed, and further improve reliability.

  Recently, with the increase in the number of terminals, narrow pitch, and improvement in processing speed due to higher performance and multi-functionality of semiconductor devices, the mounting wiring boards for mounting semiconductor devices have higher density and finer wiring than ever before. And speeding up is required. Conventionally, an example of a mounting wiring board that has been widely used is a built-up printed circuit board that is a kind of multilayer wiring board.

  FIG. 22 is a sectional view showing a conventional built-up printed circuit board. As shown in FIG. 22, in this conventional built-up substrate, a base core substrate 73 made of glass epoxy is provided, and through holes 71 having a diameter of about 300 μm are formed in the base core substrate 73 by a drill. Has been. Conductive wiring 72 is formed on both surfaces of the base core substrate 73, and an interlayer insulating film 75 is provided so as to cover the conductive wiring 72. A via hole 74 is formed in the interlayer insulating film 75 so as to be connected to the conductor wiring 72, and the conductor wiring 76 is connected to the surface of the interlayer insulating film 75 via the via hole 74 so as to be connected to the conductor wiring 72. Is provided. If necessary, the substrate may be formed into a multilayer wiring by repeatedly providing an interlayer insulating film having via holes formed on the conductor wiring 76 and the conductor wiring.

  However, since this built-up printed circuit board uses a glass epoxy printed circuit board for the base core substrate 73, the heat resistance is insufficient, and the heat build-up for forming the interlayer insulating film 75 causes the base core substrate 73 to shrink. There is a problem that deformation such as warpage and undulation occurs. As a result, in the resist exposure process when the conductor layer (not shown) is patterned to form the conductor wiring 76, the exposure positional accuracy is remarkably lowered, and the high-density and fine wiring is formed on the interlayer insulating film 75. It becomes difficult to form a pattern. Further, in order to securely connect the through through hole 71 and the conductor wiring 72, it is necessary to provide a land portion at a connection portion of the conductor wiring 72 with the through through hole 71. Even if the wiring design corresponding to the high speed is performed in the built-up layer composed of the interlayer insulating film 75 and the conductor wiring 76, the presence of the land portion makes it difficult to control the impedance and increases the loop inductance. For this reason, there is a problem that the operation speed of the entire built-up printed circuit board is lowered and it is difficult to cope with the high speed.

  In order to solve the problems caused by the through-through hole of such a built-up printed circuit board, a printed board forming method has been devised in place of a method of forming a through-through hole in a glass epoxy board by a drill (for example, (See Patent Literature 1 and Non-Patent Literature 1.)

  23A to 23C are cross-sectional views showing the conventional method of forming a printed circuit board in the order of steps. First, as shown in FIG. 23A, a prepreg 82 having a predetermined conductor wiring 81 formed on the surface is prepared. Next, a through hole 83 having a diameter of 150 to 200 μm is formed in the prepreg 82 by laser processing. Next, as shown in FIG. 23B, a conductive paste 84 is embedded in the through hole 83. Then, as shown in FIG. 23 (c), a plurality of such prepregs 82, that is, the prepregs 82 in which the through holes 83 are formed and the conductor paste 84 is embedded in the through holes 83, are laminated to each other. To do. At this time, the land pattern 86 in the conductor wiring 81 is connected to the through hole 83 of the adjacent prepreg. Thereby, the printed circuit board 85 without a through-hole can be produced.

  However, this conventional technique has a problem that the position accuracy when the prepregs 82 are stacked is low, and it is difficult to reduce the diameter of the land pattern 86. For this reason, it is difficult to increase the density of the wiring, and the effect of improving the controllability of the impedance and the effect of reducing the loop inductance are insufficient. Furthermore, there is a problem that the connection reliability of the through holes after lamination is inferior.

  In order to solve the above-mentioned many problems, the present inventors have developed a method for forming a wiring board by forming a wiring layer on a support such as a metal plate and then removing the support (patent). Reference 2). 24A and 24B are cross-sectional views showing this conventional method of manufacturing a wiring board in the order of steps. First, as shown in FIG. 24A, a support plate 91 made of a metal plate or the like is prepared. Then, a conductor wiring 92 is formed on the support plate 91, an interlayer insulating film 93 is formed so as to cover the conductor wiring 92, and a via hole 94 is connected to the interlayer insulating film 93 so as to be connected to the conductor wiring 92. Form. Thereafter, conductor wiring 95 is formed on the interlayer insulating film 93. The conductor wiring 95 is formed so as to be connected to the conductor wiring 92 through the via hole 94. If necessary, a multilayer wiring may be formed by repeating the process of forming the interlayer insulating film 93, the via hole 94, and the conductor wiring 95. Next, as shown in FIG. 24B, a part of the support plate 91 is removed by etching to expose the conductor wiring 92 and to form a support 96. Thereby, the wiring board 97 is manufactured.

  At this time, the interlayer insulating film 93 has a single layer film made of an insulating material having a film strength of 70 MPa or more, a breaking elongation of 5% or more, a glass transition temperature of 150 ° C. or more, and a thermal expansion coefficient of 60 ppm or less, or an elastic material. A single layer film made of an insulating material having a rate of 10 GPa or more, a thermal expansion coefficient of 30 ppm or less, and a glass transition temperature of 150 ° C. or more is used.

  According to this technique, since there are no through-through holes in the wiring board 97, the above-described problems caused by the through-through holes can be solved, and high-speed wiring design can be performed. In addition, since a metal plate having excellent heat resistance is used as the support plate 91, there is no deformation such as shrinkage, warping, and undulation as in the case of using a glass epoxy substrate, and high-density fine wiring. Can be realized. Furthermore, by defining the mechanical characteristics of the interlayer insulating film 93 as described above, a wiring board having high strength can be obtained.

JP 2000-269647 A Proceedings of the 11th Microelectronics Symposium, p. 131-134 Japanese Patent Laid-Open No. 2002-198462 (pages 8, 11 and 17)

  However, the conventional techniques described above have the following problems. The wiring substrate 97 shown in FIG. 24B is extremely thin because there is no base core substrate. However, by defining the mechanical characteristics of the interlayer insulating film 93 as described above, In the wiring board 97, sufficient strength can be obtained. However, the wiring board 97 is usually used by mounting a semiconductor device having a large area to form a semiconductor package, and further mounting the semiconductor package on a mounting board such as a printed board. The semiconductor device generates heat during operation and rises in temperature, and the heat generation stops during rest and the temperature falls. For this reason, thermal stress is applied to the wiring board 97 due to the difference in thermal expansion coefficient between the semiconductor device and the mounting board during operation of the semiconductor device. Therefore, when the semiconductor device is repeatedly operated in a state where the semiconductor device is mounted on the wiring board 97 as described above, thermal stress is repeatedly applied to the wiring board 97, and the interlayer insulating film 93 and the like of the wiring board 97 are cracked. May occur. For this reason, there is a problem that necessary reliability cannot be secured in the wiring board and the semiconductor package.

  The present invention has been made in view of such problems, and various devices such as semiconductor devices can be mounted at high density, and high-speed wiring and high-density fine wiring are easy, and excellent in reliability. An object is to provide a wiring board, a semiconductor package using the wiring board, a base insulating film, and a method for manufacturing the wiring board.

  The wiring board according to the present invention includes a base insulating film in which a via hole is formed, a lower layer wiring formed on a lower surface of the base insulating film and connected to the via hole, and the via hole formed on the base insulating film. The base insulating film has a film thickness of 3 to 100 μm, a breaking strength at a temperature of 23 ° C. of 80 MPa or more, and a temperature of When the breaking strength at −65 ° C. is a and the breaking strength when the temperature is 150 ° C. is b, the ratio (a / b) is 4.5 or less.

  In the present invention, by setting the thickness of the base insulating film to 3 to 100 μm and the breaking strength when the temperature is 23 ° C. to 80 MPa or more, a wiring board having high strength can be obtained. Furthermore, when the breaking strength when the temperature is −65 ° C. is b and the breaking strength when the temperature is 150 ° C. is b, the ratio (a / b) is 4.5 or less, so that It is possible to obtain a base insulating film with a small decrease in strength. Thereby, even if a thermal load is repeatedly applied by the operation of the semiconductor device, it is possible to prevent the base insulating film from being cracked and to obtain a wiring board with excellent reliability.

  In the base insulating film, when the elastic modulus is c when the temperature is −65 ° C. and d is the elastic modulus when the temperature is 150 ° C., the value of the ratio (c / d) is 4.7 or less. It is preferable that This ensures the rigidity of the base insulating film at a high temperature and prevents the base insulating film from being excessively deformed with respect to the stress applied to the base insulating film, so that the solder balls attached to the wiring board can be damaged. Can be prevented.

  Furthermore, the value of the ratio (a / b) is preferably 2.5 or less. Thereby, it can prevent more reliably that a crack generate | occur | produces in a base | substrate insulating film. Alternatively, when the value of the ratio (a / b) is greater than 2.5 and less than or equal to 4.5, the a to d preferably satisfy the following mathematical formula 1. Thereby, the breaking strength of the base insulating film at a high temperature is secured, and the occurrence of cracks in the base insulating film can be more reliably prevented.

  Furthermore, the elastic modulus of the base insulating film when the temperature is 150 ° C. is preferably 2.3 GPa or more. Thereby, the rigidity of the base insulating film at a high temperature can be increased, and the solder ball attached to the wiring board can be more reliably prevented from being damaged.

  The wiring board has one or a plurality of wiring structure layers disposed between the base insulating film and the upper layer wiring, and the wiring structure layer is connected to the lower layer wiring via the via hole. The intermediate wiring may be connected to the intermediate wiring, and the intermediate insulating film may be formed so as to cover the intermediate wiring and may be formed with another via hole that connects the intermediate wiring and the upper wiring. Thereby, a wiring board can be made into multilayer wiring. The intermediate insulating film preferably has the same mechanical properties as the base insulating film.

  In addition, a recess is formed on the lower surface of the base insulating film, and the lower layer wiring is preferably embedded in the concave portion, and the lower surface of the lower layer wiring is 0.5 times lower than the lower surface of the base insulating film. It is more preferable that it is located up to 10 μm. Thereby, when connecting a semiconductor device to a lower layer wiring via a bump, it is possible to prevent the displacement and flow of the bump.

  Further, the wiring board may have a protective film that is formed below the base insulating film and covers a part of the lower layer wiring and exposes the remaining part. Thereby, after connecting a semiconductor device to lower layer wiring, when this semiconductor device is covered with molding resin and a semiconductor package is formed, the adhesiveness between a wiring board and molding resin can be improved. Further, the thermal stress generated between the semiconductor device and the wiring board can be relaxed with the operation of the semiconductor device. As a result, the reliability of the semiconductor package can be improved.

  A semiconductor package according to the present invention includes the wiring board and a semiconductor device mounted on the wiring board.

  The method for manufacturing a wiring board according to the present invention includes a step of forming a lower layer wiring on a support substrate, a step of forming a base insulating film having a film thickness of 3 to 100 μm so as to cover the lower layer wiring, and the base insulating layer. Forming a via hole in a part of the film directly above the lower layer wiring, forming an upper layer wiring on the base insulating film so as to be connected to the lower layer wiring via the via hole, Removing the at least part of the supporting substrate, and the step of forming the base insulating film has a breaking strength of 80 MPa or more when the temperature is 23 ° C. and a breaking when the temperature is −65 ° C. A step of attaching an insulating material having a ratio (a / b) of 4.5 or less to the support substrate, where a is strength and b is strength at 150 ° C. And

  In the present invention, by setting the thickness of the base insulating film to 3 to 100 μm and the breaking strength when the temperature is 23 ° C. to 80 MPa or more, a wiring board having high strength can be obtained. Furthermore, by setting the ratio (a / b) to 4.5 or less, it is possible to ensure the breaking strength of the base insulating film at high temperatures, and even if a thermal load is repeatedly applied by driving the semiconductor device, the base insulating film is cracked. Thus, a wiring board with excellent reliability can be obtained. Furthermore, a thin wiring substrate can be formed with good flatness by sequentially forming a lower layer wiring, a base insulating film, and an upper layer wiring on the supporting substrate and then removing the supporting substrate. Furthermore, in the present invention, it is possible to form a wiring board having no through-through hole, to solve the problem caused by the through-through hole, and to design a high-speed wiring.

  In addition, before the step of forming the lower layer wiring on the support substrate, there is a step of forming an easy etching layer having a film thickness of 0.5 to 10 μm on the support substrate, and at least a part of the support substrate is formed. It is preferable to have the process of removing the said easy-to-etch layer after the process of removing. Thereby, a recess can be formed in the lower surface of the base insulating film, and the lower layer wiring can be embedded in the recess. As a result, when the semiconductor device is connected to the lower layer wiring via the bump, it is possible to prevent the bump from being displaced and flowing.

  Alternatively, the method includes a step of forming a protective layer before the step of forming a lower layer wiring on the support substrate, and the protective layer is selectively removed after the step of removing at least a part of the support substrate. And a step of exposing at least a part of the lower layer wiring. As a result, a protective film that covers a part of the lower layer wiring and exposes the remaining part under the base insulating film can be formed. As a result, after a semiconductor device is connected to the lower layer wiring, when this semiconductor device is covered with a molding resin to form a semiconductor package, the adhesion between the wiring board and the molding resin can be improved. Further, the thermal stress generated between the semiconductor device and the wiring board can be relaxed with the operation of the semiconductor device. Thereby, the reliability of the semiconductor package can be improved.

  According to the present invention, high-speed wiring and high-density fine wiring can be achieved by using an insulating film having low temperature dependence of mechanical characteristics as a base insulating film, and a thermal load is reduced by driving a mounted semiconductor device. Even if it is repeatedly applied, the substrate insulating film or the solder balls do not crack, and a highly reliable wiring board can be obtained.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a wiring board according to this embodiment, and FIG. 2 is a cross-sectional view showing a semiconductor package according to this embodiment.

  As shown in FIG. 1, the substrate insulating film 7 is provided in the wiring substrate 13 according to the present embodiment. The base insulating film 7 has a film thickness of 3 to 100 μm, a fracture strength of 80 MPa or more when the temperature is 23 ° C., and an elastic modulus of 2.3 GPa or more when the temperature is 150 ° C. Further, when the breaking strength when the temperature of the base insulating film 7 is −65 ° C. is a (MPa) and the breaking strength when the temperature is 150 ° C. is b (MPa), the value of the ratio (a / b) is 4.5 or less, more preferably 2.5 or less, for example 0.22 or more, the elastic modulus when the temperature is −65 ° C. is c (GPa), and the elasticity when the temperature is 150 ° C. When the rate is d (GPa), the fracture strengths a and b and the elastic moduli c and d have a ratio (c / d) of 4.7 or less, for example 0.21 or more, and the above formula 1 Meet. The base insulating film 7 is a resin having high heat resistance and high film strength such as polyimide and liquid crystal polymer, for example, AP-6832C (trade name) manufactured by Nitto Denko, Upilex-S (trade name) manufactured by Ube Industries, Ltd. , Upilex-RN (trade name), Kapton-H (trade name) manufactured by Toray DuPont, Kapton-V (trade name), Kapton-EN (trade name), Bexter (trade name) made by Kuraray, glass cloth, aramid A high-strength, high-modulus and low-dielectric-constant fiber material such as fiber impregnated with resin, for example, glass cloth impregnated epoxy resin such as ABF-GX-1031 (trade name) manufactured by Ajinomoto Fine Techno, or An aramid nonwoven material such as EA-541 (trade name) manufactured by Shin-Kobe Electric Machinery.

  A recess 7 a is formed on the lower surface of the base insulating film 7, a wiring body 6 is formed in the recess 7 a, and an etching barrier layer 5 is formed below the wiring body 6. The etching barrier layer 5 and the wiring body 6 form a lower layer wiring, and this lower layer wiring is embedded in the recess 7a. The lower surface of the etching barrier layer 5 is exposed and constitutes a part of the lower surface of the wiring substrate 13. The wiring body 6 is made of, for example, Cu, Ni, Au, Al, or Pd, and the film thickness thereof is, for example, 2 to 20 μm. The etching barrier layer 5 is made of, for example, Ni, Au, or Pd, and the film thickness thereof is, for example, 0.1 to 7.0 μm. The lower surface of the etching barrier layer 5 is at a position, for example, 0.5 to 10 μm above the lower surface of the base insulating film 7, that is, at a deep position in the recess 7a.

  Further, a via hole 10 is formed in a part of the base insulating film 7 immediately above the recess 7a. When the wiring board 13 is used in a CSP (chip size package) semiconductor package, the diameter of the via hole 10 is, for example, 40 μm, and the wiring board 13 is used in an FCBGA (flip chip ball grid array) semiconductor package. In this case, the diameter of the via hole 10 is, for example, 75 μm. Further, a conductive material is embedded in the via hole 10, and an upper layer wiring 11 is formed on the base insulating film 7. The conductive material in the via hole 10 and the upper layer wiring 11 are integrally formed. The upper layer wiring 11 has a film thickness of 2 to 20 μm, for example, and is connected to the lower layer wiring via the via hole 10. Furthermore, a solder resist 12 is formed on the base insulating film 7 so as to expose a part of the upper wiring 11 and cover the remaining part. The film thickness of the solder resist 12 is, for example, 5 to 40 μm. The exposed portion of the upper layer wiring 11 becomes a pad electrode.

  Next, the configuration of the semiconductor package according to the present embodiment will be described. As shown in FIG. 2, in the semiconductor package 19 according to the present embodiment, a plurality of bumps 14 are connected to the etching barrier layer 5 in the wiring substrate 13 described above. A semiconductor device 15 is provided below the wiring substrate 13, and electrodes (not shown) of the semiconductor device 15 are connected to the bumps 14. The semiconductor device 15 is, for example, an LSI (Large Scale Integrated circuit). An underfill 16 is filled around the bump 14 between the wiring substrate 13 and the semiconductor device 15. On the other hand, a solder ball 18 is mounted on the exposed portion of the upper layer wiring 11 of the wiring board 13, that is, a part of the pad electrode. The solder ball 18 is connected to the electrode of the semiconductor device 15 through the upper layer wiring 11, the via hole 10 (see FIG. 1), the lower layer wiring composed of the wiring body 6 and the etching barrier layer 5, and the bump 14. The semiconductor package 19 is mounted on a mounting board (not shown) via the solder balls 18.

  Hereinafter, the reason for the numerical limitation in each constituent requirement of the present invention will be described.

Base insulating film thickness: 3 to 100 μm
If the film thickness of the base insulating film is less than 3 μm, the mechanical characteristics required for the wiring board cannot be ensured. On the other hand, when the film thickness of the substrate insulating film exceeds 100 μm, the via hole processability by laser processing is remarkably lowered, and a fine via hole cannot be formed. Therefore, the thickness of the base insulating film is 3 to 100 μm.

The breaking strength of the base insulating film when the temperature is 23 ° C .: 80 MPa or more If the breaking strength of the base insulating film is less than 80 MPa, the mechanical characteristics required for the wiring board cannot be secured. Therefore, the breaking strength of the base insulating film when the temperature is 23 ° C. is 80 MPa or more.

In the substrate insulating film, when the breaking strength when the temperature is −65 ° C. is a and the breaking strength when the temperature is 150 ° C. is b, the ratio (a / b) is 4.5 or less. When the value of / b) exceeds 4.5, the temperature of the base insulating film rises and the breaking strength is significantly reduced when the temperature becomes high (150 ° C.). For this reason, even if the base insulating film has sufficient strength at low temperature (−65 ° C.) and normal temperature (23 ° C.), the fluctuation in strength between the low temperature and the high temperature becomes large, and the mounted semiconductor device Therefore, it is difficult to withstand the thermal stress repeatedly applied, and the possibility of cracks occurring in the base insulating film is increased. Therefore, the value of the ratio (a / b) is 4.5 or less. More preferably, it is 2.5 or less. On the other hand, the lower limit value of the ratio (a / b) value is not particularly limited, but it is considered that the occurrence of cracks can be suppressed if the reciprocal of the upper limit value (4.5) is 0.22 or more. . However, at present, there is no resin material having a ratio (a / b) value of less than 1.0, and it has not been confirmed experimentally.

In the base insulating film, when the elastic modulus is c when the temperature is −65 ° C. and d is the elastic modulus when the temperature is 150 ° C., the value of the ratio (c / d) is 4.7 or less, and The absolute value of the difference from the ratio (a / b) is 0.8 or less . FIG. 3 shows the substrate with the horizontal axis representing the elongation of the base insulating film and the vertical axis representing the stress applied to the base insulating film. It is a graph which shows the stress-strain curve of an insulating film. A line 51 shown in FIG. 3 shows a stress-strain curve of the base insulating film when the temperature is −65 ° C., and the breaking strength is a. Further, the slope of the portion of the line 51 where the elongation and stress are 0 indicates the elastic modulus, and the value thereof is c. Lines 52 to 54 shown in FIG. 3 indicate stress-strain curves of the base insulating film when the temperature is 150 ° C., and all have a breaking strength of b. A line 52 shows a case where the elastic modulus d when the temperature is 150 ° C. is equal to c, a line 53 shows a case where the elastic modulus d when the temperature is 150 ° C. is equal to (c / 2), and a line 54 Indicates a case where the elastic modulus d is equal to (c / 3) when the temperature is 150 ° C.

If the ratio (a / b) is 2.5 or less and the breaking strength of the substrate insulating film is sufficiently high when the temperature is 150 ° C., cracks are generated even if thermal stress is repeatedly applied to the substrate insulating film. It is difficult to do so and the reliability of the wiring board is high. However, when the ratio (a / b) is larger than 2.5, the occurrence of cracks in the base insulating film depends on the integrated value of the stress-strain curve. This integral value indicates the work per unit cross-sectional area applied to the base insulating film until a crack occurs in the base insulating film, and corresponds to the strength of the base insulating film. Therefore, the larger the integral value, the harder the cracks are generated in the base insulating film and the higher the resistance to cracks. Assuming that the integral values of the lines 52 to 54 are S ₅₂ , S ₅₃ , and S ₅₄ , as shown in FIG. 3, the smaller the elastic modulus d, that is, the larger the ratio (c / d), the greater the stress − The integrated value of the distortion curve is large, and S ₅₂ <S ₅₃ <S ₅₄ . For this reason, from the viewpoint of occurrence of cracks, the larger the value of (c / d), the better, and (c / d) ≧ (a / b) −0.8 is preferable.

  However, if the value of the ratio (c / d) is too large, the rigidity of the base insulating film at a high temperature decreases, and excessive deformation occurs when a thermal stress is applied. As a result, although the base insulating film itself does not crack, the solder ball attached to the wiring board cannot follow the deformation of the base insulating film and may be damaged. Therefore, the value of the ratio (c / d) is preferably 4.7 or less, and more preferably (c / d) ≦ (a / b) +0.8. That is, if the absolute value of the difference between the ratio (c / d) value and the ratio (a / b) value is greater than 0.8, the base insulating film is likely to crack or the solder balls are likely to be damaged. . Therefore, the absolute value of the difference between the ratio (c / d) value and the ratio (a / b) value is preferably 0.8 or less.

  When the elastic modulus c when the temperature is −65 ° C. is smaller than d when the elastic modulus c is 150 ° C., that is, when the ratio (c / d) is less than 1.0, If the value of the ratio (c / d) is 0.21 or more which is the reciprocal of the upper limit value (4.7), it is considered that the solder ball can be prevented from being damaged. However, at present, there is no resin material having a ratio (c / d) value of less than 1.0, and it has not been confirmed experimentally. Ideally, a material whose physical properties do not change at all when the temperature is −65 ° C. and 150 ° C., that is, the ratio (a / b) value and the ratio (c / d) value are both 1.0. If the base insulating film is formed of the material to be obtained, there is no change in physical properties due to temperature change, and no influence of the heat cycle, so that the highest reliability can be obtained.

Elastic modulus of the base insulating film when the temperature is 150 ° C .: 2.3 GPa or more By setting the elastic modulus to 2.3 GPa or higher, the rigidity of the base insulating film at a high temperature is secured, and the base insulating film becomes the base insulating film. Therefore, it is possible to prevent the solder balls attached to the wiring board from being damaged. Accordingly, the elastic modulus of the base insulating film when the temperature is 150 ° C. is preferably 2.3 GPa or more.

Distance between lower surface of lower layer wiring and lower surface of base insulating film: 0.5 to 10 μm
If the distance between the lower surface of the lower layer wiring and the lower surface of the base insulating film is less than 0.5 μm, the effect of preventing the displacement of the bumps cannot be sufficiently obtained. On the other hand, when the distance exceeds 10 μm, the gap between the base insulating film and the semiconductor device becomes small when the semiconductor device is mounted on the wiring board. For this reason, when an underfill is provided by filling the gap with an underfill resin after mounting a semiconductor device, it is difficult to pour the underfill resin into the gap. Therefore, the distance is preferably 0.5 to 10 μm.

  In the semiconductor package 19 of the present embodiment, the solder ball 18, the upper layer wiring 11, the via hole 10, the lower layer wiring composed of the wiring main body 6 and the etching barrier layer 5, and the bump 14 are used from a mounting board (not shown). Electric power is supplied to the semiconductor device 15 and signals are input / output to drive the semiconductor device 15. At this time, the semiconductor device 15 generates heat, and this heat is transmitted to the mounting board via the wiring board 13. At this time, thermal stress is applied to the bumps 14, the wiring substrate 13, and the solder balls 18 due to the difference in thermal expansion coefficient between the semiconductor device 15 and the mounting board. Then, when the semiconductor device 15 repeats operation and pause, thermal stress is repeatedly applied to the bumps 14, the wiring substrate 13, and the solder balls 18.

  In this embodiment, since the base insulating film 7 has a thickness of 3 to 100 μm and a breaking strength at 23 ° C. of 80 MPa or more, the strength of the wiring board 13 can be ensured. Moreover, since the value of ratio (a / b) is 4.5 or less, the breaking strength at the time of high temperature is securable. Furthermore, since the values of the breaking strengths a and b and the elastic moduli c and d satisfy the above mathematical formula 1, the base insulating film 7 and the solder balls 18 are hardly cracked. For this reason, the semiconductor device 15 is repeatedly operated and paused, so that even if thermal stress is repeatedly applied to the wiring substrate 13, cracks do not occur in the base insulating film 7 and the solder balls 18, and the wiring substrate 13 and the semiconductor The reliability of the package 19 is high.

  Further, since the lower layer wiring composed of the etching barrier layer 5 and the wiring body 6 is in the recess 7a, and the lower surface of the lower layer wiring is 0.5 to 10 μm above the lower surface of the base insulating film 7, when bonding the bumps 14 In addition, the displacement and flow of the bumps 14 can be prevented. For this reason, since the connection reliability of the bumps 14 is excellent and the bumps 14 can be arranged at a fine pitch, the semiconductor device 15 having a high degree of integration can be mounted.

  Furthermore, since the through-hole is not provided in the wiring board 13, the problem caused by the through-hole, that is, the problem that the control of the impedance becomes difficult or the loop inductance is increased does not occur, and the high-speed wiring design In addition, highly integrated fine wiring design can be performed.

  In the present embodiment, the underfill 16 may be omitted. In general, flip chip type semiconductor packages do not require molding, and in this embodiment, no molding is provided. However, the semiconductor package requires a high degree of moisture resistance reliability, and the sealing performance of the semiconductor device (airtightness). In the case where it is desired to increase the mechanical strength of the semiconductor package by compensating for the thinness of the wiring board, molding is performed so that the underfill 16 and the semiconductor device 15 are covered on the lower surface of the wiring board 13. May be provided.

  Next, a modification of this embodiment will be described. FIG. 4 is a cross-sectional view showing a semiconductor package according to this modification. As shown in FIG. 4, in the semiconductor package according to this modification, semiconductor devices are mounted on both surfaces of the wiring board 13. That is, in addition to the semiconductor device 15 connected to the lower layer wiring via the bump 14, a semiconductor device 15a connected to the upper layer wiring 11 via the bump 14a is provided. A part of the electrode of the semiconductor device 15 is an electrode of the semiconductor device 15a (not shown) through the lower layer wiring composed of the bump 14, the etching barrier layer 5 and the wiring body 6, the via hole 10, the upper layer wiring 11, and the bump 14a. Connected). The configuration other than the above in the present modification is the same as that in the first embodiment. In this modification, two semiconductor devices can be mounted on one wiring board 13.

  Next, a second embodiment of the present invention will be described. FIG. 5 is a cross-sectional view showing the wiring board according to the present embodiment. As shown in FIG. 5, in the wiring substrate 13a according to the present embodiment, the adhesive resin layer 9 and the base insulating film are compared with the wiring substrate 13 (see FIG. 1) according to the first embodiment described above. A two-layer film made of the insulating layer 8 is provided. The adhesive resin layer 9 forms the lower layer of the base insulating film, and the insulating layer 8 forms the upper layer of the base insulating film.

  For example, the adhesive resin layer 9 is made of a material having a breaking strength of 70 MPa or more when the temperature is 23 ° C. and a breaking elongation of 5% or more when the temperature is 23 ° C. The material forming the adhesive resin layer 9 is preferably a resin having high heat resistance, low dielectric constant, and high strength. As such a resin, for example, epoxy resin, BT resin, cyanate resin, thermoplastic polyimide and the like are suitable. Examples of the epoxy resin include ABF-GX (trade name) manufactured by Ajinomoto Fine Techno, APL-4501 (trade name) manufactured by Sumitomo Bakelite, and examples of the cyanate resin include LαZ (trade name) manufactured by Sumitomo Bakelite, Examples of the thermoplastic polyimide include TPI (trade name) manufactured by Mitsui Chemicals. Moreover, polyolefin, vinyl resin, etc. can be mentioned as resin with especially low dielectric constant and dielectric loss, These resin is more preferable as a material of the board | substrate for high frequency transmission.

  The insulating layer 8 has a thickness of 1 μm or more, for example, 3 to 50 μm, a breaking strength when the temperature is 23 ° C. is 80 MPa or more, for example, 100 MPa or more, and a breaking strength when the temperature is −65 ° C. is a, When the breaking strength when the temperature is 150 ° C. is b, the value of the ratio (a / b) is 2.5 or less. Further, when the elastic modulus is c when the temperature is −65 ° C. and d is the elastic modulus when the temperature is 150 ° C., the breaking strengths a and b and the elastic modulus c and d satisfy the above formula 1. . Furthermore, the elastic modulus at a temperature of 150 ° C. is 2.3 GPa or more. The insulating layer 8 is made of a high-strength material whose strength is higher than that of the adhesive resin layer 9. When the material forming the adhesive resin layer 9 is a thermosetting material, the insulating resin layer 9 is formed at the curing temperature. When the material is a thermoplastic material, it is preferably a heat resistant material that does not soften and deform at the softening temperature. For the insulating layer 8, for example, a polyimide film, an aramid film, a liquid crystal film, or the like is suitable. Examples of the polyimide film include a film made of wholly aromatic polyimide or thermoplastic polyimide, such as Kapton (trade name) manufactured by Toray DuPont and Upilex (trade name) manufactured by Ube Industries. Examples of the aramid film include Aramika (trade name) manufactured by Asahi Kasei, and examples of the liquid crystal film include Kuraray Bexter (trade name) and BIAC (BIAC) (trade name).

  The total film thickness of the base insulating film composed of the insulating layer 8 and the adhesive resin layer 9 is 3 to 100 μm, preferably 5 to 80 μm, and more preferably 10 to 50 μm. Other configurations and operations of the wiring board and semiconductor package of the present embodiment are the same as those of the first embodiment. Hereinafter, the reason for the numerical limitation in each constituent requirement of the present invention will be described. The reason for limiting the numerical value of the mechanical characteristics of the insulating layer is the same as the reason for limiting the numerical value of the mechanical characteristics of the base insulating film in the first embodiment.

If the film thickness of the insulating layer is 1 μm or more and the film thickness of the insulating layer is 1 μm or more, even if a crack occurs in the adhesive resin layer, the progress of the crack in the insulating layer can be stopped. On the other hand, if the thickness of the insulating layer is less than 1 μm, the effect of stopping the progress of the cracks becomes insufficient, and the mechanical characteristics required for the wiring board cannot be ensured. Therefore, the thickness of the insulating layer is set to 1 μm or more.

Film thickness of base insulating film: 100 μm or less When the total film thickness of the base insulating film exceeds 100 μm, the via hole processability by laser processing is remarkably lowered, and fine via holes cannot be formed. Therefore, the film thickness of the base insulating film is 100 μm or less.

  In the present embodiment, by setting the thickness of the insulating layer 8 to 1 μm or more and the breaking strength when the temperature is 23 ° C. to 80 MPa or more, a thermal load is repeatedly applied to the wiring board 13a, and the adhesive resin layer 9 is temporarily provided. Even if cracks occur, the progress of the cracks can be stopped in the insulating layer 8, and the occurrence of cracks penetrating the base insulating film can be prevented. As a result, it is possible to prevent the wiring in the base insulating film from being cut or the bumps connected to the base insulating film from being broken due to cracks penetrating the base insulating film. When the breaking strength when the temperature is −65 ° C. is a and the breaking strength when the temperature is 150 ° C. is b, the ratio (a / b) is 2.5 or less, and the temperature is −65. When the elastic modulus at c is c and the elastic modulus at d is 150 ° C., the breaking strengths a and b and the elastic modulus c and d satisfy Equation 1 above, and the temperature is 150 ° C. By setting the elastic modulus to 2.3 GPa or more, strain stress generated in the base insulating film can be reduced, and the reliability of the wiring board and the semiconductor package can be improved. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

  In particular, when the insulating layer 8 is formed of polyimide, the strength of the polyimide is higher than that of a general resin material, so that the effect of stopping the progress of cracks generated in the adhesive resin layer 9 is great. In addition, since polyimide is an insulating material having a lower dielectric constant and lower dielectric loss than epoxy resin, a wiring board suitable for use in a high frequency region can be obtained. Moreover, since the insulating layer 8 is formed of a liquid crystal polymer, the liquid crystal polymer has a molecular order orientation, and thus the thermal expansion coefficient can be controlled by controlling the orientation. As a result, the thermal expansion coefficient of the insulating layer 8 can be made closer to the thermal expansion coefficient of silicon, or the thermal expansion coefficient of a metal wiring made of copper or the like. By making the thermal expansion coefficient of the insulating layer 8 close to the thermal expansion coefficient of silicon, the difference in thermal expansion between the semiconductor device and the silicon substrate can be reduced, and thermal stress can be suppressed. Further, since the liquid crystal polymer has a low dielectric constant, a low dielectric loss, and a low water absorption, it is also suitable as an insulating material for forming a wiring board from these points.

  Note that the interface between the insulating layer 8 and the adhesive resin layer 9 is not necessarily clearly present. That is, the base insulating film may be a gradient material whose composition is continuously changed between the insulating layer 8 and the adhesive resin layer 9.

  Next, a modification of this embodiment will be described. FIG. 6 is a cross-sectional view showing a method of manufacturing a wiring board according to this modification. As shown in FIG. 6, in this modification, a three-layer film composed of (adhesive resin layer 9 / insulating layer 8 / adhesive resin layer 9) is provided as the base insulating film. That is, one insulating layer 8 is provided, and two adhesive resin layers 9 are provided so as to sandwich the insulating layer 8. This wiring board is formed by being formed on the support substrate 1 and then removing the support substrate 1. A detailed manufacturing method of this wiring board will be described later. Other configurations and operations in the present modification are the same as those in the second embodiment described above.

  In this modification, the adhesion between the base insulating film and the upper layer wiring 11 can be improved as compared with the second embodiment described above. The effects of the present modification other than those described above are the same as those of the first embodiment.

  Next, a third embodiment of the present invention will be described. FIG. 7 is a cross-sectional view showing the wiring board according to the present embodiment, and FIG. 8 is a cross-sectional view showing the semiconductor package according to the present embodiment.

  As shown in FIG. 7, the substrate insulating film 7 is provided in the wiring substrate 21 according to the present embodiment. The film thickness and mechanical characteristics of the base insulating film 7 are the same as those of the base insulating film 7 in the first embodiment. A recess 7 a is formed on the lower surface of the base insulating film 7, a wiring body 6 is formed in the recess 7 a, and an etching barrier layer 5 is formed below the wiring body 6. The etching barrier layer 5 and the wiring body 6 form a lower layer wiring, and this lower layer wiring is embedded in the recess 7a. The configurations of the etching barrier layer 5 and the wiring body 6 are the same as those in the first embodiment.

  Further, a via hole 10 is formed in a part of the base insulating film 7 immediately above the recess 7a. Further, a conductive material is embedded in the via hole 10, and an intermediate wiring 22 is formed on the base insulating film 7. The conductive material and the intermediate wiring 22 in the via hole 10 are integrally formed, and the intermediate wiring 22 is connected to the lower layer wiring through the via hole 10. Furthermore, a final insulating film 23 is formed on the base insulating film 7 so as to cover the intermediate wiring 22, and a via hole 24 is formed in a part of the region immediately above the intermediate wiring 22 in the final insulating film 23. Is formed. A conductive material is embedded in the via hole 24, and the upper layer wiring 11 is formed on the final insulating film 23. The conductive material in the via hole 24 and the upper layer wiring 11 are integrally formed, and the upper layer wiring 11 is connected to the intermediate wiring 22 through the via hole 24. Furthermore, a solder resist 12 is formed on the final insulating film 23 so as to expose a part of the upper wiring 11 and cover the remaining part. The exposed portion of the upper layer wiring 11 becomes a pad electrode. The film thickness and mechanical characteristics of the final insulating film 23 are the same as the film thickness and mechanical characteristics of the base insulating film 7.

  Next, the configuration of the semiconductor package according to the present embodiment will be described. As shown in FIG. 8, in the semiconductor package 25 according to the present embodiment, a plurality of bumps 14 are connected to the etching barrier layer 5 in the wiring substrate 21 described above. A semiconductor device 15 is provided below the wiring substrate 21, and electrodes (not shown) of the semiconductor device 15 are connected to the bumps 14. An underfill 16 is filled around the bumps 14 between the wiring board 21 and the semiconductor device 15. On the other hand, a solder ball 18 is mounted on an exposed portion of the upper layer wiring 11 of the wiring substrate 21, that is, a part of the pad electrode. The solder ball 18 is connected to the electrode of the semiconductor device 15 through the upper layer wiring 11, the via hole 24, the intermediate wiring 22, the via hole 10, the lower layer wiring composed of the wiring body 6 and the etching barrier layer 5, and the bump 14. Other configurations and operations of the wiring board and the semiconductor package according to the present embodiment are the same as those in the first embodiment.

  In the present embodiment, since the wiring substrate 21 has a two-layer structure including the base insulating film 7 and the final insulating film 23, the semiconductor device 15 and the solder balls 18 are compared with the first embodiment described above. The stress relaxation effect between the two is great. Further, the number of signals input to and output from the semiconductor device 15 can be increased by making the wiring board 21 have a two-layer structure. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

  In the present embodiment, the base insulating film 7 may be composed of the adhesive resin layer 9 and the insulating layer 8 as in the above-described second embodiment or its modification. In this case, the mechanical properties of the adhesive resin layer 9 and the insulating layer 8 are the same as in the second embodiment.

  Further, the structure of the base insulating film 7 is the same as that of the base insulating film in the first embodiment described above, that is, the film thickness is 3 to 100 μm and the breaking strength when the temperature is 23 ° C. is 80 MPa or more. A single layer insulating film having a ratio (a / b) of 2.5 or less, where a is the breaking strength when the temperature is −65 ° C. and b is the breaking strength when the temperature is 150 ° C. The configuration of the final insulating film 23 is the same as that of the base insulating film in the second embodiment described above, that is, an adhesive resin layer and an insulating layer. The breaking strength at 70 ° C. is 70 MPa or more, the breaking elongation when the temperature is 23 ° C. is 5% or more, the thickness of the insulating layer is 3 to 50 μm, and the breaking strength when the temperature is 23 ° C. is 80 MPa. When the temperature is −65 ° C., the breaking strength is a and the temperature is 1 When the breaking strength at 50 ° C. is b, the ratio (a / b) value may be 2.5 or less.

  Further, in the present embodiment, an example is shown in which the material of the base insulating film 7 and the final insulating film 23 is the same material as the base insulating film in the first or second embodiment described above. If one of the base insulating film 7 and the final insulating film 23 is the same material as the base insulating film in the first or second embodiment, a certain effect can be obtained.

  Next, a fourth embodiment of the present invention will be described. FIG. 9 is a cross-sectional view showing a wiring board according to this embodiment, and FIG. 10 is a cross-sectional view showing a semiconductor package according to this embodiment.

  As shown in FIG. 9, the substrate insulating film 7 is provided in the wiring substrate 31 according to the present embodiment. The film thickness and mechanical characteristics of the base insulating film 7 are the same as those of the base insulating film 7 in the first embodiment. A recess 7 a is formed on the lower surface of the base insulating film 7, a wiring body 6 is formed in the recess 7 a, and an etching barrier layer 5 is formed below the wiring body 6. The configurations of the etching barrier layer 5 and the wiring body 6 are the same as those in the first embodiment.

  Further, a via hole 10 is formed in a part of the base insulating film 7 immediately above the recess 7a. Further, a conductive material is embedded in the via hole 10, and an intermediate wiring 32 is formed on the base insulating film 7. The conductive material and the intermediate wiring 32 in the via hole 10 are integrally formed, and the intermediate wiring 32 is connected to the lower layer wiring through the via hole 10. Furthermore, an intermediate insulating film 33 is formed on the base insulating film 7 so as to cover the intermediate wiring 32, and a via hole 34 is formed in a part of the intermediate insulating film 33 directly above the intermediate wiring 32. Is formed. A conductive material is embedded in the via hole 34, and the intermediate wiring 22 is formed on the intermediate insulating film 33. The conductive material and the intermediate wiring 22 in the via hole 34 are integrally formed, and the intermediate wiring 22 is connected to the intermediate wiring 32 through the via hole 34.

  Further, a final insulating film 23 is formed on the intermediate insulating film 33 so as to cover the intermediate wiring 22, and a via hole 24 is formed in a portion of the final insulating film 23 immediately above the intermediate wiring 22. Has been. A conductive material is embedded in the via hole 24, and the upper layer wiring 11 is formed on the final insulating film 23. The conductive material in the via hole 24 and the upper layer wiring 11 are integrally formed, and the upper layer wiring 11 is connected to the intermediate wiring 22 through the via hole 24. Furthermore, a solder resist 12 is formed on the final insulating film 23 so as to expose a part of the upper wiring 11 and cover the remaining part. The exposed portion of the upper layer wiring 11 becomes a pad electrode. The film thickness and mechanical characteristics of the final insulating film 23 are the same as the film thickness and mechanical characteristics of the base insulating film 7.

  Next, the configuration of the semiconductor package according to the present embodiment will be described. As shown in FIG. 10, in the semiconductor package 35 according to the present embodiment, a plurality of bumps 14 are connected to the etching barrier layer 5 in the wiring substrate 31 described above. A semiconductor device 15 is provided below the wiring substrate 31, and electrodes (not shown) of the semiconductor device 15 are connected to the bumps 14. The underfill 16 is filled around the bumps 14 between the wiring board 31 and the semiconductor device 15. On the other hand, a solder ball 18 is mounted on an exposed portion of the upper layer wiring 11 of the wiring substrate 31, that is, a part of the pad electrode. The solder ball 18 is connected to the semiconductor device 15 via the upper layer wiring 11, the via hole 24, the intermediate wiring 22, the via hole 34, the intermediate wiring 32, the via hole 10, the lower layer wiring composed of the wiring body 6 and the etching barrier layer 5, and the bump 14. Is connected to the electrode. Other configurations and operations of the wiring board and the semiconductor package according to the present embodiment are the same as those in the first embodiment.

  In the present embodiment, since the wiring board 31 has a three-layer structure including the base insulating film 7, the intermediate insulating film 33, and the final insulating film 23, compared with the first and second embodiments described above. The stress relaxation effect between the semiconductor device 15 and the solder ball 18 is great. Further, the number of signals input to and output from the semiconductor device 15 can be increased by making the wiring board 31 have a three-layer structure. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

  In the present embodiment, the base insulating film 7 may be composed of the adhesive resin layer 9 and the insulating layer 8 as in the above-described second embodiment or its modification. In this case, the mechanical properties of the adhesive resin layer 9 and the insulating layer 8 are the same as in the second embodiment.

  Further, the structure of the base insulating film 7 is the same as that of the base insulating film in the first embodiment described above, that is, the film thickness is 3 to 100 μm and the breaking strength when the temperature is 23 ° C. is 80 MPa or more. A single layer insulating film having a ratio (a / b) of 2.5 or less, where a is the breaking strength when the temperature is −65 ° C. and b is the breaking strength when the temperature is 150 ° C. The configuration of the final insulating film 23 may be the same as that of the base insulating film in the second embodiment described above.

  Furthermore, in this embodiment, an example in which the base insulating film 7 and the final insulating film 23 are made of the same material as the base insulating film in the first or second embodiment described above is shown. It is not limited to this. For example, in addition to the base insulating film 7 and the final insulating film 23, the material of the intermediate insulating film 33 may be the same as the base insulating film in the first or second embodiment. Thereby, a more reliable wiring board and semiconductor package can be obtained. Alternatively, if one of the base insulating film 7 and the final insulating film 23 is made of the same material as that of the base insulating film in the first or second embodiment, a certain effect can be obtained while suppressing costs. be able to.

  Furthermore, in the above-described third embodiment, a wiring board provided with two insulating films is shown, and in the fourth embodiment, a wiring board provided with three insulating films is shown. However, the present invention is not limited to this, and may be a wiring board provided with four or more insulating films.

  Next, a fifth embodiment of the present invention will be described. FIGS. 11A to 11C are cross-sectional views showing the method and structure for manufacturing a wiring board according to this embodiment in the order of the steps. In the wiring board according to the present embodiment, the lower surface of the base insulating film 7 and the lower surface of the lower layer wiring composed of the etching barrier layer 5 and the wiring body 6 constitute the same plane. A protective film 41 is formed under the base insulating film 7. The protective film 41 is made of, for example, epoxy resin or polyimide, and the film thickness thereof is, for example, 1 to 50 μm. The protective film 41 is formed with an etching portion 42 that is an opening, and a part of the lower layer wiring is exposed in the etching portion 42. That is, the protective film 41 exposes a part of the lower layer wiring in the etching part 42 and covers the remaining part of the lower layer wiring by a part other than the etching part 42. The etching part 42 is a part to which the bumps 14 (see FIG. 1) are connected when a semiconductor device is mounted on the wiring board. Other configurations and operations of the wiring board and the semiconductor package according to the present embodiment are the same as those of the first embodiment.

  In the present embodiment, by providing the protective film 41, the adhesion between the wiring board and a resin layer such as an underfill can be improved. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

  Next, a sixth embodiment of the present invention will be described. FIG. 12 is a cross-sectional view showing the wiring board according to the present embodiment. As shown in FIG. 12, in the wiring board according to the present embodiment, the protective film 41 (see FIG. 11) is omitted as compared with the wiring board according to the fifth embodiment described above. Thereby, the lower surface of the lower layer wiring is not recessed from the lower surface of the wiring substrate 43 and constitutes the same plane. Other configurations of the wiring board of the present embodiment are the same as those of the fifth embodiment described above.

  In this embodiment, since the protective film is omitted as compared with the fifth embodiment described above, the cost can be reduced. Also, compared with the first embodiment described above, the formation of the easy etching layer 4 (see FIG. 13A) can be omitted, so that the cost can be reduced. The arrangement pitch of the electrodes of the semiconductor device 15 is not so fine, the arrangement density of the bumps 14 (see FIG. 1) is low, and the positioning accuracy of the bumps is not so required, and the molding is not provided, or the molding If the adhesiveness between the molding and the wiring board is not so required even if the wiring board is provided, the wiring board according to the present embodiment is suitable from the viewpoint of cost. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

  Next, a method for manufacturing a wiring board and a semiconductor package according to each of the above embodiments will be described. First, a method for manufacturing a wiring board and a semiconductor package according to the first embodiment will be described. FIGS. 13A to 13E are cross-sectional views showing the manufacturing method of the wiring board according to the present embodiment in the order of steps, and FIGS. 14A and 14B are the manufacturing method of the semiconductor package according to the present embodiment. Is a cross-sectional view showing the semiconductor package when the molding is provided. First, as shown in FIG. 13A, a support substrate 1 made of a metal or an alloy, for example, Cu, is prepared, a resist 2 is formed on the support substrate 1 and patterned. Next, the easy etching layer 4, the etching barrier layer 5, and the wiring body 6 are formed in this order by, for example, plating. At this time, in the region where the resist 2 is removed on the support substrate 1, the conductor wiring layer 3 including the easy etching layer 4, the etching barrier layer 5, and the wiring body 6 is formed, but the resist 2 remains. The conductor wiring layer 3 is not formed in the region. The easy etching layer 4 is formed of, for example, a Cu single-layer plating layer, a two-layer plating layer composed of a Cu layer and a Ni layer, or a Ni single-layer plating layer, and has a thickness of, for example, 0.5 to 10 μm. The Ni layer in the two-layer plating layer is provided in order to prevent diffusion between the Cu layer of the easy etching layer 4 and the etching barrier layer 5 at a high temperature. 1 μm or more. The etching barrier layer 5 is, for example, a Ni, Au, or Pd plating layer, and has a thickness of, for example, 0.1 to 7.0 μm. The wiring body 6 is formed of a conductor plating layer such as Cu, Ni, Au, Al or Pd, and has a thickness of 2 to 20 μm, for example. Even when the etching barrier layer 5 is formed of Au, a Ni layer is provided between the etching barrier layer 5 and the wiring body 6 in order to prevent diffusion with Cu forming the wiring body 6. Also good.

  Next, as shown in FIG. 13B, the resist 2 is removed. Next, as shown in FIG. 13C, the base insulating film 7 is formed so as to cover the conductor wiring layer 3. The base insulating film 7 is formed by, for example, laminating a sheet-like insulating film on the supporting substrate 1 or attaching the insulating film 7 to the supporting substrate 1 by a pressing method, and performing a heat treatment for holding at a temperature of 100 to 400 ° C. for 10 minutes to 2 hours, for example. And the insulating film is cured to form. The temperature and time of the heat treatment are appropriately adjusted according to the type of insulating film. Thereby, the base insulating film 7 made of, for example, aramid can be formed. Alternatively, the base insulating film 7 may be formed by applying a varnish-like insulating material on the support substrate 1 by a method such as spin coating, curtain coating, or die coating, and drying it by an oven or a hot plate. The insulating material is cured by heat treatment that is held at a temperature of 400 ° C. for 10 minutes to 2 hours. Thereby, the base insulating film 7 made of, for example, polyimide can be formed. Then, a via hole 10 is formed in a part of the base insulating film 7 immediately above the conductor wiring layer 3 by a laser processing method.

  Next, as shown in FIG. 13 (d), a conductive material is embedded in the via hole 10, and an upper layer wiring 11 is formed on the base insulating film 7. At this time, the upper layer wiring 11 is connected to the wiring body 6 through the via hole 10. When the wiring board 13 is used for a semiconductor package of CSP (chip size package), the diameter of the via hole 10 is 40 μm, for example, and the wiring board 13 is used for a semiconductor package of FCBGA (flip chip ball grid array). The diameter of the via hole 10 is, for example, 75 μm. The conductive material and the upper layer wiring 11 embedded in the via hole 10 are made of, for example, a conductor plating layer such as Cu, Ni, Au, Al, or Pd, and the thickness of the upper layer wiring 11 is, for example, 2 to 20 μm. Next, a solder resist 12 is formed so as to cover a part of the upper layer wiring 11 and expose the remaining part. The thickness of the solder resist 12 is, for example, 5 to 40 μm. The formation of the solder resist 12 can be omitted.

  Next, as shown in FIG. 13E, the support substrate 1 is removed by chemical etching or polishing. Next, as shown in FIG. 1, the easy etching layer 4 is removed by etching. Thereby, the wiring board 13 according to the present embodiment shown in FIG. 1 is formed. At this time, when the material for forming the support substrate 1 is different from the material for forming the easy-to-etch layer 4, the etching process is required twice as described above, but the support substrate 1 and the easy-to-etch layer 4 are formed of the same material. If it is, the etching process may be performed once.

  Next, as shown in FIG. 14A, a plurality of bumps 14 are bonded to the exposed portion of the etching barrier layer 5. Then, the semiconductor device 15 is mounted on the wiring board 13 by the flip chip method via the bumps 14. At this time, an electrode (not shown) of the semiconductor device 15 is connected to the bump 14.

  Next, as shown in FIG. 14B, an underfill 16 is poured between the wiring substrate 13 and the semiconductor device 15 to solidify it. As a result, the bumps 14 are embedded in the underfill 16. The formation of the underfill 16 may be omitted. Further, as shown in FIG. 14C, a molding 17 may be appropriately formed on the lower surface of the wiring board 13 so as to cover the underfill 16 and the semiconductor device 15.

  Next, as shown in FIG. 2, solder balls 18 are mounted on the exposed portions of the upper wiring 11 of the wiring board 13. Thereby, the semiconductor package 19 according to the present embodiment shown in FIG. 2 is formed.

  In the present embodiment, since the conductor wiring layer 3, the base insulating film 7, the upper layer wiring 11 and the like are formed on the hard support substrate 1 made of Cu, for example, the flatness of the wiring substrate 13 can be increased.

  In this embodiment, an example in which a substrate made of a metal or an alloy is used as the support substrate 1 is shown. However, a substrate made of an insulator such as a silicon wafer, glass, ceramic, or resin is used as the support substrate 1. Also good. When a substrate made of an insulator is used, the conductor wiring layer 3 is formed by electroless plating after the resist 2 is formed, or after the resist 2 is formed, electroless plating, sputtering, vapor deposition The power supply conductor layer may be formed by a method such as the method, and then the conductor wiring layer 3 may be formed by an electrolytic plating method.

  Further, in the present embodiment, an example in which the semiconductor device 15 is mounted on the wiring board 13 by the flip chip method has been shown. However, the semiconductor device 15 may be mounted on the wiring board 13 by another method such as a wire bonding method or a tape auto-med bonding method. May be installed.

  Next, a method for manufacturing a wiring board according to the second embodiment will be described. FIG. 15 is a cross-sectional view showing a method for manufacturing a wiring board according to the present embodiment. 13A and 13B, the conductor wiring layer 3 including the easy etching layer 4, the etching barrier layer 5, and the wiring body 6 is formed on the support substrate 1.

  Thereafter, as shown in FIG. 15, a base insulating film composed of the adhesive resin layer 9 and the insulating layer 8 is formed so as to cover the conductor wiring layer 3 on the support substrate 1. At this time, the adhesive resin layer 9 and the insulating layer 8 can be collectively laminated on the support substrate 1 to form a base insulating film, but in addition, the adhesive resin layer 9 and the insulating layer 8 are mutually connected in advance. Then, the base insulating film may be formed on the support substrate 1, or the adhesive resin layer 9 may be previously stacked on the support substrate 1, and then the adhesive resin may be laminated. The insulating layer 8 may be laminated on the layer 9 to form a base insulating film. In these cases, when the adhesive resin layer 9 is made of a thermosetting resin, the adhesive resin layer 9 made of the thermosetting resin is laminated on the insulating layer 8 or the support substrate 1 by lamination or application, and is in a semi-cured state. Then, after laminating with the support substrate 1 or the insulating layer 8, the adhesive resin layer 9 made of a thermosetting resin is cured by holding at a temperature of 100 to 400 ° C. for 10 minutes to several hours. Further, when the adhesive resin layer 9 is made of a thermoplastic resin, the adhesive resin layer 9 made of the thermoplastic resin is laminated with the insulating layer 8 or the support substrate 1 while being softened by heating. By such a method, a base insulating film is formed on the support substrate 1.

  At this time, the material of the insulating layer 8 has a breaking strength of 80 MPa or more when the temperature is 23 ° C., a is the breaking strength when the temperature is −65 ° C., and b is the breaking strength when the temperature is 150 ° C. When the value of the ratio (a / b) is 2.5 or less, the elastic modulus when the temperature is −65 ° C. is c, and the elastic modulus when the temperature is 150 ° C. is d, the ratio ( An insulating material in which the value of c / d) is 4.7 or less and the values of a to d satisfy Equation 1 above is used.

  Next, a via hole 10 is formed in the base insulating film composed of the adhesive resin layer 9 and the insulating layer 8 by laser processing. The subsequent steps in the method for manufacturing the wiring board 13a (see FIG. 5) are the same as the steps shown in FIGS. 13 (d) and 13 (e). Thereby, the wiring board 13a of the second embodiment shown in FIG. 5 is manufactured. In addition, the semiconductor package manufacturing method of the present embodiment is the same as the steps shown in FIGS. 14 (a) and 14 (b).

  In this embodiment, by providing the adhesive resin layer 9 in the base insulating film, the adhesion between the support substrate 1 and the base insulating film can be improved. Thereby, the material with low adhesiveness with the support substrate 1 can be used as the material of the insulating layer 8. That is, in the first embodiment described above, it is necessary to select a material having a predetermined mechanical characteristic and good adhesion to the support substrate 1 as the material of the base insulating film 7. On the other hand, in the present embodiment, the insulating layer 8 bears the necessary mechanical properties, and the adhesive resin layer 9 can bear the adhesion between the supporting substrate 1, so that the base insulating film is formed. The choice of materials can be expanded. As a result, the performance of the base insulating film can be improved or the cost can be reduced. Examples of the insulating layer 8 include a liquid crystal polymer and polyimide.

  Conventionally, a base insulating film made only of an epoxy resin has been used, but the epoxy resin is difficult to handle because it is small in elongation and brittle. For this reason, generally, a film made of an epoxy resin is formed on a PET (polyethylene terephthalate) as a supporting substrate, and the supporting substrate is peeled off from the epoxy resin film when used as a substrate insulating film. For this reason, when forming a wiring board, the process of peeling a support base | substrate from this epoxy resin film is needed. In addition, a base insulating film made only of an epoxy resin is likely to crack and has low resistance to thermal stress. On the other hand, according to the method of the present embodiment, the insulating layer 8 made of a high-strength material also serves as a support substrate for the epoxy film as the adhesive resin layer 9, so that the step of peeling the support substrate becomes unnecessary. In addition, since the insulating layer 8 plays a role of preventing the progress of cracks, a base insulating film having high resistance to thermal stress can be obtained.

  Next, a method for manufacturing a wiring board according to a modification of the second embodiment will be described. In this modification, the conductor wiring layer 3 is formed on the support substrate 1 by the method shown in FIGS. Thereafter, as shown in FIG. 6, a base insulating film composed of a three-layer film of (adhesive resin layer 9 / insulating layer 8 / adhesive resin layer 9) is formed so as to cover the conductor wiring layer 3. The manufacturing method other than the above in this modification is the same as that of the second embodiment described above.

  Next, a method for manufacturing a wiring board and a semiconductor package according to the third embodiment will be described. 16A to 16D are cross-sectional views showing a method of manufacturing a wiring board according to this embodiment in the order of steps. First, by the method shown in FIGS. 13A to 13C, a conductor wiring layer 3 including an easy etching layer 4, an etching barrier layer 5 and a wiring body 6 is formed on the support substrate 1. A base insulating film 7 is formed so as to cover it, and a via hole 10 is formed in the base insulating film 7.

  Next, as shown in FIG. 16A, a conductive material is embedded in the via hole 10 and an intermediate wiring 22 is formed on the base insulating film 7. At this time, the intermediate wiring 22 is connected to the wiring body 6 through the via hole 10. Next, as illustrated in FIG. 16B, a final insulating film 23 is formed so as to cover the intermediate wiring 22. The method for forming the final insulating film 23 is the same as the method for forming the base insulating film 7, for example. Then, a via hole 24 is formed in a part of the final insulating film 23 immediately above the intermediate wiring 22.

  Next, as shown in FIG. 16C, a conductive material is embedded in the via hole 24, and the upper layer wiring 11 is formed on the final insulating film 23. At this time, the upper layer wiring 11 is connected to the intermediate wiring 22 through the via hole 24. Next, a solder resist 12 is formed so as to cover a part of the upper layer wiring 11 and expose the remaining part. Next, as shown in FIG. 16D, the support substrate 1 is removed by chemical etching or polishing.

  Next, as shown in FIG. 7, the easy etching layer 4 is removed by etching. Thereby, the wiring board 21 according to the present embodiment shown in FIG. 7 is formed.

  Next, as shown in FIG. 8, a plurality of bumps 14 are bonded to the exposed portion of the etching barrier layer 5. Then, the semiconductor device 15 is mounted on the wiring board 21 via the bumps 14 by a flip chip method. At this time, an electrode (not shown) of the semiconductor device 15 is connected to the bump 14. Next, the underfill 16 is poured between the wiring substrate 21 and the semiconductor device 15 to be solidified. As a result, the bumps 14 are embedded in the underfill 16. Next, the solder ball 18 is mounted on the exposed portion of the upper layer wiring 11 of the wiring board 21. Thereby, the semiconductor package 25 according to this embodiment shown in FIG. 8 is formed. Note that the formation of the underfill 16 may be omitted as in the first and second embodiments described above. Alternatively, a molding may be formed on the lower surface of the wiring board 21 so as to cover the underfill 16 and the semiconductor device 15.

  Next, a method for manufacturing a wiring board and a semiconductor package according to the fourth embodiment will be described. 17A to 17D are cross-sectional views showing the method of manufacturing the wiring board according to this embodiment in the order of steps. First, the conductor wiring layer 3 is formed on the support substrate 1 by the method shown in FIGS. 13A to 13C, the base insulating film 7 is formed so as to cover the conductive wiring layer 3, and this base insulating film is formed. 7, a via hole 10 is formed.

  Next, as shown in FIG. 17A, a conductive material is embedded in the via hole 10, and an intermediate wiring 32 is formed on the base insulating film 7. At this time, the intermediate wiring 32 is connected to the wiring body 6 via the via hole 10. Next, as illustrated in FIG. 17B, an intermediate insulating film 33 is formed so as to cover the intermediate wiring 32. Then, a via hole 34 is formed in a part of the intermediate insulating film 33 immediately above the intermediate wiring 32. Next, a conductive material is embedded in the via hole 34, and the intermediate wiring 22 is formed on the intermediate insulating film 33. The intermediate wiring 22 is connected to the intermediate wiring 32 through the via hole 34.

  Next, as shown in FIG. 17C, a final insulating film 23 is formed so as to cover the intermediate wiring 22. Then, a via hole 24 is formed in a part of the final insulating film 23 immediately above the intermediate wiring 22.

  Next, as shown in FIG. 17D, a conductive material is embedded in the via hole 24 and the upper wiring 11 is formed on the final insulating film 23. At this time, the upper layer wiring 11 is connected to the intermediate wiring 22 through the via hole 24. Next, a solder resist 12 is formed so as to cover a part of the upper layer wiring 11 and expose the remaining part.

  Next, as shown in FIG. 9, the support substrate 1 is removed by chemical etching or polishing. Then, the easy etching layer 4 is removed by etching. Thereby, the wiring board 31 according to the present embodiment shown in FIG. 9 is formed.

  Next, as shown in FIG. 10, a plurality of bumps 14 are bonded to the exposed portion of the etching barrier layer 5. Then, the semiconductor device 15 is mounted on the wiring board 31 by the flip chip method via the bumps 14. At this time, an electrode (not shown) of the semiconductor device 15 is connected to the bump 14. Next, the underfill 16 is poured between the wiring substrate 31 and the semiconductor device 15 to be solidified. As a result, the bumps 14 are embedded in the underfill 16. Next, the solder ball 18 is mounted on the exposed portion of the upper layer wiring 11 of the wiring board 31. Thereby, the semiconductor package 35 according to the present embodiment shown in FIG. 10 is formed.

  Next, a method for manufacturing a wiring board according to the fifth embodiment will be described. First, as shown in FIG. 11A, a protective film 41 is attached to the entire surface of the support substrate 1 by, for example, laminating or pressing. Next, the protective film 41 is cured by performing a heat treatment that is held at a temperature of 100 to 400 ° C. for 10 minutes to 2 hours, for example. The temperature and time of this heat treatment are appropriately adjusted depending on the material for forming the protective film 41. The film thickness of the protective film 41 is, for example, 1 to 50 μm.

  Next, a resist (not shown) is formed on the protective film 41 and patterned, and a lower layer wiring composed of the etching barrier layer 5 and the wiring body 6 is formed in the region where the resist is removed. Then, a base insulating film 7 is formed so as to cover the lower layer wiring, a via hole 10 is formed in the base insulating film 7, a conductive material is embedded in the via hole 10, and an upper layer wiring 11 is formed on the base insulating film 7. Form. Next, a solder resist 12 is formed so as to cover a part of the upper layer wiring 11.

  Next, as shown in FIG. 11B, the support substrate 1 is removed. Next, as shown in FIG. 11C, the protective film 41 is selectively removed by etching, and the lower layer wiring is exposed in the etching portion 42 from which the protective film 41 has been removed. Thereby, the wiring board according to the present embodiment is formed. Then, bumps 14 (see FIG. 1) are attached to the etching portion 42 to mount the semiconductor device 15 (see FIG. 1), and the underfill 16 (see FIG. 1) is filled between the wiring board and the semiconductor device 15. In addition, the solder ball 18 (see FIG. 1) is connected to the upper layer wiring 11. Thereby, the semiconductor package according to the present embodiment is formed. Manufacturing methods other than those described above for the wiring board and semiconductor package of this embodiment are the same as those of the first embodiment.

  In each of the above-described embodiments, the example in which the support substrate 1 is finally removed has been shown, but the present invention is not limited to this. For example, only a part of the support substrate 1 may be removed to leave the remaining part, and the remaining part of the support substrate 1 may be used as a stiffener, for example. Alternatively, the stiffener may be attached to the wiring board again after all the support substrate 1 is removed.

  The embodiments of the wiring board, the manufacturing method thereof, the base insulating film, and the semiconductor package of the present invention have been described above with reference to the drawings. The specific configuration of the present invention is the first to sixth embodiments described above. It is not limited to the form, and the design can be changed without departing from the gist of the present invention.

  Hereinafter, the effect of the present invention will be specifically described in comparison with a comparative example that is out of the scope of the claims. 18 (a) and 18 (b) are micrographs showing the shape of a sample for evaluation test, (a) shows a CSP (chip size package) sample, and (b) shows an FCBGA (flip chip ball grid array). Samples are shown. 19 and 20 (a) to 20 (c) show the embodiment No. of the present invention. 5 is a photomicrograph showing that the progress of cracks is stopped at the insulating layer in the FCBGA sample of No. 5. Further, FIGS. 21A and 21B are micrographs showing defective portions of the opened sample, where FIG. 21A shows resin cracks and FIG. 21B shows solder ball cracks.

  As shown in FIGS. 18A and 18B, a wiring substrate having one or three insulating films was manufactured by the method described in the first, second, and fourth embodiments. Next, LSIs and solder balls as semiconductor devices were mounted on this wiring board, and two types of semiconductor packages of CSP and FCBGA were produced. A part of the semiconductor package was mounted on a mounting board, and a sample mounted on the board was produced. Hereinafter, a single CSP semiconductor package or a sample on which this is mounted on a board is referred to as a CSP sample, and a single FCBGA semiconductor package or a sample on which this is mounted on a board is referred to as an FCBGA sample. Table 1 shows the configurations of the CSP sample and the FCBGA sample. For a wiring board with one insulating layer mounted on a CSP sample, the types of resins constituting the base insulating film are different among the samples, and three insulating layers mounted on the FCBGA sample (base insulating film) , Intermediate insulating film, and final insulating film), the types of resins forming the three-layer insulating film were different among the samples.

  As shown in FIG. 18A, in the CSP sample, an LSI 56 is mounted on a wiring board 55 and sealed with a molding 57. The wiring board 55 and the LSI 56 are connected to each other by wire bonding, and are fixed to each other by a mount material (die attach material). For this reason, no underfill is provided. A solder ball 58 is connected to the wiring board 55. Similar to the semiconductor package 19 shown in FIG. 2, the wiring board 55 is a wiring board having a single insulating film, and a base insulating film is provided as the insulating film.

  Further, as shown in FIG. 18B, in the FCBGA sample, the LSI 60 is mounted on the wiring board 59. Underfill 66 is provided between the wiring board 59 and the LSI 60 and on the side of the LSI 60, and stiffeners 67 are mounted on both sides of the LSI 60 on the wiring board 59. A heat dissipation sheet 68 made of a heat conductive paste or the like is provided on the LSI 60, and a heat sink 69 made of copper is provided on the heat dissipation sheet 68 and the stiffener 67. Further, solder balls 58 are connected to the wiring board 59. Similar to the semiconductor package 35 shown in FIG. 10, the wiring substrate 59 is a wiring substrate provided with three insulating films, that is, a base insulating film, an intermediate insulating film, and a final insulating film.

  Next, the mechanical properties of the insulating film in the samples shown in Table 1, that is, the breaking strength, the elastic modulus, and the breaking elongation were measured. The measurement was performed by cutting a film of an insulating film into a strip shape having a width of 1 cm and performing a tensile test in accordance with “JPCA standard built-up wiring board JPCA-BU01 section 4.2”. The measurement temperature was set at three levels of -65 ° C, 23 ° C, and 150 ° C. The measurement results are shown in Table 2. In the types of resin of the insulating film shown in Table 2, “P” represents polyimide, “A” represents aramid, “L” represents a liquid crystal polymer, “E” represents epoxy, and “F”. Indicates a porous fluororesin. Further, “+ j” indicates that one or two adhesive resin layers are provided in addition to the insulating film.

  Further, based on the mechanical characteristic values shown in Table 2, the temperature dependence was calculated. That is, when the breaking strength when the temperature is −65 ° C. is a and the breaking strength when the temperature is 150 ° C. is b, the ratio (a / b) value is calculated, and the temperature is −65 ° C. When the elastic modulus at the time is c and the elastic modulus at the temperature of 150 ° C. is d, the ratio (c / d) value is calculated, and the value of | c / d−a / b | is calculated. did. Table 3 shows the calculation results.

  Furthermore, the thermal stress durability of the samples shown in Table 2 was evaluated. The thermal stress durability was evaluated for a single semiconductor package and a board mounting sample. For the single sample of the CSP sample, a heat cycle in which a basic cycle of holding at a temperature of −150 ° C. for 30 minutes was repeated for a predetermined number of times after being held at a temperature of −65 ° C. for 30 minutes was applied. In addition, for other samples, that is, a CSP sample board mounting sample and a single FCBGA sample sample and a board mounting sample, a basic cycle of holding at a temperature of −40 ° C. for 30 minutes and then holding at a temperature of + 125 ° C. for 30 minutes. A heat cycle was repeated for a predetermined number of times. Then, in each sample, the number of cycles in which electrical connection open, that is, disconnection occurred, was evaluated. The transition time for transition from low temperature (−65 ° C. or −40 ° C.) to high temperature (+ 150 ° C. or + 125 ° C.) and transition time for transition from high temperature to low temperature vary depending on the ability of the heat cycle tester and the heat capacity of the sample. It was adjusted.

  In addition, when evaluating the heat stress durability of a semiconductor device, if a heat cycle test is performed on actual use conditions (25-70 degreeC), a long time will be required for a test. For this reason, the heat test of (-65-150 degreeC) or (-40-125 degreeC) is applied to a sample, and an acceleration test is done. Referring to the value obtained by the Coffin-Manson equation shown in EIAJ-ET-7404 (established in April 1999) regarding the acceleration performance of the temperature cycle test, for example, the heat cycle of (−40 to 125 ° C.) is Acceleration is 5.7 times higher than actual use conditions (25 to 70 ° C., 1 cycle / day). For this reason, 600 cycles at (−40 to 125 ° C.) correspond to about 10 years under actual use conditions.

  Table 3 shows the evaluation results of the thermal stress durability test. In Table 3, “resin crack” indicates that a crack has occurred in the resin portion of the insulating film, and “solder crack” indicates that a crack has occurred in the solder ball. Further, “over 1000” and “over 500” indicate that the open state was not achieved even after 1000 cycles and 500 cycles of heat cycle, respectively.

  No. shown in Table 2 and Table 3. Reference numerals 1 to 13 are embodiments of the present invention. Example No. In Nos. 1 to 13, when the insulating film is a single layer (Example Nos. 1, 3, 7 to 13), the thickness of the insulating film is 3 to 100 μm, and the breaking strength at 23 ° C. is 80 MPa or more. And the ratio (a / b) is 4.5 or less, and the value of | c / d−a / b | is 0.8 or less, so that a crack occurs in the insulating film or the solder ball. The number of cycles until it was opened was 1000 cycles or more for the CSP sample, and the FCBGA sample was not opened even when a 500 heat cycle was applied, and the thermal stress durability was excellent. When the insulating film is composed of an insulating layer and an adhesive resin layer (Example Nos. 2, 4, 5, and 6), the thickness of the insulating film is 3 to 100 μm, and the insulating layer is broken at 23 ° C. Since the strength is 80 MPa or more, the value of ratio (a / b) is 2.5 or less, and the value of | c / d−a / b | is 0.8 or less, the insulating film or solder ball is cracked. The number of cycles until the CSP sample is opened is 1000 cycles or more for the CSP sample, and the FCBGA sample is not opened even when a 500 cycle heat cycle is applied, and the thermal stress durability is excellent. .

  In particular, Example No. In 1 to 11, since the ratio (a / b) is 2.5 or less, even if 1000 cycles of heat cycle is applied to the CSP single sample, it does not open and the thermal stress durability is extremely excellent. It was.

  As shown in FIG. 19 and FIGS. In the FCBGA sample No. 5, the insulating film has a structure in which an aramid film 61 as an insulating layer is sandwiched between two epoxy films 62 as an adhesive resin layer. In the FCBGA sample after 1000 heat cycles are applied, cracks 63 are generated in the epoxy film 62 due to thermal stress. However, the progress of the crack 63 is hindered by the aramid film 61, and the entire insulating film was not broken. For this reason, the disconnection does not occur in the wiring board and the open state is not caused.

  On the other hand, No. shown in Table 2 and Table 3. 14 to 17 are comparative examples. Comparative Example No. 14 to 17 had a ratio (a / b) value greater than 4.5 and a | c / d−a / b | value greater than 0.8, and thus the temperature dependence of the mechanical characteristics was large. For this reason, thermal stress durability was inferior.

  As shown in FIG. In the samples having 14 to 17 resin cracks, cracks 64 are generated in the base insulating film 7, and the cracks 64 break the upper wiring 11. As a result, the wiring board 13 is in an open state. Further, as shown in FIG. In the samples having 14 to 17 solder cracks, the solder balls 18 had cracks 65. As a result, the wiring board 31 is in an open state.

It is sectional drawing which shows the wiring board which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor package which concerns on this embodiment. FIG. 5 is a graph showing a stress-strain curve of a base insulating film, with the horizontal axis representing the elongation of the base insulating film and the vertical axis representing the stress applied to the base insulating film. It is sectional drawing which shows the semiconductor package which concerns on the modification of this embodiment. It is sectional drawing which shows the wiring board which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the wiring board which concerns on the modification of this embodiment. It is sectional drawing which shows the wiring board which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the semiconductor package which concerns on this embodiment. It is sectional drawing which shows the wiring board which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the semiconductor package which concerns on this embodiment. (A) thru | or (c) are sectional drawings which show the manufacturing method of the wiring board based on the 5th Embodiment of this invention in the order of the process. It is sectional drawing which shows the wiring board which concerns on the 6th Embodiment of this invention. (A) thru | or (e) are sectional drawings which show the manufacturing method of the wiring board based on 1st Embodiment in the order of the process. (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor package which concerns on 1st Embodiment in the order of the process, (c) is sectional drawing which shows a semiconductor package when a molding is provided. It is sectional drawing which shows the manufacturing method of the wiring board which concerns on 2nd Embodiment. (A) thru | or (d) are sectional drawings which show the manufacturing method of the wiring board based on 3rd Embodiment in the order of the process. (A) thru | or (d) are sectional drawings which show the manufacturing method of the wiring board based on 4th Embodiment in the order of the process. FIGS. (A) and (b) are drawings substitute photographs showing the shape of a sample for evaluation test, (a) shows a CSP (chip size package) sample, and (b) shows an FCBGA (flip chip ball grid array). A sample is shown (photomicrograph). Example No. 5 of the present invention. 5 is a drawing-substituting photograph showing a state in which the progress of cracks stops at the insulating layer in the FCBGA sample of No. 5 (optical micrograph). (A) to (c) are examples No. 1 of the present invention. 5 is a drawing-substituting photograph showing a state in which the progress of cracks stops at the insulating layer in the FCBGA sample of No. 5 (optical micrograph). (A) And (b) is drawing substitute photograph which shows the defective part of the sample which became open, (a) shows a resin crack, (b) shows a solder ball crack. (Optical micrograph) It is sectional drawing which shows the conventional built-up printed circuit board. (A) thru | or (c) is sectional drawing which shows this formation method of the conventional printed circuit board in the order of the process. (A) And (b) is sectional drawing which shows the manufacturing method of the other conventional wiring board in the order of the process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1; Support substrate 2; Resist 3; Conductor wiring layer 4; Etching easy layer 5; Etching barrier layer 6; Wiring main body 7; Substrate insulating film 7a; Concave 8; Insulating layer 9; Adhesive resin layer 10; Wiring 12; Solder resist 13, 13a; Wiring board 14, 14a; Bump 15, 15a; Semiconductor device 16; Underfill 17; Molding 18; Solder ball 19; Semiconductor package 21; Wiring board 22; Intermediate wiring 23; 24; Via hole 25; Semiconductor package 31; Wiring substrate 32; Intermediate wiring 33; Intermediate insulating film 34; Via hole 35; Semiconductor package 41; Protective film 42; Etched portion 43; Wiring substrate 51 to 53; 59; Wiring board 56, 60; LSI
57; molding 58; solder ball 61; aramid film 62; epoxy film 63, 64, 65; crack 66; underfill 67; stiffener 68; heat dissipation sheet 69; heat sink 71; 74; Via hole 75; Interlayer insulating film 76; Conductor wiring 81; Conductor wiring 82; Prepreg 83; Through hole 84; Conductor paste 85; Printed circuit board 86; Land pattern 91; Support plate 92; Conductor wiring 93; Interlayer insulating film 94 ; Via hole 95; conductor wiring 96; support 97; wiring board S _{51 to} S ₅₃ ; integrated value of stress-strain curve

Claims (33)

A base insulating film having a via hole formed thereon, a lower layer wiring formed on the lower surface of the base insulating film and connected to the via hole, and a lower layer wiring formed on the base insulating film and connected to the lower layer wiring through the via hole The base insulating film has a film thickness of 3 to 100 μm, a breaking strength when the temperature is 23 ° C. is 80 MPa or more, and a breaking strength when the temperature is −65 ° C. A wiring board, wherein the ratio (a / b) is 4.5 or less, where a is the breaking strength when the temperature is 150 ° C. and b is the breaking strength. In the base insulating film, when the elastic modulus is c when the temperature is −65 ° C. and d is the elastic modulus when the temperature is 150 ° C., the ratio (c / d) is 4.7 or less. The wiring board according to claim 1. The wiring board according to claim 1, wherein a value of the ratio (a / b) is 2.5 or less. The elastic modulus when the value of the ratio (a / b) is larger than 2.5 and not larger than 4.5, the elastic modulus when the temperature of the base insulating film is −65 ° C. is c, and the elastic modulus when the temperature is 150 ° C. The wiring board according to claim 1, wherein a to d satisfy the following formula, where d is d.

5. The wiring board according to claim 1, wherein the base insulating film has an elastic modulus of 2.3 GPa or more when the temperature is 150 ° C. 5. One or more wiring structure layers disposed between the base insulating film and the upper layer wiring, the wiring structure layer including an intermediate wiring connected to the lower layer wiring via the via hole; 6. An intermediate insulating film formed so as to cover the intermediate wiring and formed with another via hole for connecting the intermediate wiring and the upper layer wiring to each other. The wiring board according to item 1. Among the intermediate insulating films, the intermediate insulating film disposed at least in the uppermost layer has a breaking strength of 80 MPa or more when the temperature is 23 ° C., a1 when the temperature is −65 ° C., and 150 ° C. The wiring board according to claim 6, wherein the value of the ratio (a1 / b1) is 4.5 or less when the breaking strength at ° C. is b1. Of the intermediate insulating films, all of the intermediate insulating films have a breaking strength of 80 MPa or more when the temperature is 23 ° C., a1 when the temperature is −65 ° C., and a breaking strength when the temperature is 150 ° C. The wiring board according to claim 6 or 7, wherein the value of ratio (a1 / b1) is 4.5 or less, where b1 is b1. In the intermediate insulating film having a ratio (a1 / b1) value of 4.5 or less, when the elastic modulus is c1 when the temperature is −65 ° C. and d1 is the elastic modulus when the temperature is 150 ° C., The wiring board according to claim 7 or 8, wherein a value of the ratio (c1 / d1) is 4.7 or less. The wiring board according to claim 7, wherein the ratio (a1 / b1) is 2.5 or less. In the intermediate insulating film in which the value of the ratio (a1 / b1) is greater than 2.5 and is 4.5 or less, and the value of the ratio (a1 / b1) is 4.5 or less, the temperature is −65 ° C. 10. The wiring according to claim 7, wherein a1 to d1 satisfy the following formula, where c1 is an elastic modulus and d1 is an elastic modulus when the temperature is 150 ° C. substrate.

The intermediate insulating film having a ratio (a1 / b1) value of 4.5 or less has an elastic modulus of 2.3 GPa or more at a temperature of 150 ° C. The wiring board according to item 1. The wiring board according to claim 1, wherein a concave portion is formed on a lower surface of the base insulating film, and the lower layer wiring is embedded in the concave portion. 14. The wiring board according to claim 13, wherein the lower surface of the lower layer wiring is located 0.5 to 10 [mu] m above the lower surface of the base insulating film. 13. The wiring board according to claim 1, wherein a lower surface of the base insulating film and a lower surface of the lower layer wiring are flush with each other. 16. The wiring board according to claim 15, further comprising a protective film formed below the base insulating film and covering a part of the lower layer wiring and exposing the remaining part. 17. The wiring board according to claim 1, further comprising a solder resist layer that covers a part of the upper layer wiring and exposes the remaining part. 17. A semiconductor package comprising: the wiring board according to claim 1; and a semiconductor device mounted on the wiring board. A step of forming a lower layer wiring on the support substrate, a step of forming a base insulating film having a film thickness of 3 to 100 μm so as to cover the lower layer wiring, and a part of the region directly above the lower layer wiring in the base insulating film Forming a via hole on the substrate, forming an upper layer wiring on the base insulating film so as to be connected to the lower layer wiring via the via hole, and removing at least a part of the support substrate; And the step of forming the base insulating film has a breaking strength of 80 MPa or more when the temperature is 23 ° C., a is the breaking strength when the temperature is −65 ° C., and 150 ° C. A method of manufacturing a wiring board, comprising a step of attaching an insulating material having a ratio (a / b) value of 4.5 or less to the supporting board when the breaking strength is b. In the substrate insulating film, when the elastic modulus is c at a temperature of −65 ° C. and d is the elastic modulus at a temperature of 150 ° C., the ratio (c / d) is 4.7 or less. The method of manufacturing a wiring board according to claim 19. 21. The method of manufacturing a wiring board according to claim 19, wherein the value of (a / b) is 2.5 or less. The value of (a / b) is set to be larger than 2.5 and 4.5 or less. In the base insulating film, the elastic modulus when the temperature is −65 ° C. is c, and the elastic modulus when the temperature is 150 ° C. 21. The method for manufacturing a wiring board according to claim 19, wherein a to d satisfy the following mathematical formula:

The method of manufacturing a wiring board according to any one of claims 19 to 22, wherein the base insulating film has an elastic modulus of 2.3 GPa or more when the temperature is 150 ° C. A step of forming one or a plurality of wiring structure layers between the step of forming the via hole and the step of forming the upper layer wiring, and in the step of forming each of the wiring structure layers, the via hole A step of forming an intermediate wiring so as to be connected to the lower layer wiring through a step, a step of forming an intermediate insulating film so as to cover the intermediate wiring, and a part of the intermediate insulating film directly above the intermediate wiring 24. The method of manufacturing a wiring board according to claim 19, further comprising: forming a via hole in the wiring. Among the intermediate insulating films, at least the last formed intermediate insulating film has a breaking strength of 80 MPa or higher when the temperature is 23 ° C., a1 when the temperature is −65 ° C., and 150 ° C. 25. The method of manufacturing a wiring board according to claim 24, wherein the value of the ratio (a1 / b1) is set to 4.5 or less when the breaking strength at that time is b1. In the step of forming all the intermediate insulating films among the intermediate insulating films, the breaking strength when the temperature is 23 ° C. is 80 MPa or more, the breaking strength when the temperature is −65 ° C. is a, and the temperature is 150 ° C. Characterized in that, when the breaking strength is b, the insulating film having a ratio (a / b) value of 4.5 or less is applied to the base insulating film or a lower intermediate insulating film. The method for manufacturing a wiring board according to claim 24 or 25. In the intermediate insulating film having a ratio (a1 / b1) value of 4.5 or less, when the elastic modulus is c1 when the temperature is −65 ° C. and d1 is the elastic modulus when the temperature is 150 ° C., 27. A method of manufacturing a wiring board according to claim 25 or 26, wherein the value of the ratio (c1 / d1) is 4.7 or less. The method of manufacturing a wiring board according to any one of claims 25 to 27, wherein a value of the ratio (a1 / b1) is 2.5 or less. In the intermediate insulating film in which the value of the ratio (a1 / b1) is greater than 2.5 and 4.5 or less, and the value of the ratio (a1 / b1) is greater than 2.5 and 4.5 or less, the temperature is − 28. Any one of claims 25 to 27, wherein a1 to d1 satisfy the following equation, where c1 is an elastic modulus at 65 ° C. and d1 is an elastic modulus at a temperature of 150 ° C. The manufacturing method of the wiring board as described in 2 ..

30. The intermediate insulating film having the ratio (a1 / b1) value of 4.5 or less has an elastic modulus of 2.3 GPa or more at a temperature of 150 ° C. The manufacturing method of the wiring board of 1 item | term. Before the step of forming the lower layer wiring on the support substrate, the method has a step of forming an easy etching layer having a film thickness of 0.5 to 10 μm on the support substrate, and at least a part of the support substrate is removed. 31. The method of manufacturing a wiring board according to claim 19, further comprising a step of removing the easy-to-etch layer after the step. A step of forming a protective layer before the step of forming a lower layer wiring on the support substrate; and a step of selectively removing the protective layer after the step of removing at least a part of the support substrate; The method for manufacturing a wiring board according to any one of claims 19 to 30, further comprising a step of exposing at least a part of the lower layer wiring. 33. The method according to claim 19, further comprising a step of forming a solder resist layer that covers a part of the upper layer wiring and exposes the remainder after the step of forming the upper layer wiring. A method for manufacturing a wiring board.

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