JP2020072859A - Game machine and game medium discrimination device - Google Patents

Abstract

To provide a game machine which can detect the fraudulent act of playing the game by making erroneously recognized that a normal game medium is used.SOLUTION: A token sensor includes: a token rail which forms a passage where a token passes; a CMOS image sensor which images the token passing through the passage; and a control LSI which detects whether or not the token is the normal token on the basis of the image data of the imaged token. The control LSI includes an image recognition DSP circuit and an image recognition accelerator circuit 249, and these circuits perform rotation integration processing and stamp determination processing of the image data of the imaged token. The image recognition accelerator circuit 249 performs the coordinate conversion of the image data by referring to a transformation parameter 280 designating the processing contents of the coordinate conversion.SELECTED DRAWING: Figure 23

Description

  The present invention relates to a game machine and a game medium discrimination device.

  Conventionally, a game called a pachi-slot provided with a plurality of reels on each surface of which a plurality of symbols are arranged, a start switch, a stop switch, a stepping motor provided corresponding to each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter, also referred to as "start operation") after a game medium such as a medal has been inserted into the game machine, and starts the rotation of all reels. Output the requested signal. The stop switch detects that the stop button provided corresponding to each reel is pressed by the player (hereinafter, also referred to as "stop operation"), and outputs a signal requesting stop of rotation of the corresponding reel. To do. The stepping motor transmits the driving force to the corresponding reel. In addition, the control unit controls the operation of the stepping motor based on the signals output by the start switch and the stop switch, and performs the rotation operation and the stop operation of each reel.

  In such a gaming machine, when a start operation is detected, a lottery process using random numbers on the program (hereinafter referred to as “internal lottery process”) is performed, and the result of the lottery (hereinafter referred to as “internal winning combination”). ") And the timing of the stop operation, the rotation of the reel is stopped. Then, when the rotation of all reels is stopped and the combination of symbols relating to the establishment of the winning is displayed, the privilege corresponding to the combination of symbols is awarded to the player.

  In addition, such a gaming machine is provided with a medal selector for detecting a medal inserted at the tip of the medal insertion slot. In addition, for this medal selector, a medal (illegal medal) that is not a proper medal (regular medal) is inserted into the medal insertion slot, or a device is inserted into the medal insertion slot, and the regular medal is displayed in the game machine. Measures have been taken against fraudulent activity in which a game is played by misidentifying that it has been thrown.

  For example, in Patent Document 1, two medal detection proximity sensors are provided in the medal passage, and it is determined whether or not a gaming medal has passed through the medal passage based on the output of each proximity sensor. A slot machine for detecting fraudulent activity using a device such as a shape is described.

  On the other hand, Patent Document 2 discloses an image processing apparatus that performs distortion correction processing on input image data and outputs an output image. In this image processing apparatus, a DMAC that controls data transfer between memories is disclosed. Data transfer via the bus is performed using a (Direct Memory Access Controller) in response to a control signal from the DMAC instead of the CPU.

  Further, Patent Document 3 discloses a data transfer device that transfers data between a storage circuit that stores image data and a processing circuit that performs distortion correction processing by using the above-described DMAC. In the device, data transfer via the bus between the storage circuit and the cache memory in the processing circuit is performed in response to a control signal from the DMAC instead of the CPU.

JP 2002-342814 A JP, 2013-186624, A JP, 2013-186705, A

  However, in the slot machine described in Patent Document 1, various types of fraudulent devices other than the plate-shaped body are inserted into the medal insertion slot to illegally operate the counting function of the medal selector to insert a medal. It is not possible to detect fraudulent acts that appear to be doing and obtain a large number of credits, or fraudulent acts performed using fraudulent medals.

  For example, if a medal with a unit price of 20 yen and a medal with a cost of 5 yen that are rented out in the hall where this slot machine is installed have the same diameter but differ only in color and marking (pattern), There is a person who can not discriminate and uses an illegal game such as using a medal acquired with a low bet gaming machine (so-called 5 slot) with an ordinary gaming machine (so-called 20 slot), so Damage is occurring.

  In addition, in the slot machine described in Patent Document 1, a medal lent out in a hall in which a gaming machine is installed, a medal lent out in another hall, and a gaming machine purchased at a used machine store are attached. If a medal that is present or a counterfeit medal (including a device that looks like a medal) and the like has the same diameter but only the color or the marking (pattern), these cannot be distinguished. Therefore, it is difficult to detect (detect) an illegal act of playing a game using a medal (illegal medal) other than the regular medal.

  Therefore, the fraud determination according to the conventional technique using a normal sensor such as the slot machine described in Patent Document 1 cannot deal with the various fraudulent acts described above, and the effect thereof is limited. There is.

  Further, when attempting to make such fraudulent determination on a game medium such as a medal by image processing, there arises a problem of processing time. In other words, when making highly accurate fraudulent determinations on highly imitated counterfeit medals, it is necessary to image the medals inserted into the slot machine at a high resolution and perform multiple image processing on each imaged pixel data. Therefore, even if a high-performance CPU or image processing circuit is used, the fraud determination requires a considerably long time.

  In addition, since game media such as medals are normally continuously inserted into a slot machine or the like, it is extremely difficult to carry out the above-described fraud determination by image processing in real time for each inserted medal. Difficult to do.

  Although various approaches have been studied in relation to shortening the time for fraudulent determination by image processing on such a game medium, the processing time using DMA transfer as described in Patent Document 2 and Patent Document 3 is considered. A gaming machine including a circuit that realizes the shortening of the above has not been proposed so far.

  In addition, we have also proposed a gaming machine that includes a circuit that makes a fraudulent decision on a game medium by image processing, in terms of manufacturing cost and security, and that uses DMA transfer to shorten the processing time. It has not been.

Further, a circuit for making a fraud determination of a game medium such that the processing content of coordinate conversion executed in the image processing for fraud determination of a game medium is designated by a conversion parameter has not been proposed so far.

  The present invention has been made to solve the above problems, and an object of the present invention is to make it possible to detect a fraudulent act of playing a game by misidentifying that a legitimate game medium is used in a gaming machine. An object is to provide a game machine and a game medium discrimination device.

In order to achieve the above object, the first embodiment of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Direct transfer control means (for example, DMAC252) for controlling the direct transfer of data,
Storage means capable of storing data (for example, SRAM 243),
The image data obtained via the image capturing unit is acquired from the storage unit by the direct transfer control unit, a predetermined format conversion is performed, and the image data after the format conversion (for example, target image data 275, captured image 362B) is stored in the storage unit by the direct transfer (for example, the conversion unit 363, the ISP circuit 245, etc.),
A characteristic image generation unit (for example, a characteristic image generation unit 364, an image recognition accelerator circuit 249, etc.) that generates a characteristic image showing the characteristic of the game medium based on the image data after the format conversion,
The characteristic image generating means,
Image data relating to the image data after the format conversion is acquired from the storage unit, image processing including coordinate conversion is performed on the acquired image data, and the image data after the image processing is transferred by the direct transfer. It is configured to be stored in the storage means.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the storage of the image data in the storage means (SRAM or the like) in the game medium determination means is realized by the direct transfer control means for controlling the direct transfer of the data, the host controller (processor of the game medium determination means in the data transfer) ) Is not involved, parallel processing of each circuit (hardware) included in the game medium determination means is possible, and as a result, the processing efficiency is improved and the processing time regarding the determination of the game medium is shortened.

The second embodiment of the present invention provides a game medium discriminating apparatus having the following configuration.
A game medium passing portion that is a passage through which the game medium passes,
Imaging means for imaging a passing object which is an object passing through the passage,
A game medium determining unit that determines whether or not the game medium is a regular one by performing image processing based on the image data obtained through the image capturing unit,
The game medium determination means,
Direct transfer control means for controlling direct transfer of data,
Storage means capable of storing data,
The image data obtained via the image pickup means is acquired from the storage means by the direct transfer control means, a predetermined format conversion is performed, and the image data after the format conversion is stored in the storage means by the direct transfer. Conversion means to
A characteristic image generating means for generating a characteristic image showing the characteristic of the game medium based on the image data after the format conversion,
The characteristic image generating means,
Image data relating to the image data after the format conversion is acquired from the storage unit, image processing including coordinate conversion is performed on the acquired image data, and the image data after the image processing is transferred by the direct transfer. It is configured to be stored in the storage means.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the storage of the image data in the storage means (SRAM or the like) in the game medium determination means is realized by the direct transfer control means for controlling the direct transfer of the data, the host controller (processor of the game medium determination means in the data transfer) ) Is not involved, parallel processing of each circuit (hardware) included in the game medium determination means is possible, and as a result, the processing efficiency is improved and the processing time regarding the determination of the game medium is shortened.

  According to the present invention, it is possible to misidentify that a legitimate game medium is used in a gaming machine and detect a fraudulent act of playing a game.

It is explanatory drawing explaining the function flow in the game machine of one Embodiment of this invention. It is a perspective view showing an example of appearance composition in a game machine of one embodiment of the present invention. 1 is a perspective view showing an internal structure of a gaming machine according to an embodiment of the present invention and showing a state in which a middle door is closed. It is a perspective view showing an internal structure in a game machine of one embodiment of the present invention, and showing a state in which a middle door is opened. It is an explanatory view showing the inside of the cabinet in the game machine of one embodiment of the present invention. It is an explanatory view showing the back side of the front door in the game machine of one embodiment of the present invention. It is the perspective view which looked at the medal selector in the game machine of one embodiment of the present invention from the slanting back of the game machine. It is an exploded view of a medal selector in the gaming machine of one embodiment of the present invention. It is the perspective view which looked at the medal selector in the game machine of one embodiment of the present invention from the slanting front of the game machine. It is a perspective view of the select plate of the medal selector in the gaming machine of one embodiment of the present invention. It is a figure which shows the path | route of the medal when the medal selector in the game machine of one embodiment of an invention guides a medal to a hopper apparatus. It is a figure showing a course of a medal when a medal selector in a game machine of one embodiment of the invention guides a medal to a medal shoot. It is a block diagram showing a control system in a game machine of one embodiment of the present invention. It is a block diagram showing an example of composition of a main control circuit in a game machine of one embodiment of the present invention. It is a block diagram showing an example of composition of a sub control circuit in a game machine of one embodiment of the present invention. It is a block diagram showing an example of circuit composition of a medal selector in a game machine of one embodiment of the present invention. It is a block diagram showing an example of circuit composition of control LSI in a game machine of one embodiment of the present invention. It is a functional block diagram of the camera unit in the game machine of one embodiment of the present invention. It is a figure which shows an example of the regular medal used for the game machine of one Embodiment of this invention, A shows one side of a regular medal, B is a figure which shows the image data of a regular medal. It is a figure for explaining generation (composition) of processing image data about a regular medal used for a game machine of one embodiment of the present invention. It is a block diagram showing an example of circuit composition of an image recognition accelerator circuit contained in control LSI in a game machine of one embodiment of the present invention. It is a figure which shows the concept which performs coordinate conversion with respect to target image data, and produces | generates the image data after conversion. It is a figure showing an example of circuit composition of a coordinate conversion circuit of an image recognition accelerator circuit contained in control LSI in a game machine of one embodiment of the present invention. It is a figure showing an example of a conversion parameter of an image recognition accelerator circuit contained in control LSI in a game machine of one embodiment of the present invention. It is a figure showing an example of specific information on an image recognition accelerator circuit contained in control LSI in a game machine of one embodiment of the present invention. It is a figure which shows typically the example which after-conversion image data is produced | generated by the image recognition accelerator circuit contained in the control LSI in the game machine of one embodiment of this invention by the conversion parameter from which each rotation angle differs. It is a figure for explaining an example of coordinate conversion by a conversion parameter. It is a figure which shows the concept which synthesize | combines several post-conversion image data and produces | generates process image data. It is a figure for explaining the outline of operation of the image processing circuit of the image recognition accelerator circuit contained in the control LSI in the game machine of one embodiment of the present invention. It is a figure showing composition of an image processing circuit of an image recognition accelerator circuit contained in control LSI in a game machine of one embodiment of the present invention. It is a figure for explaining a flow of regular medal discrimination processing about the 1st medal in a game machine of one embodiment of the present invention. It is a figure for explaining the flow of the regular medal discrimination processing about the 1st-6th medal in the game machine of one embodiment of the present invention. It is a figure which shows the operation | movement flow of the image recognition accelerator circuit contained in control LSI in the game machine of one Embodiment of this invention. It is a figure which shows the one side of an illegal medal, and the example of the image data of an illegal medal. It is a figure which shows the one side of an illegal medal, the image data of an illegal medal, and the process image data of an illegal medal. It is a figure which shows typically an example of the captured image obtained through the imaging device of the camera unit in the game machine of one embodiment of this invention. It is a functional block diagram of the camera unit in the game machine of one embodiment of the present invention. It is a figure which shows the structure of the characteristic image production | generation part in the game machine of one Embodiment of this invention in detail. It is a flow chart which shows a series of operation of regular medal discrimination processing carried out with a camera unit in a game machine of one embodiment of the present invention. It is a figure which shows an example of a medal area typically. It is a figure which shows an example of a background image typically. It is a figure which shows an example of a background difference image typically. It is a figure which shows an example of an outline template typically. It is a figure for demonstrating template matching. It is a figure for explaining the extraction processing of the medal area. It is a figure which shows an example of an edge image typically. It is a figure for explaining a generating method of a rotation synthetic picture. It is a figure which shows the circuit structural example of the image recognition accelerator circuit contained in the control LSI in the modification 1 of one Embodiment of this invention. It is a figure which shows the concept which overlaps several coordinate conversion with respect to target image data, and produces | generates process image data. It is a figure which shows the circuit structural example of the image recognition accelerator circuit contained in the control LSI in the modification 2 of one Embodiment of this invention. It is a figure which shows the circuit structural example of the image processing circuit of the image recognition accelerator circuit contained in the control LSI in the modification 2 of one Embodiment of this invention. It is a figure which shows the example of the conversion parameter of the image recognition accelerator circuit contained in the control LSI in the modification 2 of one Embodiment of this invention. It is a figure which shows the example of the specific information of the image recognition accelerator circuit contained in the control LSI in the modification 2 of one Embodiment of this invention. FIG. 11 is a diagram for explaining the operation of the image recognition accelerator circuit included in the control LSI in the second modification of the embodiment of the present invention. It is a figure which shows the circuit structural example of the image recognition accelerator circuit contained in the control LSI in the modification 3 of one Embodiment of this invention. It is a figure which shows the circuit structural example of the image processing circuit of the image recognition accelerator circuit contained in the control LSI in the modification 3 of one Embodiment of this invention. It is a figure which shows the circuit structural example of the image processing circuit of the image recognition accelerator circuit contained in the control LSI in the modification 4 of one Embodiment of this invention.

<< one embodiment >>
Hereinafter, a pachi-slot which is a gaming machine according to an embodiment of the present invention will be described with reference to FIGS. 1 to 47.

<Function flow>
First, the functional flow of the pachi-slot will be described with reference to FIG. In the pachi-slot of the present embodiment, medals are used as a game medium for playing a game. It should be noted that all of the embodiments and modifications of the present invention are not limited to pachi-slot machines, but can be applied to gaming machines other than pachi-slot machines (for example, pachinko machines and the like). In addition to medals, coins, game balls, game point data, tokens, etc. can be used as the game medium.

  At the start of the game, when the player inserts a medal and operates the start lever, one value (hereinafter, a random number value) is extracted from a random number in a predetermined numerical value range (for example, 0 to 65535). To be done.

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. This internal lottery means is carried out by the main control circuit described later. By the determination of the internal winning combination, the combination of symbols that is allowed to be displayed along the winning determination line described below is determined. The types of symbol combinations include those related to "winning", in which benefits such as payout of medals, operation of re-game, operation of bonus, etc. are given to the player, and those related to other so-called "miss". Is provided.

  Further, when the start lever is operated, the plurality of reels are rotated. After that, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means controls the rotation of the corresponding reel based on the internal winning combination and the timing at which the stop button is pressed. To do. The reel stop control means is carried out by a main control circuit described later.

  In the pachi-slot, basically, control is performed to stop the rotation of the corresponding reel within a specified time (190 msec or 75 msec) from when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within this specified time is referred to as the “number of sliding pieces”. When the specified period is 190 msec, the maximum number of sliding pieces is set to 4 symbols, and when the specified period is 75 msec, the maximum number of sliding pieces is set to 1 symbol.

  The reel stop control means, when the internal winning combination permitting the combination display of the symbols relating to the winning is determined, the combination of the symbols is usually within the prescribed time of 190 msec (4 symbols), and the winning combination is the winning determination line. Stop the rotation of the reel so that it is displayed along with as much as possible. Further, the reel stop control means defines, for example, one or more reels at the time of the operation of the challenge bonus (CB) and the middle bonus (MB) of continuously operating the second type special accessory. Within 75 msec (one frame of the symbol), the rotation of the reel is stopped so that the symbol combination is displayed as much as possible along the winning determination line. Furthermore, the reel stop control means uses various prescribed times corresponding to the gaming state to rotate the reels so that a combination of symbols which is not permitted to be displayed by the internal winning combination is not displayed along the winning determination line. Stop.

  In this way, when the rotation of the plurality of reels is all stopped, the winning determination means determines whether or not the symbol combination displayed along the winning determination line is related to winning. This winning determination means is carried out by the main control circuit described later. When it is determined by the prize determination means that the game is related to a prize, a bonus such as payout of medals is given to the player. In the pachi-slot, the above-described series of flows is performed as one game.

  Further, in the pachi-slot, in the above-described series of flows, the image display performed by the display device such as a liquid crystal display device, the light output performed by various lamps, the sound output performed by the speaker, or a combination thereof is used. Various performances are performed.

  When the start lever is operated, a random number value for rendering (hereinafter, a random number value for rendering) is extracted in addition to the random number value used for determining the internal winning combination described above. When the random number value for effect is extracted, the effect content determination means randomly determines the effect content to be executed this time from the plurality of types of effect content associated with the internal winning combination. The sub-control circuit described later plays a role of this effect content determination means.

  When the content of the effect is determined, the effect executing means executes the corresponding effect in association with each trigger such as the start of the rotation of the reel, the stop of the rotation of each reel, the determination of the presence or absence of the winning. In this way, in the pachi-slot, the player has the opportunity to know or predict the determined internal winning combination (in other words, the combination of the symbols to be aimed) by executing the effect contents associated with the internal winning combination. It is provided, and the interest of the player can be improved.

<Structure of pachi-slot>
Next, the structure of the pachi-slot 1 according to the present embodiment will be described with reference to FIGS.

[Appearance structure]
FIG. 2 is a perspective view showing an external structure of the pachi-slot 1.

  As shown in FIG. 2, the pachi-slot 1 includes an exterior body 2. The exterior body 2 has a cabinet 2a that houses a hopper device 51, a medal auxiliary storage 52, and the like (see FIG. 5) described later, and a front door 2b that is openably and closably attached to the cabinet 2a. Handles 7 are provided on both sides of the cabinet 2a (only one handle 7 is shown in FIG. 2). The handle 7 is a recess for holding the pachi-slot 1 when carrying it.

  Inside the exterior body 2, three reels 3L, 3C, 3R are provided side by side. Hereinafter, the reels 3L, 3C, and 3R are referred to as the left reel 3L, the middle reel 3C, and the right reel 3R, respectively. Each of the reels 3L, 3C, and 3R has a reel main body formed in a cylindrical shape, and a translucent sheet material mounted on the peripheral surface of the reel main body. On the surface of the sheet material, a plurality of (for example, 20) patterns are drawn at predetermined intervals along the circumferential direction.

  The front door 2b includes a door body 9, a front panel 10, and a liquid crystal display device 11 showing a specific example of a display device.

  The door body 9 is attached to the cabinet 2a using a hinge (not shown), and opens and closes the opening of the cabinet 2a. The hinge is provided at the left end of the door body 9 when the door body 9 is viewed from the front of the pachi-slot 1. The liquid crystal display device 11 is attached to the upper part of the door body 9. The liquid crystal display device 11 includes a display unit (display screen) 11 a, and the liquid crystal display device 11 is used to perform an effect by displaying an image.

  The front panel 10 is arranged so as to overlap the display portion 11a side of the liquid crystal display device 11, and is formed in a frame shape having a panel opening 10a that exposes the display portion 11a of the liquid crystal display device 11. A lamp group 18 is provided on the front panel 10. The lamp group 18 includes LEDs (Light Emitting Diodes) and the like, and turns on and off the light in a pattern corresponding to the effect contents.

  A pedestal portion 12 is formed at the center of the front door 2b. The pedestal portion 12 is provided with the symbol display area 4 and various devices to be operated by the player.

  The symbol display area 4 is arranged on the front side overlapping with the three reels 3L, 3C, 3R when viewed from the front, and is provided corresponding to the three reels 3L, 3C, 3R. The symbol display area 4 functions as a display window and is configured to allow the reels 3L, 3C, 3R provided behind it to pass through. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  The reel display window 4, when the rotation of the reels 3L, 3C, 3R provided behind it is stopped, among the plurality of types of symbols of each reel 3L, 3C, 3R, the upper, middle and lower stages in the frame One symbol is displayed in each area (3 in total). In the present embodiment, a pseudo line formed by combining any one of predetermined three areas including the upper stage, the middle stage, and the lower stage of the reel display window 4 is an object for determining whether or not to win. Is defined as a line (winning determination line).

  The reel display window 4 is formed by a frame member 13 provided on the pedestal portion 12. The frame member 13 has a reel display window 4, an information display window 14, and a stop button mounting portion 15.

  The information display window 14 is provided continuously to the lower portion of the reel display window 4 and opens upward. That is, the reel display window 4 and the information display window 14 are formed as one continuous opening. The information display window 14 and the reel display window 4 are covered with a transparent window cover 16.

  The window cover 16 is arranged on the inner surface side of the frame member 13 and cannot be removed from the front surface side of the front door 2b. Further, the frame member 13 has a sheet placing portion 17 that faces the opening of the information display window 14 with the window cover 16 interposed therebetween. Then, a sheet member (information sheet) in which information regarding a game is written is arranged between the sheet placing portion 17 and the window cover 16. Therefore, the information sheet is covered with the window cover 16 having a smooth surface without irregularities or gaps.

  Since the window cover 16 constituting the mounting portion of the information sheet cannot be removed from the front side of the front door 2b and has a smooth surface without irregularities or gaps, the pachi-slot 1 can be used by using the mounting portion of the information sheet. You can prevent fraudulent activities that access the inside of the.

  The stop button mounting portion 15 is provided below the information display window 14 and is formed in a plane facing the front. The stop button mounting portion 15 is provided with a through hole through which the stop buttons 19L, 19C, 19R penetrate. The stop buttons 19L, 19C, 19R are associated with each of the three reels 3L, 3C, 3R, and are provided to stop the rotation adjustment of the corresponding reels. Hereinafter, the stop buttons 19L, 19C, and 19R are referred to as the left stop button 19L, the middle stop button 19C, and the right stop button 19R, respectively.

  The stop buttons 19L, 19C, 19R are examples of various devices that are targets of operations by the player. In addition, the pedestal portion 12 is provided with a medal insertion slot 21, a BET button 22, and a start lever 23 as various devices to be operated by the player.

  The medal insertion slot 21 is provided for receiving medals dropped from the outside by the player. The medals received in the medal insertion slot 21 will be inserted into one game with a predetermined number (for example, 3) set in advance as an upper limit, and the amount exceeding the specified number will be deposited inside the pachi-slot 1. It becomes possible (a so-called credit function).

  The BET button 22 is provided to determine the number of medals deposited in the pachi-slot 1 for one game. The start lever 23 is provided to start rotation of all reels (3L, 3C, 3R).

  A 7-segment display 24 including a 7-segment LED (Light Emitting Diode) is provided on the left side of the reel display window 4 when the front door 2b is viewed from the front. The 7-segment display 24 digitally displays information such as the number of medals to be paid out to the player as a privilege (hereinafter, the number of payouts) and the number of medals stored in the pachi-slot (hereinafter, the number of credits). ..

  A settlement button 27 is provided on the left side of the pedestal portion 12 when the front door 2b is viewed from the front. The settlement button 27 is provided for pulling out (discharging) to the outside stored in the pachi-slot 1. A waist panel unit 31 is provided below the pedestal portion 12. The waist panel unit 31 has a decorative panel on which an arbitrary image is drawn and a light source that emits light for illuminating the decorative panel from the back side.

  Below the waist panel unit 31, a medal payout opening 32, speaker holes 33L and 33R, and a medal tray unit 34 are provided. The medal payout port 32 guides the medals discharged from the medal selector 201 described later and the medals discharged by driving the hopper device 51 described later to the outside. The medals discharged from the medal payout opening 32 are stored in the medal tray unit 34. The speaker holes 33L and 33R are provided to output a sound effect such as a sound effect and a music according to the effect contents.

[Internal structure]
3 and 4 are perspective views showing the internal structure of the pachi-slot 1. In FIG. 3, the front door 2b is opened, and the middle door 41 provided on the back side of the front door 2b is shown closed to the front door 2b. Further, FIG. 4 shows a state in which the front door 2b is opened and the middle door 41 is opened with respect to the front door 2b. Further, FIG. 5 is an explanatory diagram showing the inside of the cabinet 2a. FIG. 6 is an explanatory diagram showing the back surface side of the front door 2b.

  The cabinet 2a has a top plate 20a, a bottom plate 20b, left and right side plates 20c and 20d, and a back plate 20e (see FIG. 5). A cabinet-side speaker 42 is arranged on the upper side inside the cabinet 2a. The cabinet-side speaker 42 is attached to the back plate 20e of the cabinet 2a via mounting brackets 43L and 43R. The cabinet side speaker 42 is, for example, a speaker for outputting a sound effect.

  A cabinet-side relay board 44 is arranged on the left side of the cabinet-side speaker 42 when the inside of the cabinet 2a is viewed from the front. The cabinet-side relay board 44 is attached to the left side plate 20c of the cabinet 2a. The cabinet side relay board 44 includes a main control board 71 (see FIG. 13), which will be described later, attached to the middle door 41 (see FIGS. 3 and 4), a hopper device 51, a medal auxiliary storage switch (not shown), and a medal payout. The wiring for connecting with a count switch (not shown) is relayed.

  An amplifier board 45 that controls the output of sound from the cabinet-side speaker 42 is arranged in the center of the cabinet 2a. The amplifier board 45 is attached to a mounting shelf 46 fixed to the left and right side plates 20c and 20d.

  Further, when the inside of the cabinet 2a is viewed from the front, an external concentrated terminal board 47 is arranged on the right side of the amplifier board 45 (see FIG. 5). The external centralized terminal board 47 is attached to the right side surface board 20d of the cabinet 2a. The external centralized terminal board 47 is provided for outputting signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachi-slot 1.

  A sub power supply device 48 is disposed on the left side of the amplifier board 45 when the inside of the cabinet 2a is viewed from the front. The sub power supply device 48 is attached to the left side plate 20c of the cabinet 2a. The sub power supply device 48 supplies electric power with an AC voltage of 100 V to the power supply device 53 described later. Further, the AC voltage of 100 V is converted into the DC voltage and supplied to the amplifier board 45.

  A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are arranged below the inside of the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 20b of the cabinet 2a. The hopper device 51 has a structure capable of accommodating a large amount of medals and discharging them one by one. For example, when the settlement button 27 (see FIG. 2) is pressed and the medals stored in the pachi-slot are settled, the hopper device 51 discharges the stored medals by the number of credits. The medals paid out by the hopper device 51 are discharged from the medal payout opening 32 (see FIG. 2).

  The medal auxiliary storage 52 stores the medals overflowing from the hopper device 51. The medal auxiliary storage 52 is arranged on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. The medal auxiliary storage 52 is engaged with the bottom plate 20b of the cabinet 2a and is configured to be detachable from the bottom plate 20b.

  The power supply device 53 is arranged on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side face plate 20c. The power supply device 53 has a power switch 53a and a power board 53b (see FIG. 13). The power supply device 53 converts the power of the AC voltage 100V supplied from the sub power supply device 48 into the power of the DC voltage required by each unit, and supplies the converted power to each unit.

  As shown in FIGS. 3, 4 and 6, the middle door 41 is arranged at the center of the back surface of the front door 2b, and is configured to open and close the reel display window 4 (see FIG. 4) from the back side. Door stoppers 41a, 41b, 41c are provided on the upper and lower portions of the middle door 41. The door stoppers 41a, 41b, 41c fix (prohibit) the opening operation of the middle door 41 with the reel display window 4 closed from the back side. That is, in order to open the middle door 41, it is necessary to rotate the door stoppers 41a, 41b, 41c to release the fixation of the middle door 41.

  A main control board case 55 accommodating a main control board 71 (see FIG. 13) and three reels 3L, 3C, 3R are attached to the middle door 41. A stepping motor is connected to the three reels 3L, 3C, and 3R via a gear having a predetermined reduction ratio.

  As shown in FIG. 6, the main control board case 55 is provided with a setting key type switch 56. The setting key type switch 56 is used when changing the setting of the pachi-slot 1 or confirming the setting of the pachi-slot 1. In the present embodiment, the main control board case 55 and the main control board 71 housed in the main control board case 55 constitute a main control board unit.

  The main control board 71 housed in the main control board case 55 constitutes a main control circuit 91 (see FIG. 14) described later. The main control circuit 91 is a circuit that controls the main flow of the game in the pachi-slot 1, such as determination of an internal winning combination, rotation and stop of the reels 3L, 3C, and 3R, and determination of presence or absence of a prize. The specific configuration of the main control circuit 91 will be described later.

  A sub control board case 57 that accommodates the sub control board 72 (see FIG. 13) is provided above the middle door 41, and a center speaker 58 is provided above the sub control board case 57. The sub-control board 72 housed in the sub-control board case 57 constitutes a sub-control circuit 101 (see FIG. 15). The sub-control circuit 101 is a circuit that controls execution of effects such as video display. The specific configuration of the sub control circuit 101 will be described later.

  A sub relay board 61 is disposed on the right side of the sub control board case 57 when the front door 2b is viewed from the back side. The sub relay board 61 relays the wiring connecting the sub control board 72 and the main control board 71. The sub-control board 72 is a board that relays the wiring that connects the sub-control board 72 and the board arranged around the sub-control board 72. It should be noted that LED boards 62A, 62B, and 62C, which will be described later, can be given as the boards arranged around the sub-control board 72.

  The LED boards 62A, 62B, and 62C are arranged on both sides of the sub control board case 57 when viewed from the back surface side of the front door 2b. These LED boards 62A, 62B, and 62C have a plurality of LEDs (Light Emitting Diodes) 85 (see FIG. 13) showing a specific example of a light source according to the effect executed by the control of the sub control circuit 101 (see FIG. 15). ) Is lit to display the blinking pattern. The gaming machine according to the present embodiment includes a plurality of LED boards in addition to the LED boards 62A, 62B, 62C.

  Below the sub relay board 61, a 24h door opening / closing monitoring unit 63 is arranged. The 24h door opening / closing monitoring unit 63 stores a history of opening / closing of the middle door 41. Also, when the middle door 41 is opened, a signal for displaying an error on the liquid crystal display device 11 is output to the sub control board 72 (sub control circuit 101).

  A board speaker 64 and lower speakers 65L and 65R are disposed below the middle door 41. The board speaker 64 faces the waist panel unit 31 (see FIG. 2), and the lower speakers 65L and 65R face the speaker holes 33L and 33R (see FIG. 2), respectively.

  A medal selector 201, a medal chute 202, and a door opening / closing monitoring switch 67 are arranged above the lower speaker 65L. The medal selector 201 is a device that determines whether or not the material, shape, etc. of the medal are appropriate, and guides the medal inserted into the medal insertion slot 21 to the hopper device 51 via the slope 203, or Guide to the chute 202. The specific configuration of the medal selector 201 will be described later.

  The medal chute 202 is a substantially Y-shaped tubular member, and guides the medals guided by the medal selector 201 and the medals discharged from the hopper device 51 to the medal payout outlet 32 (see FIG. 2).

  The door open / close monitor switch 67 is arranged on the left side of the medal selector 201 when the front door 2b is viewed from the back side. The door open / close monitor switch 67 outputs a security signal for notifying the opening / closing of the front door 2b to the outside of the pachi-slot 1.

  Further, a door relay terminal plate 68 is arranged in a region below the reel display window 4 and opened / closed by the middle door 41 (see FIG. 4). The door relay terminal board 68 includes a main control board 71 (see FIG. 13) in the main control board case 55, various buttons and switches, a sub-control board 72 (see FIG. 13), a medal selector 201, and a game operation display board. 81 is a substrate that relays the wiring with 81 (see FIG. 13). The various buttons and switches include, for example, the BET button 22, the settlement button 27, the door opening / closing monitoring switch 67, the BET switch 77 and the start switch 79, which will be described later.

<Medal selector configuration>
Next, a specific configuration of the medal selector 201 will be described with reference to FIGS. FIG. 7 is a perspective view of the medal selector 201 seen from diagonally behind the pachi-slot 1. FIG. 8 is an exploded view of the medal selector 201. FIG. 9 is a perspective view of the medal selector 201 as seen obliquely from the front of the pachi-slot 1. FIG. 10 is a perspective view of a later-described select plate 207 of the medal selector 201. FIG. 11 is a diagram showing a route of medals when the medal selector 201 guides the medals to the hopper device 51. FIG. 12 is a diagram showing a route of medals when the medal selector 201 guides the medals to the medal shoot 202. In addition, arrow X shown in FIGS. 7-12 shows the left-right direction of the pachi-slot 1, arrow Y shows the front-back direction of the pachi-slot 1, and arrow Z shows the up-down direction.

  As shown in FIGS. 7 to 9, the medal selector 201 includes a base plate portion 204, a sub plate 205, a cancel shooter 206, a select plate 207, a medal solenoid 208 (see FIG. 9), a camera unit 209, Is equipped with.

  The base plate portion 204 is a substantially plate-shaped member that forms the outer frame housing of the medal selector 201, and is formed such that both left and right ends of the pachi-slot 1 are bent rearward of the pachi-slot 1. The base plate portion 204 has a rear surface 204b, which is one plane orthogonal to the front-back direction of the pachi-slot 1, and a front surface 204a (see FIG. 9) which is the other plane. A medal rail 210 is formed on the rear surface 204b so as to be recessed forward of the pachi-slot 1 and in a substantially L-shape. A plurality of ridges are formed on the surface of the medal rail 210.

  A medal entrance 211 for receiving medals inserted from the medal insertion slot 21 (see FIG. 2) is provided at the upper end of the base plate portion 204. The medals inserted into the medal selector 201 from the medal entrance portion 211 move from the upper side to the lower side along the medal rail 210. A medal exit portion 204c (see FIG. 8) is provided below the base plate portion 204. The medals that have moved inside the medal selector 201 are discharged from the medal exit portion 204c and are housed in the hopper device 51 via the slope 203 (see FIG. 4).

  A center hole 212 penetrating in the front-rear direction is formed at a substantially middle position of the medal rail 210, and an end portion of the medal pressure 213 (see FIG. 8) is exposed from the center hole 212. As shown in FIG. 9, the medal pressure 213 is rotatably supported by a shaft portion 214 provided on the front surface 204 a of the base plate portion 204. A coil spring 215 is attached to the shaft portion 214, and the medal pressure 213 is biased by the coil spring 215 so that the medal pressure 213 projects from the central hole 212.

  As shown in FIG. 9, a magnet 217 is provided on the front surface 204 a of the base plate portion 204. The magnet 217 attracts (magnetizes) illegal medals that are not made of an appropriate material among the medals moving on the medal rail 210.

  Further, as shown in FIG. 8, an upper exposure hole 219 is formed in a substantially central portion of a downstream region of the medal rail 210, the upper exposure hole 219 penetrating in the front-rear direction and exposing a rear end portion of an after medal pressure 218 described later. .. Further, a lower exposure hole 220 is formed in the lower portion of the downstream region of the medal rail 210 so as to penetrate in the front-rear direction and expose a later-described medal stopper portion 227 of the select plate 207.

  As shown in FIG. 9, the after medal pressure 218 is rotatably supported by the front surface 204 a of the base plate portion 204. When the front end of the after medal pressure 218 is pressed to the rear of the pachi-slot 1 by the medal solenoid 208, the after medal pressure 218 rotates, and the rear end of the after medal pressure 218 comes out from the upper exposure hole 219 (see FIG. 8). Exposed.

  As shown in FIGS. 7 and 8, the cancel shooter 206 is a substantially plate-shaped member, and is formed such that the left and right ends of the pachi-slot 1 are bent forward of the pachi-slot 1. The cancel shooter 206 is detachably fixed to the base plate portion 204 and covers the lower portion of the base plate portion 204 from the rear side. The cancel shooter 206 guides the medals discharged without passing through the medal exit portion 204c to the medal chute 202 (see FIG. 4). A notch portion 206a, which is cut out in a substantially rectangular shape downward, is formed at an upper portion of a substantially central portion in the left-right direction of the cancel shooter 206.

  As shown in FIG. 7, the sub plate 205 is a plate-shaped member that covers the medal rail 210 from the rear side. The sub-plate 205 has a flat plate-shaped main body portion 221 and a shaft portion 222 provided on the upper portion of the main body portion 221. A through hole 221a penetrating in the front-rear direction is provided at a substantially central portion of the main body portion 221, and a downstream region is exposed from the substantially central portion of the medal rail 210 through the through hole 221a.

  The shaft portion 222 is supported by the base plate portion 204, and the sub-plate 205 is attached to the base plate portion 204 so as to be rotatable around the shaft portion 222. A coil spring 223 is attached to the shaft portion 222. Normally, the sub-plate 205 is pressed against the base plate portion 204 side by the biasing force of the coil spring 223. At this time, a space through which medals can pass is formed between the sub plate 205 and the upper portion of the medal rail 210 covered by the sub plate 205. That is, the sub plate 205 functions as a guide plate that allows medals to pass through.

  Here, for example, when a medal jam occurs in the medal selector 201, the sub plate 205 can be rotated against the biasing force of the coil spring 223 to eliminate the medal jam.

  As shown in FIG. 8, the select plate 207 is a member that guides medals that move in a substantially central portion of the medal rail 210 that is not covered by the sub-plate 205. As shown in FIG. 10, the select plate 207 includes a plate body 224 having a substantially trapezoidal plate shape, and a pair of bearing portions formed by bending the left and right ends of the plate body 224 toward the front of the pachi-slot 1. 225 and. In addition, a flange portion 226 formed by bending the pachi-slot 1 forward and bending the rear end portion upward is formed on the upper portion of the plate body 224. Further, a medal stopper portion 227 extending downward is formed on one bearing portion 225.

  As shown in FIG. 8, the plate body 224 faces the substantially central portion of the medal rail 210 not covered by the sub-plate 205 in the front-back direction of the pachi-slot 1.

  As shown in FIG. 9, the select plate 207 is rotatably supported by a shaft portion 228 provided on the front surface 204 a of the base plate portion 204. The shaft portion 228 is provided with a coil spring 229 and biases the flange portion 226 toward the front of the pachi-slot 1. The flange portion 226 is in contact with one end of the medal solenoid 208. When the medal solenoid 208 is in the ON state, the flange portion 226 is pressed by one end of the medal solenoid 208 and moves rearward of the pachi-slot 1 against the biasing force of the coil spring 229. The rotation position of the select plate 207 at this time is referred to as a “guide position”. The distance between the plate body 224 of the select plate 207 at the guide position and the medal rail 210 is set to a predetermined distance that can guide the medal to the hopper device 51 without discharging the medal to the cancel shooter 206 side. Further, at this time, the medal stopper portion 227 does not protrude from the lower exposed hole 220 (see FIG. 8).

  Further, when the medal solenoid 208 is in the OFF state, the flange portion 226 is released from the pressure of the medal solenoid 208 and moves to the front of the pachi-slot 1 by the biasing force of the coil spring 229. The rotation position of the select plate 207 at this time is referred to as a “discharge position”. The distance between the plate body 224 of the select plate 207 at the ejection position and the medal rail 210 is set to be longer than a predetermined distance. At this time, the flange portion 226 moving to the front of the pachi-slot 1 is pressed, and one end of the medal solenoid 208 moves to the front of the pachi-slot 1. Along with this, the other end of the medal solenoid 208 moves to the rear of the pachi-slot 1 and presses the front end of the after medal pressure 218. As a result, the after medal pressure 218 rotates, and the rear end of the after medal pressure 218 is exposed from the upper exposure hole 219 (see FIG. 8).

  The medal stopper portion 227 does not protrude from the lower exposure hole 220 (see FIG. 8) when the select plate 207 is at the guide position, and protrudes from the lower exposure hole 220 when it is at the ejection position.

  As shown in FIG. 11, when the medal moving on the medal rail 210 meets the standard size, the select plate 207 in the guide position contacts the upper part of the moving medal and moves the medal to the medal exit portion 204c (see FIG. 8). ) To. The medal pushes the medal pressure 213 toward the front of the pachi-slot 1 when being guided by the select plate 207. In FIG. 11, the sub-plate 205 of the medal selector 201 and the cancel shooter 206 are not shown.

  On the other hand, as shown in FIG. 12, even if the medals moving on the medal rails 210 satisfy the standard size, the select plate 207 in the ejection position has a large distance between the plate body 224 and the medal rails 210. Therefore, the medal cannot be guided to the medal exit portion 204c (see FIG. 8). Further, the medal is pushed out to the medal pressure 213, the after medal pressure 218 protruding from the upper exposure hole 219, or the medal stopper portion 227 protruding from the lower exposure hole 220, and is ejected toward the cancel shooter 206. 12, the sub-plate 205 and the cancel shooter 206 of the medal selector 201 are omitted as in FIG.

  In addition, in the present embodiment, the select plate 207 is normally positioned at the guide position, but under a predetermined condition (for example, when a specified number of medals are inserted, when an error occurs, when a game is started, etc.), the select plate 207 is placed at the discharge position. It is positioned.

  Further, when the medal moving on the medal rail 210 has a diameter smaller than the standard size, even if the select plate 207 is at the guide position, the medal is not guided to the select plate 207 but pushed out to the medal pressure 213 and the cancel shooter 206. Is discharged toward.

  As shown in FIGS. 7 and 8, the camera unit 209 includes a first substrate 230 and a second substrate 231, and is a unit that determines whether an object moving on the medal rail 210 is a regular medal. Is. A CMOS image sensor 232 (see FIG. 16) and an LED 233 (see FIG. 16) are provided on the first substrate 230. The second substrate 231 is provided with a control LSI 234 (see FIG. 16) communicatively and controllably connected to the CMOS image sensor 232 and the LED 233. The first substrate 230 and the second substrate 231 are connected by a BtoB (Board-to-Board) type connector (not shown), and the leg portions 235 provided at the corners of the respective substrates 230 and 231 are used. It is fixed. The specific configuration of the circuit of the camera unit 209 will be described later. Further, in the present embodiment, the mode in which the camera unit 209 is configured with the two substrates 230 and 231 has been described, but instead of this, one substrate provided with the CMOS image sensor 232, the LED 233, and the control LSI 234 may be used. May be configured.

  The camera unit 209 is fixed by screwing the first substrate 230 into a screw hole 206b provided around the notch 206a in the upper portion of the cancel shooter 206. The CMOS image sensor 232 (see FIG. 16) is provided in a substantially central portion of the first substrate 230. The CMOS image sensor 232 images a medal moving on the medal rail 210, and outputs image data of the imaged medal to the control LSI 234 (see FIG. 16). The LED 233 (see FIG. 16) emits surface light around the CMOS image sensor 232, and illuminates the medal moving on the medal rail 210. The control LSI 234 (see FIG. 16) determines whether the object moving on the medal rail 210 is a regular medal based on the image data output from the CMOS image sensor 232, and outputs the determination result. That is, in the present embodiment, the control LSI 234 constitutes a game medium determination unit that determines whether or not the medal moving on the medal rail 210 is a regular medal. In the present embodiment, the mode in which the camera unit 209 is fixed to the cancel shooter 206 by screwing in the screw hole 206b formed around the notch 206a has been described, but the mode in which the camera unit is fixed is not limited to this. Not done. For example, a mounting rail is provided between the first substrate 230 and the second substrate 231, a recess is provided in the upper portion of the cancel shooter 206, and the mounting rail is fitted into this recess, and then the mounting rail and the cancel shooter 206 are provided. May be fixed with screws or an adhesive.

<Pachislot circuit configuration>
Next, the configuration of the circuit included in the pachi-slot 1 will be described with reference to FIGS. First, an overview of the entire circuit of the pachi-slot 1 will be described with reference to FIG. FIG. 13 is a block configuration diagram of the entire circuit included in the pachi-slot 1.

  The pachi-slot 1 has a main control board 71 arranged on the middle door 41 and a sub-control board 72 arranged on the front door 2b. On the main control board 71, there are a reel relay terminal board 74, a setting key type switch 56, an external centralized terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, and a power supply board 53b of the power supply device 53. It is connected. The setting key type switch 56, the external centralized terminal plate 47, the hopper device 51, and the medal auxiliary storage switch 75 are connected to the main control board 71 via the cabinet side relay board 44. Since the external centralized terminal board 47 and the hopper device 51 have been described above, the description thereof will be omitted.

  The reel relay terminal plate 74 is arranged inside the reel bodies of the reels 3L, 3C, 3R. The reel relay terminal plate 74 is electrically connected to a stepping motor (not shown) of each reel 3L, 3C, 3R and relays a signal output from the main control board 71 to the stepping motor.

  The medal auxiliary storage case switch 75 penetrates a switch through hole (not shown) of the medal auxiliary storage case 52. The medal auxiliary storage switch 75 detects whether or not the medal auxiliary storage 52 is full of medals.

  A power switch 53a is connected to a power board 53b of the power supply device 53. The power switch 53a is turned on when the pachi-slot 1 is supplied with necessary power.

  Further, on the main control board 71, via the door relay terminal board 68, the medal selector 201, the door opening / closing monitoring switch 67, the BET switch 77, the settlement switch 78, the start switch 79, the stop switch board 80, the game operation display board 81. And the sub relay board 61 is connected. Since the door open / close monitor switch 67 and the sub relay board 61 have been described above, the description thereof will be omitted. The circuit configuration of the medal selector 201 will be described later.

  The BET switch 77 detects that the BET button 22 has been pressed by the player. The settlement switch 78 detects that the settlement button 27 has been pressed by the player. The start switch 79 detects that the start lever 23 has been operated by the player (start operation).

  The stop switch board 80 is a board that constitutes a circuit for stopping the spinning reel and a circuit for displaying the reel that can be stopped by means of LEDs or the like. The stop switch board 80 is provided with a stop switch. The stop switch detects that the stop buttons 19L, 19C, 19R are pressed by the player (stop operation).

  The game operation display board 81 displays the number of inserted medals on the 7-segment display 24 when receiving the insertion of medals, when the three reels 3L, 3C, and 3R are rotatable and when replaying. It is a substrate for making. The 7-segment display 24 and the LED 82 are connected to the game operation display board 81. The LED 82 lights, for example, a mark indicating the start of a game or a mark for performing a re-game.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. A sound I / O board 84, LED boards 62A, 62B, 62C, and a 24h door opening / closing monitoring unit 63 are connected to the sub control board 72 via a sub relay board 61. The LED boards 62A, 62B, 62C and the 24h door opening / closing monitoring unit 63 have been described above, and thus the description thereof will be omitted.

  The sound I / O board 84 outputs sound to a center speaker 58, a board speaker 64, lower speakers 65L and 65R, and speakers (not shown) provided on the front door 2b.

  A ROM cartridge substrate 86 and a liquid crystal relay substrate 87 are connected to the sub control substrate 72. The ROM cartridge board 86 and the liquid crystal relay board 87 are housed in the sub control board case 57 together with the sub control board 72. The ROM cartridge board 86 is a board for managing images for production (video), sound, LED boards 62A and 62B, other LED boards (not shown), and communication data. The liquid crystal relay board 87 is a board that relays the wiring that connects the sub-control board 72 and the liquid crystal display device 11.

[Main control circuit]
Next, the main control circuit 91 configured by the main control board 71 will be described with reference to FIG. FIG. 14 is a block diagram showing a configuration example of the main control circuit 91 of the pachi-slot 1.

  The main control circuit 91 has a microcomputer 92 installed on the main control board 71 as a main component. The microcomputer 92 includes a main CPU 93, a main ROM 94 and a main RAM 95. The main CPU 93 and the above-mentioned hopper device 51 constitute the game medium payout device of the present invention.

  In the main ROM 94, a control program executed by the main CPU 93 (for example, a program for executing the above-mentioned internal lottery process), a data table, and various control commands (commands) to the sub-control circuit 101 are transmitted. Data and the like are stored. The main RAM 95 is provided with a storage area for storing various data such as an internal winning combination determined by executing the control program.

  A clock pulse generation circuit 96, a frequency divider 97, a random number generator 98, and a sampling circuit 99 are connected to the main CPU 93. The clock pulse generation circuit 96 and the frequency divider 97 generate clock pulses. The main CPU 93 executes the control program based on the generated clock pulse. The random number generator 98 generates a random number in a predetermined range (for example, 0 to 65535). The sampling circuit 99 extracts one value from the generated random numbers.

  After detecting the reel index, the main CPU 93 counts the number of times pulses are output to the stepping motors of the reels 3L, 3C, 3R. Thereby, the main CPU 93 manages the rotation angle of each reel 3L, 3C, 3R (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has rotated once. The reel index is provided, for example, at a predetermined position of each reel 3L, 3C, 3R with an optical sensor having a light emitting unit and a light receiving unit, and the rotation of each reel 3L, 3C, 3R makes the light emitting unit and the light receiving unit. It is detected by a reel position detection unit (not shown) having a detection piece interposed therebetween.

  Here, the management of the rotation angle of each reel 3L, 3C, 3R will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 95. Then, each time the pulse counter counts a predetermined number of times (for example, 16 times) of pulse output required to rotate one symbol, the symbol counter provided in the main RAM 95 is incremented by one. The symbol counter is provided for each reel 3L, 3C, 3R. The value of the symbol counter is cleared when the reel index is detected by the reel position detector (not shown).

  That is, in the present embodiment, by managing the symbol counter, the number of symbols rotated after the reel index is detected is managed. Therefore, the position of each symbol on each reel 3L, 3C, 3R is detected with reference to the position at which the reel index is detected.

  As described above, when the maximum number of sliding pieces is set to 4 symbols, the symbol of the left reel 3L in the middle stage of the reel display window 4 when the left stop button 19L is pressed, and the 4 symbols Each symbol within the range up to the previous symbol is a symbol that can be stopped in the middle stage of the reel display window 4.

[Sub control circuit]
Next, the sub control circuit 101 configured by the sub control board 72 will be described with reference to FIG. FIG. 15 is a block diagram showing a configuration example of the sub control circuit 101 of the pachi-slot 1.

  The sub control circuit 101 is electrically connected to the main control circuit 91, and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 91. The sub control circuit 101 basically includes a sub CPU 102, a sub RAM 103, a rendering processor 104, a drawing RAM 105, and a driver 106.

  The sub CPU 102 controls the output of video, sound, and light according to the control program stored in the ROM cartridge substrate 86 in response to the command transmitted from the main control circuit 91. The ROM cartridge board 86 basically includes a program storage area and a data storage area.

  A control program executed by the sub CPU 102 is stored in the program storage area. For example, in the control program, a main board communication task for controlling communication with the main control circuit 91, and a performance registration task for extracting a random number value for performance and determining and registering the performance content (performance data). Is included. In addition, a drawing control task that controls the display of an image by the liquid crystal display device 11 (see FIG. 2) based on the determined effect contents, a lamp control task that controls the output of light by a light source such as the LED 85, and speakers 58, 64, 65L. , 65R, and the like, including a voice control task for controlling the output of sound by a speaker.

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to image creation. In addition, a storage area for storing sound data regarding BGM and sound effects, a storage area for storing lamp data regarding a pattern of turning on / off light, and the like are included.

  The sub RAM 103 is provided with a storage area for registering the determined effect contents and effect data, and a storage area for storing various data such as an internal winning combination transmitted from the main control circuit 91.

  The sub CPU 102, the rendering processor 104, the drawing RAM (including a frame buffer) 105, and the driver 106 create a video according to the animation data specified by the effect contents, and display the created video on the liquid crystal display device 11.

  Further, the sub CPU 102 causes the speakers 58, 64, 65L, 65R and the like to output sounds such as BGM according to the sound data specified by the effect contents. In addition, the sub CPU 102 controls the turning on and off of the light source such as the LED 85 according to the lamp data specified by the effect contents.

<Circuit configuration of medal selector>
Next, the circuit configuration of the medal selector 201 will be described with reference to FIG. FIG. 16 is a block diagram showing a circuit configuration example of the medal selector 201.

  As shown in FIG. 16, the medal selector 201 includes a camera unit 209 and a medal solenoid 208. Further, the medal selector 201 is connected to the main control board 71 via the door relay terminal plate 68. That is, the medal selector 201 is electrically connected to the main control circuit 91. Therefore, the main control circuit 91 can set the medal solenoid 208 of the medal selector 201 to the ON state or the OFF state.

  The camera unit 209 includes a control LSI 234, a CMOS image sensor 232, and an LED 233. The control LSI 234 of the camera unit 209 is configured as an LSI dedicated to image processing control, such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field-programmable Gate Array), and is electrically connected to the CMOS image sensor 232 and the LED 233. Has been done. The control LSI 234 controls the light emission of the LED 233. Further, the control LSI 234 determines whether or not the insertion is a regular medal based on the image data output from the CMOS image sensor 232, and outputs the determination result to the main control board 71 via the door relay terminal board 68. .. The CMOS image sensor 232 used in the present embodiment is a CMOS image sensor having a resolution of 648 × 488 pixels and a frame rate of 240 fps (Frames Per Second), but is not limited to such an image sensor. It need not be done (an imager other than CMOS could also be used). A light emitting device other than the LED can also be used.

[Circuit configuration of control LSI]
Next, the circuit configuration of the control LSI 234 will be described with reference to FIGS. FIG. 17 is a block diagram showing a circuit configuration example of the control LSI 234. FIG. 18 is a functional block diagram of the camera unit 209 including the control LSI 234, FIG. 19 is a diagram for explaining a regular medal, FIG. 19A shows one side of the regular medal, and FIG. 19B is an image of the regular medal. Shows the data. FIG. 20 is a diagram for explaining the generation (combination) of the processed image data (gradient average image data) related to the regular medal. Note that the camera unit 209 includes a light emitting unit including an LED or the like, but the illustration thereof is omitted in FIG. 18.

  The control LSI 234 includes a host controller 241, an image recognition DSP (digital signal processor) circuit 242, a DMAC (Direct Memory Access Controller) 252, an SRAM (Static Random Access Memory) 243, a flash memory 244, an ISP (Image). Signal processing) circuit 245 and medal counting circuit 246. The control LSI 234 also includes a color recognition circuit 247, a fisheye correction scaler circuit 248, an image recognition accelerator circuit 249, and a GPIO (General Purpose Input / Output) 250. The devices forming the control LSI 234 are connected to each other via a bus, and the control LSI 234 of the present embodiment employs AXI (Advanced eXtensible Interface) as a bus protocol.

  Further, the control LSI 234 includes an ISI (Image Sensor Interface) circuit 251. The ISI circuit 251 is electrically connected to the CMOS image sensor 232 and the ISP circuit. The ISI circuit 251 converts the image data output from the CMOS image sensor 232 by the LVDS (Low voltage differential signaling) method into an RGB Bayer image and outputs the RGB Bayer image to the ISP circuit 245.

  The DMAC 252 is a circuit that controls direct transfer (that is, DMA (direct memory access) transfer) that transfers data between a memory and an input / output device without passing through the host controller 241. In the present embodiment, when data transfer is performed between the memory of each circuit described above included in the control LSI 234 and the SRAM 243, DMA transfer under the control of the DMAC 252 is performed as necessary. In the present embodiment, the DMAC 252 is controlled by the control of the DMAC 252 for at least one transfer / storing of the predetermined data as necessary. However, such a DMA transfer is not performed, and the DMAC 252 may be deleted from the configuration. You can also That is, in the present embodiment, the DMAC 252 that controls the DMA for directly transferring the data transfer between each circuit and the SRAM 243 without passing through the host controller 241 constitutes the direct transfer control means.

  Upon receiving the RGB Bayer image from the ISI circuit 251, the ISP circuit 245 outputs a VSYNC (Vertical Synchronization) interrupt signal to the host controller 241. The ISP circuit 245 also performs format conversion processing for converting the RGB Bayer image output from the ISI circuit 251 into various formats. In the format conversion process, the ISP circuit 245 converts the RGB Bayer image into Y (luminance of each pixel), and stores the converted image data in the SRAM 243 by, for example, DMA transfer. Further, the ISP circuit 245 converts the RGB Bayer image into image data (YUV image data) corresponding to the YUV color space, and outputs the data relating to the luminance in this YUV image data to the medal count circuit 246. Further, the ISP circuit 245 converts the RGB Bayer image into image data (HSV image data) corresponding to the HSV color space, and outputs the data relating to the hue and the saturation in this HSV image data to the color recognition circuit 247.

  Here, the CMOS image sensor 232 corresponds to the imaging unit 261 shown in FIG. Further, a processing function of converting the ISI circuit 251 (and the host controller 241 that controls the ISI circuit 251) and part of the ISP circuit 245 (at least the RGB Bayer image into image data (YUV image data) corresponding to the YUV color space). 18) and the host controller 241 for controlling the same correspond to the conversion unit 263 in FIG. The captured image 262 is sent from the image capturing unit 261 to the converting unit 263.

  The medal counting circuit 246 performs a counting process based on the brightness-related data output from the ISP circuit 245. In the counting process, the medal counting circuit 246 compares the data relating to the luminance of the count area, which is a predetermined area in the image, with the count threshold value, and determines whether or not the medal has passed by the background difference method. The count threshold value is a threshold value that is predetermined based on the data relating to the brightness of the count area in the image of the regular medal. The medal counting circuit 246 determines that the medal has passed if the difference is small, and determines that the medal has not passed (if something other than the medal has passed) if the difference is large. Then, the medal counting circuit 246 stores the determination result in the SRAM 243.

  The count area can be arbitrarily set according to the medals used by the pachi-slot 1 as a regular medal, but it is preferable to set the count area so that the rotation angle of the medals does not significantly affect the brightness difference. For example, when using a regular medal 400 having the same markings (patterns) on both sides as shown in FIG. 19A, one of the regular medals in the area is shown in the image data 402 (see FIG. 19B) of this regular medal 400. The place (area 403 in FIG. 19B) is set as the count area so that the marking (pattern) on the surface does not change depending on the rotation angle of the medal, that is, the rotation angle of the medal does not significantly affect the difference in brightness. Is preferred. Also, the narrower the range of the count area, the faster the counting process can be.

  The color recognition circuit 247 performs color determination processing based on the hue and saturation data output from the ISP circuit 245. In the color determination process, the color recognition circuit 247 first expresses the integrated value of the data relating to the hue and saturation near the center of the image data as a vector (vector conversion) and calculates the angle of the vector in the three-dimensional space. To do. Next, the color recognition circuit 247 compares the calculated angle of the vector with a predetermined color threshold value and determines whether or not the color matches the color of the regular medal. The predetermined threshold value is a predetermined threshold value based on the angle of the vector calculated by the same method as the above-described process for the image data of the regular medals (for example, 3 for the regular medals to be compared). It is within ± 10 degrees of the angle on each coordinate (XYZ) of the vector in the dimensional space). Then, the color recognition circuit 247 stores the determination result in the SRAM 243.

  The fisheye correction scaler circuit 248 acquires image data obtained by Y-converting the RGB Bayer image from the SRAM 243 (luminance of each pixel) by, for example, DMA transfer, and performs fisheye correction processing. In the fisheye correction process, the fisheye correction scaler circuit 248 performs fisheye correction (for example, bilinear interpolation) on the acquired image data to create reduced image data reduced to 1/2, 1/4, and 1/8. .. Then, the fisheye correction scaler circuit 248 stores the created reduced image data in the SRAM 243 by, for example, DMA transfer.

  The fisheye correction scaler circuit 248 and the host controller 241 that controls the scaler circuit 248 are included in the conversion unit 263 in FIG. 18.

  The image recognition DSP circuit 242 acquires reduced image data (in the present embodiment, reduced image data reduced to 1/4) from the SRAM 243 by, for example, DMA transfer, and performs preprocessing. In the pre-processing, the image recognition DSP circuit 242 converts the acquired reduced image data into edge image data through a non-linear diffusion filter, and stores the edge image data in the SRAM 243 by DMA transfer, for example.

  Here, a part of the image recognition DSP circuit 242 (the above-mentioned processing function unit for converting the acquired reduced image data into edge image data through a non-linear diffusion filter) and the host controller 241 for controlling the same are shown in FIG. It is included in the conversion unit 263.

  The image recognition accelerator circuit 249 performs image processing (for example, rotation integration processing here) for creating processed image data (for example, gradient average image data here). In this image processing, the image recognition accelerator circuit 249 acquires edge image data from the SRAM 243 by, for example, DMA transfer, and acquires the acquired edge image data (for example, the image data 402 shown in FIG. 19B) once, for example, once. The processed image data is generated by accumulating (overlapping) the converted image data for 360 degrees generated by being rotated by. The processed image data generated by the image recognition accelerator circuit 249 is stored in the SRAM 243 by, for example, DMA transfer. As an example in which the processed image data is generated (combined), the processed image data 405 of the regular medal 400 shown in FIG. 19A is shown in FIG. The processed image data 405 is image data (gradient average image data) in which the edge image data in the shape of “A” is integrated while rotating, for example, 360 degrees (that is, integrated 360 times). Are simplified and shown.

  The processing function unit of the image recognition accelerator circuit 249 that generates processed image data and the host controller 241 that controls the processing function unit correspond to the characteristic image generation unit 264 of FIG. 18.

  Further, the image recognition DSP circuit 242 performs marking determination processing for determining whether the marking (pattern) of the medal matches the marking of the regular medal. In the marking determination process, the image recognition DSP circuit 242 acquires the processed image data created by the image processing by the image recognition accelerator circuit 249 from the SRAM 243 by, for example, DMA transfer. Next, the image recognition DSP circuit 242 makes a difference between the acquired processed image data and the template data for the marking determination process (for example, the processed image data of the regular medal stored in the SRAM 243 or the flash memory 244 prepared in advance). To calculate. Then, the image recognition DSP circuit 242 determines whether the marking of the medal matches the marking of the regular medal based on the calculated difference value and the threshold value for marking determination, and stores the determination result in the SRAM 243. .. For example, the image recognition DSP circuit 242 compares the brightness of each pixel of the acquired processed image data and the template data, and determines whether they match (in the case of multi-tone, the difference is within a predetermined range), When the number of matching pixels (the difference is within a predetermined range) is a certain number or more, it is determined that the marking (pattern) of the medal matches the marking of the regular medal, and when the number of matching pixels is less than the certain number, the marking of the medal ( It is determined that the pattern does not match the marking of the regular medal.

  Note that the processing function unit related to the marking determination process of the image recognition DSP circuit 242 and the host controller 241 that controls the processing function unit correspond to the determination unit 265 shown in FIG. 18, and the template data is the template data 267. Corresponding to.

  The image recognition DSP circuit 242 and the host controller 241 that perform the above-described marking determination processing operate by a program (sequence program), and the program is, for example, a memory (for example, a memory arranged in the image recognition DSP circuit 242 and the host controller 241). , DRAM). Further, these programs may be stored in the SRAM 243 or the flash memory 244. The template data is stored in the SRAM 243, for example.

  The host controller 241 includes a processor and controls each device, that is, the medal count circuit 246, the color recognition circuit 247, the fisheye correction scaler circuit 248, the image recognition DSP circuit 242, the image recognition accelerator circuit 249, and the GPIO 250. Further, the host controller 241 outputs a signal related to a lighting instruction or a light extinguishing instruction to the LED 233 via the GPIO 250. Further, the host controller 241 outputs the determination result regarding the count process, the determination result regarding the color determination process, and the determination result regarding the marking determination process stored in the SRAM 243 via the GPIO 250.

  The GPIO 250 that outputs the determination result of the color determination process or the marking determination process and the host controller 241 that controls the GPIO 250 described above correspond to the input / output unit 266 illustrated in FIG. 18, and the determination result is the determination of FIG. Corresponds to result 268.

  Each of the host controller 241, the image recognition DSP circuit 242, the fisheye correction scaler circuit 248, and the image recognition accelerator circuit 249 has a memory (for example, DRAM), and the memory has parameters and data (for example, for example) used for various processes. Image data) is stored. Also, these parameters and data can be stored in the SRAM 243 or the flash memory 244.

[Image recognition accelerator circuit configuration]
Next, the configuration of the image recognition accelerator circuit 249 will be described with reference to FIG. FIG. 21 is a block diagram showing a circuit configuration example of the image recognition accelerator circuit 249.

  As shown in FIG. 21, the image recognition accelerator circuit 249 includes an input frame buffer 271, a coordinate conversion circuit 272, an image processing circuit 273, and a memory 274 (the memory 274 includes a storage circuit such as a DRAM). Is equipped with. The target image data 275 generated based on the image data of the medal imaged by the CMOS image sensor 232 and stored in the SRAM 243 or the like is input to the input frame buffer 271.

  Under the control of the DMAC 252, the image recognition accelerator circuit 249 can access the SRAM 243 without passing through the host controller 241 and transfer the target image data 275 from the SRAM 243 to the input frame buffer 271 (DMA transfer). That is, data transfer is performed between the image recognition accelerator circuit 249 and the SRAM 243 without going through the CPU of the host controller 241.

  The input frame buffer 271 can store one frame of target image data 275. The DMAC 252 controls to read the target image data 275 stored in the SRAM 243 and write the data in the input frame buffer 271. The DMAC 252 repeats such control at a predetermined timing, reads the target image data 275 stored in the SRAM 243, and sequentially stores it in the input frame buffer 271.

  Further, the DMAC 252 can also be configured to have a buffer capable of storing image data composed of a plurality of pixel data. The buffer is, for example, a FIFO (first in first out) buffer. In this case, the DMAC 252 reads the target image data 275 stored in the SRAM 243 and temporarily stores the data in the buffer. Then, the DMAC 252 writes the plurality of pixel data in the buffer into the input frame buffer 271. By repeating this processing a plurality of times, the target image data 275 for one frame is written in the input frame buffer 271.

  The coordinate conversion circuit 272 performs image coordinate conversion on the target image data 275 stored in the input frame buffer 271. The converted image data 276 after the coordinate conversion is input to the image processing circuit 273. When the new target image data 275 is stored in the input frame buffer 271, the coordinate conversion circuit 272 performs image coordinate conversion on the new target image data 275 stored in the input frame buffer 271. In this specification, the image data subjected to the coordinate conversion by the coordinate conversion circuit 272 is referred to as “converted image data”, and the image data before the coordinate conversion is referred to as “target image data”.

  Further, the coordinate conversion circuit 272 is provided with the conversion parameter 280 stored in the memory 274. The conversion parameter 280 is, for example, copied from the SRAM 243 at a timing such as initial setting of the image recognition accelerator circuit 249.

  The image processing circuit 273 performs predetermined image processing on the converted image data 276 obtained by the coordinate conversion circuit 272. For example, the image processing circuit 273 synthesizes the plurality of converted image data 276 obtained by the coordinate conversion circuit 272, and outputs the processed image data 277 obtained thereby. In the present specification, image data generated as a result of image processing by the image processing circuit 273 (for example, image data obtained by integrating a plurality of pieces of converted image data, or a plurality of coordinate conversions on target image data is executed. Image data) is referred to as “processed image data”.

  The processed image data 277 generated by the image processing circuit 273 is transferred to the SRAM 243 (DMA transfer) under the control of the DMAC 252. When the DMAC 252 has a buffer, the DMAC 252 temporarily stores the plurality of pixel data of the processed image data 277 output from the image processing circuit 273 in the buffer, and then writes the plurality of pixel data in the buffer into the SRAM 243. By repeating this processing a plurality of times, the processed image data for one frame is written in the SRAM 243.

[Operation and configuration of coordinate conversion circuit]
Here, first, an outline of the operation of the coordinate conversion circuit 272 will be described, and then the configuration and detailed operation of the coordinate conversion circuit 272 will be described.

[Outline of operation of coordinate conversion circuit]
The coordinate conversion circuit 272 uses the target image data 275 for one frame stored in the input frame buffer 271 to perform a plurality of coordinate conversions. Specifically, the coordinate conversion circuit 272 individually performs a plurality of coordinate conversions on the target image data 275, as shown in FIG. 22, to obtain a plurality of converted image data 276 (for example, 276- 1-276-360).

  In the present embodiment, the coordinate conversion circuit 272 performs the coordinate conversion for performing the affine transformation of the image on the target image data 275. Specifically, the coordinate conversion circuit 272 performs coordinate conversion for rotating the image on the target image data 275. As a result, the coordinate conversion circuit 272 rotates the target image data 275, and the rotated image data is obtained as the converted image data 276. Here, the rotation of the image is the rotation of the subject reflected in the image, and even if the image is rotated, the outer shape of the image does not change. Hereinafter, the rotated image represented by the converted image data 276 may be simply referred to as “rotated image”.

  The coordinate conversion circuit 272 individually performs a plurality of coordinate conversions on the target image data 275 stored in the input frame buffer 271 to generate a plurality of converted image data 276 having different rotation angles. Each time the target image data 275 is written in the input frame buffer 271, the coordinate conversion circuit 272 individually performs a plurality of coordinate conversions on the target image data 275 stored in the input frame buffer 271.

[Configuration of coordinate conversion circuit]
FIG. 23 is a diagram mainly showing the configuration of the coordinate conversion circuit 272, and the image recognition accelerator circuit 249 shown in FIG. 23 is the same circuit as that shown in FIG. As shown in FIG. 23, the coordinate conversion circuit 272 includes a conversion circuit 281 that performs coordinate conversion and a control circuit 282. The coordinate conversion circuit 272 according to the present embodiment is configured as hardware that operates without using software, unlike the configuration in which predetermined processing is performed by executing a program by a CPU, for example.

  As shown in FIG. 23, the memory 274 stores conversion parameters 280 used in coordinate conversion. The conversion parameter 280 includes a plurality of conversion parameters 280 necessary for a plurality of coordinate conversions. The conversion parameter 280 is written from the SRAM 243 to the memory 274 by the host controller 241 as described later.

  The conversion circuit 281 individually performs a plurality of coordinate conversions on one target image data 275 stored in the input frame buffer 271 to generate a plurality of converted image data 276.

  FIG. 24 is a diagram showing an example of how the conversion parameter 280 is stored in the memory 274. As shown in FIG. 24, the conversion parameter 280 includes a plurality of conversion parameters (280-1 to 280-360) for performing a plurality of rotations on the image. The conversion parameters 280 shown in FIG. 24 are, for example, 360 conversion parameters (280-1 to 280-360) for rotating the image from 1 ° to 360 °.

  In the memory 274, the conversion parameter 280 having a smaller rotation angle is stored in a storage area having a smaller address. Therefore, when the conversion parameters 280 of 360 stored in the memory 274 are viewed in ascending order of the address of the storage area in which they are stored, the conversion parameters 280 of 360 are arranged in the descending order of the rotation angle.

  The conversion circuit 281 performs coordinate conversion on the target image data 275 based on the conversion parameter 280 stored in the memory 274. As a result, the target image data 275 is subjected to coordinate conversion processing so as to rotate by the rotation angle according to the conversion parameter 280. In the present embodiment, the target image data 275 is assumed to be converted so as to be rotated clockwise around the center of gravity of the figure represented in the target image data 275, for example.

  The control circuit 282 sequentially reads the plurality of conversion parameters 280 from the memory 274 and supplies the conversion parameters 280 to the conversion circuit 281. As a result, the conversion circuit 281 is sequentially input with the plurality of conversion parameters 280 stored in the memory 274 by the function of the control circuit 282, and the conversion circuit 281 is input each time the conversion parameter 280 is input. The target image data 275 in the input frame buffer 271 is rotated based on the conversion parameter 280, and the converted image data 276 thus obtained is output to the image processing circuit 273.

  The control circuit 282 also has a register 283. The register 283 has a specification for specifying a plurality of conversion parameters 280 used in the conversion circuit 281 among the conversion parameters 280 (in the example of FIG. 24, 360 conversion parameters (280-1 to 280-360)). Information 290 is stored. The control circuit 282 sequentially reads the conversion parameter 280 from the memory 274 based on the specific information 290 of the register 283. The specific information 290 is set in the register 283 by the host controller 241 as described later.

  FIG. 25 is a diagram showing an example of the specific information 290. As shown in FIG. 25, the specific information 290 includes, for example, the number of use parameters 291, the use start position 292, and the use interval 293. In the present embodiment, as described above, the coordinate conversion circuit 272 sequentially and continuously performs coordinate conversion of the target image data 275 based on the plurality of conversion parameters 280 that are sequentially input. In addition, the conversion parameters 280 input in this way are provided in the order of, for example, the rotation angle (which performs coordinate conversion) is smaller.

  The number of used parameters 291 indicates the number of conversion parameters 280 used in the coordinate conversion circuit 272 for one target image data 275. In the present embodiment, since one conversion parameter 280 is used for the target image data 275 and the coordinate conversion is performed once, the number of used parameters 291 is the number of coordinate conversion times for one target image data 275. It can be said that it shows. When the number of used parameters 291 indicates, for example, “180”, the conversion circuit 281 individually performs 180 times of coordinate conversion on one target image data 275, and 180 converted image data having different rotation angles from each other. 276 is continuously generated.

  The use start position 292 indicates the storage position of the conversion parameter 280 used first, that is, the address (in the storage area of the memory 274) where the conversion parameter 280 used first is stored. In the example of FIG. 25, when the use start position 292 indicates “0001h”, for example, the conversion parameter (280-2) for rotating the target image data 275 by 2 ° is used first.

  When the coordinate conversion is performed, the use interval 293 is used to determine how many conversion parameters 280 are used from the conversion parameters 280 used in the previous coordinate conversion in the plurality of conversion parameters 280 arranged in the order of smaller rotation angles. Shows. For example, when the usage interval 293 indicates “2”, when performing the coordinate conversion, the conversion parameter 280 used in the previous coordinate conversion (for example, the conversion parameter 280 for rotating the target image data 275 by 2 °- The conversion parameter 280 separated from 2) by 2 (for example, the conversion parameter 280-4 for rotating the target image data 275 by 4 °) is used.

  As described above, when one target image data 275 stored in the input frame buffer 271 is rotated by 2 ° from 2 ° to 360 ° by 2 °, the use parameter number 291 becomes “180” and the use start position 292 becomes “0001h. , And the use interval 293 becomes “2”. In this case, the control circuit 282 causes the conversion parameter 280-2 with a rotation angle of 2 °, the conversion parameter 280-4 with a rotation angle of 4 °, the conversion parameter 280-6 with a rotation angle of 6 °, ... The conversion parameters 280-358 having a rotation angle of 358 ° and the conversion parameters 280-360 having a rotation angle of 360 ° are sequentially read and sequentially input to the conversion circuit 281. As a result, in the conversion circuit 281, as shown in FIG. 26, 180 converted image data 276 (276-1, 276-2, 276-3, ..., 276-179, 276) having different rotation angles by 2 °. -180) are sequentially generated.

  In addition, in the example of FIG. 25, if the number of used parameters 291 is set to “360”, the use start position 292 is set to “0000h”, and the use interval 293 is set to “1”, it is stored in the input frame buffer 271. The obtained one target image data 275 is rotated by 1 ° from 1 ° to 360 °, and 360 converted image data 276 is generated.

  Further, the number of used parameters 291 is set to "36", the use start position 292 is set to the address of the storage area in which the conversion parameter 280 having a rotation angle of 10 ° is stored, and the use interval 293 is set to "10". Then, one target image data 275 stored in the input frame buffer 271 is rotated by 10 ° from 10 ° to 360 °, and 36 converted image data 276 are generated.

  Also, the number of use parameters 291 is set to "18", the use start position 292 is set to the address of the storage area in which the conversion parameter 280 having a rotation angle of 270 ° is stored, and the use interval 293 is set to "5". Then, one target image data 275 stored in the input frame buffer 271 is rotated by 5 ° from 270 ° to 360 °, and 18 converted image data 276 are generated.

  The conversion circuit 281 outputs the converted image data 276 one by one to the image processing circuit 273. Further, the conversion circuit 281 outputs the plurality of pixels forming the converted image data 276 to the image processing circuit 273 in units of a predetermined number of pixels or one pixel at a time (every time the pixel is generated). be able to.

  As described above, in the coordinate conversion circuit 272, since the conversion parameter 280 is specified by the specification information 290, it is possible to determine what kind of coordinate conversion the coordinate conversion circuit 272 should perform by the specification information 290. ..

  Further, since the conversion parameter 280 is specified by the specification information 290, the control LSI 234 or the medal selector 201 changes the specification information 290 used by the coordinate conversion circuit 272, so that the plurality of control LSIs 234 or the medal selector 201 can be changed. Different coordinate transformations can be performed between them.

  Further, a plurality of pieces of specific information 290 may be used in one control LSI 234 or medal selector 201. In this case, the coordinate conversion circuit 272 uses the first specifying information 290-1 when performing coordinate conversion on certain target image data 275, and performs coordinate conversion at other target image data 275 ′. For this, the second specific information 290-2 different from the first specific information 290-1 is used. Accordingly, the coordinate conversion circuit 272 can perform different coordinate conversion for each target image data.

  In addition, in the present embodiment, the specific information 290 is configured to include the number of use parameters 291, the use start position 292, and the use interval 293, but some information may be omitted (for example, If the number of conversion parameters 280 stored in the memory 274 is known, the number of used parameters 291 can be omitted).

[Example of conversion parameters]
In the coordinate conversion of the target image data 275, the pixel at the coordinate CZ corresponding to the certain coordinate Z in the target image data 275 is adopted as the pixel at the certain coordinate Z in the converted image data 276. In the target image data 275, when a pixel does not exist at the coordinate CZ corresponding to a certain coordinate Z in the converted image data 276, the pixel data at the corresponding coordinate CZ is a plurality of pixels around the corresponding coordinate CZ. It is obtained by interpolation using the pixel data of a plurality of pixels existing at the coordinates PCZ. For this pixel interpolation, for example, bilinear interpolation or bicubic interpolation is used.

  FIG. 27 is a diagram for explaining an example of coordinate conversion by the conversion parameter 280. In the present embodiment, the conversion parameter 280 includes an image represented by the target image data 275 corresponding to the coordinates A1, B1, C1, and D1 of the four corner pixels in the image represented by the converted image data 276, respectively. 4 coordinates A0, B0, C0, D0 are included.

  When the conversion parameter 280 is input, the conversion circuit 281 receives the coordinates of a plurality of pixels forming the converted image data 276 based on the four coordinates A0, B0, C0, D0 included in the input conversion parameter 280. A plurality of coordinates in the target image data 275, which respectively correspond to Then, the conversion circuit 281 determines the pixel data at each of the plurality of coordinates obtained for the target image data 275 based on the pixel data of the plurality of pixels forming the target image data 275. At this time, pixel interpolation is used as needed. After that, the conversion circuit 281 adopts the pixel data at the corresponding coordinates in the target image data 275 as the pixel data at each coordinate in the converted image data 276. Thereby, in the conversion circuit 281, the image represented by the target image data 275 is rotated based on the input conversion parameter 280, and a rotated image is generated.

  By performing a predetermined coordinate transformation on the target image data 275, it is possible to correct image distortion such as barrel distortion included in the target image data 275. Therefore, as the conversion parameter 280, the conversion parameter 280 corresponding to both the coordinate conversion for rotating the image and the coordinate conversion for performing the distortion correction is stored in the memory 274, and the coordinate conversion circuit 272 is based on the conversion parameter 280. Then, the image rotation and the distortion correction may be simultaneously performed on the target image data 275. The above-mentioned Patent Documents 2 and 3 disclose a barrel distortion correction technique.

[Operation and configuration of image processing circuit]
Here, first, an outline of the operation of the image processing circuit 273 will be described, and then the configuration and detailed operation of the image processing circuit 273 will be described.

[Outline of operation of image processing circuit]
As shown in FIG. 28, the image processing circuit 273 synthesizes a plurality of post-conversion image data 276 generated by the coordinate conversion circuit 272, and the processed image data 277 thus obtained is output to the SRAM 243 (DMA). Output (by transfer). The image processing circuit 273 has a frame memory capable of storing one frame of image data, and uses the frame memory to generate processed image data 277.

  FIG. 29 is a diagram for explaining the outline of the operation of the image processing circuit 273. The image processing circuit 273 generates processed image data 277 (processed image data 277- (N-1) shown in FIG. 29) by sequentially accumulating the N converted image data 276 '.

  As shown in FIG. 29, the image processing circuit 273 uses the converted image data 276-1 generated first by the conversion circuit 281 (for example, the converted image data 276-1 whose rotation angle is 2 ° in the example of FIG. 26). Corresponding to) is stored in the frame memory.

  Next, the image processing circuit 273 converts the converted image data 276-2 generated second by the conversion circuit 281 (for example, in the example of FIG. 26, corresponds to the converted image data 276-2 having a rotation angle of 4 °). Is added to the first converted image data 276-1 in the frame memory to generate once processed image data 277-1. Here, the image processing circuit 273 stores the one-time processed image data 277-1 in the frame memory.

  Next, the image processing circuit 273 converts the converted image data 276-3 generated third by the conversion circuit 281 (for example, in the example of FIG. 26, corresponds to the converted image data 276-3 having a rotation angle of 6 °). Is added to the once processed image data 277-1 in the frame memory to generate twice processed image data 277-2. Here, the image processing circuit 273 stores the twice-processed image data 277-2 in the frame memory.

  After that, the image processing circuit 273 repeats the same operation, and the converted image data 276-N finally generated by the conversion circuit 281 (for example, the converted image data 276-180 whose rotation angle is 360 ° in the example of FIG. 26). Is added to (N-2) times processed image data 277- (N-2) in the frame memory to generate (N-1) times processed image data 277- (N-1). .. This (N-1) times processed image data 277- (N-1) becomes processed image data 277. The image processing circuit 273 stores the processed image data 277 in the frame memory. After that, the processed image data 277 in the frame memory is output from the frame memory to the SRAM 243 by DMA transfer under the control of the DMAC 252.

[Structure of image processing circuit]
FIG. 30 is a diagram showing the configuration of the image processing circuit 273. As shown in FIG. 30, the image processing circuit 273 includes a frame memory 309, a storage control unit 300, an addition processing unit 305, a write buffer 306, a read buffer 307, and an output control unit 308. The image processing circuit 273 in the present embodiment is hardware that operates without using software, unlike a configuration in which predetermined processing is performed by executing a program by a CPU, for example. Therefore, the storage control unit 300 can be called a storage control circuit, the addition processing unit 305 can be called an addition processing circuit, and the output control unit 308 can be called an output control circuit. The image processing circuit 273 is a kind of data processing device that processes image data.

  The frame memory 309 is a kind of storage circuit, and is composed of, for example, SRAM. The frame memory 309 can store image data for one frame (one image), for example. Further, the frame memory 309 may be configured to be able to store image data for a plurality of frames.

  The output control unit 308 inputs the data read from the frame memory 309, and further controls to output the data to the SRAM 243 (by DMA transfer). Also, the output control unit 308 can be configured to have, as operation modes, a DMA output mode in which input data is output by DMA transfer and a non-DMA output mode in which input data is output regardless of DMA transfer. .. In this embodiment, the output control unit 308 basically operates in the non-DMA output mode, and operates in the DMA output mode only when the output target data is read from the frame memory 309. As a result, the output target data read from the frame memory 309 is output from the output control unit 308 by DMA transfer.

  The storage control unit 300 controls the frame memory 309, the write buffer 306, the read buffer 307, and the output control unit 308. By the storage controller 300 controlling the frame memory 309, data is written in the frame memory 309 or data is read from the frame memory 309. The output control unit 308 controls the output by the DMA transfer of the data read from the frame memory 309 under the control of the storage control unit 300. The storage control unit 300 will be described in detail later.

  The addition processing unit 305 adds the converted image data generated by the conversion circuit 281 to the addition target image read from the frame memory 309 under the control of the storage control unit 300. For example, as shown in FIG. 29, the image to be added to the second post-conversion image data 276-2 becomes the first post-conversion image data 276-1, and the m-th (m is a variable, 3 ≦ m ≦. The image to be added to the converted image data 276-m of N) is (m-2) times processed image data 277- (m-2).

  Here, one of the two image data to be added is referred to as "first image data", and the other is referred to as "second image data". Then, each of the plurality of pixel data forming the first image data is referred to as “first pixel data”, and each of the plurality of pixel data forming the second image data is referred to as “second pixel data”.

  The addition processing unit 305, for each of the plurality of first pixel data forming the first image data, at the same position (coordinates) as the first pixel data in the first pixel data and the second image data. The first image data and the second image data are added by adding the two pixel data.

  In the present embodiment, the coordinate conversion circuit 272 outputs, for each pixel, a plurality of pixel data forming the image data of the converted image data 276, as described above. When the pixel data of the first converted image data 276 is input for one pixel, the addition processing unit 305 writes the input pixel data as it is in the write buffer 306 without performing the addition processing. The write buffer 306 can store pixel data for four pixels, for example. When the pixel data for four pixels is accumulated in the write buffer 306, the pixel data for four pixels in the write buffer 306 is written to the frame memory 309 at once by the control of the frame memory 309 by the storage controller 300. By repeating such a writing process, pixel data is repeatedly written in the frame memory 309 in units of four pixels.

  In the frame memory 309, pixel data for four pixels in the write buffer 306 is stored in the frame memory 309 and written in the storage area of the same address of the original image data read out. When the data in the write buffer 306 is written in the frame memory 309, the written data is erased from the write buffer 306. As described above, when the image data after the image processing is written in the frame memory 309, the image data is erased from the write buffer 306, and therefore, immediately after the image data is written, the write request output unit 302 outputs the image data. Requests become possible, and as a result, efficient writing of image data to the write buffer 306 is sequentially performed.

  By the control of the frame memory 309 by the storage controller 300, pixel data is read from the frame memory 309 in units of 4 pixels. That is, pixel data for four pixels is read from the frame memory 309 by one read access to the frame memory 309. Pixel data for four pixels read at once from the frame memory 309 is written in the read buffer 307.

  When the pixel data input from the coordinate conversion circuit 272 is the L-th (L is a variable, 2 ≦ L ≦ N) converted image data 276-L pixel data, the addition processing unit 305 outputs the read buffer 307. The pixel data to be added is read. Then, the addition processing unit 305 adds the input pixel data to the pixel data read from the read buffer 307. As a result, the addition processing unit 305 obtains (L-1) times processed image data 277- (L-1) pixel data.

  The addition processing unit 305 stores the pixel data of (L-1) times processed image data 277- (L-1) in the write buffer 306. The pixel data of the write buffer 306 is stored in the frame memory 309. The addition processing unit 305 performs similar processing each time pixel data is input from the coordinate conversion circuit 272. As a result, the image data of the processed image data 277 (that is, (N-1) times processed image data 277- (N-1)) is stored in the frame memory 309. When the data is read from the read buffer 307, the read data is erased from the read buffer 307. As described above, when the image data to be subjected to the image processing is read out for the image processing, the image data is erased from the read buffer 307. Therefore, immediately after the image data is read out, the first image data is read out. Requests can be made from the read request output unit 301, and as a result, efficient reading of image data to the read buffer 307 is sequentially performed.

  As described above, the addition processing unit 305 adds the pixel data of the L-th converted image data 276-L to the addition target pixel data in the read buffer 307, and performs (L-1) times processing. The pixel data of the image data 277- (L-1) is generated.

  For example, when the pixel data of the second converted image data 276-2 is input from the coordinate conversion circuit 272, the addition target pixel data of the input pixel data is the first converted image data 276-1. In, the pixel data at the same position as the input pixel data. When the pixel data of the third converted image data 276-3 is input from the coordinate conversion circuit 272, the pixel data to be added with respect to the input pixel data is the one-time processed image data 277-1. , The pixel data at the same position as the input pixel data. The pixel data to be added is stored in the read buffer 307 when the input pixel data is provided to the addition processing unit 305 under the control of the frame memory 309 by the storage control unit 300.

  In the present embodiment, the frame memory 309 is, for example, a 1-port memory. Therefore, data cannot be written to the frame memory 309 while the data is being read from the frame memory 309.

  Further, in the image processing circuit 273, read-modify-write is performed on the frame memory 309. For example, after the pixel data stored in the storage area at a certain address of the frame memory 309 is read from the frame memory 309, the addition processing unit 305 performs addition processing, and (L-1) times processed image data 277- (L-1) pixel data is generated and stored in the write buffer 306. After that, the pixel data thus added is written back from the write buffer 306 to the storage area of the same address of the frame memory 309.

  In other words, when the pixel data of the processed image data stored in the write buffer 306 is written in the frame memory 309, the pixel data of the processed image data is stored at the storage position of the frame memory 309 in which the pixel data to be added was stored. Is stored in the same position as.

  In this embodiment, pixel data for four pixels is read from the frame memory 309 at one time and stored in the read buffer 307. Further, the pixel data for four pixels of the write buffer 306 stored by the addition process is also written to the frame memory 309 at once.

  In the image processing circuit 273, the pixel data of four pixels stored in the storage area of a certain address of the frame memory 309 is read from the frame memory 309, temporarily stored in the read buffer 307, and then added. The addition processing is executed in the unit 305. Then, the pixel data of four pixels that have been subjected to the addition processing are temporarily stored in the write buffer 306 and then written back to the frame memory 309 (a storage area at the same address as the certain address).

  As described above, in this embodiment, the frame memory 309 is a one-port memory, and the read-modify-write is performed on the frame memory 309. Therefore, with such a configuration, the circuit scale of the frame memory 309 can be reduced, and as a result, the circuit scale of the image processing circuit 273 can be reduced.

  The final processed image data 277 stored in the frame memory 309 is output from the output control unit 308 to the SRAM 243 by DMA transfer. For example, when the pixel data of the processed image data 277 is read from the frame memory 309 by the control of the frame memory 309 by the storage control unit 300, the output control unit 308 outputs the read pixel data to the SRAM 243 by DMA transfer. To do. Since the pixel data for four pixels is read at once from the frame memory 309, the output control unit 308 outputs the processed image data 277 read from the frame memory 309 in units of four pixels. The pixel data of the processed image data 277 read from the frame memory 309 is not stored in the read buffer 307 due to the control of the read buffer 307 by the storage controller 300.

  When the DMAC 252 has a buffer, the DMAC 252 temporarily stores the pixel data input from the image processing circuit 273 in the buffer. The buffer can store pixel data for a plurality of pixels. When the buffer becomes full, the DMAC 252 controls to transfer the pixel data of a plurality of pixels in the buffer to the SRAM 243. As a result, the SRAM 243 stores the processed image data 277 generated by the image recognition accelerator circuit 249. In the DMAC 252, when the data in the buffer is transferred to the SRAM 243, the transferred data is erased from the buffer. The DMAC 252 can also be configured to transfer the data in the buffer to the SRAM 243 when the amount of data in the buffer exceeds a predetermined amount.

[Detailed Operation in Storage Control Unit of Image Processing Circuit]
The storage control unit 300 executes a first reading process of reading the pixel data of the addition target processed by the addition processing unit 305 from the frame memory 309. The storage control unit 300 also performs a writing process of writing the pixel data of the processed image data 277 generated by the addition processing unit 305 into the frame memory 309. It can be said that the pixel data of the processed image data 277 is the pixel data subjected to the addition processing by the addition processing unit 305. Then, the storage control unit 300 executes the second reading process of reading the pixel data of the processed image data 277, which is the final output target data, from the frame memory 309.

  The storage control unit 300 includes a first read request output unit 301, a write request output unit 302, a second read request output unit 303, and an arbitration unit 304.

  The first read request output unit 301 outputs a first read request that is a request to execute the first read process. The write request output unit 302 outputs a write request that is a write request execution request. The second read request output unit 303 outputs a second read request that is a request to execute the second read process.

  The output of the first read request by the first read request output unit 301 is, for example, to output a first read request signal indicating the first read request. The first read request signal includes the address of the storage area in the frame memory 309 where the pixel data to be read is stored.

  The output of the write request by the write request output unit 302 is, for example, to output a write request signal indicating the write request. The write request signal includes the address of the storage area in the frame memory 309 where the pixel data to be written is written.

  The output of the second read request by the second read request output unit 303 is to output the second read request signal indicating the second read request. The second read request signal includes the address of the storage area in the frame memory 309 where the pixel data to be read is stored.

  The first read request output unit 301, the write request output unit 302, and the second read request output unit 303 output the first read request, the write request, and the second read request, respectively, based on mutually independent criteria. To do.

  The first read request output unit 301 outputs a first read request (first read request signal) when the read buffer 307 is empty, for example. As described above, since the first read request output unit 301 outputs a request to read the image data to be image-processed from the frame memory 309 when the read buffer 307 is empty, the circuit scale of the read buffer 307 is reduced. Further, it is possible to reduce the size, and further, an independent effective criterion determines the timing of reading the image data.

  The write request output unit 302, when a predetermined amount of data is written in the write buffer 306 (for example, when it is full, that is, when the same amount of data as the capacity of the write buffer 306 is written), A write request (write request signal) is output. In this way, the write request output unit 302 outputs a request to write the image data after the image processing to the frame memory 309 from the write buffer 306 when the write buffer 306 is full, for example. The circuit scale of 306 can be reduced, and the write timing of the image data is determined by an independent and effective reference.

  The second read request output unit 303 reads the processed image data 277 stored in the frame memory 309 and transfers the data to the SRAM 243 under the control of the DMAC 252 at a predetermined timing (second read request (second read request)). Signal) is output.

  Further, when the DMAC 252 includes a buffer, the second read request output unit 303 outputs a second read request (second read request signal) based on, for example, the availability of the buffer of the DMAC 252. For example, the second read request output unit 303 outputs the second read request when the buffer is empty. Alternatively, the second read request output unit 303 outputs the second read request when the free space of the buffer is equal to or larger than a predetermined amount (for example, the data amount of pixel data of 4 pixels or more). In other words, the second read request output unit 303 outputs the second read request when the amount of data that can be stored in the buffer is equal to or larger than the predetermined amount.

  However, when the output target data, that is, the processed image data 277 is not stored in the frame memory 309, the storage control unit 300 cannot read the output target data from the frame memory 309. Therefore, the second read request output unit 303 outputs the second read request when the pixel data of the processed image data 277 is stored in the frame memory 309 for four pixels or more and the buffer is empty. To do. Alternatively, if the pixel data of the processed image data 277 is stored in four or more pixels in the frame memory 309 and the free space of the buffer is equal to or more than a predetermined amount, the second read request output unit 303 2 Output a read request.

  As described above, the first read request output unit 301, the write request output unit 302, and the second read request output unit 303 are based on the criteria independent of each other, and the first read request, the write request, and the second read request. Since each request is output, at least two requests of the first read request, the write request, and the second read request may conflict with each other. That is, a request may be simultaneously output from at least two of the first read request output unit 301, the write request output unit 302, and the second read request output unit 303.

  Therefore, the storage control unit 300 is provided with an arbitration unit 304 that arbitrates at least two competing requests when at least two of the first read request, the write request, and the second read request conflict. There is.

  If the first read request, the write request, and the second read request do not conflict with each other, the arbitration unit 304 performs processing on the frame memory 309 according to the input request. On the other hand, when at least two requests of the first read request, the write request, and the second read request conflict, the arbitration unit 304 arbitrates at least two conflicting requests, thereby arbitrating the two requests. Select one. Then, the arbitration unit 304 performs the process according to the selected request on the frame memory 309.

  In the present embodiment, in response to the first read request, the write request, and the second read request (or each of the first read request output unit 301, the write request output unit 302, and the second read request output unit 303). Process priority is assigned). For example, the first read request is assigned the highest priority, the write request is assigned the second highest priority, and the second read request is assigned the lowest priority. Then, the arbitration unit 304 arbitrates the request based on the priority of the conflicting request. The arbitration unit 304 selects the request having the highest priority from among the competing requests, and performs the process according to the selected request. Therefore, for example, when the three requests of the first read request, the write request, and the second read request compete with each other, the first read request is selected. If the two requests, the write request and the second read request, conflict with each other, the write request is selected.

  When performing processing according to the first read request, the arbitration unit 304 outputs the address included in the first read request signal input from the first read request output unit 301 and the read signal to the frame memory 309. To do. As a result, the pixel data of four pixels is read from the storage area of the address included in the first read request signal in the frame memory 309, and the read pixel data is written in the read buffer 307. When the arbitration unit 304 performs the processing in response to the first read request, the data read from the frame memory 309 is output from the output control unit 308 because the output control unit 308 operates in the non-DMA output mode. It is not output to the SRAM 243 or the like.

  When performing processing in response to a write request, the arbitration unit 304 reads out pixel data of four pixels from the write buffer 306 and outputs the pixel data to the frame memory 309, and at the same time, the writing input from the write request output unit 302. The address included in the add request signal and the write signal are output to the frame memory 309. As a result, the pixel data for four pixels output from the write buffer 306 is written to the storage area of the address included in the write request signal in the frame memory 309.

  When performing processing in response to the second read request, the arbitration unit 304 outputs the address included in the second read request signal input from the second read request output unit 303 and the read signal to the frame memory 309. At the same time, the operation mode of the output control unit 308 is changed from the non-DMA output mode to the DMA output mode. As a result, pixel data of four pixels is read from the storage area of the address included in the second read request signal in the frame memory 309, and the read pixel data of four pixels is output from the output controller 308 to the DMAC 252. Is output to the SRAM 243 under the control of.

  In the above example, the processing time in the coordinate conversion circuit 272 is relatively long, and the pixel data of the converted image data 276 cannot be immediately obtained in the coordinate conversion circuit 272. As a result, the pixel data of the processed image data 277 is obtained. In order to improve the processing speed of the entire control LSI 234, the priority of the first read request and the write request necessary for generating the pixel data of the processed image data 277 is set to the second priority. It is set higher than the priority of the read request. However, the method of assigning the priority to the first read request, the write request, and the second read request is not limited to this.

  For example, when the processed image data 277 of the frame memory 309 is DMA-transferred to the SRAM 243 under the control of the DMAC 252, the bus usage rate of the control LSI 234 is always high, and it is difficult to transfer the data to the SRAM 243. When the transfer rate of the processed image data 277 does not increase, the output target data (pixel data of the processed image data 277) is likely to be accumulated in the frame memory 309. In this case, if the priority of the first read request and the write request is made higher than the priority of the second read request, the processed image data 277 stored in the frame memory 309 will not be output from the image processing circuit 273 forever. there is a possibility. Therefore, in such a case, the priority of the second read request for reading the processed image data 277 from the frame memory 309 is set higher than the priority of the first read request and the write request. The processing speed of the entire control LSI 234 can be improved.

  Further, for example, when the DMAC 252 includes a buffer, the bus utilization rate of the control LSI 234 is always high, it is difficult to transfer data from the DMAC 252 to the SRAM 243, and as a result, the buffer of the DMAC 252 is unlikely to have a vacancy. Indicates that the output target data (pixel data of the processed image data 277) is likely to be accumulated in the frame memory 309. In this case, if the priority of the first read request and the write request is made higher than the priority of the second read request, the processed image data 277 stored in the frame memory 309 will not be output from the image processing circuit 273 forever. there is a possibility. Therefore, in such a case, the priority of the second read request for reading the processed image data 277 from the frame memory 309 is set higher than the priority of the first read request and the write request. The processing speed of the entire control LSI 234 can be improved.

  In this way, in the storage control unit 300, when at least two requests of the first read request, the write request, and the second read request conflict, the at least two requests are arbitrated. Therefore, the first read request output unit 301, the write request output unit 302, and the second read request output unit 303 can operate independently of each other. Therefore, it is possible to prevent a process at a specific output unit of the first read request output unit 301, the write request output unit 302, and the second read request output unit 303 from becoming a bottleneck. As a result, the processing speed of the entire control LSI 234 can be improved.

  The processing priority can be changed. For example, the control LSI 234 may be configured such that the processing priority can be changed by a user operation or automatically. Further, the image processing circuit 273 may change the processing priority according to the operation status of the control LSI 234. For example, a bus usage rate calculating circuit for obtaining a bus usage rate is provided in the control LSI 234, and the image processing circuit 273 changes the processing priority based on the bus usage rate obtained by the bus usage rate calculating circuit. You may comprise. Specifically, when the bus usage rate is higher than a predetermined value, the priority of the second read request is set higher than the priority of the first read request and the write request, and the bus usage rate is increased. When the value is equal to or smaller than the predetermined value, the priority of the first read request and the write request is set higher than that of the second read request. By dynamically changing the processing priority in this way, the processing speed of the entire image processing circuit 273 can be further improved.

[Flow of Regular Medal Discrimination Processing by Control LSI 234]
Next, with reference to FIG. 31 to FIG. 33, a process performed by the control LSI 234 for determining whether the object moving on the medal rail 210 is a regular medal (hereinafter, referred to as “regular medal discrimination process”) There is)).

  31 and 32 are diagrams for explaining the regular medal determination process of the control LSI 234. FIG. 31 and FIG. 32 show the processing relationship in each device constituting the control LSI 234 in a time series manner. The relatively thick line portion of the vertical line extending below each device name indicates that device. This indicates that the various processes described above are being performed. Further, a dashed arrow extending from a line corresponding to each device to a vertical line extending below “IN” in the host controller indicates an interrupt signal output from each device to the host controller 241.

  In addition, a dashed arrow extending from a vertical line extending below “OUT” in the host controller toward a line corresponding to each device indicates a signal output from the host controller 241 to each device. In addition, a solid line arrow between a vertical line extending below “IN” and a vertical line extending below “OUT” in the host controller indicates from the interrupt signal detected by the host controller 241 and the host controller 241. The correspondence with the output signal is shown.

  Note that FIG. 31 shows the regular medal discrimination processing when six medals are continuously inserted into the medal insertion slot 21 (see FIG. 2), and the discrimination processing regarding the first medal is extracted and shown. Shows the entire regular medal discrimination process (including the discrimination process for the first medal) when six medals are continuously inserted. In addition, in order to clarify what number of medals is related to the signal, a number indicating the order of inserting the medals is added to the head of the code attached to each signal. For example, a VSYNC interrupt signal output to the host controller 241 from the ISP circuit 245, which will be described later, for the first medal is denoted by "1IH", and the same VSYNC interrupt for the second medal is added. The signal is labeled with "2IH".

  First, when the CMOS image sensor 232 (see FIG. 17) images an object (the first medal in this example) moving on the medal rail 210 and outputs the image data to the control LSI 234, the ISP circuit 245 causes the ISI circuit to operate. Image data is acquired (received) via 251 and a VSYNC (Vertical Synchronization) interrupt signal is output to the host controller 241 (1IH). The ISP circuit 245 also performs conversion processing for converting the RGB Bayer image into various formats. Then, the converted image data and the hue, saturation, and luminance data related to the image data are output to the SRAM 243, the medal count circuit 246, and the color recognition circuit 247. The detailed description of the conversion process has been described above, and will be omitted.

  Upon receiving data from the ISP circuit 245, the color recognition circuit 247 performs color determination processing, stores the determination result in the SRAM 243, and outputs a color determination interrupt signal to the host controller 241 (1CH). The detailed description of the color determination process has been described above, and will be omitted.

  Upon receiving the data from the ISP circuit 245, the medal count circuit 246 performs a count process, stores the determination result in the SRAM 243, and outputs a medal count interrupt signal to the host controller 241 (1 MH). The detailed description of the counting process is omitted because it has been described above.

  When detecting the color determination interrupt signal, the host controller 241 acquires the determination result of the color determination processing from the SRAM 243 and outputs it to the allocation PORT of the GPIO 250 (1HG1). That is, the host controller 241 outputs the determination result of the color determination process to the main control board 71 (main control circuit 91) via the GPIO 250.

  When detecting the count interrupt signal, the host controller 241 acquires the determination result of the count processing from the SRAM 243 and outputs it to the allocation PORT of the GPIO 250 (1HG2). That is, the host controller 241 outputs the determination result of the count process to the main control board 71 (main control circuit 91) via the GPIO 250. When the determination result of the counting process is “a medal has passed”, the main control circuit 91 sets the value of the inserted number counter, which is a counter provided for the main CPU 93 to count the number of inserted medals. Add one. When the value of the inserted number counter is the maximum value (for example, 3), 1 is added to the value of the credit counter which is a counter provided for the main CPU 93 to count the number of credited medals. When the credit counter has the maximum value (for example, 50), the main control circuit 91 sets the medal solenoid 208 of the medal selector 201 to the OFF state. As a result, the select plate 207 is positioned at the “discharging position” and the medals inserted after the credit counter reaches the maximum value are guided to the medal chute 202 and ejected from the medal payout opening 32 to the medal tray unit 34. In the present embodiment, when the start lever is operated when the value of the thrown-in number counter is a prescribed value (for example, 2 or 3), the main CPU 93 performs the above-mentioned internal lottery process.

  The fish-eye correction scaler circuit 248 performs fish-eye correction processing when the image data converted by the ISP circuit 245 is stored in the SRAM 243, stores the reduced image data created in the SRAM 243, and also causes the host controller 241 to perform the reduction end allocation. Sending an embedded signal (1SH). The detailed description of the fish-eye correction process is omitted because it has been described above.

  When the host controller 241 detects the reduction end interrupt signal, it refers to the SRAM 243 and the determination result of the count process is “a medal has passed”, and the determination result of the color determination process is “match with the color of the regular medal”. On condition that "Yes", the image recognition DSP circuit 242 is instructed to start the preprocessing (1HD).

  The image recognition DSP circuit 242 performs preprocessing according to an instruction from the host controller 241, stores the edge image data in the SRAM 243, and outputs a preprocessing end interrupt signal to the host controller 241 (1DH1). The detailed description of the preprocessing is omitted because it has been described above. Further, the image recognition DSP circuit 242 of the present embodiment acquires the reduced image data from the SRAM 243 by DMA transfer, and further stores the edge image data generated as a result of the preprocessing in the SRAM 243 by DMA transfer. The processing time of the preprocessing is shortened as compared with the same circuit that does not use the DMA transfer.

  When the host controller 241 detects the preprocessing completion interrupt signal, the host controller 241 instructs the image recognition accelerator circuit 249 to start image processing (for example, rotation integration processing here) (1HA).

  The image recognition accelerator circuit 249 performs image processing according to an instruction from the host controller 241, stores the processed image data in the SRAM 243, and outputs an image processing end interrupt signal to the image recognition DSP circuit 242 (1AD). The detailed description of the rotation integration processing, which is an example of the image processing, has been described above, and will be omitted. Further, since the image recognition accelerator circuit 249 of the present embodiment acquires edge image data from the SRAM 243 by DMA transfer and stores the generated processed image data in the SRAM 243 by DMA transfer, such a DMA transfer is not used. The processing time of the image processing is shortened as compared with the circuit.

  When the image recognition DSP circuit 242 detects the image processing end interrupt signal, the image recognition DSP circuit 242 acquires the processed image data stored in the SRAM 243, performs the marking determination process, and stores the determination result in the SRAM 243. Then, the image recognition DSP circuit 242 outputs a marking determination end interrupt signal to the host controller 241 (1DH2). Further, since the image recognition DSP circuit 242 of the present embodiment acquires the processed image data created by the image processing from the SRAM 243 by, for example, DMA transfer, the marking judgment is performed as compared with the circuit which does not use such DMA transfer. The processing time of processing is shortened.

  When the host controller 241 detects the marking determination end interrupt signal, the host controller 241 acquires the determination result of the marking determination processing stored in the SRAM 243 and outputs it to the GPIO allocation PORT (1HG3). That is, the host controller 241 outputs the determination result of the marking determination process to the main control board 71 (main control circuit 91) via the GPIO 250.

  As shown in FIG. 31, in the present embodiment, the preprocessing and marking determination processing by the image recognition DSP circuit 242 and the image processing by the image recognition accelerator circuit 249 are shortened in time by the DMA transfer as described above. However, it takes a relatively long time. Therefore, when medals are continuously inserted, when the host controller 241 detects the reduction end interrupt signal (1SH or the like), the image recognition DSP circuit 242 or the image recognition accelerator circuit 249 is processing ( It is checked whether or not it is in a busy state), and if neither is in process, control is performed so as to instruct the image recognition DSP circuit 242 to perform preprocessing and marking determination processing, and the image recognition accelerator circuit 249 to start image processing.

  Next, with reference to FIG. 32, the entire regular medal determination process when six medals are continuously inserted will be described. FIG. 32 includes all the determination processing regarding the first medal shown in FIG.

  In the example shown in FIG. 32, since the regular medal determination process is continuously performed for medals that are continuously inserted, the reduction end interrupt signals (2SH and 4SH) related to the second and fourth medals are sent to the host. When the controller 241 detects, the image recognition DSP circuit 242 or the image recognition accelerator circuit 249 is in processing (busy state), so the host controller 241 instructs the start of the above-described image processing (preprocessing, image processing, and Do not give an instruction to start the marking determination process). Therefore, for the second and fourth medals, the count process, the color determination process, and the fisheye correction process are performed, but the preprocessing, the image processing, and the marking determination process are not performed. On the other hand, when the host controller 241 detects the reduction end interrupt signal (3SH) related to the third medal, the image recognition DSP circuit 242 and the image recognition accelerator circuit 249 are not in process (busy state). Therefore, for the third medal, preprocessing, image processing, and marking determination processing are performed in addition to the count processing, color determination processing, and fisheye correction processing.

  Further, here, between the output of the determination result of the count processing by the host controller 241 to the GPIO 250 (1HG2) and the transmission of the preprocessing end interrupt signal by the image recognition DSP circuit 242 (1DH1), the ISP circuit 245 is used. The output (2IH) of the VSYNC interrupt signal relating to the second medal is generated. However, since the storage area of the SRAM 243 for storing the determination result of various processes (count process, color determination process, marking determination process, etc.) related to each medal is individually set, data overwriting does not occur. .. Such a situation also applies to the processing of the third and subsequent medals.

  The pre-processing and the marking determination processing by the image recognition DSP circuit 242 and the image processing by the image recognition accelerator circuit 249 are accelerated to make the counting processing, the color determination processing, and the marking determination processing for all the inserted medals. May be performed.

  Various signals relating to the second, third, fourth, fifth, and sixth medals shown in FIG. 32 (the reference numerals start with "2", "3", "4", "5") , Each signal of "6") is the same as the above-mentioned various signals (the reference numeral is "1") related to the first medal which is different only in the number at the beginning, and detailed description thereof will be omitted. Note that the processing timing of each device in the regular medal discrimination processing of the control LSI 234 shown in FIG. 32 is merely an example. The regular medal determination process may be performed at various processing timings depending on the processing capability of each device, the processing content, and the processing procedure.

  Next, the flow of image processing by the image recognition accelerator circuit 249 will be described in more detail with reference to FIG.

  FIG. 33 is a diagram showing an operation flow of the host controller 241 and the image recognition accelerator circuit 249, and basically corresponds to a part of the processing of FIG. 32 described above. First, when the power of the pachi-slot 1 is turned on (not shown in FIG. 32), the host controller 241 initializes each circuit including the image recognition accelerator circuit 249 (step S0).

  The image recognition accelerator circuit 249 is provided with various setting registers (not shown). In the initial setting, the host controller 241 sets data in various setting registers of the image recognition accelerator circuit 249. For example, the host controller 241 sets the address of the storage area on the SRAM 243 in which the target image data 275 is stored in the first setting register, or the SRAM 243 that is the write destination of the processed image data 277 obtained by the image recognition accelerator circuit 249. The address of the storage area is set in the second setting register, and the image size of the target image data 275 processed by the image recognition accelerator circuit 249 is set in the third setting register.

  Further, in the initial setting of the image recognition accelerator circuit 249, the host controller 241 sets the conversion parameter 280 in the memory 274 of the image recognition accelerator circuit 249. The host controller 241 reads the conversion parameters 280 from the SRAM 243, for example, and writes these conversion parameters 280 in the memory 274. Note that the host controller 241 may create the conversion parameter 280 at the time of initial setting and write the conversion parameter 280 thus created in the memory 274 of the image recognition accelerator circuit 249.

  After the initialization is completed, the host controller 241 instructs the image recognition accelerator circuit 249 to start the image processing on the first target image data 275 (step S1). By this instruction, the signal (1HA) shown in FIG. 32 is transmitted to the image recognition accelerator circuit 249. Here, the host controller 241 sets the specific information 290 used in the image processing regarding the first target image data 275 in the register 283 included in the control circuit 282 of the image recognition accelerator circuit 249.

  When the specific information 290 is set in the register 283, the image recognition accelerator circuit 249, based on the control of the DMAC 252, the first target image data 275 from the address (address of the SRAM 243) set in the above-mentioned first setting register. Is read by DMA transfer and written in the input frame buffer 271 (step S1-1). The coordinate conversion circuit 272 reads the conversion parameter 280 to be used first from the memory 274 based on the specific information 290 in the register 283, and the target image data 275 stored in the input frame buffer 271 based on the read conversion parameter 280. Then, the first coordinate conversion is performed (step S1-1). As a result, the first converted image data 276-1 is obtained. The first converted image data 276-1 is stored in the frame memory 309 of the image processing circuit 273.

  When the coordinate conversion circuit 272 generates the first converted image data 276-1, the coordinate conversion circuit 272 reads the conversion parameter 280 to be used second from the memory 274 based on the specific information 290, and inputs it based on the read conversion parameter 280. The target image data 275 stored in the frame buffer 271 is subjected to the second coordinate conversion (step S1-2). As a result, the second converted image data 276-2 is obtained. On the other hand, the image processing circuit 273 performs image processing of adding the second converted image data 276-2 to the first converted image data 276-1 to generate the once processed image data 277-1. Yes (step S1-2).

  Here, the coordinate conversion circuit 272 outputs the generated pixel data to the image processing circuit 273 every time the pixel data of the converted image data 276 is generated. Further, when the pixel data is input from the coordinate conversion circuit 272, the image processing circuit 273 adds the input pixel data to the pixel data of the addition target read from the read buffer 307. Therefore, the image recognition accelerator circuit 249 does not generate the processed image data 277-1 once after the converted image data 276-2 is generated but the converted image data 276− in the coordinate conversion circuit 272. The second generation process and the one-time processed image data 277-1 generation process in the image processing circuit 273 are executed in parallel.

  When generating the second converted image data 276-2, the coordinate conversion circuit 272 reads the conversion parameter 280 to be used third from the memory 274 based on the specific information 290, and based on the read conversion parameter 280, The target image data 275 stored in the input frame buffer 271 is subjected to the third coordinate conversion. As a result, the third converted image data 276-3 is obtained. On the other hand, the image processing circuit 273 performs image processing for adding the third converted image data 276-3 to the one-time processed image data 277-1 to generate the twice-processed image data 277-2. ..

  After that, the image recognition accelerator circuit 249 operates in the same manner, and the coordinate conversion circuit 272 generates the Nth converted image data 276-N (step S1-N). On the other hand, the image processing circuit 273 performs the image processing of adding the N-th converted image data 276-N to the (N-2) times processed image data 277- (N-2), and (N- 1) Time processed image data 277- (N-1), that is, processed image data 277 is generated (step S1-N). After that, the image processing circuit 273 outputs the processed image data 277 to the SRAM 243 under the control of the DMAC 252 (step S1-N).

  The processed image data 277 is written in the storage area of the address set in the above-mentioned second setting register (step S1-N). As described above, since the first read request output unit 301, the write request output unit 302, and the second read request output unit 303 operate independently of each other, the addition processing unit 305 performs addition in the image processing circuit 273. The process and the output process of the output control unit 308 are executed in parallel. Therefore, the image processing circuit 273 does not output the pixel data of the processed image data 277 after all the pixel data forming the processed image data 277 are generated, but generates the pixel data of the processed image data 277. Then, the output processing of the pixel data of the processed image data 277 is executed in parallel.

  When the image recognition accelerator circuit 249 finishes writing the processed image data 277 to the SRAM 243, the image recognition accelerator circuit 249 notifies the host controller 241 that the image processing for the first target image data 275 is completed (step S1). -E). For the completion notification from the image recognition accelerator circuit 249 to the host controller 241, for example, the interrupt function of the host controller 241 is used.

  Upon receipt of the completion notification, the host controller 241 gives an instruction regarding the second target image data 275 to the image recognition accelerator circuit 249 (step S2). Specifically, the host controller 241 sets the specific information 290 used in the process for the second target image data 275 in the register 283 included in the control circuit 282 of the image recognition accelerator circuit 249. The image recognition accelerator circuit 249 operates similarly to the processing for the first target image data 275, generates the processed image data 277 based on the second target image data 275, and writes the processed image data 277 in the SRAM 243. After that, the image recognition accelerator circuit 249 performs the same processing on the third and subsequent target image data 275.

  The identification information 290 used in the process on the p-th (p is a variable, p ≧ 2) target image data 275 is the identification information used in the process on the (p−1) -th target image data 275. When the information is the same as the information 290, the host controller 241 that has received the completion notification regarding the (p−1) th target image data 275 registers the specific information 290 used in the processing for the pth target image data 275. The image recognition accelerator circuit 249 may be instructed to start processing on the p-th target image data 275 without setting it to 283.

  In the present embodiment, as shown in FIGS. 31 and 32, when the image recognition accelerator circuit 249 completes the image processing for one target image data 275, the image recognition DSP circuit 242 receives the image processing end interrupt signal. When the image recognition DSP circuit 242 outputs (1AD or the like) and detects the image processing end interrupt signal, it acquires the processed image data 277 stored in the SRAM 243 and then performs the marking determination process. However, in the example shown in FIG. 33, this processing is different. That is, when the image recognition accelerator circuit 249 finishes the image processing, the host controller 241 is configured to notify the completion (step S1-e). As described above, when the image recognition accelerator circuit 249 finishes the image processing for one target image data 275, the next processing may be started by various operation patterns.

  As described above, the coordinate conversion circuit 272 continuously performs a plurality of coordinate conversions using one target image data 275 based on the plurality of conversion parameters 280. That is, the coordinate conversion circuit 272 generates a plurality of converted image data 276 from one target image data 275 based on the plurality of conversion parameters 280 without exchanging data with the host controller 241. Therefore, it is possible to reduce the processing time for a plurality of coordinate conversions, as compared with the case where the coordinate conversion circuit 272 receives the conversion parameter 280 used in the coordinate conversion each time the coordinate conversion is performed from the host controller 241.

  In addition, the coordinate conversion circuit 272 generates a plurality of converted image data 276 from one target image data 275 based on the plurality of conversion parameters 280 without exchanging data with the host controller 241, so that the host controller The processing load of 241 can be reduced. Further, as in the present embodiment, when the host controller 241 and the image recognition accelerator circuit 249 are connected by a bus, it becomes possible to secure a larger band for the bus.

  Furthermore, in the present embodiment, when the image recognition accelerator circuit 249 is initialized, the host controller 241 sets the conversion parameter 280 in the memory 274 of the image recognition accelerator circuit 249. Therefore, the coordinate conversion circuit 272 is initialized. After that, the conversion parameter 280 can be read from the memory 274. Therefore, the coordinate conversion circuit 272 does not need to receive the conversion parameter 280 to be used from the host controller 241 every time the conversion parameter 280 is used, and therefore the processing time in the coordinate conversion circuit 272 can be shortened. ..

  The SRAM 243 may include only the conversion parameter 280 used by the image recognition accelerator circuit 249 of the control LSI 234. For example, when the coordinate conversion circuit 272 performs coordinate conversion for rotating any 2 ° to 360 ° from 2 ° to any target image data 275, only the conversion parameter 280 having an even rotation angle is stored. Can be configured as. Further, at this time, the SRAM 243 stores the conversion parameters 280 regarding all the rotation angles, and the conversion parameters 280 that are actually used when the image recognition accelerator circuit 249 is initialized (that is, the conversion parameters 280 having an even rotation angle). ) May be stored in the memory 274.

  Furthermore, a common conversion parameter 280 may be stored in each of the plurality of image recognition accelerator circuits 249 that perform different coordinate conversions on the target image data 275. For example, the first image recognition accelerator circuit 249 performs a process of rotating the target image data 275 by 1 ° from 1 ° to 90 °, and the second image recognition accelerator circuit 249 converts the target image data 275 from 91 ° to 180 °. The third image recognition accelerator circuit 249 performs the process of rotating the target image 110 by 1 ° from 181 ° to 270 °, and the fourth image recognition accelerator circuit 249 When the processing of rotating the target image data 275 by 1 ° from 271 ° to 360 ° is performed, the same conversion parameter 280 (that is, the above-mentioned example and the same) is applied to each of the first to fourth image recognition accelerator circuits 249. Similarly, 360 kinds of conversion parameters 280 for rotating the target image data 275 from 1 ° to 360 °) Memorize As a result, it is not necessary to individually prepare the conversion parameter 280 for each image recognition accelerator circuit 249, and thus it is possible to prevent the wrong conversion parameter 280 from being stored.

  Although the example in which the common conversion parameter 280 is stored in the plurality of image recognition accelerator circuits 249 is shown here, the same applies to the plurality of control LSIs 234 and the medal selectors 201 (having different specifications) incorporated in the pachi-slot 1. , A common conversion parameter 280 can be stored.

  Further, in the above example, the image processing circuit 273 outputs the processed image data 277 under the control of the DMAC 252, but the converted image data 276 obtained by the coordinate conversion circuit 272 may be output. In this case, the image processing circuit 273 does not require the addition processing unit 305, the read buffer 307, and the first read request output unit 301. Then, the pixel data of the converted image data 276 output from the coordinate conversion circuit 272 is temporarily stored in the write buffer 306, and the pixel data of the converted image data 276 stored in the write buffer 306 is written in the frame memory 309. .. The pixel data stored in the frame memory 309 is output (DMA transferred) from the output control unit 308 to the SRAM 243 under the control of the DMAC 252.

  Further, the conversion parameter 280 may be configured to include a conversion parameter for instructing coordinate conversion other than rotation instead of the parameter for specifying the rotation angle or in addition to the parameter for specifying the rotation angle.

  For example, the conversion parameter 280 may include a conversion parameter for enlargement necessary for coordinate conversion for enlarging an image. In this case, the conversion parameter 280 may include a plurality of conversion parameters 280 required for a plurality of coordinate conversions having different enlargement ratios. The coordinate conversion circuit 272 performs coordinate conversion on the target image data 275 based on the conversion parameter 280 relating to such image enlargement, thereby expanding the target image data 275 at an enlargement ratio according to the conversion parameter 280. You can

  For example, the coordinate conversion circuit 272 performs coordinate conversion on the target image data 275 based on the conversion parameter 280 that instructs to enlarge the image at the enlargement ratio of 1.1 times, thereby expanding the image to 1.1 times. The converted image data 276 is obtained. Here, enlargement of the image is enlargement of the image (subject) represented by the target image data 275, and does not increase the number of pixels in the vertical and horizontal directions of the image.

  When the conversion parameter 280 includes a conversion parameter related to image rotation and a conversion parameter related to image enlargement, the coordinate conversion circuit 272 expands the rotated image obtained by rotating the target image data 275 and the target image data 275. The enlarged image obtained by doing so can be generated as the converted image data 276. Similar to the conversion parameter 280 regarding the rotation of the image, the conversion parameter 280 regarding the enlargement of the image includes, for example, the coordinates of the four pixels in the target image data 275 (that is, the mapping source The coordinates of four pixels) are included.

  Further, the conversion parameter 280 may include a conversion parameter for reduction necessary for coordinate conversion for reducing the image. In this case, the conversion parameter 280 may include a plurality of conversion parameters 280 required for a plurality of coordinate conversions having different reduction rates. The coordinate conversion circuit 272 reduces the target image data 275 at a reduction rate according to the conversion parameter 280 by performing coordinate conversion on the target image data 275 based on the conversion parameter 280 relating to such image reduction. You can

  For example, the coordinate conversion circuit 272 performs the coordinate conversion on the target image data 275 based on the conversion parameter 280 instructing the reduction of the image with the reduction ratio of 0.9 times, thereby reducing the size to 0.9 times. The converted image data 276 is obtained. Here, the reduction of the image is reduction of the image (subject) represented by the target image data 275 and does not reduce the number of vertical and horizontal pixels of the image.

  When the conversion parameter 280 includes the conversion parameter regarding the rotation of the image and the conversion parameter 280 regarding the reduction of the image, the coordinate conversion circuit 272 outputs the rotated image obtained by rotating the target image data 275 and the target image data 275. A reduced image obtained by reduction can be generated as the converted image data 276. Similar to the conversion parameter 280 regarding the rotation of the image, the conversion parameter 280 regarding the reduction of the image includes, for example, the coordinates of four pixels in the target image data 275 (that is, the mapping source The coordinates of four pixels) are included.

  Furthermore, the conversion parameter 280 may include a conversion parameter necessary for coordinate conversion for performing parallel movement of the image. In this case, the conversion parameter 280 may include a plurality of conversion parameters 280 required for a plurality of coordinate conversions having different moving directions. Further, the conversion parameter 280 may include a plurality of conversion parameters which are respectively required in a plurality of coordinate conversions in which the amounts of parallel movement are different from each other.

  The coordinate conversion circuit 272 moves the target image data 275 in the moving direction according to the conversion parameter 280 by performing coordinate conversion on the target image data 275 based on the conversion parameter 280 relating to such parallel movement. Further, when the conversion parameter 280 specifies the parallel movement amount, the target image data 275 can be moved in parallel by the designated movement amount.

  For example, the coordinate conversion circuit 272 may perform coordinate conversion on the target image data 275 based on a conversion parameter 280 that instructs parallel movement in which the movement direction is “right” and the movement amount is “1 pixel”. As a result, the converted image data 276 which is translated by one pixel to the right is obtained. Here, the parallel movement of the image is the parallel movement of the image (subject) represented by the target image data 275.

  When the conversion parameter 280 includes a conversion parameter related to image rotation and a conversion parameter 280 related to image translation, the coordinate conversion circuit 272 causes the rotated image obtained by rotating the target image data 275 and the target image data 275. It is possible to generate a translated image obtained by translating the image as the converted image data 276. Similar to the conversion parameter 280 regarding the rotation of the image, the conversion parameter 280 regarding the parallel movement includes, for example, the coordinates of four pixels in the target image data 275 (that is, the mapping source The coordinates of four pixels) are included.

[Detection of illegal medals]
In the gaming machine (pachi-slot 1) according to the present embodiment, the control LSI 234 of the medal selector 201 performs regular medal discrimination processing including color determination processing, count processing, and marking determination processing. When an unauthorized device that is not a medal moves on the medal rail 210, it is determined that the color does not match the color of the regular medal in the color determination process, and that the medal has not passed in the counting process. Therefore, it is possible to misidentify that a regular medal is used for the pachi-slot 1 and detect an illegal act of playing a game.

  In addition, an illegal medal 310 (a medal having the same diameter and the same color as the regular medal 400 (see FIG. 19A) but having a different engraved mark (pattern) on the surface of the medal) shown in FIG. 34A moves on the medal rail 210. In this case, in the color determination process, it is determined that the color matches the color of the regular medal. However, in the counting process, the marking (pattern) in the count area (the area 313 surrounded by the dotted line) of the image data 312 of the illegal medal shown in FIG. 34B and the count area of the image data of the regular medal (the dotted line in FIG. 19B). Since the engraving (pattern) in the enclosed area 403) is significantly different, it is determined that “the medal has not passed”. Therefore, it is possible to misidentify that a regular medal is used for the pachi-slot 1 and detect an illegal act of playing a game.

  In addition, an illegal medal 315 (another medal having the same diameter and the same color as the regular medal 400 (see FIG. 19A) but different only in the inscription (pattern) on the surface of the medal) on the medal rail 210 is shown in FIG. 35A. When moved, it is determined in the color determination process that the color matches the color of the regular medal. Further, in the counting process, the marking (pattern) in the count area (the area 318 surrounded by the dotted line) of the illegal medal image data 317 shown in FIG. 35B and the count area of the image data of the regular medal (the dotted line in FIG. 19B). Since the difference between the engraved mark (pattern) in the enclosed area 403) is small, it is determined that the medal has passed. However, in the marking determination process, the processed image data 319 of the illegal medal shown in FIG. 35C and the processed image data 405 of the regular medal 400 (see FIG. 20) are significantly different from each other. It does not match the stamp ”. Therefore, it is possible to misidentify that a regular medal is used for the pachi-slot 1 and detect an illegal act of playing a game.

  Further, on the medal rail 210, a regular medal 400 (see FIG. 19A), a different diameter (a diameter slightly smaller or larger than the regular medal diameter, and a diameter that can be guided by the select plate 207) and a medal of the same color have moved. In this case, in the color determination process, it is determined that the color matches the color of the regular medal. However, in the image data of this medal, if this medal is slightly smaller than the diameter of the regular medal and there is a boundary between the outer edge of the medal and the background in the count area, "the medal has not passed" in the counting process. Is determined. Further, even if it is determined in the counting process that a medal has passed, the processed image data of this medal and the processed image data 405 of the regular medal 400 (see FIG. 20) are determined from the difference in diameter between this medal and the regular medal 400. ) Will be very different. Therefore, in the marking determination process, it is determined that "the marking (pattern) of the medal does not match the marking of the regular medal". Therefore, it is possible to misidentify that a regular medal is used for the pachi-slot 1 and detect an illegal act of playing a game.

  Further, when a medal having the same diameter and different color as the regular medal 400 (see FIG. 19A) moves on the medal rail 210, it is determined in the color determination process that the color does not match the regular medal color. Therefore, it is possible to misidentify that a regular medal is used for the pachi-slot 1 and detect an illegal act of playing a game.

  Further, the control LSI 234 outputs the determination results of the color determination processing, the count processing, and the marking determination processing to the main control circuit 91 composed of the main control board 71 via GPIO. Therefore, it is possible to cause the main control circuit 91 to perform various kinds of processing when there is an illegal act. Here, the various processes in the case of the illegal activity include, for example, forcibly interrupting the game by the main control circuit 91 and notifying that the illegal activity has been performed via the sub control circuit 101 (for example, , Processing for displaying that the fraudulent activity has occurred on the liquid crystal display device 11).

  Further, when the misconduct is detected by the determination result of the color determination process and the count process, the main control circuit 91 may set the medal solenoid 208 of the medal selector 201 to the OFF state. As a result, the select plate 207 is positioned at the "discharging position", so that the illegal medal can be guided to the medal chute 202 and ejected from the medal payout opening 32. Note that the main control circuit 91 sets the medal solenoid 208, which has been set to the OFF state by detecting the fraudulent activity by the color determination processing and the count processing, to the ON state after guiding the fraudulent medal related to this fraudulent activity to the medal chute 202. May be.

  Further, even when an improper act is detected by the marking determination process, the main control circuit 91 may set the medal solenoid 208 of the medal selector 201 to the OFF state. In this embodiment, as shown in FIG. 32, after the VSYNC interrupt signal (3IH) for the third medal is output from the ISP circuit 245 to the main control circuit 91, the VSYNC interrupt for the fourth medal is output. By the time the signal (4IH) is output, the determination result of the marking determination process for the first medal is output to the main control circuit (1HG3). Therefore, when illegal medals are continuously inserted, the illegal medals inserted after the fourth coin can be guided to the medal chute 202 and ejected from the medal payout opening 32.

  As a result, it is possible to suppress the spread of damage caused by fraudulent acts. In addition, by increasing the speed of the marking determination processing, if the fraudulent activity can be detected by the marking determination processing before the medal imaged by the camera unit 209 passes over the after-medal pressure 218 or the medal stopper 227. By immediately setting the medal solenoid 208 to the OFF state by the main control circuit 91, it is possible to prevent the damage caused by the fraudulent act. Further, the main control circuit 91 sets the medal solenoid 208, which has been set to the OFF state by detecting fraudulent activity by the marking determination processing, to the following determination result of the marking determination processing, "the marking of the medal (pattern) matches the marking of the regular medal." If “Yes”, it may be set to the ON state. As a result, since the illegal medals were accidentally mixed in, when the player unintentionally inserts the illegal medals and the medal solenoid 208 is set to the OFF state and becomes unplayable, the player is authorized. If you insert a medal, you can restart the game.

  Heretofore, the gaming machine according to the embodiment of the present invention has been described, including its effects. However, the game machine of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention described in the claims.

  For example, in the above description, an example in which medals having the same marking (pattern) on both sides are used as the game medium has been described, but instead of this, different markings may be provided on one side and the other side of the medal. A given medal may be used. In this case, data relating to each side of the medal may be prepared in advance as data relating to the threshold value in the counting process, the color determining process, and the marking determining process.

  Further, as a method of setting the data related to the threshold value, a fixed unit game period (for example, 100 games) is set as a collection period of the data related to the threshold value, and an image is taken by the camera unit 209 during this unit game period. It is also possible to adopt a method of setting based on the image data of the medals.

  In the gaming machine according to the present embodiment described above, it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image acquired by the imaging unit 261 including the CMOS image sensor 232. Therefore, it is possible to determine the difference in patterns of medals and the like. Moreover, since the control LSI 234 of the camera unit 209 is configured as an ASIC or the like, the manufacturing cost can be effectively suppressed. Furthermore, since the control LSI 234 is provided in a packaged state such as an ASIC, an illegal act from the outside (for example, invalidate the regular medal discrimination process or steal the processing logic of the regular medal discrimination process). It has a significant advantage in terms of security.

<Outline of Camera Unit Configuration and Regular Medal Discrimination Processing According to this Embodiment>
FIG. 36 is a diagram schematically showing an example of a captured image 362A obtained via the imaging device (CMOS image sensor 232) of the camera unit 209 of this embodiment. The captured image 362A shown in FIG. 36 includes an image of the captured medal 410. Further, the background of the medal rails 351a and 351b is captured, and the image is included in the captured image 362A. The medal rails 351a and 351b correspond to the above-mentioned medal rail 210, but the shape of the rail is shown in a simplified form here.

  On one main surface 410a of the medal 410, for example, a pattern of the alphabet "A" is shown. This shows the pattern of the regular medal, but other patterns may be used. Further, patterns may be provided on both main surfaces of the regular medal.

  In the present embodiment, the medal 410 moves along the medal rails 351a and 351b while rotating around a rotation axis along the thickness direction passing through the centers of both main surfaces thereof. Then, the imaging unit 361, which will be described later, images the medal 410 from the one main surface 410a side of the medal 410. Therefore, the captured image 362A includes the image of the one main surface 410a of the medal 410. Further, in the present embodiment, the captured image 362A generated by the image capturing unit 361 is a color image, but it may be a grayscale image.

  FIG. 37 is a functional block diagram of such a camera unit 209 and corresponds to the functional block diagram shown in FIG.

  As shown in FIG. 37, the camera unit 209 according to this embodiment includes an imaging unit 361, a conversion unit 363, a characteristic image generation unit 364, a determination unit 365, and an input / output unit 366. Note that the camera unit 209 includes a light emitting unit such as an LED, but the illustration thereof is omitted in FIG. 37.

  The imaging unit 361 includes a CMOS image sensor 232, and outputs the image data imaged by the CMOS image sensor 232 (performing a predetermined conversion as necessary) as a captured image 362A.

  The conversion unit 363 (for example, corresponding to the ISP circuit 245) converts the captured image 362A input from the image capturing unit 361 from a color image to a grayscale image, and outputs the converted captured image as a captured image 362B.

  The characteristic image generation unit 364 (corresponding to, for example, the image recognition accelerator circuit 249 and the image recognition DSP circuit 242) generates a characteristic image 362C indicating the characteristic of the medal 410 based on the captured image 362B in which the medal 410 is captured. To do. The determination unit 365 determines that the medal 410 (that is, the medal 410 corresponding to the image of the medal 410 included in the captured image 362B) in the captured image 362B is valid based on the characteristic image 362C generated by the characteristic image generation unit 364. It is determined whether or not it is the one, and the determination result 368 is output via the input / output unit 366 (for example, corresponding to the GPIO 250).

  The determination unit 365 (for example, corresponding to the image recognition DSP circuit 242) compares the characteristic image 362C generated from the captured image 362B by the characteristic image generation unit 364 with the template data (template characteristic image) 367 indicating the characteristic of the regular medal. Then, based on the comparison result, it is determined whether or not the medal 410 related to the captured image 362B is an authentic one. The template data 367 is stored in the SRAM 243 or the flash memory 244.

  FIG. 38 is a diagram showing the configuration of the characteristic image generation unit 364 in more detail. As shown in FIG. 38, the characteristic image generation unit 364 includes a first image generation unit 370 and a second image generation unit 380. The first image generation unit 370 generates a first image 374 showing the medal 410 based on the captured image 362B. The second image generation unit 380 integrates (combines) a plurality of rotated images (corresponding to the converted image data 276 described above) obtained by rotating the first image 374 generated by the first image generation unit 370, and then rotates. At least a part of the combined image (corresponding to the above-described processed image data 277) is generated as a characteristic image 362C (second image).

  The first image generation unit 370 includes an extraction unit 371 and an edge image generation unit 372. The extraction unit 371 extracts the medal area 373 in which the medal 410 is shown from the captured image 362B. The edge image generation unit 372 performs edge detection on the medal area 373 extracted by the extraction unit 371 to generate an edge image (first image 374).

  In the present embodiment, the first image generation unit 370 is realized by, for example, the image recognition DSP circuit 242, and the second image generation unit 380 is realized by, for example, the image recognition accelerator circuit 249.

  When the power of the gaming machine according to this embodiment is turned on, the host controller 241 initializes the image recognition DSP circuit 242 and the image recognition accelerator circuit 249. In the initial setting, as described above, the host controller 241 sets the conversion parameter 280 in the memory 274 of the image recognition accelerator circuit 249. The specific information 290 is set in the register 283 of the coordinate conversion circuit 272 by the host controller 241 for each target image data 275, for example.

  When the initial setting is completed, the image pickup unit 361 starts image pickup and picks up an image at a predetermined frame rate. The captured images 362A sequentially generated by the image capturing unit 361 are stored in the SRAM 243, and based on the captured image 362A read from the SRAM 243, the converting unit 363, the characteristic image generating unit 364, and the determining unit 365 determine the regular medal. Processing is performed.

<Flow of regular medal discrimination processing in the camera unit>
Next, with reference to FIG. 39, a series of operations of the regular medal determination process performed by the camera unit 209 in the present embodiment will be described.

  First, the conversion unit 363 reads the captured image 362A stored in the SRAM 243 by the image capturing unit 361 from the SRAM 243, converts the read captured image 362A from a color image into a grayscale image, and obtains the captured image 362B thus obtained. It is stored in the SRAM 243 as a target of the discrimination processing (step S11).

  Next, in step S12, the extraction unit 371 extracts the medal area 373 in which the medal 410 appears from the captured image 362B that is the target of the discrimination processing (see FIG. 40). After that, in step S13, the edge image generation unit 372 performs edge detection on the medal area 373 extracted by the extraction unit 371, and generates an edge image as the first image 374 showing the medal 410.

  Next, in step S14, the second image generation unit 380 rotates the edge image (first image 374) generated by the edge image generation unit 372, and combines the plurality of rotated images to obtain a rotation combined image (process). At least a part of the image data 277) is generated as the characteristic image 362C.

  Next, in step S15, the determination unit 365 compares the characteristic image 362C generated by the second image generation unit 380 with the characteristic image included in the template data 367, and based on the comparison result, the processing target It is determined whether the medal 410 shown in the captured image 362B is a legitimate one. In other words, based on the comparison result between the characteristic image 362C and the characteristic image included in the template data 367, the determination unit 365 determines whether the medal 310 shown in the captured image 362A generated by the image pickup unit 261 is a regular medal. Determine whether or not.

  Then, in step S16, the determination unit 365 outputs the determination result 368 to the main control circuit (corresponding to the main control circuit 91 in the gaming machine of the above embodiment) via the input / output unit 366 (corresponding to the GPIO 250 of the above embodiment). ) Is output. In this way, when the medal 410 shown in the captured image 362A is not a proper one, the main control circuit forcibly interrupts the game, for example, and the sub control circuit (the sub control circuit 101 in the gaming machine of the above-described embodiment). It is possible to notify that there has been a fraudulent activity. For example, it is possible to output a warning to the outside by outputting a warning sound from a speaker or displaying warning information on a display which is a liquid crystal display device.

  After that, when a new captured image 362A is input, the above-described regular medal determination process is executed with the captured image 362B obtained from the captured image 362A as the target of the new determination process. After that, the same regular medal determination process is executed every time the captured image 362A is input.

<Detailed description of each component of the camera unit>
Next, operations of the extraction unit 371, the edge image generation unit 372, the second image generation unit 380, and the determination unit 365 of the first image generation unit 370 will be described in more detail.

[Extractor]
FIG. 40 is a diagram schematically showing an example of the medal area 373 extracted by the extraction unit 371 from the captured image 362B. There are various methods for extracting the medal area 373 from the captured image 362B.

  For example, there is a first extraction method that utilizes the outer shape of the medal 410. In the first extraction method, first, edge detection is performed on the captured image 362B to generate an edge image. As a method of generating an edge image, for example, the Sobel method, Laplacian method, Canny method or the like is used. Next, a circular area is extracted from the generated edge image. As a method of extracting the circular area, for example, Hough transform is used. Then, the circular area in the captured image 362B existing at the same position as the position of the circular area in the edge image is set as the medal area 373.

  As another method, there is a second extraction method for extracting the medal area 373 from the captured image 362B using the background subtraction method and labeling. In the second extraction method, first, a background difference image indicating a difference between the captured image 362B and a background image (an image showing only the background of the captured image 362B) is generated, and the generated background difference image is binarized. It Then, labeling such as 4-connection is performed on the binary background difference image. The partial area in the captured image 362B existing at the same position as the position of the connected area (independent area) obtained as a result of labeling in the binary background difference image is set as the medal area 373.

  In the present embodiment, the extraction unit 371 extracts the medal area 373 from the captured image 362B by a method different from the above two methods. The operation of the extraction unit 371 according to this embodiment will be described below. The extraction unit 371 may extract the medal area 373 from the captured image 362B using either one of the above two methods.

  First, the extraction unit 371 generates a background difference image indicating a difference between the captured image 362B and the background image 375 (an image in which only the background of the captured image 362B appears), and binarizes the generated background difference image. 41 is a diagram schematically showing the background image 375, and FIG. 42 is a diagram schematically showing a binary background difference image 376. Note that in the binary image schematically shown in FIG. 42 and the later-described drawings in the present embodiment, the region (high-luminance region) having the pixel value “1” is shown in black, and the pixel value “0”. The area (low brightness area) is shown in white. The background image 375 can be stored in the SRAM 243 or the like, for example.

  Next, the extraction unit 371 performs template matching on the binary background difference image 376 using the binary outline template 377 indicating the outline of the medal 410. That is, the extraction unit 371 specifies where in the background difference image 376, a region similar to the outer shape template 377 exists. In other words, the extraction unit 371 identifies where, in the background difference image 376, an area that matches the outer shape of the medal 410 indicated by the outer shape template 377 exists. FIG. 43 is a diagram schematically showing the outer shape template 377. The outer shape template 377 can be stored in the SRAM 243 or the like, for example.

  In template matching, as shown in FIG. 44, the extraction unit 371 moves the outline template 377 on the background difference image 376 little by little (for example, by one pixel) in the raster scan direction. In other words, the extraction unit 371 raster-scans the outer shape template 377 on the background difference image 376. At this time, the extraction unit 371 generates an AND image of the outer shape template 377 and the partial area of the background difference image 376 that overlaps with the outer shape template 377 at each position of the outer shape template 377. As a result, a plurality of binary AND images are generated. Then, the extraction unit 371 causes the background difference image 376 of the outer shape template 377 used in the generation of the AND image having the largest number of pixels (high-luminance pixels) having the pixel value “1” among the generated AND images. Identify the top position. This position is a position where a region similar to the outer shape template 377 exists in the background difference image 376.

  Then, as shown in FIG. 45, the extraction unit 371 extracts, as the medal area 373, the partial area 378 in the captured image 362B existing at the same position as the specified position. In other words, the extraction unit 371 extracts, as the medal area 373, the partial area 378 in the captured image 362B that overlaps with the outline template 377 when the outline template 377 is arranged in the captured image 362B at the same position as the specified position. .. At this time, in the partial area 378, a medal area 373 may be one in which the pixel value of each pixel outside the circle indicated by the outer shape template 377 above it is zero. The medal area 373 extracted by the extraction unit 371 is a grayscale image. In the present embodiment, the outer shape of the medal area 373 is a quadrangle, but it may be another shape such as a circle.

[Edge image generator]
The edge image generation unit 372 performs edge detection on the medal area 373 extracted by the extraction unit 371 by using, for example, the Sobel method, the Laplacian method, the Canny method, etc., and outputs the edge image (first image 374). To generate. In the present embodiment, the edge image generation unit 372 uses, for example, the Sobel method which is light in processing. The edge image is a binary image. FIG. 46 is a diagram schematically showing an edge image.

[Second image generator]
The second image generation unit 380 uses, as the characteristic image 362C, at least a part of the rotation combined image obtained by combining the plurality of rotation images obtained by rotating the first image (edge image) 374 generated by the edge image generation unit 372. To generate. In the present embodiment, the second image generation unit 380 generates, for example, a rotation combined image (that is, the above-described processed image data 277) obtained by combining a plurality of rotation images obtained by rotating the first image (edge image) 374. It is generated as a characteristic image 362C. Here, the rotation of the first image (edge image) 374 includes the case where the rotation angle is 0 °. The method of generating the rotation composite image will be described below.

  FIG. 47 is a diagram for explaining a method in which the second image generation unit 380 generates the rotation composite image 381, and corresponds to FIGS. 20 and 28 described above. The second image generation unit 380 rotates the first image (edge image) 374 by a predetermined angle α to generate a plurality of rotated images 374a as shown in FIG. Here, the second image generation unit 380 rotates the first image (edge image) 374 by a predetermined angle α. In the present embodiment, the second image generation unit 380, for example, rotates the first image (edge image) 374 by 2 ° (α = 2 °) as shown in FIG. 26 to generate 180 rotated images 374a. To generate. The above-mentioned angle α can be adjusted to various angles such as 1 ° and 4 °.

  Then, the second image generation unit 380 generates a rotation combined image 381 by combining the generated plurality of rotated images 374a. Specifically, the second image generation unit 380 averages a plurality of rotated images 374a with their centers coincident with each other, and adds and averages the resulting rotated average image 381. The second image generation unit 380 uses the generated rotation composite image 381 as a characteristic image 362C showing the characteristic of the medal 310 shown in the captured image 362B.

  When the plurality of rotated images 374a are combined, the second image generation unit 380 rotates the rotated images 374a having a total rotation angle of 0 ° in each of the rotated images 374a (that is, the first image that is not rotated ( It is possible not to use a region protruding from the outer shape of the edge image) 374). Therefore, in this case, the rotation composite image 381 is a grayscale image having the same size as the first image (edge image) 374.

  As described above, the image capturing unit 361 captures an image of the rotating medal 410 and generates a captured image 362A showing the medal 410. Therefore, the rotation angle (the rotation angle of the pattern attached to the medal 410) of the medal 410 in the captured image 362B generated by the conversion unit 363 is not always the same. On the other hand, since the rotation composite image 381 is a composite of a plurality of rotation images 374a obtained by rotating the first image (edge image) 374 showing the medal 410 of the captured image 362B, the medal of the captured image 362B is combined. Even if there are variations in the rotation angle of 410, if the medal 410 is a legitimate one, the rotation composite image 381 obtained from the captured image 362B hardly changes. Therefore, it can be said that the rotation composite image 381 is the characteristic image 362C showing the characteristics of the medal 410, which is hardly influenced by the rotation angle of the medal 410 of the captured image 362B.

[Judgment part]
The determination unit 365 compares the rotation combined image 381 (feature image 362C) generated by the second image generation unit 380 with the feature image of the template data 267 indicating the feature of the regular medal 410, and based on the comparison result. Then, it is determined whether or not the medal 410 included in the captured image 362B is authentic. As the characteristic image of the template data 267, the characteristic image 362C (rotated image) showing the characteristic of the regular medal 410 generated by the characteristic image generation unit 364 from the captured image 362B including the image of the regular medal 410 in the same manner as described above. The composite image 381) is used.

  The characteristic image of the template data 367 can be obtained by inserting the medal 310 into the game machine. For example, when a regular medal 410 is inserted into a gaming machine equipped with the camera unit 209 of the present embodiment, a captured image 362B (this captured image 362B is referred to as "standard image 391") is captured, and then Based on the standard image 391, the characteristic image generation unit 364 generates a characteristic image 362C (rotational combined image 381) indicating the characteristic of the regular medal 410 included in the standard image 391. This characteristic image 362C is called a "standard characteristic image 392". In this embodiment, the standard feature image 392 is the feature image of the template data 367. Such template data 367 is stored in the SRAM 243 or the like of the camera unit 209 as described above. Hereinafter, in order to distinguish the characteristic image 362C (the characteristic image 362C generated to discriminate the regular medal) from the standard characteristic image 392, the characteristic image 362C generated during the actual operation of the gaming machine is referred to as a "target characteristic image 362C". There is.

  The determination unit 365 compares the rotation combined image 381 (target feature image 362C) and the feature image of the template data 367 by calculating the degree of similarity (difference) between them, for example. In the present embodiment, the determination unit 365 uses, for example, SAD (Sum of Absolute Difference) as a value indicating the degree of similarity. A large SAD means a low degree of similarity, and a small SAD means a high degree of similarity. Other values such as SSD (Sum of Squared Difference) or NCC (Normalized Correlation Coffiecient) may be used as the value indicating the degree of similarity.

  When the similarity between the rotated combined image 381 and the characteristic image of the template data 367 is high, the determination unit 365 determines that the medal 410 included in the captured image 362B is a regular one, and the similarity is If it is low, it is determined that the medal 410 included in the captured image 362B is not a legitimate one. Specifically, the determination unit 365 determines that the medal 410 of the captured image 362B is a valid one if the SAD between the rotation combined image 381 and the characteristic image of the template data 367 is less than or equal to the threshold value. However, when the SAD is larger than the threshold, it is determined that the medal 410 of the captured image 362B is not an authorized one. Then, the determination unit 365 outputs the determination result 368.

  The threshold value used in the determination unit 365 is determined, for example, by using a plurality of medals 410. Specifically, when the gaming machine is not in actual operation, a plurality of regular medals are sequentially inserted into the gaming machine. Then, a plurality of captured images 362B in which the plurality of inserted regular medals are captured are generated. The determination unit 365 obtains the SAD between the rotation combined image 381 generated by the characteristic image generation unit 364 from the captured image 362B and the characteristic image of the template data 367 for each of the generated plurality of captured images 362B. Then, the maximum value of the plurality of SADs determined by the determination unit 365 is determined as the threshold value. The determined threshold value is stored in, for example, the SRAM 243 or the like.

  Note that such determination of the threshold value by the gaming machine can be performed when a predetermined mode is selected in the gaming machine. Further, the threshold value may be determined in advance by the gaming machine or another device and stored in the SRAM or the like of each gaming machine.

  When the type of the regular medal 410 is changed by determining the threshold value used in the determination unit 365 in this way, the changed medal 410 is inserted into the gaming machine that is not in actual operation. By doing so, the threshold value according to the changed medal 410 is determined. Therefore, even when the type of the medal 410 is changed, it is possible to appropriately determine whether or not the medal 410 inserted in the gaming machine is a valid one.

  In the above example, the binary first image (edge image) 374 is input to the second image generation unit 380 as the first image 374 showing the medal 310 of the captured image 362B. The image showing the region 373 may be input to the second image generation unit 380 as the first image. In this case, a rotation combined image obtained by combining a plurality of rotated images obtained by rotating the medal area 373 is the characteristic image 362C.

  As described above, in the pachi-slot 1 which is the gaming machine according to the present embodiment, at least one of the rotation combined images 381 obtained by combining a plurality of rotation images obtained by rotating the first image (edge image) 374 showing the medal 410. The copy is generated as the second image (feature image 362C). The characteristic image 362C is less likely to be affected by the rotation angle of the medal 410 included in the captured image 362B. Therefore, even if the rotation angle (rotational posture) of the medal 410 included in the captured image 362B varies, the medal 410 included in the captured image 362B using the characteristic image 362C (target characteristic image 362C, standard characteristic image 392). Can be more accurately determined, and the determination accuracy is improved.

  Further, in the present embodiment, since the binary edge image is the first image 374, the brightness of the image pickup area in the image pickup unit 361 is higher than that in the case where the medal area 373 of the grayscale image is the first image 374. It is possible to prevent the first image 374 from being affected by the change in the height. Therefore, it is possible to suppress the characteristic image 362C from being affected by the change in the brightness of the imaging area in which the medal 410 is imaged, and as a result, the accuracy of discriminating the regular medal is improved.

  In addition, in the present embodiment, the extraction unit 371 extracts the medal region 373 from the captured image 362B by using template matching, so that the above-described first extraction method using Hough conversion and labeling are used. The extraction process is simplified as compared with the second extraction method that is performed.

  Further, in the present embodiment, the determination unit 365 compares the characteristic image 362C generated from the captured image 362B with the characteristic image of the template data 367 using SAD or the like, and based on the comparison result, the captured image 362B. Since it is determined whether or not the medal 410 according to “1” is authentic, the determination process is simplified.

  The second image generation unit 380 determines the number of rotated images (for example, the value of N shown in FIG. 29) used when generating the characteristic image 362C (rotated combined image 381) as the camera unit 209 of the present embodiment. May be changed in accordance with the operating status of the gaming machine in which is incorporated. For example, it is assumed that the speed of the medal 410 moving on the medal rail 210 differs depending on the game machine or the like. In such a situation, when the moving speed of the medal 410 is high, the second image generation unit 380 gives priority to the processing time over the determination accuracy, and the number of rotation images used when generating the characteristic image 362C. Can be configured to reduce. For example, the second image generation unit 380 rotates the edge image (first image 374) by 10 ° from 0 ° to 350 ° to generate 36 rotated images 374a, and synthesizes these rotated images 374a. To generate a characteristic image 362C.

  On the other hand, when the moving speed of the medal 410 is high, the second image generation unit 380 prioritizes the determination accuracy over the processing time and increases the number of rotated images used when generating the characteristic image 362C. Can be configured. For example, the second image generation unit 380 rotates the edge image (first image 374) by 1 ° from 0 ° to 359 °, generates 360 rotated images 374a, and synthesizes these rotated images 374a. To generate a characteristic image 362C.

  Further, as shown in FIG. 32, when the host controller 241 detects a reduction end interrupt signal (2SH, 4SH, etc.) indicating the end of the fisheye correction processing by the fisheye correction scaler circuit 248, the image recognition DSP circuit is detected. Even when the 242 or the image recognition accelerator circuit 249 is processing (busy state) and a situation occurs in which the marking determination process (regular medal discrimination process) is skipped, regular medal discrimination for more medals 410 is performed. The number of rotated images used when generating the characteristic image 362C can be reduced so that the processing can be performed, and the processing time can be shortened.

  Further, in the gaming machine in which the camera unit 209 of the present embodiment is incorporated, when the medal 410 is thrown into the gaming machine by moving on the medal rail 210 without changing its posture, the captured image 362B is displayed. Although the attitude of the medal 410 reflected is constant, the lateral position of the medal 410 reflected on the medal 410 may vary. For example, the medal 410 may appear on the left side in one captured image 362B, the medal 410 may appear on the center in another captured image 362B, and the medal 410 may appear on the right side in another captured image 362B.

  In such a case, the conversion parameter 280 includes a plurality of parallel movement parameters (the above-mentioned conversion parameter 280 relating to parallel movement), and the captured image 362B or the like is used as the second image instead of the edge image (first image 374). Input to the generation unit 380. Therefore, the second image generation unit 380 individually performs coordinate conversion on the captured image 362B and the like based on the plurality of parallel movement parameters to generate a plurality of parallel movement images. For example, the second image generation unit 380 generates a plurality of right parallel movement images by moving the captured image 362B by 2 pixels in the right direction, and moves the captured image 362B by 2 pixels in the left direction. Generate a plurality of left translation images. Then, the second image generation unit 380 generates a combined image by combining the plurality of right translation images and the plurality of left translation images generated in this way. It is also possible to generate a plurality of such parallel movement images for the edge image (first image 374) and combine these parallel movement images to generate a combined image.

  The determination unit 365 determines whether or not the medal 410 is a regular medal by using the composite image as a characteristic image. As a result, it is possible to properly determine whether or not the medal 410 is a regular medal even if the position of the medal 410 reflected in the captured image 362B in the left-right direction varies.

  Further, in the gaming machine in which the camera unit 209 of the present embodiment is incorporated, when the medal 410 is imaged, the size of the medal 410 shown in the captured image 362B may vary. For example, when the distance between the medal 410 and the CMOS image sensor 232 is not kept constant due to a slight margin in the passage path of the medal 410, the size of the medal 410 shown in the captured image 362B varies to some extent. Sometimes.

  In such a case, the conversion parameter 280 includes a plurality of enlargement parameters (the above-described conversion parameter 280 for image enlargement) and a plurality of reduction parameters (the above-mentioned conversion parameter 280 for image reduction). Then, the second image generation unit 380 individually performs a plurality of coordinate conversions on the edge image (first image 374) based on the plurality of enlargement parameters to generate a plurality of enlarged images. Further, the second image generation unit 380 individually performs a plurality of coordinate conversions on the edge image (first image 374) based on the plurality of reduction parameters to generate a plurality of reduced images. Then, the second image generation unit 380 generates a combined image by combining a plurality of images including a plurality of enlarged images and a plurality of reduced images.

  The determination unit 365 determines whether or not the medal 410 is a regular medal by using the composite image as a characteristic image. As a result, it is possible to appropriately determine whether or not the medal 410 is a regular medal even when the size of the medal 410 reflected in the captured image 362B varies.

  Further, in the gaming machine in which the camera unit 209 of the present embodiment is incorporated, when a plurality of types of medals 410 are used, a plurality of conversions used by the second image generation unit 380 are performed according to the types of the medals 410. The set of parameters 280 may vary. For example, when a certain type of medal 410 is used and imaged by the CMOS image sensor 232, the second image generation unit 380 uses the plurality of rotation parameters included in the conversion parameter 280 to generate an edge image (first image). 374) and the like are individually subjected to a plurality of coordinate transformations. On the other hand, when another type of medal 410 is used, the second image generation unit 380 uses a plurality of parallel movement parameters included in the conversion parameter 280 for the edge image (first image 374) and the like. Multiple coordinate transformations individually.

<Modification of this embodiment>
Various modifications of the camera unit 209 (particularly, the image recognition accelerator circuit 249) according to the embodiment of the present invention will be described below.

[Modification 1]
FIG. 48 is a diagram showing the configuration of the image recognition accelerator circuit 449 according to the present modification. The image recognition accelerator circuit 449 corresponds to the image recognition accelerator circuit 249 shown in FIG. 23, and at least the coordinate conversion circuit 272 is changed to the coordinate conversion circuit 472. The input frame buffer 471 corresponds to the input frame buffer 271 of FIG. 23, the image processing circuit 473 corresponds to the image processing circuit 273 of FIG. 23, and the memory 474 corresponds to the memory 274 of FIG.

  When the coordinate conversion circuit 472 rotates the first image (edge image) 374 shown in FIG. 47 to obtain the rotated image (374a), the coordinate conversion circuit 472 selects a specific subject among the subjects included in the first image (edge image) 374. It is possible to adjust the position (hereinafter, referred to as “specific subject”). Hereinafter, the coordinate conversion circuit 472 according to the present modification will be described focusing on the differences from the coordinate conversion circuit 272 shown in FIG.

  The coordinate conversion circuit 472 according to this modification includes a conversion circuit 481 for performing coordinate conversion, a control circuit 482, and an addition circuit 485. The control circuit 482 includes a register 483 corresponding to the register 283 as compared with the control circuit 282 shown in FIG. 23, and stores therein the specific information 490 corresponding to the specific information 290. The addition circuit 485 adds the parameter offset 495 to the conversion parameter 280 read from the memory 474 of the image recognition accelerator circuit 449 by the control circuit 482. Then, the addition circuit 485 outputs the conversion parameter 280 to which the parameter offset 495 has been added to the conversion circuit 481.

  The parameter offset 495 is stored in the register 483 of the control circuit 482. The parameter offset 495 is represented in the first image (edge image) 374, for example, with respect to the position of the center of gravity of the rectangular image represented by the first image (edge image) 374 (that is, the intersection of the diagonal lines of the rectangle). The amount of displacement of the position of the center of gravity of the specific subject is shown. In the case of the gaming machine according to this embodiment, the specific subject is the medal 410 shown in the first image (edge image) 374. In this case, the center of gravity of the specific subject is the center of gravity of the medal 410, that is, the center of the circular medal 410.

  The parameter offset 495 is the x direction of the position of the center of gravity of the specific subject represented by the first image (edge image) 374 with respect to the position of the center of gravity of the quadrangle represented by the first image (edge image) 374 (for example, left and right of the image). Direction deviation amount xoff and the position of the center of gravity of the specific subject represented by the first image (edge image) 374 with respect to the position of the center of gravity of the rectangle represented by the first image (edge image) 374 in the y direction (for example, It is composed of a shift amount yoff in the vertical direction of the image). Hereinafter, the shift amount xoff will be referred to as “x offset xoff”. Further, the shift amount yoff is referred to as “y offset yoff”.

  Here, the coordinates of the center of gravity of the quadrangle represented by the first image (edge image) 374 are (x1, y1), and the coordinates of the center of gravity of the specific subject represented by the first image (edge image) 374 are (x2, y2). y2). At this time, x offset xoff = x2-x1 and y offset yoff = y2-y1. In the example of the first image (edge image) 374 shown in FIG. 46, each side of the quadrangle represented by the first image (edge image) 374 is in contact with the circumference of the medal 410 that is a perfect circle. , Xoff = 0 and yoff = 0.

  When adding the parameter offset 495 to the conversion parameter 280, the adding circuit 485 adds the x offset xoff of the parameter offset 495 to each x coordinate of the four coordinates forming the conversion parameter 280. Then, the adding circuit 485 adds the y offset yoff of the parameter offset 495 to each y coordinate of the four coordinates forming the conversion parameter 280.

  The conversion circuit 481 performs coordinate conversion on the target image data 275 (first image 374) based on the conversion parameter 280 to which the parameter offset 495 is added. When the conversion parameter 280 is the conversion parameter 280 related to the image rotation, the conversion circuit 481 performs coordinate conversion of the target image data 275 based on the conversion parameter 280 to which the parameter offset 495 is added. As a result, even if the position of the center of gravity of the specific subject represented by the target image data 275 is deviated from the position of the center of gravity of the quadrangle represented by the target image data 275, the positions of the center of gravity of the two coincide with each other. Like In the gaming machine according to the present embodiment, the position of the center of gravity of the medal 410 represented by the first image (edge image) 374, which is the target image data 275, is changed from the position of the center of gravity of the quadrangle represented by the first image 374. Even if they are deviated from each other, the positions of the centers of gravity of the both will match.

  The parameter offset 495 is set by the host controller 241 when the host controller 241 instructs the image recognition accelerator circuit 449 to start image processing (rotation integration processing) on the target image data 275 (step S1 in FIG. 33, etc.). It is set in the register 483 of the control circuit 482 together with the specific information 290. The host controller 241 reads, for the target image data 275 to be processed, the specific information 290 corresponding to the target image data 275 and the parameter offset 495 from the SRAM 243 or the like to the image recognition accelerator circuit 249, and the read specific information. 290 and the parameter offset 495 are set in the register 483 of the control circuit 482.

  The control circuit 482 outputs the parameter offset 495 stored in the register 483 to the addition circuit 485, and reads the conversion parameter 280 from the memory 274 based on the specific information 290 stored in the register 483. The addition circuit 485 adds the parameter offset 495 to the conversion parameter 280 read from the memory 274, and the conversion parameter 280 to which the parameter offset 495 is added is provided to the conversion circuit 481.

  In the gaming machine according to the present embodiment, the parameter offset 495 is generated by the image recognition DSP circuit 242 that functions as the first image generation unit 370, for example. The first image generation unit 370 can generate the parameter offset 495 when generating the first image (edge image) 374 based on the captured image 362B.

  The first image generation unit 370 stores the parameter offset 495 obtained when generating the first image (edge image) 374 in the SRAM 243 in association with the first image 374.

  As described above, in the coordinate conversion circuit 472 according to the present modification, the conversion circuit 481 performs coordinate conversion on the first image (edge image) 374 based on the conversion parameter 280 to which the parameter offset 495 is added. Therefore, by adjusting the parameter offset 495 for each first image (edge image) 374, the rotation image 374a (converted image data 276) obtained by the conversion circuit 481 or the characteristic image 362C (processed image data 277) is obtained. The position of the specific subject is adjusted.

  In the gaming machine according to the present embodiment, when the position of the medal 410 in the rotation image 374a varies, the composite image varies, and as a result, the characteristic image 362C varies. If the characteristic image 362C varies, even if the medal 410 inserted into the game machine is a regular medal, it may be significantly different from the template data 367, and as a result, the determination accuracy of the determination unit 365 may be reduced. is there. Therefore, as in this modification, the position of the center of gravity of the medal 410 represented by the first image (edge image) 374 is made to coincide with the position of the center of gravity of the quadrangle represented by the first image 374. The variation of 362C is reduced, and as a result, the determination accuracy of the determination unit 365 can be improved.

[Modification 2]
In this modified example, as shown in FIG. 49, the image recognition accelerator circuit 549 performs coordinate conversion on the target image data 575 stored in the input frame buffer a plurality of times to generate one processed image data 577. To do.

  FIG. 50 is a diagram showing the configuration of the image recognition accelerator circuit 549 according to the present modification. The image recognition accelerator circuit 549 corresponds to the image recognition accelerator circuit 249 shown in FIG. 23. At least the coordinate conversion circuit 272 is changed to the coordinate conversion circuit 572, and the image processing circuit 273 is changed to the image processing circuit 573. Has been done. The input frame buffer 571 corresponds to the input frame buffer 271 of FIG. 23, and the memory 574 corresponds to the memory 274 of FIG.

  FIG. 51 is a diagram showing the configuration of the image processing circuit 573 according to the present modification. As shown in FIG. 51, the image processing circuit 573 according to the present modified example does not include an addition processing unit as compared with the image processing circuit 273 shown in FIG. 30 described above. Further, the image processing circuit 573 has a first read request output unit 601 corresponding to the first read request output unit 301 and a write request output unit 602 corresponding to the write request output unit 302, as compared with the image processing circuit 273. , And a second read request output unit 603 corresponding to the second read request output unit 303 is provided in the storage control unit 600. Further, the image processing circuit 573 of FIG. 51 includes an arbitration unit 604 corresponding to the arbitration unit 304 of the image processing circuit 273, further includes a write buffer 606 corresponding to the write buffer 306 and a read buffer 607 corresponding to the read buffer 307. A frame memory 609 corresponding to the frame memory 309 is provided. The converted image data 576 is output to the write buffer 606 from the coordinate conversion circuit 572 described above.

  In the image processing circuit 573, the pixel data (of the converted image data 576) output from the conversion circuit 581 of the coordinate conversion circuit 572 of the image recognition accelerator circuit 549 is directly written in the write buffer 606. The pixel data stored in the read buffer 607 is output to the selection circuit 585 of the coordinate conversion circuit 572.

  As shown in FIG. 50, the coordinate conversion circuit 572 according to the present modification further includes a selection circuit 585 as compared with the coordinate conversion circuit 272 shown in FIG. 23 described above. The selection circuit 585 selects either the output of the input frame buffer 571 or the output of the image processing circuit 573 based on the control signal CNT1 output from the control circuit 582, and the selected output is input to the conversion circuit 581. As described above, the conversion circuit 581 is connected.

  In the present modification, when the control signal CNT1 output from the control circuit 582 is in the first state (for example, indicating “1”), the selection circuit 585 selects the output of the input frame buffer 571. When the selection circuit 585 selects the output of the input frame buffer 571, the conversion circuit 581 can access the target image data 575 stored in the input frame buffer 571.

  On the other hand, when the control signal CNT1 output from the control circuit 582 is in the second state (for example, indicates “0”), the selection circuit 585 selects the output of the image processing circuit 573. When the selection circuit 585 selects the output of the image processing circuit 573, the conversion circuit 581 is connected to the read buffer 607 of the image processing circuit 573, and pixel data can be read from the read buffer 607.

  FIG. 52 is a diagram showing an example of the conversion parameter 580 according to the present modification. In the conversion parameter 580 according to this modification, a unique parameter number (identification information) is associated with each of the plurality of conversion parameters 580. In the example shown in FIG. 52, the conversion parameters associated with the parameter numbers “1” to “360” are the conversion parameters (580-1 to 580-360) related to the rotation of the image. There are 360 conversion parameters 580 for rotating from ° to 360 °. Also, the conversion parameters associated with the parameter numbers “361” to “360” are conversion parameters (580-361 to 580-390) related to image enlargement, and these are 1.1 to 4 times larger than an image. 30 conversion parameters 580 for up to 0.0 times magnification.

  Furthermore, the conversion parameters associated with the parameter numbers “391” to “399” are conversion parameters (580-391 to 580-399) related to image reduction, and these are 0.9 to 0 times the image. 9 conversion parameters 580 for reducing to 1 time. Further, the conversion parameters associated with the parameter numbers “400” and “401” are the conversion parameters (580-400 to 580-401) related to the parallel movement of the image, and these convert the image to the right by one pixel. It corresponds to the conversion parameter 580 for parallel translation and the conversion parameter 580 for parallel translation of the image right by two pixels.

  FIG. 53 is a diagram showing an example of the specific information 590 according to the present modification. As shown in FIG. 53, the identification information 590 according to this modification includes reference mode information 591 and a lookup table (LUT) 592.

  The reference mode information 591 includes a reference count 591a, a reference start position 591b, and a reference interval 591c. The reference count 591a indicates the number of times the parameter number stored in the LUT 592 is referenced. The reference start position 591b indicates the position of the parameter number referred to first in the LUT 592. The reference interval 591c indicates how many conversion parameters 580 apart from the previously referred conversion parameter 580 in the LUT 592 when the conversion parameter 580 is referenced at a certain timing.

  The LUT 592 describes a plurality of parameter numbers. The reference mode information 591 is information indicating how to refer to the plurality of parameter numbers described in the LUT 592 as described above. The control circuit 582 refers to the parameter numbers of the LUT 592 one by one according to the reference mode information 591, and reads the conversion parameter 580 corresponding to the referred parameter number each time the parameter number is referenced. The read conversion parameter 580 is input to the conversion circuit 581.

  The control circuit 582 sequentially refers to the plurality of parameter numbers of the LUT 592 from the head side to the tail side of the LUT 592 (for example, from the head storage position (head address) to the last storage position (final address) of the storage area forming the LUT 592). To do. When the coordinate conversion circuit 572 performs M (≧ 2) number of coordinate conversions on the target image data 575, the control circuit 582 first, based on the reference start position 591b of the reference mode information 591, the LUT 592. The parameter number of the corresponding reference start position of is referred to. Next, the control circuit 582 reads the conversion parameter 580 corresponding to the referred parameter number from the memory 574 and inputs it to the conversion circuit 581.

  Next, based on the reference interval 591c of the reference mode information 591, the control circuit 582 refers to the parameter number in the LUT 592, which is separated from the previously referenced parameter number by the number indicated by the reference interval 591c toward the end. Then, the control circuit 582 reads the conversion parameter 580 corresponding to the referred parameter number from the memory 574 and inputs it to the conversion circuit 581.

  After that, the control circuit 582 repeats the same operation, refers to the parameter number for the number of times (M times) indicated by the reference count 591a of the reference mode information 591, and stores the conversion parameter 580 corresponding to the referenced parameter number in the memory 574. Read out from and input to the conversion circuit 581. As a result, among the plurality of conversion parameters 580 stored in the memory 574, the M conversion parameters 580 used by the conversion circuit 581 in the coordinate conversion for the target image data 575 stored in the input frame buffer 571 are sequentially converted. It is input to the circuit 581.

  In the examples of FIGS. 52 and 53, for example, when the reference count 591a of the reference mode information 591 is “3”, the reference start position 591b is “0000h” indicating the start address, and the reference interval 591c is “1”, the control is performed. The circuit 582 sequentially refers to “1”, “361”, and “400” among the plurality of parameter numbers stored in the LUT 592. As a result, the conversion circuit 581 indicates to the conversion parameter 580-1 regarding the rotation for rotating the image 1 ° corresponding to the parameter number = “1” and the image corresponding to the parameter number = “361” to 1. Conversion parameters 580-361 related to enlargement for 1-time enlargement and conversion parameters 580-400 corresponding to parameter number = “400” and related to translation for parallel translation of an image by one pixel in the right direction. Entered in order.

[Operation of Image Recognition Accelerator Circuit in Modification 2]
FIG. 54 is a diagram for explaining the operation of the image recognition accelerator circuit 549 according to the present modification. When the target image data 575 is written in the input frame buffer 571, the control circuit 582 sets the control signal CNT1 to the first state, which causes the target image data 575 in the input frame buffer 571 to pass through the selection circuit 585. It is input to the conversion circuit 581. Further, the control circuit 582 reads the conversion parameter 580 used first from the memory 574 and outputs it to the conversion circuit 581 together with the setting of the control signal CNT1. The conversion circuit 581 performs coordinate conversion on the target image data 575 stored in the input frame buffer 571 based on the input conversion parameter 580 to generate first converted image data 576-1. When the conversion circuit 581 generates the first converted image data 576-1, the control circuit 582 sets the control signal CNT1 to the second state. As a result, the read buffer 607 of the image processing circuit 573 is connected to the conversion circuit 581 via the selection circuit 585.

  When the conversion circuit 581 performs coordinate conversion on the target image data 575 based on the conversion parameter 580, the conversion circuit 581 writes the pixel data of the first converted image data 576-1 in the write buffer 606 of the image processing circuit 573. The pixel data written in the write buffer 606 is written in the frame memory 609. As a result, the first converted image data 576-1 is stored in the frame memory 609.

  The image processing circuit 573 writes the pixel data of the first converted image data 576-1 stored in the frame memory 609 into the read buffer 607. Here, the conversion circuit 581 reads out the pixel data of the first converted image data 576-1 in the read buffer 607, so that the conversion circuit 581 causes the conversion circuit 581 to read the first converted image data 576-1 from the image processing circuit 573. Is entered.

  Next, the conversion circuit 581 performs coordinate conversion on the first converted image data 576-1 based on the conversion parameter 580 used secondly read from the memory 574 by the control circuit 582, The second converted image data 576-2 is generated. The conversion circuit 581 writes the pixel data of the second converted image data 576-2 in the write buffer 606 of the image processing circuit 573, and the pixel data thus written in the write buffer 606 is written in the frame memory 609. As a result, the second converted image data 576-2 is stored in the frame memory 609.

  The image processing circuit 573 writes the pixel data of the second converted image data 576-2 stored in the frame memory 609 to the read buffer 607, and the conversion circuit 581 outputs the second converted image data 576- from the read buffer 607. The pixel data of 2 is read. As a result, the second converted image data 576-2 is input to the conversion circuit 581 from the image processing circuit 573. The conversion circuit 581 performs coordinate conversion on the second converted image data 576-2 based on the conversion parameter 580 used thirdly read from the memory 574 by the control circuit 582 to perform the third conversion. After-image data 576-3 is generated. The conversion circuit 581 writes the pixel data of the third converted image data 576-3 to the write buffer 606 of the image processing circuit 573, and the pixel data of the write buffer 606 thus written is written to the frame memory 609. As a result, the third converted image data 576-3 is stored in the frame memory 609.

  Thereafter, the image recognition accelerator circuit 549 repeats the same operation, and the conversion circuit 581 of the coordinate conversion circuit 572 controls the control circuit 582 for the (M−1) th converted image data 576− (M−1). Coordinate conversion is performed based on the Mth used conversion parameter 580 read from the memory 574 to generate Mth converted image data 576-M. Then, the Mth converted image data 576-M is written in the frame memory 609 as the processed image data 577.

  52 and 53, for example, the reference count 591a in the reference mode information 591 of the identification information 590 is "3", the reference start position 591b is "0000h" indicating the start address, and the reference interval 591c is "1". In the case shown, by referring to the LUT 592 as described above, the conversion circuit 581 provides the conversion circuit 581 with the conversion parameter 580-1 relating to the rotation for rotating the image by 1 ° and the conversion parameter 580-1 for enlarging the image 1.1 times. Conversion parameters 580-361 related to enlargement and conversion parameters 580-400 related to parallel movement for moving the image in the right direction by one pixel are sequentially input. Therefore, in this case, the conversion circuit 581 performs coordinate conversion for rotating the image by 1 °, coordinate conversion for enlarging the image 1.1 times, and image conversion for one target image data 575. Coordinate conversion for parallel translation by one pixel to the right is executed in this order. That is, the conversion circuit 581 rotates the image related to one target image data 575 by 1 °, enlarges the rotated image obtained by 1.1 times, and enlarges the obtained enlarged image by 1 to the right. By performing parallel translation by a pixel, one processed image data 577 is generated.

  The output control unit 608 of the image processing circuit 573 outputs the processed image data 577 as an output image to the SRAM 243 by DMA transfer as in the above. Further, the output control unit 608 controls the frame memory 609 by the storage control unit 600, and when the pixel data of four pixels of the final processed image data 577 is read from the frame memory 609, the read four pixels are read. Minute pixel data is output to the SRAM 243 by DMA transfer. The DMAC 252 controls so that the processed image data 577 is DMA-transferred from the frame memory 609 to the SRAM 243.

  When the DMAC 252 includes a buffer, the output control unit 608 reads the pixel data of 4 pixels of the final processed image data 577 from the frame memory 609, and the read pixel data of 4 pixels is stored in the buffer of the DMAC 252. Then, the host controller 241 writes the pixel data for four pixels or the entire processed image data 577 to the SRAM 243.

  The conversion circuit 581 writes the generated pixel data in the write buffer 606 every time the pixel data is generated, and the write request output unit 602 and the second read request output unit 603 operate independently. Therefore, after the processed image data 577 is generated, the entire data is not output to the SRAM 243 or the DMAC 252, but the conversion circuit 581 performs the coordinate conversion in pixel data units for generating the processed image data 577. The processing and the output processing of the pixel data of the processed image data 577 by the output control unit 608 are executed in parallel.

  As described above, the coordinate conversion circuit 572 according to the present modification superimposes a plurality of coordinate conversions on one target image data 575 based on the plurality of conversion parameters 580 without exchanging data with the host controller 241. Do it. Therefore, similar to the above, each time the coordinate conversion circuit 572 performs the coordinate conversion, the processing time for a plurality of coordinate conversions is shortened as compared with the case where the conversion parameter 580 used in the coordinate conversion is received from the host controller 241. be able to.

  Further, in the same manner as described above, in the storage control unit 600, when at least two requests of the first read request, the write request, and the second read request conflict, the arbitration unit 604 determines that at least the two requests. Arbitrated. Therefore, the first read request output unit 601, the write request output unit 602, and the second read request output unit 603 can operate independently of each other, and the first read request output unit 601 and the write request output unit 601. It is possible to prevent a process at a certain output unit of the output unit 602 and the second read request output unit 603 from becoming a bottleneck. As a result, the processing speed of the entire image recognition accelerator circuit 549 can be improved.

  Further, in the present modification, the specific information 590 is the LUT 592 in which the parameter number corresponding to the conversion parameter 580 is described, and the reference mode information 591 indicating how to refer to the plurality of parameter numbers described in the LUT 592. It is composed of. Therefore, the conversion parameter 580 used in the conversion circuit 581 is designated by the parameter number. Therefore, the conversion parameter 580 used in the conversion circuit 581 can be specified regardless of the position and order of the plurality of conversion parameters 580 stored in the memory 574.

  For example, consider the case where the conversion parameters 280 regarding a plurality of rotations are stored in the memory 574 as shown in FIG. Here, as shown in FIG. 25, when the specific information 290 is composed of the use parameter number 291, the use start position 292, and the use interval 293, the image is rotated by 1 ° according to the specific information 290. Conversion parameter 280-1 for rotating the image by 2 °, a conversion parameter 280-2 for rotating the image by 2 °, a conversion parameter 280-4 for rotating the image by 4 °, and a conversion parameter 280-7 for rotating the image by 7 °. Only (not shown) cannot be specified.

  On the other hand, in this modification, the LUT 592 has a parameter number corresponding to the conversion parameter 580-1 for rotating the image by 1 ° and a parameter number corresponding to the conversion parameter 580-2 for rotating the image by 2 °. , The conversion parameter 580-4 for rotating the image by 4 ° and the conversion parameter 580-7 for rotating the image by 7 ° by individually describing these conversions. It is possible to specify the parameter 580.

  Although the specific information 590 is composed of the reference mode information 591 and the LUT 592, it may be composed of only the LUT 592. In this case, the control circuit 582 refers to the plurality of parameter numbers stored in the LUT 592 in order from the beginning of the LUT 592, for example. Even in such a case, since the conversion parameter 580 used in the conversion circuit 581 is designated by the parameter number, the plurality of conversion parameters 580 are stored in the memory 574 no matter how they are stored. The conversion parameter 580 used in the conversion circuit 581 can be freely specified from the conversion parameter 580 of FIG. Further, the image recognition accelerator circuit 549 according to the present modification may use the specific information 290 shown in FIG. 25 described above.

  As shown in FIG. 51, the image processing circuit 573 does not include an addition processing unit and exchanges the converted image data 576 with the coordinate conversion circuit 572 shown in FIG. Data 577 is generated (see FIG. 54). In the present specification, such processing (data handling) in the image processing circuit 573 is also regarded as a form of image processing.

[Modification 3]
The image recognition accelerator circuit 749 according to the present modification has, as operation modes, an individual conversion processing mode in which individual conversion processing is performed on each target image data 775 to generate a composite image, and one target image data 775 is processed. It has a multiple conversion processing mode for performing multiple conversion processing. 55 and 56 are diagrams showing the configurations of the image recognition accelerator circuit 749 and the image processing circuit 773 according to the present modification, respectively.

  FIG. 55 is a diagram showing the configuration of the image recognition accelerator circuit 749 according to the present modification. The image recognition accelerator circuit 749 corresponds to the image recognition accelerator circuit 549 shown in FIG. 50. At least the coordinate conversion circuit 572 is changed to the coordinate conversion circuit 772, and the image processing circuit 573 is changed to the image processing circuit 773. Has been done. The input frame buffer 771 corresponds to the input frame buffer 771 in FIG. 50, and the memory 774 corresponds to the memory 774 in FIG. In the coordinate conversion circuit 772 of FIG. 55, the selection circuit 785 corresponds to the selection circuit 585 of the coordinate conversion circuit 572 of FIG. 50, the conversion circuit 781 corresponds to the conversion circuit 581 of the coordinate conversion circuit 572, and the control circuit 782 performs coordinate conversion. It corresponds to the control circuit 582 of the circuit 572.

  As shown in FIG. 55, the coordinate conversion circuit 772 according to this modification has a configuration similar to that of the coordinate conversion circuit 572 shown in FIG. 50 described above, but in this modification, the register 783 of the control circuit 782 is provided. Stores operation mode information 795 indicating the operation mode in which the image recognition accelerator circuit 749 should operate. Based on this operation mode information 795, the control signal CNT2 is provided to the image processing circuit 773.

  The operation mode information 795 is set in the register 783 by the host controller 241, for example. When setting the specific information 790 in the register 783, the host controller 241 also sets the operation mode information 795 in the register 783.

  The control circuit 782 controls the control signal CNT1 based on the operation mode information 795. Further, the control circuit 782 outputs a control signal CNT2 for controlling a selection circuit 806 described later included in the image processing circuit 773. The control signal CNT2 is determined based on the operation mode information 795.

  As shown in FIG. 56, the image processing circuit 773 according to the present modification further includes a selection circuit 806, as compared with the image processing circuit 273 shown in FIG. 30 described above. In addition, the image processing circuit 773 according to the present modification is different from the image processing circuit 273 in that the first read request output unit 801 corresponding to the first read request output unit 301 and the write request output unit 302 corresponding to the first read request output unit 301. The storage control unit 800 includes a second read request output unit 803 corresponding to the input request output unit 802 and the second read request output unit 303. Further, the image processing circuit 773 of FIG. 56 includes an arbitration unit 804 corresponding to the arbitration unit 304 of the image processing circuit 273, further includes an addition processing unit 805 corresponding to the addition processing unit 305 and a write buffer corresponding to the write buffer 306. 706, a read buffer 707 corresponding to the read buffer 307, a frame memory 709 corresponding to the frame memory 309, and an output control unit 708 corresponding to the output control unit 308. The converted image data 776 is output from the coordinate conversion circuit 772 described above to the addition processing unit 805.

  Here, the selection circuit 806 receives the control signal CNT2 from the control circuit 782 of the coordinate conversion circuit 772 of the image recognition accelerator circuit 749, and based on this control signal CNT2, the output of the conversion circuit 781 of the coordinate conversion circuit 772, and One of the outputs obtained as a result of the output of the conversion circuit 781 of the coordinate conversion circuit 772 being input to the addition processing unit 805 is selected, and the selected output is output to the write buffer 706. In the present modification, when the control signal CNT2 is in the first state (for example, a state indicating “1”), the selection circuit 806 selects the output of the addition processing unit 805 and outputs the selected output (pixel data) to the write buffer. Output to 706. On the other hand, when the control signal CNT2 is in the second state (for example, the state indicating “0”), the selection circuit 806 selects the output of the conversion circuit 781 and outputs the selected output (pixel data) to the write buffer 706. ..

[Operation of Image Recognition Accelerator Circuit in Modification 3]
When the operation mode information 795 indicates the individual conversion processing mode, the control circuit 782 sets both the control signal CNT1 and the control signal CNT2 to the first state. As a result, the operation mode of the image recognition accelerator circuit 749 according to the present modification becomes the individual conversion processing mode, and its configuration is the same as that of the image recognition accelerator circuit 249 shown in FIG. 23 and the image processing circuit 273 shown in FIG. The image recognition accelerator circuit 749 in the individual conversion processing mode operates in the same manner as these circuits.

  In the individual conversion processing mode, for example, with respect to one target image data 775, all 360 (for 360 degrees) converted image data 776 generated by rotating in 1-degree units based on the conversion parameter 780 are integrated, One processed image data 777 is generated (see FIG. 29).

  On the other hand, the control circuit 782 sets the control signal CNT2 to the second state when the operation mode information 795 indicates the multiple conversion processing mode. As a result, the operation mode of the image recognition accelerator circuit 749 according to the present modification becomes the multiple conversion processing mode, and its configuration is the same as the image recognition accelerator circuit 549 shown in FIG. 50 and the image processing circuit 573 shown in FIG. With the same configuration, the operation of the image recognition accelerator circuit 749 in the multiple conversion processing mode is the same as those circuits.

  In the multiple conversion processing mode, for example, one target image data 775 is subjected to coordinate conversion based on the conversion parameter 780, and then the generated converted image data 776 is sequentially subjected to coordinate conversion based on the conversion parameter 780. Then, one processed image data 777 is generated (see FIG. 54).

  After the camera unit 209 including the image recognition accelerator circuit 749 according to this modification is activated, the host controller 241 causes the image recognition accelerator circuit 749 to select the q-th target image (q is a variable, q ≧ 1). When the setting related to the data 775 is performed (the setting in step S1, step S2, etc. in FIG. 33 described above), the host controller 241 determines the specific information 790 used in the process for the q-th target image data 775 and the q-th target image data 775. The operation mode information 795 indicating the operation mode of the image recognition accelerator circuit 749 related to the processing of the target image data 775 of (1) is set in the register 783 included in the control circuit 782 of the image recognition accelerator circuit 749.

  In the image recognition accelerator circuit 749, when the specific information 790 and the operation mode information 795 are set in the register 783, the q-th target image data 775 is written from the SRAM 243 to the input frame buffer 771 by DMA transfer. In the coordinate conversion circuit 772, the control circuit 782 controls the control signals CNT1 and CNT2 to set the operation mode of the image recognition accelerator circuit 749 to the operation mode indicated by the operation mode information 795 of the register 783. .. Then, the image recognition accelerator circuit 749 performs processing on the q-th target image data 775 stored in the input frame buffer 771 according to the set operation mode.

  When the host controller 241 sets the (q + 1) th target image data 775 to the image recognition accelerator circuit 749, the host controller 241 is similarly used in the processing for the (q + 1) th target image data 775. Setting specific information 790 and operation mode information 795 indicating the operation mode of the image recognition accelerator circuit 749 related to the processing on the (q + 1) th target image data 775 is set in the register 783 included in the control circuit 782 of the image recognition accelerator circuit 749. To do.

  As described above, since the image recognition accelerator circuit 749 according to the present modification includes the individual conversion processing mode and the multiple conversion processing mode as the operation modes, two processings in one camera unit 209, that is, It is possible to execute both the individual conversion process and the multiple conversion process.

  Further, the two camera units 209 and the gaming machines having the same configuration can be configured such that on the one hand, only the individual conversion processing is executed, and on the other hand, only the conversion processing is executed plural times.

[Modification 4]
The configuration of the image recognition accelerator circuit 949 (not shown) according to this modification corresponds to the image recognition accelerator circuit 249 shown in FIG. 23, and at least the image processing circuit 273 is changed to the image processing circuit 973. .. In addition, the image recognition accelerator circuit 949 includes an input frame buffer 971 corresponding to the input frame buffer 271 of the image recognition accelerator circuit 249 shown in FIG. 23, a coordinate conversion circuit 972 corresponding to the coordinate conversion circuit 272, and a memory corresponding to the memory 274. It has 974.

  FIG. 57 is a diagram showing the configuration of the image processing circuit 973 of the image recognition accelerator circuit 949 according to the present modification. The image processing circuit 973 according to the present modification is different from the image processing circuit 273 shown in FIG. 30 described above in that the first read request output unit 1001 corresponding to the first read request output unit 301 and the write request output unit. The storage controller 1000 is provided with a write request output unit 1002 corresponding to 302, but is not provided with a second read request output unit. Further, the image processing circuit 973 in FIG. 57 includes an arbitration unit 1004 corresponding to the arbitration unit 304 of the image processing circuit 273. The arbitration unit 1004 outputs the first read request output from the first read request output unit 1001. , The write request output from the write request output unit 1002 is arbitrated, one of the first read request and the write request is selected, and the process according to the selected request is performed.

  Further, the image processing circuit 973 shown in FIG. 57 includes an addition processing unit 1005 corresponding to the addition processing unit 305, a write buffer 1006 corresponding to the write buffer 306, and a read buffer 307 as compared with the image processing circuit 273 shown in FIG. A corresponding read buffer 1007 and a frame memory 909 corresponding to the frame memory 309 are provided. The converted image data 976 is output from the above-described coordinate conversion circuit 972 to the addition processing unit 1005.

  Further, the image processing circuit 973 according to the present modification includes an output control unit 1008, which is different from the output control unit 308 of the image processing circuit 273 shown in FIG. 30 and is read from the frame memory 909. Instead of outputting the processed pixel data of the processed image data 977, the pixel data of the processed image data 977 stored in the write buffer 1006 is output. When the pixel data of four pixels of the processed image data 977 that is the image data to be output is stored in the write buffer 1006, the output control unit 1008 reads the pixel data of four pixels from the write buffer 1006 and performs the DMA transfer. Is output to the SRAM 243. The DMAC 252 controls so that the processed image data 977 is DMA-transferred from the write buffer 1006 to the SRAM 243.

  When the DMAC 252 includes a buffer, the output control unit 1008 reads pixel data of four pixels of the processed image data 977 from the write buffer 1006 and stores the read pixel data of four pixels in the buffer of the DMAC252. Then, the host controller 241 writes the pixel data of four pixels or the entire processed image data 577 into the SRAM 243.

  In the present modification, when the write buffer 1006 stores the pixel data of the processed image data 977 to be output, the write request output unit 1002 exceptionally requests the write request even if the write buffer 1006 is full. Do not output.

  As described above, in the image processing circuit 973 according to the present modification, when the first read request and the write request conflict with each other, the two requests are arbitrated, so that the first read request output unit 1001 and The write request output unit 1002 can operate independently of each other. Therefore, it is possible to prevent the processing at one of the first read request output unit 1001 and the write request output unit 1002 from becoming a bottleneck. As a result, the overall processing speed of the image recognition accelerator circuit 949 can be improved.

  Further, the output control unit 1008 outputs the pixel data of the processed image data 977 not written in the frame memory 909 to the SRAM 243 by DMA transfer. Therefore, as compared with the case where the output control unit 1008 outputs the pixel data of the processed image data 977 read from the frame memory 909, the DMAC 252 has the output target data (processed image data) output from the addition processing unit 1005. 977) can be received immediately. Therefore, it is possible to shorten the time from the generation of the output target data to the writing of the data in the SRAM 243.

[Other modifications]
In the above example, the coordinate conversion circuit 272 and the like perform a plurality of coordinate conversions using one (one frame) target image data, but only one coordinate conversion is performed for one target image 110. You may go. Further, the coordinate conversion circuit 272 and the like may repeatedly perform one coordinate conversion for one target image data. For example, in the modified example 2 described above, the coordinate conversion circuit 472 performs the coordinate conversion on one target image data 475 based on the conversion parameter 480 for rotating the image by 2 °, and then performs the coordinate conversion ( That is, an image obtained by rotating the target image data 475 by 180 ° is obtained as the converted image data 476 by performing 89 times of coordinate conversion with a rotation angle of 2 °.

  Further, all or part of the functions of the coordinate conversion circuit 272 and the like may be realized by a processor (CPU or DSP, etc.). Further, all or part of the functions of the image processing circuit 273 and the like may be realized by the processor.

  Further, the image recognition accelerator circuit 249 and the like may not be provided with the image processing circuit 273 and the like. In this case, the data output from the coordinate conversion circuit 272 or the like is written in the SRAM 243 by DMA transfer. Further, the image processing circuit 273 may process data other than image data. Further, in the image processing circuit 273 and the like, a processing unit that performs a process other than the addition process may be provided instead of the addition processing unit.

  As described above, the image recognition accelerator circuit 249 of the camera unit 209 and its modified example have been described in detail, but the above description is merely an example, and the present invention is not limited to such an example configuration. Absent. Further, the various modifications described above can be applied in combination with each other as long as they do not conflict with each other.

  Further, in the above-described embodiments and modified examples, a pachi-slot has been described as an example of a gaming machine, but the present invention is not limited to this, and the present invention is also applicable to a gaming machine called a “pachinko”. The effect of is obtained.

  The game machine according to the embodiment of the present invention and the modified examples thereof have been described above. It is additionally disclosed that the gaming machine described above basically has the following features and operational effects.

[Appendix 1-1]
Embodiment 1-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
Direct transfer control means (for example, DMAC252) for controlling the direct transfer of data,
First storage means (for example, SRAM 243) for storing data,
A predetermined format conversion is performed on the image data obtained via the image capturing means, and the image data after the format conversion (for example, target image data 275 and captured image 362B) is directly transferred to the first storage means. Conversion means for storing (for example, the conversion unit 363, the ISP circuit 245, etc.),
A characteristic image generation unit (for example, a characteristic image generation unit 364, an image recognition accelerator circuit 249, etc.) that generates a characteristic image showing the characteristic of the game medium based on the image data after the format conversion,
The characteristic image generating means,
Image data relating to the image data after the format conversion is acquired from the first storage unit, image processing including coordinate conversion is performed on the acquired image data (for example, a graphic rotation process), and the image processing is performed. The subsequent image data (for example, the processed image data 277 and the characteristic image 362C) is stored in the first storage unit by the direct transfer.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, since writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determining means is realized by the direct transfer control means for controlling the direct transfer of data, the host controller of the game medium determining means in the data transfer ( (Processor) is not involved, the parallel processing of each circuit (hardware) included in the game medium determining means is possible, and as a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

[Appendix 1-2]
Embodiment 1-2 of the present invention has the following configuration in Embodiment 1-1.
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
A second storage means (for example, a memory 274) for storing the conversion parameter (for example, the conversion parameter 280),
The coordinate conversion is configured to be performed based on the conversion parameter acquired from the second storage unit.

  With such a configuration of the present invention, the processing content of coordinate conversion can be appropriately changed by changing the conversion parameter. Further, when performing image processing including coordinate conversion in the characteristic image generating means, the conversion parameter can be obtained by accessing the memory in the circuit, access via the bus is avoided, and the bus band is secured, The processing efficiency can be further improved.

[Appendix 1-3]
Embodiment 1-3 of the present invention has the following configuration in Embodiment 1-2.
The characteristic image generating means,
A third storage means (for example, a register 283) for storing the specific information (for example, the specific information 290),
It is configured to specify a conversion parameter used for the coordinate conversion based on the specification information acquired from the third storage means.

  With such a configuration of the present invention, by changing the specific information, the conversion parameter used for the coordinate conversion can be appropriately changed, and as a result, the processing content of the coordinate conversion can be changed.

[Appendix 2-1]
Embodiment 2-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
First storage means (for example, SRAM 243) for storing data,
A conversion unit that performs a predetermined format conversion on the image data obtained through the image capturing unit and stores the image data after the format conversion (for example, target image data 775 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.),
A characteristic image generation unit (for example, a characteristic image generation unit 364, an image recognition accelerator circuit 749, or the like) that generates a characteristic image showing the characteristic of the game medium based on the image data after the format conversion,
The characteristic image generating means,
Image data relating to the image data after the format conversion is acquired from the first storage unit, image processing including coordinate conversion (for example, graphic rotation processing) is performed on the acquired one image data, and Image data after image processing (for example, processed image data 777, characteristic image 362C) is stored in the first storage means,
Including at least two conversion processing modes for said image processing,
In the first conversion processing mode, a plurality of converted image data are generated by individually performing different coordinate conversions on the one image data, and the plurality of converted image data are combined to form one processed image. It is a conversion processing mode that performs image processing to obtain data,
The second conversion processing mode is a conversion processing mode in which a plurality of coordinate conversions are successively and successively overlapped on the one image data to perform image processing to obtain one processed image data.
The game medium determination means is further
Direct transfer control means (for example, DMAC252) for controlling direct transfer of data is provided,
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of the image data after the image processing in the characteristic image generation unit in the first storage unit, This is done by the direct transfer.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, regarding the image processing for generating the characteristic image of the game medium used for determining the game medium, since there are at least two conversion processing modes, the conversion processing mode can be switched according to the characteristics and the situation of the game medium. it can. Furthermore, writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determining means is realized by the direct transfer control means that controls the direct transfer of data, so that the host controller ( (Processor) is not involved, the parallel processing of each circuit (hardware) included in the game medium determining means is possible, and as a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

[Appendix 2-2]
Embodiment 2-2 of the present invention has the following configuration in Embodiment 2-1.
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
A second storage means (for example, a memory 774) for storing the conversion parameter (for example, the conversion parameter 780),
The coordinate conversion is configured to be performed based on the conversion parameter acquired from the second storage unit.

  With such a configuration of the present invention, the processing content of coordinate conversion can be appropriately changed by changing the conversion parameter. Further, when performing image processing including coordinate conversion in the characteristic image generating means, the conversion parameter can be obtained by accessing the memory in the circuit, access via the bus is avoided, and the bus band is secured, The processing efficiency can be further improved.

[Appendix 2-3]
Embodiment 2-3 of the present invention has the following configuration in Embodiment 2-2.
The conversion parameter is configured to be a parameter that specifies coordinate conversion regarding rotation of a predetermined angle.

  With such a configuration of the present invention, it is possible to set the conversion parameter to rotate the figure represented by the image data by a predetermined angle.

[Appendix 2-4]
Embodiment 2-4 of the present invention has the following configuration in any of Embodiments 2-1 to 2-3.
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
A third storage means (eg, memory 774) for storing operation mode information (eg, operation mode information 795),
The conversion processing mode is configured to be determined based on the operation mode information.

  With such a configuration of the present invention, the conversion processing mode can be switched by changing the operation mode information.

[Appendix 2-5]
Embodiment 2-5 of the present invention has the following configuration in Embodiment 2-4.
The operation mode information is configured such that it can be set for each of the image data obtained via the image pickup means.

  With such a configuration of the present invention, the conversion processing mode can be switched for each captured image of the game medium, and a characteristic image according to the situation can be obtained.

[Appendix 3-1]
Embodiment 3-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
First storage means (for example, SRAM 243) for storing data,
A conversion unit that performs a predetermined format conversion on the image data obtained via the image capturing unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.),
A characteristic image generation unit (for example, a characteristic image generation unit 364, an image recognition accelerator circuit 249, etc.) that generates a characteristic image showing the characteristic of the game medium based on the image data after the format conversion,
The characteristic image generating means,
Image data relating to the image data after the format conversion is acquired from the first storage means, image processing including coordinate conversion is performed on the acquired image data, and the image data after the image processing is converted into the first image data. Stored in the storage means,
The processing content of the coordinate conversion is specified by a conversion parameter (for example, conversion parameter 280),
The game medium determination means is further
Direct transfer control means (for example, DMAC252) for controlling direct transfer of data is provided,
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of the image data after the image processing in the characteristic image generation unit in the first storage unit, This is done by the direct transfer.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, by changing the conversion parameter, the processing content of the coordinate conversion can be changed appropriately. Furthermore, writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determining means is realized by the direct transfer control means that controls the direct transfer of data, so that the host controller ( (Processor) is not involved, the parallel processing of each circuit (hardware) included in the game medium determining means is possible, and as a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

[Appendix 3-2]
Embodiment 3-2 of the present invention has the following configuration in Embodiment 3-1.
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
A second storage means (for example, the memory 274) for storing the conversion parameter,
The coordinate conversion is configured to be performed based on the conversion parameter acquired from the second storage unit.

  With such a configuration of the present invention, when performing image processing including coordinate conversion in the characteristic image generating means, the conversion parameter can be obtained by accessing the memory in the circuit, and access via the bus is avoided. As a result, the bus band is secured and the processing efficiency is further improved.

[Appendix 3-3]
Embodiment 3-3 of the present invention has the following configuration in Embodiment 3-1 or Embodiment 3-2.
The conversion parameter is configured to be a parameter for instructing at least one of coordinate conversion regarding rotation, coordinate conversion regarding enlargement, coordinate conversion regarding reduction, and coordinate conversion regarding translation.

  With such a configuration of the present invention, it is possible to instruct the coordinate conversion related to rotation, the coordinate conversion related to enlargement, the coordinate conversion related to reduction, and the coordinate conversion related to translation by the conversion parameter.

[Appendix 4-1]
Embodiment 4-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
First storage means (for example, SRAM 243) for storing data,
A conversion unit that performs a predetermined format conversion on the image data obtained via the image capturing unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.),
A characteristic image generation unit (for example, a characteristic image generation unit 364, an image recognition accelerator circuit 449 or the like) that generates a characteristic image showing the characteristic of the game medium based on the image data after the format conversion,
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
Second storage means (eg, memory 474) for storing the conversion parameter (eg, conversion parameter 480);
A conversion circuit (for example, a conversion circuit 481) that acquires image data related to the image data after the format conversion from the first storage unit and performs image processing including coordinate conversion on the acquired image data;
A control circuit (eg, control circuit 482) that stores the parameter offset (eg, parameter offset 495);
An addition circuit (for example, an addition circuit 485) that adds the conversion parameter and the parameter offset under the control of the control circuit and outputs the addition result to the conversion circuit,
The conversion circuit performs the coordinate conversion based on the addition result by the addition circuit,
The game medium determination means is further
Direct transfer control means (for example, DMAC252) for controlling direct transfer of data is provided,
Storing the image data after the format conversion in the conversion unit in the first storage unit, and storing the image data related to the image data after the image processing obtained by the conversion circuit in the first storage unit. At least one is performed by the direct transfer.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, by adding the conversion parameter and the parameter offset, the coordinate conversion performed based on the conversion parameter can be changed in consideration of the contents of the parameter offset. Furthermore, writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determining means is realized by the direct transfer control means that controls the direct transfer of data, so that the host controller ( (Processor) is not involved, the parallel processing of each circuit (hardware) included in the game medium determining means is possible, and as a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

[Appendix 4-2]
Embodiment 4-2 of the present invention has the following configuration in Embodiment 4-1.
The conversion parameter includes a plurality of coordinates before conversion respectively corresponding to the predetermined coordinates after conversion,
The parameter offset is configured to include an offset for a plurality of coordinates before the conversion.

  With such a configuration of the present invention, by adding the conversion parameter and the parameter offset, the coordinate conversion performed based on the conversion parameter can be controlled to be shifted by the amount designated by the parameter offset.

[Appendix 5-1]
Embodiment 5-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
A processor (eg, host controller 241),
First storage means (for example, SRAM 243) for storing data,
A conversion unit that performs a predetermined format conversion on the image data obtained via the image capturing unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.),
A characteristic image generation unit (for example, a characteristic image generation unit 364, an image recognition accelerator circuit 249, etc.) that generates a characteristic image showing the characteristic of the game medium based on the image data after the format conversion,
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing the conversion parameter (eg, conversion parameter 280);
A conversion circuit (for example, a conversion circuit 281) that acquires image data related to the image data after the format conversion from the first storage unit and performs image processing including coordinate conversion on the acquired image data;
A control circuit (for example, a control circuit 282) that acquires the conversion parameter from the second storage means and outputs the conversion parameter to the conversion circuit.
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The processor controls the conversion parameter to be stored in the second storage unit at a predetermined timing,
The game medium determination means is further
Direct transfer control means (for example, DMAC252) for controlling direct transfer of data is provided,
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of image data relating to the image data after the image processing in the conversion circuit in the first storage unit. Is performed by the direct transfer.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, by storing the conversion parameter in the circuit of the characteristic image generating means and changing the conversion parameter, the processing content of the coordinate conversion can be appropriately changed. Furthermore, since writing and reading of image data to and from the storage means (SRAM or the like) of the game medium determining means is realized by the direct transfer control means for controlling the direct transfer of data, the host controller of the game medium determining means in data transfer ( (Processor) is not involved, the parallel processing of each circuit (hardware) included in the game medium determining means is possible, and as a result, the processing efficiency is improved and the processing time for determining the game medium is shortened.

[Appendix 5-2]
Embodiment 5-2 of the present invention has the following configuration in Embodiment 5-1.
The predetermined timing is configured to be a timing of initial setting of the game medium determination means.

  With such a configuration of the present invention, when the conversion parameter is copied into the circuit at a predetermined timing and the conversion parameter is referred to during coordinate conversion, access to the bus is suppressed.

[Appendix 5-3]
Embodiment 5-3 of the present invention has the following configuration in Embodiment 5-1 or Embodiment 5-2.
The processor is configured to copy only the conversion parameter used for coordinate conversion in the characteristic image generating means out of the conversion parameters stored in the first storage means and store it in the second storage means. To be done.

  With this configuration of the present invention, common conversion parameters are prepared in the first storage means, and only the necessary conversion parameters are copied to the memory in the circuit, so that the control LSI can be manufactured in common. The memory in the circuit can be effectively used.

[Appendix 6-1]
Embodiment 6-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
First storage means (for example, SRAM 243) for storing data,
A conversion unit that performs a predetermined format conversion on the image data obtained via the image capturing unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.),
Characteristic image generation means (for example, characteristic image generation unit 364, image recognition accelerator circuit 249, etc.) that generates a characteristic image (for example, characteristic image 362C) indicating the characteristics of the game medium based on the image data after the format conversion. And
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing the conversion parameter (eg, conversion parameter 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data relating to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, a control circuit 282) that controls the acquisition of the conversion parameter from the second storage unit and the output to the conversion circuit;
An image processing circuit (for example, image processing) that acquires the image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 277) in the first storage unit. Circuit 273),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit,
Third storage means (for example, a frame memory 309) for temporarily storing image data relating to the image data after the coordinate conversion for the image processing,
A first read request output unit (for example, a first read request output unit 301) that outputs a request to read the image data to be subjected to the image processing from the third storage unit,
A write request output unit (for example, a write request output unit 302) that outputs a request to write the image data after the image processing to the third storage unit,
When the image data after the image processing is the image data to be output, a second read request output unit (for example, a second read request output unit that outputs a request to read the image data after the image processing from the third storage unit). A read request output unit 303),
An arbitration unit (for example, arbitration unit 304) that performs arbitration so that the requests output from the first read request output unit, the write request output unit, and the second read request output unit do not conflict with each other. Prepare

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, by providing the arbitration unit, it is possible to avoid conflicting access requests to the third storage unit for image processing.

[Appendix 6-2]
Embodiment 6-2 of the present invention has the following configuration in Embodiment 6-1.
The game medium determination means further includes direct transfer control means (for example, DMAC252) for controlling direct transfer of data,
At least one of storing the image data after the format conversion in the conversion unit in the first storage unit and storing the image data to be output in the image processing circuit in the first storage unit is directly Configured to be done by transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage unit (SRAM or the like) of the game medium determination unit is realized by the direct transfer control unit that controls the direct transfer of the data, and thus the game in the data transfer. The host controller (processor) of the medium determination means does not participate, and the parallel processing of each circuit (hardware) included in the game medium determination means becomes possible. As a result, the processing efficiency is improved and the processing time regarding the determination of the game medium is increased. Is shortened.

[Appendix 7-1]
Embodiment 7-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
First storage means (for example, SRAM 243) for storing data,
A conversion unit that performs a predetermined format conversion on the image data obtained via the image capturing unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.),
Characteristic image generation means (for example, characteristic image generation unit 364, image recognition accelerator circuit 949, etc.) that generates a characteristic image (for example, characteristic image 362C) indicating the characteristics of the game medium based on the image data after the format conversion. And
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing the conversion parameter (eg, conversion parameter 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data relating to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, a control circuit 282) that controls the acquisition of the conversion parameter from the second storage unit and the output to the conversion circuit;
An image processing circuit (for example, image processing) that acquires the image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 977) in the first storage unit. Circuit 973),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit,
Third storage means (for example, a frame memory 909) for temporarily storing image data relating to the image data after the coordinate conversion for the image processing,
A first read request output unit (for example, a first read request output unit 1001) that outputs a request to read the image data to be subjected to the image processing from the third storage unit,
A write request output unit (for example, a write request output unit 1002) that outputs a request to write the image data after the image processing to the third storage unit,
An arbitration unit (for example, an arbitration unit 1004) that performs arbitration so that the respective requests output from the first read request output unit and the write request output unit do not conflict with each other,
When the image data after the image processing is the image data of the output target, an output control unit (for example, an output control unit 1008) that controls to store the image data after the image processing in the first storage unit. And

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, by providing the arbitration unit, it is possible to avoid conflicting access requests to the third storage unit for image processing.

[Appendix 7-2]
Embodiment 7-2 of the present invention has the following configuration in Embodiment 7-1.
The game medium determination means further includes direct transfer control means (for example, DMAC252) for controlling direct transfer of data,
At least one of storage of the image data after the format conversion in the conversion unit in the first storage unit and storage of the image data after the image processing in the output control unit in the first storage unit, It is configured to be done by direct transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage unit (SRAM or the like) of the game medium determination unit is realized by the direct transfer control unit that controls the direct transfer of the data, and thus the game in the data transfer. The host controller (processor) of the medium determination means does not participate, and the parallel processing of each circuit (hardware) included in the game medium determination means becomes possible. As a result, the processing efficiency is improved and the processing time regarding the determination of the game medium is increased. Is shortened.

[Appendix 8-1]
Embodiment 8-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
First storage means (for example, SRAM 243) for storing data,
A conversion unit that performs a predetermined format conversion on the image data obtained via the image capturing unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.),
Characteristic image generation means (for example, characteristic image generation unit 364, image recognition accelerator circuit 249, etc.) that generates a characteristic image (for example, characteristic image 362C) indicating the characteristics of the game medium based on the image data after the format conversion. And
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing the conversion parameter (eg, conversion parameter 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data relating to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, a control circuit 282) that controls the acquisition of the conversion parameter from the second storage unit and the output to the conversion circuit;
An image processing circuit (for example, image processing) that acquires the image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 277) in the first storage unit. Circuit 273),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit,
Third storage means (for example, a frame memory 309) for temporarily storing image data relating to the image data after the coordinate conversion for the image processing,
A first read request output unit (for example, a first read request output unit 301) that outputs a request to read the image data to be subjected to the image processing from the third storage unit,
A write request output unit (for example, a write request output unit 302) that outputs a request to write the image data after the image processing to the third storage unit,
When the image data after the image processing is the image data to be output, a second read request output unit (for example, a second read request output unit that outputs a request to read the image data after the image processing from the third storage unit). A read request output unit 303),
An arbitration unit (for example, arbitration unit 304) that performs arbitration so that the requests output from the first read request output unit, the write request output unit, and the second read request output unit do not conflict with each other. Prepare,
The arbitration unit relates to each output unit of the first read request output unit, the write request output unit, and the second read request output unit, or the first read request output unit and the write request output unit. , And the priority assigned to each of the requests output from the second read request output unit.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, by providing the arbitration unit, it is possible to avoid conflicting access requests to the third storage unit for image processing, and the arbitration by the arbitration unit is performed based on priority.

[Appendix 8-2]
Embodiment 8-2 of the present invention has the following configuration in Embodiment 8-1.
The game medium determination means further includes direct transfer control means (for example, DMAC252) for controlling direct transfer of data,
At least one of storing the image data after the format conversion in the conversion unit in the first storage unit and storing the image data to be output in the image processing circuit in the first storage unit is directly Configured to be done by transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage unit (SRAM or the like) of the game medium determination unit is realized by the direct transfer control unit that controls the direct transfer of the data, and thus the game in the data transfer. The host controller (processor) of the medium determination means does not participate, and the parallel processing of each circuit (hardware) included in the game medium determination means becomes possible. As a result, the processing efficiency is improved and the processing time regarding the determination of the game medium is increased. Is shortened.

[Appendix 8-3]
Embodiment 8-3 of the present invention has the following configuration in Embodiment 8-1 or Embodiment 8-2.
The priority is configured to be changed by a user's operation or according to the operation status of the game medium determination means.

  With such a configuration of the present invention, the priority can be set according to, for example, the user's setting, or can be set according to the bus usage rate of the game medium determination means. The priority effectively reduces the processing time for determining the game medium.

[Appendix 9-1]
Embodiment 9-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
First storage means (for example, SRAM 243) for storing data,
A conversion unit that performs a predetermined format conversion on the image data obtained via the image capturing unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.),
Characteristic image generation means (for example, characteristic image generation unit 364, image recognition accelerator circuit 249, etc.) that generates a characteristic image (for example, characteristic image 362C) indicating the characteristics of the game medium based on the image data after the format conversion. And
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing the conversion parameter (eg, conversion parameter 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data relating to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, a control circuit 282) that controls the acquisition of the conversion parameter from the second storage unit and the output to the conversion circuit;
An image processing circuit (for example, image processing) that acquires the image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 277) in the first storage unit. Circuit 273),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit,
Third storage means (for example, a frame memory 309) for temporarily storing image data relating to the image data after the coordinate conversion for the image processing,
A first read request output unit (for example, a first read request output unit 301) that outputs a request to read the image data to be subjected to the image processing from the third storage unit,
A write request output unit (for example, a write request output unit 302) that outputs a request to write the image data after the image processing to the third storage unit,
When the image data after the image processing is the image data to be output, a second read request output unit (for example, a second read request output unit that outputs a request to read the image data after the image processing from the third storage unit). And a read request output unit 303),
The third storage means is a one-port memory,
The image data after the image processing is written in a predetermined position of the third storage unit based on a request from the write request output unit,
In the third storage means, the predetermined position is image data read out based on the request by the first read request output unit, and image data corresponding to the image data after the image processing is stored. The position.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, when the image data after the image processing is written in the third storage unit, the pixel data of the processed image data is stored at the same position as the storage position of the third storage unit that was stored before the image processing (read modification). Since it is written, the circuit scale of the third storage means can be reduced.

[Appendix 9-2]
Embodiment 9-2 of the present invention has the following configuration in Embodiment 9-1.
The game medium determination means further includes direct transfer control means (for example, DMAC252) for controlling direct transfer of data,
At least one of storing the image data after the format conversion in the conversion unit in the first storage unit and storing the image data to be output in the image processing circuit in the first storage unit is directly Configured to be done by transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage unit (SRAM or the like) of the game medium determination unit is realized by the direct transfer control unit that controls the direct transfer of the data, and thus the game in the data transfer. The host controller (processor) of the medium determination means does not participate, and the parallel processing of each circuit (hardware) included in the game medium determination means becomes possible. As a result, the processing efficiency is improved and the processing time regarding the determination of the game medium is increased. Is shortened.

[Appendix 9-3]
Embodiment 9-3 of the present invention has the following configuration in Embodiment 9-1 or Embodiment 9-2.
The image data after the image processing written in the third storage unit based on the request from the write request output unit is an image to be subjected to the image processing based on the request from the first read request output unit. The data is read from the third storage means.

  With such a configuration of the present invention, the image data after the image processing written in the third storage unit is read again from the third storage unit as the target of the image processing, so that the circuit scale of the third storage unit can be reduced. can do.

[Appendix 10-1]
Embodiment 10-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
First storage means (for example, SRAM 243) for storing data,
A conversion unit that performs a predetermined format conversion on the image data obtained via the image capturing unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.),
Characteristic image generation means (for example, characteristic image generation unit 364, image recognition accelerator circuit 249, etc.) that generates a characteristic image (for example, characteristic image 362C) indicating the characteristics of the game medium based on the image data after the format conversion. And
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing the conversion parameter (eg, conversion parameter 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data relating to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, a control circuit 282) that controls the acquisition of the conversion parameter from the second storage unit and the output to the conversion circuit;
An image processing circuit (for example, image processing) that acquires the image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 277) in the first storage unit. Circuit 273),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit,
Third storage means (for example, a frame memory 309) for temporarily storing image data relating to the image data after the coordinate conversion for the image processing,
A first read request output unit (for example, a first read request output unit 301) that outputs a request to read the image data to be subjected to the image processing from the third storage unit,
A write request output unit (for example, a write request output unit 302) that outputs a request to write the image data after the image processing to the third storage unit,
When the image data after the image processing is the image data to be output, a second read request output unit (for example, a second read request output unit that outputs a request to read the image data after the image processing from the third storage unit). A read request output unit 303),
A buffer (for example, a read buffer 307) that temporarily stores the image data to be subjected to the image processing read from the third storage unit based on the request from the first read request output unit,
The first read request output unit outputs a request to read the image data to be subjected to the image processing from the third storage unit when the buffer is empty.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, when the read buffer is empty, the first read request output unit outputs a request to read the image data to be image-processed from the third storage unit, so that the circuit scale of the read buffer can be reduced. The read timing of the image data is determined by an independent and effective standard.

[Appendix 10-2]
Embodiment 10-2 of the present invention has the following configuration in Embodiment 10-1.
The game medium determination means further includes direct transfer control means (for example, DMAC252) for controlling direct transfer of data,
At least one of storing the image data after the format conversion in the conversion unit in the first storage unit and storing the image data to be output in the image processing circuit in the first storage unit is directly Configured to be done by transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage unit (SRAM or the like) of the game medium determination unit is realized by the direct transfer control unit that controls the direct transfer of the data, and thus the game in the data transfer. The host controller (processor) of the medium determination means does not participate, and the parallel processing of each circuit (hardware) included in the game medium determination means becomes possible. As a result, the processing efficiency is improved and the processing time regarding the determination of the game medium is increased. Is shortened.

[Appendix 10-3]
Embodiment 10-3 of the present invention has the following configuration in Embodiment 10-1 or Embodiment 10-2.
When the image data targeted for the image processing stored in the buffer is read out for the image processing, the image data targeted for the image processing is erased from the buffer.

  With such a configuration of the present invention, when the image data to be image-processed is read out for image processing, the image data is deleted from the read buffer, so that the image data is immediately read out. In addition, the first read request output unit can make a request, and as a result, the image data can be efficiently read into the read buffer sequentially.

[Appendix 11-1]
Embodiment 11-1 of the present invention provides a gaming machine having the following configuration.
An insertion slot (for example, a medal insertion slot 21) for inserting a game medium (for example, a medal),
And a game medium detecting means (for example, a medal selector 201 including a camera unit 209) for detecting a game medium inserted from the slot,
The game medium detection means,
A game medium passing portion (for example, a medal rail 210) which is a passage through which the game medium passes,
Imaging means (for example, means including a CMOS image sensor 232) for imaging a passing object which is an object passing through the passage,
By performing image processing based on the image data obtained through the image pickup means (for example, the imaged image 362A obtained by the image pickup unit 361), it is determined whether or not the game medium is legitimate. And a game medium determining means (for example, control LSI 234),
The game medium determination means,
Configured as a dedicated integrated circuit for determining the game medium,
First storage means (for example, SRAM 243) for storing data,
A conversion unit that performs a predetermined format conversion on the image data obtained via the image capturing unit and stores the image data after the format conversion (for example, target image data 275 and captured image 362B) in the first storage unit. (For example, the conversion unit 363, the ISP circuit 245, etc.),
Characteristic image generation means (for example, characteristic image generation unit 364, image recognition accelerator circuit 249, etc.) that generates a characteristic image (for example, characteristic image 362C) indicating the characteristics of the game medium based on the image data after the format conversion. And
The characteristic image generating means,
Configured as a circuit in the game medium determination means,
Second storage means (eg, memory 274) for storing the conversion parameter (eg, conversion parameter 280);
A conversion circuit (for example, a conversion circuit 281) that performs coordinate conversion on the image data relating to the image data after the format conversion acquired from the first storage unit;
A control circuit (for example, a control circuit 282) that controls the acquisition of the conversion parameter from the second storage unit and the output to the conversion circuit;
An image processing circuit (for example, image processing) that acquires the image data after the coordinate conversion from the conversion circuit, performs image processing, and stores image data to be output (for example, processed image data 277) in the first storage unit. Circuit 273),
The conversion circuit performs the coordinate conversion based on the conversion parameter,
The image processing circuit,
Third storage means (for example, a frame memory 309) for temporarily storing image data relating to the image data after the coordinate conversion for the image processing,
A first read request output unit (for example, a first read request output unit 301) that outputs a request to read the image data to be subjected to the image processing from the third storage unit,
A write request output unit (for example, a write request output unit 302) that outputs a request to write the image data after the image processing to the third storage unit,
When the image data after the image processing is the image data to be output, a second read request output unit (for example, a second read request output unit that outputs a request to read the image data after the image processing from the third storage unit). A read request output unit 303),
A buffer (for example, a write buffer 306) for temporarily storing the image data after the image processing,
When a predetermined amount of image data is stored in the buffer (for example, when the write buffer 306 is full), the write request output unit outputs the image data after the image processing from the buffer to the third image data. A request to write to the storage means is output.

  With such a configuration of the present invention, it is possible to execute the regular medal determination process using the image data acquired by the image pickup means. Since it is possible to determine a medal or the like by each processing of image conversion and image recognition performed based on the captured image, it is possible to determine the difference in the pattern of the medal or the like. Further, since the game medium determining means is configured as a dedicated integrated circuit for determining the game medium, the manufacturing cost can be effectively suppressed. Furthermore, since the game medium determination means is provided in a packaged state such as an ASIC, a fraudulent act from the outside (for example, invalidating the regular medal discrimination process or a process logic of the regular medal discrimination process is executed). It has a remarkable advantage in terms of security as well. Further, when the write buffer is full, the write request output unit outputs a request to write the image data after the image processing to the third storage means, so that the circuit scale of the write buffer can be reduced. The writing timing of the image data is determined by an independent and effective standard.

[Appendix 11-2]
Embodiment 11-2 of the present invention has the following configuration in Embodiment 11-1.
The game medium determination means further includes direct transfer control means (for example, DMAC252) for controlling direct transfer of data,
At least one of storing the image data after the format conversion in the conversion unit in the first storage unit and storing the image data to be output in the image processing circuit in the first storage unit is directly Configured to be done by transfer.

  With such a configuration of the present invention, writing and reading of image data to and from the storage unit (SRAM or the like) of the game medium determination unit is realized by the direct transfer control unit that controls the direct transfer of the data, and thus the game in the data transfer. The host controller (processor) of the medium determination means does not participate, and the parallel processing of each circuit (hardware) included in the game medium determination means becomes possible. As a result, the processing efficiency is improved and the processing time regarding the determination of the game medium is increased. Is shortened.

[Appendix 11-3]
Embodiment 11-3 of the present invention has the following configuration in Embodiment 11-1 or Embodiment 11-2.
When the image data after the image processing stored in the buffer is written in the third storage unit, the image data after the image processing is erased from the buffer.

  With such a configuration of the present invention, when the image data to be image-processed is written in the third storage means, the image data is erased from the write buffer, so immediately after the image data is written, Requests can be made from the write request output unit, and as a result, efficient writing of image data to the write buffer is sequentially performed.

1 Pachi-slot 3L Left reel 3C Middle reel 3R Right reel 4 Reel display window 21 Medal slot 23 Start lever 32 Medal payout outlet 51 Hopper device 71 Main control board 72 Sub control board 79 Start switch 80 Stop switch board 91 Main control circuit 101 Sub Control circuit 201 Medal selector 202 Medal shoot 203 Slope 204 Base plate 205 Sub-plate 206 Cancel shooter 207 Select plate 208 Medal solenoid 209 Camera unit 210 Medal rail 211 Medal inlet 212 Central hole 213 Medal pressure 217 Magnet 218 After medal pressure 227 Medal Stopper 230 First substrate 231 Second substrate 232 CMOS image sensor 233 LED
234 Control LSI
235 Legs 241 Host controller 242 Image recognition DSP circuit 243 SRAM
244 Flash memory 245 ISP circuit 246 Medal counting circuit 247 Color recognition circuit 248 Fisheye correction scaler circuit 249, 449, 549, 749, 949 Image recognition accelerator circuit 250 GPIO
251 ISI circuit 252 DMAC
261, 361 Imaging unit 262, 362A Captured image 362B Captured image 362C Characteristic image 263, 363 Conversion unit 264, 364 Characteristic image generation unit 265, 365 Determination unit 266, 366 Input / output unit 267, 367 Template data 268, 368 Determination result 271 , 471,571,771,971 Input frame buffer 272,472,572,772,972 Coordinate conversion circuit 273,473,573,773,973 Image processing circuit 274,474,574,774,974 Memory 275,475,575 , 775 Target image data 276, 476, 576, 776, 976 Converted image data 277, 577, 777, 977 Processed image data 280, 480, 580, 780 Conversion parameter 281, 481, 581, 781 Conversion Circuit 282,482,582,782 Control circuit 283,483,583,783 Register 290,490,590,790 Specific information 300,600,800,1000 Storage controller 301,601,801,1001 First read request output unit 302, 602, 802, 1002 Write request output section 303, 603, 803 Second read request output section 304, 604, 804, 1004 Arbitration section 305, 805, 1005 Addition processing section 306, 606, 706, 1006 Write buffer 307 , 607, 707, 1007 read buffer 308, 608, 708, 1008 output control unit 309, 609, 709, 909 frame memory 370 first image generation unit 371 extraction unit 372 edge image generation unit 374 first image 380 second image generation Part 400 Tadashi Medals 310, 410 Medals 485 adder circuit 495 parameter offset 585,785 selecting circuit 795 operation mode information 806 selection circuit

Claims (2)

An input port for inputting game media,
And a game medium detecting means for detecting the game medium input from the input port,
The game medium detection means,
A game medium passing portion which is a passage through which the game medium passes,
Imaging means for imaging a passing object which is an object passing through the passage,
A game medium determining unit that determines whether or not the game medium is a regular one by performing image processing based on the image data obtained through the image capturing unit,
The game medium determination means,
Direct transfer control means for controlling direct transfer of data,
Storage means capable of storing data,
The image data obtained via the image pickup means is acquired from the storage means by the direct transfer control means, a predetermined format conversion is performed, and the image data after the format conversion is stored in the storage means by the direct transfer. Conversion means to
A characteristic image generating means for generating a characteristic image showing the characteristic of the game medium based on the image data after the format conversion,
The characteristic image generating means,
Image data relating to the image data after the format conversion is acquired from the storage unit, image processing including coordinate conversion is performed on the acquired image data, and the image data after the image processing is transferred by the direct transfer. A game machine characterized by being stored in a storage means. A game medium passing portion that is a passage through which the game medium passes,
Imaging means for imaging a passing object which is an object passing through the passage,
A game medium determining unit that determines whether or not the game medium is a regular one by performing image processing based on the image data obtained through the image capturing unit,
The game medium determination means,
Direct transfer control means for controlling direct transfer of data,
Storage means capable of storing data,
The image data obtained via the image pickup means is acquired from the storage means by the direct transfer control means, a predetermined format conversion is performed, and the image data after the format conversion is stored in the storage means by the direct transfer. Conversion means to
A characteristic image generating means for generating a characteristic image showing the characteristic of the game medium based on the image data after the format conversion,
The characteristic image generating means,
Image data relating to the image data after the format conversion is acquired from the storage unit, image processing including coordinate conversion is performed on the acquired image data, and the image data after the image processing is transferred by the direct transfer. A game medium discrimination device characterized by storing in a storage means.

Images