JP2020061149A5 - - Google Patents

Claims (20)

a system,
NVMe (Non-Volatile Memory Express) SSD (Solid State Drive);
a Peripheral Component Interconnect Express (PCIe) switch containing Erasure Coding Logic;
The PCIe switch is
an external connector that enables the PCIe switch to communicate with a processor;
at least one connector that enables the PCIe switch to communicate with the NVMe SSD;
a power processing unit (PPU) that configures the PCIe switch;
an erasure coding controller having circuitry for applying an erasure coding scheme to data stored on the NVMe SSD. The system includes:
a second NVMe SSD;
a second PCIe switch;
The second PCIe switch
a second external connector enabling the second PCIe switch to communicate with the processor;
a second connector enabling the second PCIe switch to communicate with the second NVMe SSD;
a third connector enabling the second PCIe switch to communicate with the PCIe switch containing the erasure coding logic;
the PCIe switch containing the erasure coding logic includes a fourth connector that enables the PCIe switch containing the erasure coding logic to communicate with the second PCIe switch;
The system of claim 1, wherein the erasure coding scheme is applied to data stored on the NVMe SSD and the second NVMe SSD. 2. The erasure coding logic of claim 1, wherein the erasure coding logic operates to return a response to the read request from a host based at least in part on the residing of data requested by the read request in a cache. system. The system of claim 1, wherein the erasure coding logic operates to return a response to the write request to the host prior to completing the write request. The erasure coding logic intercepts data transmissions received at the PCIe switch from a host and converts the host's LBA (Logical Block Address) used by the host in the data transmission to the device's LBA used by the NVMe SSD. 2. The system of claim 1, wherein the system operates as an alternative to 2. The system of claim 1 , further comprising a second device coupled to the PCIe switch containing the erasure coding logic. the second device includes at least one of a storage device and a non-storage device having native erasure coding logic;
7. The system of claim 6 , wherein the PCIe switch containing the erasure coding logic operates to disable the erasure coding logic based at least in part on the second device. . the second device includes at least one of a storage device and a non-storage device having native erasure coding logic;
7. The system of claim 6 , wherein the PCIe switch containing the erasure coding logic is operable to enable the erasure coding logic and disable access to the second device. the system further comprising a second NVMe SSD;
2. The system of claim 1, wherein the PCIe switch containing erasure coding logic includes a second connector that enables the PCIe switch containing erasure coding logic to communicate with the second NVMe SSD. . 3. The system of claim 2, wherein the second PCIe switch further comprises disabled second erasure coding logic. 4. The system of claim 3, the erasure coding logic further comprising the cache. the PCIe switch containing the erasure coding logic is located in a chassis;
4. The system of claim 3, wherein the chassis contains memory used as the cache by the erasure coding logic. the PCIe switch containing the erasure coding logic further includes a write buffer;
5. The system of claim 4, wherein the erasure coding controller is operable to store data in the write request in the write buffer. The erasure coding logic includes Look-Aside erasure coding logic;
2. The system of claim 1 , wherein the Look-Aside erasure coding logic includes snooping logic. 6. The system of claim 5, wherein the erasure coding logic is further operable to direct the data transmission to the NVMe SSD. The erasure coding logic intercepts data transmissions received at the PCIe switch from the NVMe SSDs and replaces device LBAs used by the NVMe SSDs with host LBAs used by a host in the data transmissions . 2. The system of claim 1 , wherein the system operates in 2. The system of claim 1, wherein the erasure coding logic defines a virtual storage device across the NVMe SSD and a second NVMe SSD. The PCIe switch containing the erasure coding logic operates to enable the erasure coding logic based at least in part on the NVMe SSD being a storage device that does not contain native erasure coding logic. The system of claim 1 , wherein: 7. The system of claim 6, wherein the second device includes at least one of a storage device, an SSD including a Field Programmable Gate Array (FPGA), and a Graphics Processing Unit (GPU). the second device includes at least one of a storage device and a non-storage device having native erasure coding logic;
7. The system of claim 6 , wherein the PCIe switch containing the erasure coding logic is operable to enable the erasure coding logic and disable access to the second device.