CN112148227B - Storage device and information processing method - Google Patents
Storage device and information processing method Download PDFInfo
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- CN112148227B CN112148227B CN202011026508.0A CN202011026508A CN112148227B CN 112148227 B CN112148227 B CN 112148227B CN 202011026508 A CN202011026508 A CN 202011026508A CN 112148227 B CN112148227 B CN 112148227B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0626—Reducing size or complexity of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the application discloses a storage device, which comprises: the data transmission module comprises a first data interface and a second data interface, the first data interface is connected with an external data source, and the data transmission module is used for transmitting data between the external data source and the data storage module and managing the transmitted data; the data storage module comprises a third data interface and at least two fast nonvolatile storage (NVMe) units, the second data interface is connected with the third data interface, and the data storage module is used for storing the transmission data. The embodiment of the application also discloses an information processing method.
Description
Technical Field
The present application relates to the field of storage and recording technologies, and in particular, to a storage device and an information processing method.
Background
The high-speed data recording technology is the realization basis of modern signal processing technology, and in many signal processing application scenarios, such as astronomical telescopes and synthetic aperture radars, etc., the real-time processing and recording of high-speed data are greatly required.
A conventional high speed data recording device usually adopts a computer and memory unit architecture, for example, as shown in fig. 1, a conventional high speed data recording device 1 includes: a data connection Unit 11, a Central Processing Unit (CPU) 12, and a data storage Unit 13. As shown in fig. 1, the data connection unit 11 is configured to connect the external data source 2 and the CPU 12 to implement data transmission between the external data source and the CPU 12; the CPU 12 is used for controlling the output or input data stream to realize the transmission between the data connection unit and the data storage unit; the data storage unit 13 is used to store data under the control of the CPU 12.
However, the conventional high-speed data recording device is a structure in which a computer is matched with a storage unit, so that the problems of complex system, poor portability, high maintenance difficulty and the like exist in the actual use process, so that the application scene of the conventional high-speed data recording device is single, and the storage flow of the stored data is complex. Therefore, in order to address the complex application scenario, it is necessary to provide a new high-speed data storage device.
Content of application
In order to solve the above technical problems, embodiments of the present application desirably provide a storage device and an information processing method, so as to solve the problem that the flow of storing data in a high-speed data recording device is complicated due to the fact that a recording function of the high-speed data recording device is implemented by relying on a computer CPU at present, reduce the system complexity of the high-speed data recording device, effectively shorten the data transmission flow in the high-speed data recording device, and improve the portability of the high-speed data recording device.
The technical scheme of the application is realized as follows:
in a first aspect, a storage device, the device comprising: the data transmission module and the data storage module; wherein:
the data transmission module comprises a first data interface and a second data interface, the first data interface is connected with an external data source, and the data transmission module is used for transmitting data between the external data source and the data storage module and managing the transmitted data;
the data storage module comprises a third data interface and at least two fast nonvolatile storage (NVMe) units, the second data interface is connected with the third data interface, and the data storage module is used for storing the transmission data.
Optionally, the data transmission module includes: a field programmable gate array FPGA; wherein:
the FPGA is used for managing the transmission data between the external data source and the data storage module.
Optionally, the second data interface and the third data interface are PCIe buses of high-speed serial computer expansion bus standard; wherein the number of interfaces of the third data interface is the same as the number of the at least two NVMe units.
Optionally, the data transmission module is configured to, after establishing a communication connection with the external data source through the first data interface, when receiving a data storage instruction sent by the external data source through the first data interface, respond to the data storage instruction, receive first target data sent by the external data source through the first data interface, determine n NVMe units from the at least two NVMe units, allocate the first target data to n sub-target data, and send the n sub-target data to the n NVMe units in parallel through the second data interface and the third data interface; wherein n is greater than or equal to 2 and less than or equal to the number of the at least two NVMe units, the data storage instruction is used to instruct the storage device to store the first target data;
and the NVMe unit stores the sub-target data if receiving the sub-target data sent by the data transmission module.
Optionally, the data transmission module is further configured to, after establishing a communication connection with the external data source through the first data interface, respond to the data playback instruction when receiving the data playback instruction sent by the external data source through the first data interface, obtain second target data corresponding to the data playback instruction from the at least two NVMe units, and send the second target data to the external data source through the first data interface.
Optionally, the data transmission module is further configured to establish a communication connection with a control device through the first data interface, receive a management control instruction sent by the control device, respond to the management control instruction, and execute a target operation corresponding to the management control instruction on third target data stored in the at least two NVMe units; wherein the third target data corresponds to the management control instruction, and the target operation at least includes: a query operation, a write operation, a read operation, and a delete operation.
Optionally, the first data interface and the external data source are in communication connection based on a remote communication protocol.
Optionally, the number of the at least two NVMe units is the same as the number of PCIe hard cores in the FPGA.
In a second aspect of the present invention, an information processing method is applied to a storage device, where the storage device includes a first data interface, a data transmission module, and a data storage module, and the method includes:
establishing communication connection with an external data source through a first data interface;
receiving an operation instruction sent by the external data source through the first data interface;
responding to the operation instruction through the data transmission module, and performing storage management operation on the data storage module; the data storage module comprises at least two NVMe units, and the storage management operation corresponds to the operation instruction.
Optionally, the performing, by the data transmission module, a storage management operation on the data storage module in response to the operation instruction includes:
if the operation instruction is a data storage instruction, responding to the data storage instruction through the data transmission module, and receiving first target data sent by the external data source through the first data interface; wherein the data storage instructions are to instruct the storage device to store the first target data;
determining n NVMe units from the at least two NVMe units by the data transfer module; wherein n is greater than or equal to 2 and less than or equal to the number of the at least two NVMe units;
distributing the first target data into n parts of sub-target data through the data transmission module;
the n parts of sub-target data are stored in the n NVMe units in parallel through the data transmission module; wherein the storage management operation comprises the parallel storage.
Optionally, the responding, by the data transmission module, the operation instruction to perform a storage management operation on the data storage module further includes:
if the operation instruction is a data playback instruction, responding to the data playback instruction through the data transmission module, and acquiring second target data corresponding to the data playback instruction from the at least two NVMe units; wherein the storage management operation comprises an operation of acquiring the second target data from the at least two NVMe units, and the data playback instruction is used for instructing the storage device to play back the stored second target data;
and sending the second target data to the external data source through the first data interface.
Optionally, the data transmission module is an FPGA.
Optionally, the data transmission module and the data storage module are connected by a PCIe bus, and the number of the PCIe bus is the same as the number of the at least two NVMe units.
Optionally, if a management control instruction sent by the control device is received through the first data interface, responding to the management control instruction through the data transmission module, and executing a target operation corresponding to the management control instruction on third target data stored in the at least two NVMe units; wherein the third target data corresponds to the management control instruction, and the target operation at least includes: the storage management operation comprises a query operation, a write operation, a read operation and a delete operation, and the storage management operation comprises the target operation.
The storage device and the information processing method provided by the embodiment of the application comprise a data transmission module and a data storage module, wherein: the data storage module comprises a third data interface and at least two fast nonvolatile storage NVMe units, the second data interface is connected with the third data interface, and the data storage module is used for storing and transmitting data. Therefore, the storage device which is composed of the data transmission module and the data storage module and provides storage service for the external data source does not depend on the CPU of the computer to realize the storage function of the external data source any more, solves the problem that the flow of storing data in the high-speed data recording device is complex because the recording function of the high-speed data recording device is realized by depending on the CPU of the computer at present, reduces the system complexity of the high-speed data recording device, effectively shortens the data transmission flow in the high-speed data recording device, and improves the portability of the high-speed data recording device.
Drawings
Fig. 1 is a schematic structural diagram of a conventional high-speed data recording apparatus according to an embodiment of the present application;
fig. 2 is a schematic flowchart of an information processing method according to an embodiment of the present application;
fig. 3 is a schematic flowchart of another information processing method according to an embodiment of the present application;
fig. 4 is a schematic flowchart of another information processing method according to an embodiment of the present application;
fig. 5 is a schematic flowchart of an information processing method according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of a storage device according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of another storage device according to an embodiment of the present application.
Detailed Description
It should be noted that the references to "one", "another", and "another" in the description of the drawings are not intended to limit a certain embodiment. In some application scenarios, the various embodiments in the present application may be combined arbitrarily without conflict.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
An embodiment of the present application provides an information processing method, and as shown in fig. 2, the method is applied to a storage device, where the storage device includes a first data interface, a data transmission module, and a data storage module, and the method includes the following steps:
In embodiments of the present application, the external data sources may be lidar signals, aircraft flight detection data, network communication data, and the like. The communication connection between the first data interface and the external data source may be implemented using a telecommunication protocol.
In the embodiment of the present application, the operation instruction sent by the external data source is an instruction for performing operation control on the storage device, and may be, for example, a data storage instruction or a data playback instruction.
And 303, responding to the operation instruction through the data transmission module, and performing storage management operation on the data storage module.
The data storage module comprises at least two NVMe units, and the storage management operation corresponds to the operation instruction. The data transmission module and the data storage module are connected through a PCIe bus, and the number of the PCIe bus is the same as that of the at least two NVMe units.
In this embodiment of the present application, a data transmission module in a storage device, in response to an operation instruction, performs a corresponding storage management operation on a data storage module according to the content of the operation instruction, where the storage management operation may be, for example, a data storage operation, and may also be a data playback operation.
The number of buses of the PCIe bus is the same as that of at least two NVMe units, namely, one NVMe unit corresponds to one PCIe bus.
According to the information processing method provided by the embodiment of the application, firstly, communication connection is established with an external data source through a first data interface, an operation instruction sent by the external data source is received through the first data interface, and then, the operation instruction is responded through a data transmission module, and storage management operation is performed on at least two NVMe units. Therefore, the storage device which is composed of the data transmission module and the data storage module and provides storage service for the external data source does not depend on the CPU of the computer to realize the storage function of the external data source any more, solves the problem that the flow of storing data in the high-speed data recording device is complex because the recording function of the high-speed data recording device is realized by depending on the CPU of the computer at present, reduces the system complexity of the high-speed data recording device, effectively shortens the data transmission flow in the high-speed data recording device, and improves the portability of the high-speed data recording device.
Based on the foregoing embodiments, an embodiment of the present application provides an information processing method, as shown in fig. 3, where the method is applied to a storage device, the storage device includes a first data interface, a data transmission module, and a data storage module, and the method includes the following steps:
In the embodiment of the present application, the external data source is taken as an example of aircraft flight detection data, and the storage device establishes a communication link with the external data source based on a remote communication protocol, for example, an ethernet protocol.
In this embodiment of the application, the operation instruction sent by the external data source may be automatically sent to the storage device by the external data source according to a preset setting, for example, the external data source is timed to send to the storage device.
And 403, if the operation instruction is a data storage instruction, responding to the data storage instruction through the data transmission module, and receiving first target data sent by an external data source through the first data interface.
The data storage instruction is used for instructing the storage device to store first target data sent by an external data source.
In this embodiment of the present application, the data transmission module may be specifically implemented by an FPGA, and the corresponding first data interface may be an ethernet data channel. Correspondingly, after receiving first target Data sent by an external Data source, the FPGA stores the first target Data in a Double Data Rate (DDR) included in the FPGA for caching, so that the Data transmission module performs corresponding processing on the received first target Data to determine an NVMe unit to be stored. The processing of the first target data by the data transmission module at least comprises identification, disassembly and distribution.
And 404, determining n NVMe units from the at least two NVMe units through the data transmission module.
The data transmission module is connected with the data storage module through a PCIe bus, and the number of the PCIe bus is the same as that of the at least two NVMe units.
In this embodiment, in some application scenarios, the data transmission module may determine n NVMe units from the at least two NVMe units according to the received first target data, for example, the n NVMe units may be determined according to the size of the first target data. In some application scenarios, the storage device may also determine n NVMe units according to a storage state of each of the at least two NVMe units, for example, when n preset numbers are provided, after the data transmission module sorts remaining storage spaces of the NVMe units in the at least two NVMe units, the NVMe units with larger n remaining storage spaces are sequentially selected to obtain the n NVMe units, or n is an uncertain number, and the NVMe units with larger remaining storage spaces than a preset threshold are directly determined from the at least two NVMe units to obtain the n NVMe units.
In an embodiment of the present application, the data transmission module may equally allocate the first target data into n shares.
And 406, storing the n parts of sub-target data into the n NVMe units in parallel through the data transmission module.
Wherein n is greater than or equal to 2 and less than or equal to the number of at least two NVMe units, and the storage management operation comprises parallel storage.
In the embodiment of the application, the data transmission module transmits n parts of sub-target data to n NVMe units in parallel, wherein one part of sub-target data is transmitted to one NVMe unit. Therefore, the parallelization of data transmission is achieved by utilizing the characteristics of the FPGA, the data input and output of a multi-channel data source are supported, the transmission rate loss caused by the mutual coupling among channels is avoided, and the complexity of an FPGA control program is greatly simplified. By storing data in multiple NVMe units, expansion of storage speed and storage capacity is achieved.
In other embodiments of the present application, referring to fig. 4, after the storage device performs step 402, it may select to perform steps 407 to 408:
The storage management operation comprises an operation of acquiring second target data from at least two NVMe units, and the data playback instruction is used for instructing the storage device to play back the stored second target data.
In an embodiment of the present application, the second target data is history data stored in the storage device. After the storage device receives the data playback instruction, the data playback instruction is responded through the FPGA, the NVMe unit in which the subdata belonging to the second target data is stored is determined from the at least two NVMe units, the subdata of the second target data is read out from the subdata in which the second target data is stored to the DDR of the FPGA, and then the read subdata of the second target data is correspondingly assembled according to the splitting sequence to obtain the second target data.
And step 408, sending the second target data to an external data source through the first data interface.
In the embodiment of the application, the storage device sends the complete second target data to the external data source through the first data interface.
In other embodiments of the present application, after the storage device performs step 402, as shown in fig. 5, step 409 may also be optionally performed:
Wherein the third target data corresponds to the management control instruction, and the target operation at least includes: the system comprises an inquiry operation, a write operation, a read operation and a delete operation, wherein the storage management operation comprises a target operation.
In the embodiment of the present application, the control device may be a device that performs management control on the storage device, and may be, for example, a local server or a computer device corresponding to the storage device.
Based on the foregoing embodiments, an application scenario of a storage device is provided in the embodiments of the present application, and referring to fig. 6, a data communication connection is established between the storage device 6 and an external data source or server 5, where the storage device 6 includes: FPGA 61 and 4 NVMe 62 memories. Wherein: the FPGA 61 connects the external data source or server 5 with the 4 NVMe 62 memories to implement control operations on transmission data streams between the external data source or server 5 and the 4 NVMe 62 memories, where the control operations include integration, splitting, and bidirectional transmission of the data streams. The FPGA 61 establishes a connection with an external data source or server 5 via a telecommunications protocol, such as a gigabit ethernet, fibre optics, etc. When the FPGA controls the transmission data stream, the data stream can be carried through Direct Memory Access (DMA) in the FPGA, so that two paths of transmission of the data stream from the external data source to the data storage module and transmission of the data stream from the data storage module to the external data source are realized.
The 4 NVMe 62 memories constitute the aforementioned data storage module, and are used to implement high-bandwidth and large-capacity storage of data, four data channels are provided between the FPGA 61 and the 4 NVMe 62 memories, each memory corresponds to one data channel, and the data channels may specifically be PCIe buses. And the number of the NVMe memories is the PCIe hard core number in the FPGA. The NVMe memory at least comprises three parts of DDR, NVMe controller and Nand Flash memory (Flash).
Based on the storage device shown in fig. 6, when the storage device receives a data storage instruction sent by an external data source, the storage device is in a data recording mode. At this moment, after the FPGA establishes Ethernet connection with an external data source, the FPGA informs the NVMe controller to initialize, and the initialization process comprises the following steps: a Physical Region Page (PRP) list, a user command queue, and an IO command list are created. The FPGA starts a timer and informs the NVMe controller to read the file storage allocation table from the FPGA, wherein the FPGA sends the file storage allocation table to the NVMe memory at regular time so as to update the file storage allocation table stored in the NVMe memory. Specifically, the FPGA acquires a data storage request sent by an external data source in a polling manner, and then caches serial data sent by the external data source in the DDR of the FPGA by using the DMA, and updates the file storage allocation table according to storage table entry information of the data storage request. Meanwhile, the FPGA specifies the size of a data strip, namely the size of each piece of sub-target data after splitting the received first target data, calculates a first address and the size of the data, the first address is a starting address when the sub-target data is stored in each Nand Flash in the NVMe memory, and then sends a write-in command to the NVMe Host (Host) module. And the NVMe Host module selects a corresponding NVMe controller in an RAID0 mode according to the write command and submits an Input/Output (IO) submission queue request. After the NVMe controller finishes data storage, the IO completion queue is updated, the FPGA polls the IO completion queue, and the IO operation completion state is returned. And when the data storage is finished, the FPGA executes a data refreshing command and updates the file storage allocation table into the NVMe memory.
Based on the storage device shown in fig. 6, when the storage device receives a data playback instruction sent by an external data source, the storage device is in a data playback mode. At this moment, after the FPGA establishes Ethernet connection with an external data source, the FPGA informs the NVMe controller to initialize, and the initialization process comprises the following steps: a Physical Region Page (PRP) list, a user command queue, and an IO command list are created. The FPGA starts a timer and informs the NVMe controller to read the file storage allocation table from the FPGA, wherein the FPGA sends the file storage allocation table to the NVMe memory at regular time so as to update the file storage allocation table stored in the NVMe memory. The FPGA acquires a data playback request sent by an external data source in a polling mode, determines the size, the first address and the cache index of a data strip specified by second target data requested in the data playback request, and sends a read command to the NVMe Host module. And the NVMe Host module selects a corresponding NVMe controller in a RAID0 mode according to the read command and submits an IO submission queue request. And after the NVMe controller finishes data reading, updating the IO completion queue. And polling an IO completion queue by the FPGA, returning an IO operation completion state, converting data in the DDR into serial data by using the DMA and transmitting the serial data. And when the data playback is finished, the FPGA executes a data refreshing command and updates the storage allocation table into the memory.
In other application scenarios, the file management function of the storage device further supports classification storage according to data types, and provides functions of querying, writing, reading, deleting and the like of files through an ethernet interface.
It should be noted that, for the description of the same steps and the same contents in this embodiment as those in other embodiments, reference may be made to the description in the other embodiments, which is not repeated herein.
According to the information processing method provided by the embodiment of the application, firstly, communication connection is established with an external data source through a first data interface, an operation instruction sent by the external data source is received through the first data interface, and then, the operation instruction is responded through a data transmission module, and storage management operation is performed on at least two NVMe units. Therefore, the storage device which is composed of the data transmission module and the data storage module and provides storage service for the external data source does not depend on the CPU of the computer to realize the storage function of the external data source any more, solves the problem that the flow of storing data in the high-speed data recording device is complex because the recording function of the high-speed data recording device is realized by depending on the CPU of the computer at present, reduces the system complexity of the high-speed data recording device, effectively shortens the data transmission flow in the high-speed data recording device, and improves the portability of the high-speed data recording device. The data transmission module and the data storage module are in communication connection by adopting a plurality of PCIe buses and a plurality of NVMe units, so that the transmission bandwidth is improved, the transmission delay is reduced, the data transmission module is realized by utilizing the FPGA, the parallelization of data transmission is realized by effectively utilizing the characteristics of the FPGA, the data input and output of a multi-channel data source can be supported, the transmission rate loss caused by mutual coupling among channels is avoided, and the improvement of the storage speed and the reading speed and the capacity expansion of the storage capacity are effectively finished. And by adopting the FPGA and the NVMe units, the integration level of the storage equipment is effectively improved, the size and the weight of the storage equipment are effectively reduced, and the use experience of a user is ensured.
Based on the foregoing embodiments, an embodiment of the present application provides a storage device, where the storage device may be applied to the information processing method provided in the embodiments corresponding to fig. 2 to 5, and as shown in fig. 7, the storage device 7 may include: a data transmission module 71 and a data storage module 72; wherein:
the data transmission module 71 comprises a first data interface 711 and a second data interface 712, wherein the first data interface 711 is connected with an external data source, and the data transmission module is used for transmitting data between the external data source and the data storage module and managing the transmitted data;
and the data storage module 72 comprises a third data interface 721 and at least two fast nonvolatile storage (NVMe) units 722, wherein the second data interface is connected with the third data interface, and the data storage module is used for storing transmission data.
Note that the external data source is not shown in fig. 7.
In other embodiments of the present application, the data transmission module comprises a field programmable gate array FPGA;
wherein:
and the FPGA is used for managing the transmission data between the external data source and the data storage module.
In other embodiments of the present application, the second data interface and the third data interface are PCIe buses of high-speed serial computer expansion bus standard; wherein the number of interfaces of the third data interface is the same as the number of the at least two NVMe units.
In other embodiments of the present application, the data transmission module is configured to, after establishing a communication connection with an external data source through a first data interface, when receiving a data storage instruction sent by the external data source through the first data interface, respond to the data storage instruction, receive first target data sent by the external data source through the first data interface, determine n NVMe units from at least two NVMe units, allocate the first target data to n sub-target data, and send the n sub-target data to the n NVMe units in parallel through a second data interface and a third data interface; the data storage instruction is used for indicating the storage equipment to store first target data sent by an external data source;
and the NVMe unit stores the sub-target data if receiving the sub-target data sent by the data transmission module.
In other embodiments of the present application, the data transmission module is further configured to, after establishing a communication connection with an external data source through the first data interface, respond to a data playback instruction when receiving the data playback instruction sent by the external data source through the first data interface, obtain second target data corresponding to the data playback instruction from the at least two NVMe units, and send the second target data to the external data source through the first data interface.
In other embodiments of the present application, the data transmission module is further configured to establish a communication connection with the control device through the first data interface, receive a management control instruction sent by the control device, respond to the management control instruction, and execute a target operation corresponding to the management control instruction on third target data stored in the at least two NVMe units; wherein the third target data corresponds to the management control instruction, and the target operation at least includes: query operation, write operation, read operation, and delete operation.
In other embodiments of the present application, the first data interface and the external data source are communicatively coupled based on a remote communication protocol.
In other embodiments of the present application, the number of the at least two NVMe units is the same as the number of PCIe hardcores in the FPGA.
It should be noted that, in this embodiment, a specific implementation process of information interaction between modules may refer to an implementation process in the information processing method provided in the embodiments corresponding to fig. 2 to 5, and is not described here again.
The storage device provided by the embodiment of the application comprises a data transmission module and a data storage module, wherein: the data storage module comprises a third data interface and at least two fast nonvolatile storage NVMe units, the second data interface is connected with the third data interface, and the data storage module is used for storing and transmitting data. Therefore, the storage device which is composed of the data transmission module and the data storage module and provides storage service for the external data source does not depend on the CPU of the computer to realize the storage function of the external data source any more, solves the problem that the flow of storing data in the high-speed data recording device is complex because the recording function of the high-speed data recording device is realized by depending on the CPU of the computer at present, reduces the system complexity of the high-speed data recording device, effectively shortens the data transmission flow in the high-speed data recording device, and improves the portability of the high-speed data recording device. The data transmission module and the data storage module are in communication connection by adopting a plurality of PCIe buses and a plurality of NVMe units, so that the transmission bandwidth is improved, the transmission delay is reduced, the data transmission module is realized by utilizing the FPGA, the parallelization of data transmission is realized by effectively utilizing the characteristics of the FPGA, the data input and output of a multi-channel data source can be supported, the transmission rate loss caused by mutual coupling among channels is avoided, and the improvement of the storage speed and the reading speed and the expansion of the storage capacity are effectively finished. And the FPGA and the NVMe units are adopted, so that the integration level of the storage equipment is effectively improved, the size and the weight of the storage equipment are effectively reduced, and the use experience of a user is ensured.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application.
Claims (12)
1. A storage device, the device comprising: the data transmission module and the data storage module; wherein:
the data transmission module comprises a first data interface and a second data interface, the first data interface is connected with an external data source, and the data transmission module is used for transmitting data between the external data source and the data storage module and managing the transmitted data;
the data storage module comprises a third data interface and at least two fast nonvolatile storage (NVMe) units, the second data interface is connected with the third data interface, and the data storage module is used for storing the transmission data;
after establishing communication connection with the external data source through the first data interface, when receiving a data storage instruction sent by the external data source through the first data interface, the data transmission module is configured to respond to the data storage instruction, receive first target data sent by the external data source through the first data interface, determine n NVMe units from the at least two NVMe units, allocate the first target data to n sub-target data, and send the n sub-target data to the n NVMe units in parallel through the second data interface and the third data interface; wherein n is greater than or equal to 2 and less than or equal to the number of the at least two NVMe units, the data storage instruction is to instruct the storage device to store the first target data;
and the NVMe unit stores the sub-target data if receiving the sub-target data sent by the data transmission module.
2. The storage device of claim 1, wherein the data transfer module comprises: a field programmable gate array FPGA; wherein:
the FPGA is used for managing transmission data between the external data source and the data storage module.
3. The storage device of claim 2,
the second data interface and the third data interface are high-speed serial computer expansion bus standard PCIe buses; wherein the number of interfaces of the third data interface is the same as the number of the at least two NVMe units.
4. The storage device according to any one of claims 1 to 3,
the data transmission module is further configured to respond to a data playback instruction when receiving the data playback instruction sent by the external data source through the first data interface after establishing a communication connection with the external data source through the first data interface, acquire second target data corresponding to the data playback instruction from the at least two NVMe units, and send the second target data to the external data source through the first data interface.
5. The storage device of claim 1,
the data transmission module is further configured to establish a communication connection with a control device through the first data interface, receive a management control instruction sent by the control device, respond to the management control instruction, and execute a target operation corresponding to the management control instruction on third target data stored in the at least two NVMe units; wherein the third target data corresponds to the management control instruction, and the target operation at least includes: a query operation, a write operation, a read operation, and a delete operation.
6. The storage device of any one of claims 1 to 3, wherein the first data interface is communicatively coupled to an external data source based on a remote communication protocol.
7. The storage device of claim 3,
the number of the at least two NVMe units is the same as the number of PCIe hard cores in the FPGA.
8. An information processing method is applied to a storage device, the storage device comprises a first data interface, a data transmission module and a data storage module, and the method comprises the following steps:
establishing communication connection with an external data source through a first data interface;
receiving an operation instruction sent by the external data source through the first data interface;
responding to the operation instruction through the data transmission module, and performing storage management operation on the data storage module; the data storage module comprises at least two NVMe units, and the storage management operation corresponds to the operation instruction;
wherein, the responding to the operation instruction through the data transmission module, and performing storage management operation on the data storage module includes:
if the operation instruction is a data storage instruction, responding to the data storage instruction through the data transmission module, and receiving first target data sent by the external data source through the first data interface;
wherein the data storage instructions are to instruct the storage device to store the first target data;
determining, by the data transmission module, n NVMe units from the at least two NVMe units; wherein n is greater than or equal to 2 and less than or equal to the number of the at least two NVMe units;
distributing the first target data into n parts of sub-target data through the data transmission module;
the n parts of sub-target data are stored in the n NVMe units in parallel through the data transmission module; wherein the storage management operation comprises the parallel storage.
9. The method of claim 8, wherein performing a storage management operation on the data storage module in response to the operation instruction by the data transmission module further comprises:
if the operation instruction is a data playback instruction, responding to the data playback instruction through the data transmission module, and acquiring second target data corresponding to the data playback instruction from the at least two NVMe units; wherein the storage management operation comprises an operation of acquiring the second target data from the at least two NVMe units, and the data playback instruction is used for instructing the storage device to play back the stored second target data;
and sending the second target data to the external data source through the first data interface.
10. The method according to any one of claims 8 to 9, wherein the data transmission module is an FPGA.
11. The method according to any one of claims 8 to 9, wherein the data transmission module and the data storage module are connected by a PCIe bus, and the number of PCIe buses is the same as the number of the at least two NVMe units.
12. The method of claim 8, further comprising:
if a management control instruction sent by control equipment is received through the first data interface, responding to the management control instruction through the data transmission module, and executing target operation corresponding to the management control instruction on third target data stored in the at least two NVMe units; wherein the third target data corresponds to the management control instruction, and the target operation at least includes: the storage management operation comprises a query operation, a write operation, a read operation and a delete operation, and the storage management operation comprises the target operation.
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