JP2020057969A - Imaging device and method for controlling imaging device - Google Patents

Abstract

To provide an imaging device capable of suppressing a decrease in accuracy of analog-digital conversion due to rounding or delay of a reference signal.SOLUTION: Analog-to-digital conversion means generates, in a first period, a first digital value by comparing a signal based on the reset release of a pixel with a first reference signal and performing counting on the basis of a first clock signal, generates in a second period, a second digital value by comparing the signal based on the reset release of the pixel with a second reference signal, and performing counting on the basis of a second clock signal, and in a third period, generates a third or fourth digital value by comparing a signal based on charges converted by photoelectric conversion means with the first or second reference signal, and performing counting on the basis of a third or fourth clock signal, and pulse generation of the first to fourth clock signals is started after a predetermined time from a level change start time of the first or second reference signal generated by generating means.SELECTED DRAWING: Figure 8

Description

  The present invention relates to an imaging device and a control method of the imaging device.

  2. Description of the Related Art There is known an imaging apparatus capable of capturing an image using an imaging element and storing the captured image as digital data. As an image sensor, there is a CMOS (Complementary Metal Oxide Semiconductor) type image sensor (hereinafter referred to as a CMOS sensor) that reads each pixel signal by an XY address method. The pixel circuit of the CMOS sensor converts a charge of the photodiode into a potential of a signal line by a source follower circuit and outputs the signal. The CMOS sensor sequentially performs pixel selection on a row-by-row basis, performs analog-to-digital (AD) conversion of a pixel signal of each column in a selected row, and outputs the result as an image signal. The single-slope AD converter has a comparator and a counter for comparing an image signal and a ramp-shaped reference signal, and the counter counts according to the comparison result of the comparator, thereby converting a pixel signal from analog to digital. Conversion (for example, refer to Patent Document 1).

  In addition, the image signal that performs the analog-to-digital conversion using the reference signal with a small change rate on the pixel signal of the low illuminance part and the analog-to-digital conversion using the reference signal with the large change rate on the pixel signal of the high illuminance part A device is known (for example, see Patent Document 2).

JP 2005-323331 A JP-A-2015-164278

  In a CMOS sensor, the reference signal is rounded or delayed due to the parasitic capacitance of a wiring for transmitting the reference signal and the input capacitance and input resistance of the AD conversion circuit. Further, when the reference signal changes at high speed, it becomes difficult to supply the same reference signal to all columns simultaneously and in parallel, and a rounding and a delay different from the case where the reference signal changes at low speed occur. .

  In such a state, when the pixel signals of the low illuminance portion and the high illuminance portion are AD-converted by using the reference signal having the small change rate and the reference signal having the large change rate, the linearity of the output signal with respect to the brightness is low. The problem that it is not maintained occurs.

  Further, when AD conversion is performed using two kinds of reference rates of change rate, signal unevenness generated by each reference signal overlaps, and it is also difficult to correct it in subsequent signal processing.

  An object of the present invention is to provide an imaging apparatus and a control method of the imaging apparatus, which can suppress a decrease in accuracy of analog-to-digital conversion due to rounding or delay of a reference signal.

  An image pickup apparatus according to the present invention includes a pixel including photoelectric conversion means for converting light into electric charges, a first reference signal that changes at a first rate of change, and a first reference signal that changes at a second rate of change larger than the first rate of change. Generating means for generating a second reference signal, and analog-to-digital conversion means for converting an output signal of the pixel from analog to digital, wherein the analog-to-digital conversion means converts the output signal of the pixel during a first period. By comparing the output signal of the pixel based on the reset release with the first reference signal and counting based on a first clock signal, the output signal of the pixel based on the reset release of the pixel is converted from analog to digital. And generating a first digital value converted into the first digital value. In a second period different from the first period, the output signal of the pixel based on the reset release of the pixel and the second reference signal are compared. Then, by counting based on the second clock signal, a second digital value obtained by converting the output signal of the pixel based on the reset release of the pixel from analog to digital is generated, and the first and second digital values are generated. In a third period different from the period, when the output signal of the pixel based on the charge converted by the photoelectric conversion unit is smaller than the determination signal, the output of the pixel based on the charge converted by the photoelectric conversion unit A signal is compared with the first reference signal and counted based on a third clock signal, so that the pixel output signal based on the charge converted by the photoelectric conversion means is converted from analog to digital. 3 is generated, and when the output signal of the pixel based on the charge converted by the photoelectric conversion unit is larger than the determination signal, The output signal of the pixel based on the charge converted by the conversion means is compared with the second reference signal, and counting is performed based on a fourth clock signal, so as to be based on the charge converted by the photoelectric conversion means. Generating a fourth digital value obtained by converting the output signal of the pixel from analog to digital, wherein the first clock signal is a level change of the first reference signal generated in the first period by the generation unit; The pulse generation is started after a first time from the start time, and the second clock signal is a second time from the level change start time of the second reference signal generated by the generation means in the second period. The pulse generation is started later, and the third clock signal is generated at a third time after the level change start time of the first reference signal generated by the generation means in the third period. Generation of the fourth clock signal is started, and pulse generation of the fourth clock signal is started a fourth time after a level change start time of the second reference signal generated in the third period by the generation unit.

  ADVANTAGE OF THE INVENTION According to this invention, the fall of the precision of an analog-digital conversion resulting from the dullness or delay of a reference signal can be suppressed, and the image quality of an image can be improved.

It is a figure showing the example of composition of an imaging system. FIG. 3 is a diagram illustrating a configuration example of an imaging element. FIG. 3 is a diagram illustrating a configuration example of a pixel. FIG. 3 is a diagram illustrating a configuration example of a column signal processing unit. 5 is a timing chart illustrating a control method of a column signal processing unit. 5 is a timing chart illustrating a control method of a column signal processing unit. 5 is a timing chart illustrating a control method of a column signal processing unit. 5 is a timing chart illustrating a control method of a column signal processing unit. FIG. 3 is a diagram illustrating a configuration example of a counter circuit. 5 is a timing chart illustrating a control method of a column signal processing unit. FIG. 3 is a diagram illustrating a configuration example of a counter circuit. 5 is a timing chart illustrating a control method of a column signal processing unit.

  The embodiment described below is an example as a means for realizing the present invention, and should be appropriately modified or changed depending on the configuration of the apparatus to which the present invention is applied and various conditions. However, the present invention is not limited to this.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of an imaging system 10 according to the first embodiment of the present invention. The imaging system 10 includes an optical system 11, an image sensor 12, a signal processing unit 13, a compression / expansion unit 14, a synchronization control unit 15, an operation unit 16, an image display unit 17, and an image recording unit 18. Have.

  The optical system 11 has a lens, a lens driving mechanism, a mechanical shutter mechanism, an aperture mechanism, and the like. The movable section of the optical system 11 is driven based on a control signal from the synchronization control section 15.

  The imaging element 12 is, for example, an XY address type CMOS sensor, and is an imaging device that performs an imaging operation according to a control signal from the synchronization control unit 15. Then, the image sensor 12 converts the image signal from analog to digital by the analog-to-digital conversion circuit, and outputs the digital image signal to the signal processing unit 13. Details of the image sensor 12 will be described later.

  The signal processing unit 13 performs signal processing, control information such as AF (Auto Focus) and AE (Auto Exposure) on a digital image signal input from the image sensor 12 under the control of the synchronization control unit 15. Perform detection. Then, the signal processing unit 13 outputs the signal-processed image signal and control information to the synchronization control unit 15.

  The compression / decompression unit 14 performs a compression encoding process on an image signal and performs a decompression decoding process on encoded data of a still image under the control of the synchronization control unit 15. Further, the compression / decompression unit 14 may perform a compression encoding / decompression decoding process on a moving image.

  The synchronization control unit 15 is, for example, a microcontroller having a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. The synchronization control unit 15 controls each unit of the imaging system 10 by executing a program stored in a ROM or the like.

  The operation unit 16 includes various operation members such as a shutter release button, and outputs a control signal corresponding to an input operation by a user to the synchronization control unit 15. The image display unit 17 supplies an image signal to a display device such as an LCD (Liquid Crystal Display) to display an image. The image recording unit 18 stores, for example, a compression-encoded image data file on a portable recording medium.

  Next, the operation of the imaging system 10 will be described. Before capturing a still image, the image sensor 12 sequentially supplies image signals to the signal processing unit 13. The signal processing unit 13 performs signal processing on the image signal from the imaging element 12 and supplies the signal to the image display unit 17 through the synchronization control unit 15 as a camera-through image signal. The image display unit 17 displays the camera through image, and the user can adjust the angle of view while viewing the display image.

  In this state, when the shutter release button of the operation unit 16 is pressed, the image sensor 12 outputs an image signal for one frame to the signal processing unit 13 under the control of the synchronization control unit 15. The signal processing unit 13 performs signal processing on the image signal for one frame, and supplies the processed image signal to the compression / decompression unit 14. The compression / expansion unit 14 generates encoded data by compression-encoding the input image signal, and supplies the generated encoded data to the image recording unit 18 through the synchronization control unit 15. The image recording unit 18 records the encoded data as a still image data file.

  Next, a process of reproducing a data file of a still image recorded in the image recording unit 18 will be described. The synchronization control unit 15 reads the selected data file from the image recording unit 18 according to the operation input from the operation unit 16 and supplies the data file to the compression / decompression unit 14. The compression / decompression unit 14 generates an image signal by performing a decompression decoding process on the data file, and supplies the image signal to the image display unit 17 via the synchronization control unit 15. The image display unit 17 displays a still image.

  Next, processing for recording a moving image will be described. The imaging element 12 outputs an image signal of a moving image to the signal processing unit 13. The signal processing unit 13 processes the image signal of the moving image and outputs the processed image signal to the compression / expansion unit 14. The compression / decompression unit 14 performs a compression encoding process on the image signal of the moving image, generates encoded data of the moving image, and outputs the encoded data to the image recording unit 18. The image recording unit 18 records the encoded data of the moving image as a data file of the moving image.

  Next, processing for reproducing a moving image data file recorded in the image recording unit 18 will be described. The synchronization control unit 15 reads the data file of the selected moving image from the image recording unit 18 and supplies the data file of the moving image to the compression / expansion unit 14 in response to an operation input from the operation unit 16. The compression / expansion unit 14 generates an image signal of the moving image by performing an expansion decoding process on the data file of the moving image, and supplies the image signal of the moving image to the image display unit 17 via the synchronization control unit 15. I do. The image display unit 17 displays a moving image.

  FIG. 2 is a diagram illustrating a configuration example of the imaging element 12 in FIG. The imaging device 12 includes a pixel area 201, a vertical scanning unit 202, a plurality of column signal processing units 203, a horizontal scanning unit 207, an output unit 209, and a timing unit 211.

  The pixel area 201 has a plurality of pixels 200 arranged in a two-dimensional matrix. Each of the plurality of pixels 200 is arranged in a matrix in the horizontal and vertical directions as indicated by P11 to P86. The pixels 200 in the first row are represented by P11 to P16. The pixels 200 in the eighth row are represented by P81 to P86. FIG. 2 illustrates an example of the pixels 200 in a 6 × 8 array (8 rows and 6 columns), but the number of pixels 200 is not limited to this number. The plurality of pixels 200 are 2 × in which R (red) filters and G (green) filters are alternately arranged in odd rows, and G (green) filters and B (blue) filters are alternately arranged in even rows. It has two color filters.

  The vertical scanning unit 202 selects an array of the pixels 200 row by row, and controls a reset operation and a read operation of the pixels 200 in the selected row. The pixel control line 221 is commonly connected to each row of the pixels 200. The vertical scanning unit 202 transmits a control signal to the pixels 200 on a row-by-row basis via the pixel control line 221.

  The column signal line 231 is commonly connected to each column of the pixels 200. When the pixel 200 in each column is selected by the pixel control line 221, the pixel 200 outputs a pixel signal to the corresponding column signal line 231.

  The column signal processing unit 203 is provided for each corresponding column signal line 231. The column signal processing unit 203 of each column inputs a pixel signal of each row through the column signal line 231 of each column, and converts the pixel signal from analog to digital.

  The horizontal scanning unit 207 sequentially selects the column signal processing unit 203 of each column via the column selection line 251 of each column. When selected, the column signal processing unit 203 of each column outputs the stored digital pixel signal to the output unit 209 via the output line 261. The output unit 209 outputs a digital pixel signal for each row to the signal processing unit 13.

  The timing section 211 outputs various clock signals and control signals necessary for the operation of each section of the image sensor 12 based on the control signal from the synchronization control section 15. The control lines 271, 281 and 285 are control lines for outputting a clock signal, a control signal, and the like from the timing unit 211 to the vertical scanning unit 202, the column signal processing unit 203, and the horizontal scanning unit 207, respectively.

  FIG. 3 is a circuit diagram showing a configuration example of the pixel 200 in FIG. The pixel 200 is connected to the pixel control line 221 and the column signal line 231. The pixel control line 221 has a reset control line pR, a transfer control line pT, and a selection line pSEL. The pixel control line 221 is connected to the vertical scanning unit 202, is commonly connected to the pixels 200 in each row, and simultaneously controls the pixels 200 in the same row. The column signal line 231 is connected to the load transistor Tlod, and is commonly connected to the pixels 200 in each column.

  The pixel 200 has a photoelectric conversion element D1, a transfer transistor T1, a floating diffusion capacitance (FD capacitance) Cfd, a reset transistor T2, an amplification transistor Tdrv, and a selection transistor T3.

  The photoelectric conversion element D1 is a photodiode that converts light into charges and stores the converted charges. In the photoelectric conversion element D1, the P side of the PN junction is grounded, and the N side is connected to the source of the transfer transistor T1.

  The transfer transistor (transfer switch) T1 has a gate connected to the transfer control line pT, a drain connected to the node 301 of the FD capacitor Cfd, and transfers the charge of the photoelectric conversion element D1 to the FD capacitor Cfd. The FD capacitor Cfd is connected between the node 301 and the ground node, stores the charge transferred from the photoelectric conversion element D1, and converts the charge into a voltage.

  The reset transistor (reset switch) T2 has a gate connected to the reset control line pR, a drain connected to the node of the power supply voltage Vdd, a source connected to the node 301 of the FD capacitor Cfd, and a potential of the node 301 changed to the power supply voltage Vdd. Reset to.

  The amplifying transistor (amplifying unit) Tdrv is a transistor constituting an in-pixel amplifier, and has a gate connected to the node 301 of the FD capacitor Cfd, a drain connected to the node of the power supply voltage Vdd, and a source connected to the drain of the selection transistor T3. Connected. The amplification transistor Tdrv outputs a voltage corresponding to the voltage of the node 301 of the FD capacitor Cfd.

  The selection transistor (selection switch) T3 has a gate connected to the selection line pSEL, a source connected to the column signal line 231, and outputs an output signal of the amplification transistor Tdrv to the column signal line 231 as an output signal of the pixel 200.

  In the load transistor Tlod, the source and the gate are connected to the ground node, and the drain is connected to the column signal line 231. The load transistor Tlod is provided for each column signal line 231. The load transistor Tlod, together with the amplification transistor Tdrv, forms a source follower circuit serving as an in-pixel amplifier. Normally, when the signal of the pixel 200 is output, the load transistor Tlod is operated as a gate-grounded constant current source.

  Transistors other than the amplification transistor Tdrv and the load transistor Tlod function as switches, and conduct (turn on) when the control line connected to the gate is at a high level, and shut off (turn off) when the control line is at a low level.

  FIG. 4 is a diagram illustrating a configuration example of the column signal processing unit 203 in FIG. The column signal processing unit 203 includes a switch circuit 401, a comparator 402, a counter circuit 403, a latch circuit 404, and an arithmetic circuit 405.

  The timing unit 211 of FIG. 2 outputs a ramp signal reference signal G1 or a determination signal Vjd that changes with time in FIG. 5A to the ramp signal line Vrmp1. Further, the timing section 211 outputs a ramp wave reference signal G4 that changes with time in FIG. 5A to the ramp wave signal line Vrmp4.

  A first input terminal of the comparator 402 is connected to the column signal line 231. The switch circuit 401 connects the ramp wave signal line Vrmp1 or Vrmp4 to the second input terminal of the comparator 402 according to the signals on the switch control lines pSwR and pSwC.

  The comparator 402 compares the signal Vsig (FIG. 5A) of the column signal line 231 with the output signal of the switch circuit 401, and outputs a comparison result signal to the counter circuit 403 and the switch control line pSwC. The comparator 402 inverts the comparison result signal from a high level to a low level when the magnitude relationship between the signal Vsig of the column signal line 231 and the output signal of the switch circuit 401 is reversed.

  The timing unit 211 supplies a clock signal to the counter control line pCNT. The counter circuit 403 counts based on the clock signal supplied from the counter control line pCNT in accordance with the result of the comparison by the comparator 402. The counter circuit 403 starts the counting operation in accordance with the start of the level change of the reference signal G1 or G4, and when the comparison result signal from the comparator 402 is inverted, outputs the count value at that time. The count value at this time is a value obtained by converting the analog signal Vsig of the column signal line 231 into a digital signal. The latch circuit 404 temporarily holds the count value output by the counter circuit 403, and outputs the held count value according to the signal of the latch control line pLTC.

  The arithmetic circuit 405 stores the count value output from the latch circuit 404 as a digital signal of the pixel 200 according to the signal on the arithmetic control line pCAL, and performs signal processing described later. Further, the arithmetic circuit 405 outputs the stored digital signal of the pixel 200 to the output line 261 in accordance with the signal of the column selection line 251.

  The comparator 402, the counter circuit 403, and the latch circuit 404 constitute an analog-to-digital conversion circuit. The control line 281 has ramp wave signal lines Vrmp1 and Vrmp4, a switch control line pSwR, a counter control line pCNT, a latch control line pLTC, and an operation control line pCAL.

  FIG. 5A is a timing chart illustrating a control method of the column signal processing unit 203 according to the basic technique. FIG. 5B is a diagram illustrating a waveform of a signal on the ramp signal line Vrmp1. FIG. 5C is a diagram illustrating a waveform of a signal on the ramp signal line Vrmp4. FIG. 5D is a diagram illustrating a waveform of the signal Vsig in FIG.

  The signal Vsig is a pixel signal of the column signal line 231. The signal Vrmp is a signal that the switch circuit 401 outputs to the second input terminal of the comparator 402. Comparator 402 compares signals Vsig and Vrmp. In FIG. 5A, the V direction represents the potential of the signals Vsig and Vrmp, and the t direction represents the passage of time.

  The pixel signal Vsig has an N signal Vn based on the reset release of the pixel 200 and S signals VsigL and VsigH based on the photoelectric conversion of the pixel 200. The S signal VsigL is an output signal of the pixel 200 at low illuminance based on the charge converted by the photoelectric conversion element D1. The S signal VsigH is an output signal of the pixel 200 at high illuminance based on the charge converted by the photoelectric conversion element D1.

  The signal Vrmp has reference signals G1 and G4 and a determination signal Vjd. The reference signal G1 changes at a first change rate (slope). The reference signal G4 changes at the second change rate. For example, the second rate of change is four times (coefficient multiple) the first rate of change. The reference signal G1 and the determination signal Vjd are supplied to the ramp signal line Vrmp1. The reference signal G4 is supplied to the ramp signal line Vrmp4.

  The image sensor 12 clamps the initial potential of the pixel signal Vsig and the initial potential of the ramp wave signal line Vrmp1 in advance in the comparator 402 as an operation of matching the reference of comparison between the pixel signal Vsig and the signal Vrmp input to the comparator 402. Keep it.

  Hereinafter, a control method of the column signal processing unit 203 will be described. The photoelectric conversion element D1 converts light into electric charges by photoelectric conversion and accumulates the charges. First, the switch circuit 401 connects the ramp signal line Vrmp1 to the second input terminal of the comparator 402 under the control of the timing unit 211 by the switch control line pSwR.

  Before the period t1, the reset transistor T2 resets the node 301 of the FD capacitance Cfd. After the period t1, the reset transistor T2 releases the reset of the node 301 of the FD capacitance Cfd. Then, the pixel 200 outputs the N signal Vn based on the reset release to the column signal line 231. The N signal Vn is an output signal of the pixel 200 based on the reset release of the pixel 200.

  In the period t2, the timing section 211 changes the level of the reference signal G1 and outputs the reference signal G1 to the second input terminal of the comparator 402. Under the control of the timing section 211, the counter circuit 403 starts counting the count value when the level change of the reference signal G1 starts. The comparator 402 compares the N signal Vn with the reference signal G1, and when the magnitude relationship between the N signal Vn and the reference signal G1 is reversed, the comparator 402 inverts the comparison result signal from a high level to a low level. When the comparison result signal of the comparator 402 is inverted, the counter circuit 403 stops counting the count value, and outputs the count value cn1 to the latch circuit 404. The counter circuit 403 counts in the period tn1 and outputs the count value cn1 to the latch circuit 404. The latch circuit 404 outputs the count value cn1 to the arithmetic circuit 405. The arithmetic circuit 405 stores the count value cn1. The count value cn1 is generated as a digital value obtained by converting the N signal Vn from analog to digital using the reference signal G1.

  Next, the switch circuit 401 connects the ramp signal line Vrmp4 to the second input terminal of the comparator 402 under the control of the timing unit 211 by the switch control line pSwR. In the period t3, the timing unit 211 changes the level of the reference signal G4, and outputs the reference signal G4 to the second input terminal of the comparator 402. Under the control of the timing section 211, the counter circuit 403 starts counting the count value at the start of the level change of the reference signal G4. The comparator 402 compares the N signal Vn with the reference signal G4, and when the magnitude relationship between the N signal Vn and the reference signal G4 is reversed, the comparator 402 inverts the comparison result signal from a high level to a low level. When the comparison result signal from the comparator 402 is inverted, the counter circuit 403 stops counting the count value, and outputs the count value cn4 to the latch circuit 404. The counter circuit 403 performs counting in a period tn4, and outputs a count value cn4 to the latch circuit 404. The latch circuit 404 outputs the count value cn4 to the arithmetic circuit 405. The arithmetic circuit 405 stores the count value cn4. The count value cn4 is generated as a digital value obtained by converting the N signal Vn from analog to digital using the reference signal G4.

  At the start of the period t4, the transfer transistor T1 transfers the charge converted by the photoelectric conversion element D1 to the FD capacitor Cfd. Then, the pixel 200 outputs the S signal VsigL or VsigH based on the photoelectric conversion of the photoelectric conversion element D1 to the column signal line 231. The S signal VsigL is a pixel signal at low illuminance. The S signal VsigH is a pixel signal at the time of high illuminance. The switch circuit 401 connects the ramp wave signal line Vrmp1 to the second input terminal of the comparator 402 under the control of the timing unit 211 by the switch control line pSwR.

  First, the processing in the periods t4 to t7 in the case of low illuminance will be described. At low illuminance, the pixel 200 outputs the S signal VsigL. In the period t6, the timing unit 211 outputs the determination signal Vjd at a constant level to the second input terminal of the comparator 402. Since the S signal VsigL is smaller than the determination signal Vjd, the comparator 402 outputs a low level to the switch control line pSwC.

  In the period t7, the timing section 211 changes the levels of the reference signals G1 and G4, outputs the reference signal G1 to the ramp wave signal line Vrmp1, and outputs the reference signal G4 to the ramp wave signal line Vrmp4. The switch circuit 401 connects the ramp signal line Vrmp1 to the second input terminal of the comparator 402 because the switch control line pSwC is at low level. Under the control of the timing section 211, the counter circuit 403 starts counting the count value when the level change of the reference signal G1 starts. The comparator 402 compares the S signal VsigL with the reference signal G1, and when the magnitude relationship between the S signal VsigL and the reference signal G1 is reversed, the comparator 402 inverts the comparison result signal from a high level to a low level. When the comparison result signal from the comparator 402 is inverted, the counter circuit 403 stops counting the count value, and outputs the count value cs1 to the latch circuit 404. The counter circuit 403 counts in the period ts1 and outputs the count value cs1 to the latch circuit 404. The latch circuit 404 outputs the count value cs1 to the arithmetic circuit 405. The arithmetic circuit 405 stores the count value cs1. Then, the arithmetic circuit 405 outputs the result of subtraction of the count value cn1 from the count value cs1 to the signal processing unit 13 via the output line 261 as the pixel value of the pixel 200.

  Next, processing in the period t4 to t7 in the case of high illuminance will be described. At the time of high illuminance, the pixel 200 outputs the S signal VsigH. In the period t6, the timing unit 211 outputs the determination signal Vjd at a constant level to the second input terminal of the comparator 402. Since the S signal VsigH is greater than the determination signal Vjd, the comparator 402 outputs a high level to the switch control line pSwC.

  In the period t7, the timing section 211 changes the levels of the reference signals G1 and G4, outputs the reference signal G1 to the ramp wave signal line Vrmp1, and outputs the reference signal G4 to the ramp wave signal line Vrmp4. The switch circuit 401 connects the ramp signal line Vrmp4 to the second input terminal of the comparator 402 because the switch control line pSwC is at the high level. Under the control of the timing section 211, the counter circuit 403 starts counting the count value at the start of the level change of the reference signal G4. The comparator 402 compares the S signal VsigH with the reference signal G4, and when the magnitude relationship between the S signal VsigH and the reference signal G4 is reversed, the comparator 402 inverts the comparison result signal from a high level to a low level. When the comparison result signal of the comparator 402 is inverted, the counter circuit 403 stops counting the count value, and outputs the count value cs4 to the latch circuit 404. The counter circuit 403 counts in the period ts4 and outputs the count value cs4 to the latch circuit 404. The latch circuit 404 outputs the count value cs4 to the arithmetic circuit 405. The arithmetic circuit 405 stores the count value cs4. Then, the arithmetic circuit 405 subtracts the count value cn4 from the count value cs4, and outputs a value obtained by quadrupling the result of the subtraction to the signal processing unit 13 via the output line 261 as a pixel value of the pixel 200. Since the rate of change of the reference signal G4 is four times the rate of change of the reference signal G1, the arithmetic circuit 405 performs the above four-fold operation.

  Through the above processing, the column signal processing unit 203 can convert the pixel signal of the pixel 200 from analog to digital. Note that the comparator 402 may determine the level of the S signal by comparing the S signal with the signal Vrmp during the period t5 when the level of the signal Vrmp changes.

  FIG. 6 is a timing chart when a delay occurs in the reference signals G1 and G4 with respect to FIG. The reference signals G1 and G4 in FIG. 6 are delayed with respect to the reference signals G1 and G4 in FIG. The cause of the delay is the parasitic capacitance of the ramp signal lines Vrmp1 and Vrmp4 and the input capacitance and input resistance of the comparator 402.

  A region 601 surrounded by a dotted line indicates a rising portion of the reference signal G1 in the period t2. A region 602 surrounded by a dotted line indicates a rising portion of the reference signal G4 in the period t3. A region 603 surrounded by a dotted line shows rising portions of the reference signals G1 and G4 in the period t7. In the regions 601 to 603, the reference signals G1 and G4 indicated by dotted lines show states delayed from the reference signals G1 and G4 indicated by solid lines, respectively.

  The clock signal pCNTck is a clock signal input to the counter circuit 403. The pulse of the clock signal pCNTck is generated in periods t2, t3, and t7 during which the level of the reference signal G1 or G4 changes. The pulse generation start time of the clock signal pCNTck is the level change start time of the reference signal G1 or G4. The counter circuit 403 starts counting the number of pulses of the clock signal pCNTck in accordance with the start of the level change of the reference signal G1 or G4, and when the output signal of the comparator 402 is inverted, counts the number of pulses of the clock signal pCNTck. finish.

  However, the level change start times of the delayed reference signals G1 and G4 indicated by the dotted lines are later than the pulse generation start time of the clock signal pCNTck. Therefore, the counter circuit 403 starts counting the number of pulses of the clock signal pCNTck earlier than the level change start time of the delayed reference signals G1 and G4 indicated by the dotted line. Therefore, there is a problem that the counter circuit 403 counts a count value larger than the original count value by the number of pulses of the clock signal pCNTck generated during the delay time of the reference signals G1 and G4.

  FIG. 7 is a timing chart in the case where dullness and delay occur in the reference signal G1. Causes of dullness and delay of the reference signals G1 and G4 are the parasitic capacitance of the ramp signal lines Vrmp1 and Vrmp4 and the input capacitance and input resistance of the comparator 402. In FIG. 7, in order to explain the problem, the rising portions of the reference signal G1 in the regions 601 and 603 in FIG.

  The signal levels Vn0 and Vn1 show examples of different potentials of the N signal Vn. The signal level Vs indicates an example of the potential of the S signal VsigL or VsigH.

  The reference signal G1e is an actual reference signal that is rounded and delayed with respect to the reference signal G1. The reference signal G1es indicates a signal component delayed from the reference signal G1 without being affected by rounding in the reference signal G1e. The delay amount s1d is a delay amount of the reference signal G1e with respect to the reference signal G1.

  The clock signal pCNTcks1 is a signal obtained by delaying the clock signal pCNTck of FIG. 6 by the delay amount s1d, and is a clock signal in a case where analog-to-digital conversion is performed using the reference signal G1e.

  First, the case where the N signal Vn is at the signal level Vn1 that is not affected by the rounding of the reference signal G1e will be described. For example, a case will be described where the signal level of the reference signal G1e from which the rounding has been eliminated is Vn1 and the N signal Vn is at the signal level Vn1. Hereinafter, the period t2 will be described. The comparator 402 compares the signal level Vn1 of the N signal Vn with the reference signal G1es (G1e), and the counter circuit 403 counts the number of pulses of the clock signal pCNTcks1 in the count period tn11es, and outputs the count value cn11es at that time. I do. The count value cn11es is a digital value obtained by converting the signal level Vn1 of the N signal Vn from analog to digital using the reference signal G1es.

  Next, the period t7 will be described. The comparator 402 compares the signal level Vs of the S signal with the reference signal G1es (G1e), and the counter circuit 403 counts the number of pulses of the clock signal pCNTcks1 in the count period ts1es, and outputs the count value cs1es at that time. . The count value cs1es is a digital value obtained by converting the signal level Vs of the S signal from analog to digital using the reference signal G1es. The arithmetic circuit 405 outputs the pixel value of the pixel 200 by subtracting the count value cn11es from the count value cs1es.

  Next, the case where the N signal Vn is at the signal level Vn0 affected by the rounding of the reference signal G1e will be described. The reference signal G1es is a signal when there is no rounding of the reference signal G1e. Hereinafter, the case where the analog-to-digital conversion is performed using the reference signal G1es in the period t2 will be described. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G1es, and the counter circuit 403 counts the number of pulses of the clock signal pCNTcks1 in the count period tn01es, and outputs the count value cn01es at that time. The count value cn01es is a digital value obtained by converting the signal level Vn0 of the N signal Vn from analog to digital using the reference signal G1es.

  However, actually, the column signal processing unit 203 converts the signal level Vn0 of the N signal Vn from analog to digital using the reference signal G1e. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G1e, and the counter circuit 403 counts the number of pulses of the clock signal pCNTcks1 in the count period tn01e, and outputs the count value cn01e at that time. The count value cn01e is a digital value obtained by converting the signal level Vn0 of the N signal Vn from analog to digital using the reference signal G1e. The count period tn01e is shorter than the count period tn01es. Therefore, the count value cn01e becomes smaller than the original count value cn01es.

  Here, a virtual reference signal G1en is assumed in consideration of the fact that the N signal Vn has a relatively stable potential compared to the S signals VsigL and VsigH. The reference signal G1en is a reference signal passing through the intersection of the signal level Vn0 of the N signal Vn and the reference signal G1e and having the same rate of change as the reference signal G1es. The delay amount n1d is a delay amount of the reference signal G1en with respect to the reference signal G1. The clock signal pCNTckn1 is a signal obtained by delaying the clock signal pCNTck of FIG. 6 by the delay amount n1d, and is a clock signal in a case where analog-digital conversion is performed using the reference signal G1en.

  The case where the signal level Vn0 of the N signal Vn is converted from analog to digital in the period t2 using the reference signal G1en will be described. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G1en (G1e), and the counter circuit 403 counts the number of pulses of the clock signal pCNTckn1 in the count period tn01en, and outputs the count value cn01en at that time. I do. The count value cn01en is a digital value obtained by converting the signal level Vn0 of the N signal Vn from analog to digital using the reference signal G1en. At this time, the count value cn01en becomes the same as the count value cn01es. As described above, by using the clock signals pCNTcks1 and pCNTckn1, it is possible to eliminate the error of the count value due to the delay and rounding of the reference signal G1e.

  The column signal processing unit 203 uses two types of reference signals G1 and G4 having different rates of change. In general, the reference signal G4 having a large change rate is designed to improve the followability to the change rate by increasing the current driving capability of the reference signal generation circuit in the timing section 211. Accordingly, there is a problem that the reference signals G1 and G4 having different rates of change have different delay amounts and round shapes. Hereinafter, embodiments for solving the above problems will be described.

  FIG. 8 is a timing chart illustrating a control method of the column signal processing unit 203 according to the present embodiment. The reference signals G1 and G4 are rounded and delayed. 8, the rising portions of the reference signals G1 and G4 in the regions 601 to 603 in FIG.

  The signal levels Vn0, Vn1, and Vn4 show examples of different potentials of the N signal Vn. The signal level Vs in FIG. 7 is higher than the signal level Vn4. In FIG. 8, the signal levels Vn0, Vn1, and Vs are the same as those in FIG. The reference signals G1e, G1es, G1en and the delay amounts s1d, n1d are the same as those in FIG. The count periods tn11es, ts1es, tn01es, and tn01en are the same as those in FIG.

  Here, as with the reference signal G1 of FIG. 7, the reference signal G4 also has rounding and delay. Further, since the change rate of the reference signal G4 is larger than the ramp wave G1, the current driving capability of the reference signal generation circuit in the timing section 211 is set to be large. The reference signal G4e is an actual reference signal that is rounded and delayed with respect to the reference signal G4. The reference signal G4e is different from the reference signal G1e in round shape and delay amount.

  The reference signal G4es indicates a signal component delayed from the reference signal G4 without being affected by rounding in the reference signal G4e. The delay amount s4d is a delay amount of the reference signal G4e with respect to the reference signal G4. The clock signal pCNTcks4 is a signal obtained by delaying the clock signal pCNTck of FIG. 6 by the delay amount s4d, and is a clock signal when converting from analog to digital using the reference signal G4e.

  First, the case where the N signal Vn is at the signal level Vn4 that is not affected by the rounding of the reference signal G4e will be described. The signal level Vn4 is a signal level in which the rounding of the reference signal G4e has been eliminated. The case where the N signal Vn is at the signal level Vn4 in the period t3 will be described. The comparator 402 compares the signal level Vn4 of the N signal Vn with the reference signal G4es (G4e), and the counter circuit 403 counts the number of pulses of the clock signal pCNTcks4 in the count period tn44es, and outputs the count value cn44es at that time. I do. The count value cn44es is a digital value obtained by converting the signal level Vn4 of the N signal Vn from analog to digital using the reference signal G4es.

  Next, a case in which the signal level Vs of the S signal is converted from analog to digital in the period t7 using the reference signal G4es will be described. The comparator 402 compares the signal level Vs of the S signal with the reference signal G4es (G4e), and the counter circuit 403 counts the number of pulses of the clock signal pCNTcks4 in the count period ts4es, and outputs the count value cs4es at that time. . The count value cs4es is a digital value obtained by converting the signal level Vs of the S signal from analog to digital using the reference signal G4es. The arithmetic circuit 405 subtracts the count value cn44es from the count value cs4es, and outputs a value obtained by quadrupling the result of the subtraction as the pixel value of the pixel 200.

  Next, the case where the N signal Vn is at the signal level Vn0 affected by the rounding of the reference signal G4e will be described. Signal levels Vn0 and Vn1 are both signal levels affected by the rounding of reference signal G4e. The processing at the signal level Vn1 is the same as the processing at the signal level Vn0. Hereinafter, the processing of the signal level Vn0 will be described as an example.

  In the period t3, the signal level Vn0 of the N signal Vn is converted from analog to digital using the reference signal G4es. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G4es, and the counter circuit 403 counts the number of pulses of the clock signal pCNTcks4 in the count period tn04es, and outputs the count value cn04es at that time. The count value cn04es is a digital value obtained by converting the signal level Vn0 of the N signal Vn from analog to digital using the reference signal G4es.

  However, in practice, the column signal processing unit 203 converts the signal level Vn0 of the N signal Vn from analog to digital using the reference signal G4e. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G4e, and the counter circuit 403 counts the number of pulses of the clock signal pCNTcks4 and outputs the count value cn04e at that time. The count value cn04e is smaller than the original count value cn04es.

  Here, a virtual reference signal G4en is assumed, considering that the N signal Vn has a relatively stable potential as compared with the S signals VsigL and VsigH. The reference signal G4en passes through the intersection of the signal level Vn0 of the N signal Vn and the reference signal G4e, and has the same rate of change as the reference signal G4es. The delay amount n4d is a delay amount of the reference signal G4en with respect to the reference signal G4. The clock signal pCNTckn4 is a signal obtained by delaying the clock signal pCNTck in FIG. 6 by the delay amount n4d, and is a clock signal in the case where analog-digital conversion is performed using the reference signal G4en.

  The case where the signal level Vn0 of the N signal Vn is converted from analog to digital in the period t3 using the reference signal G4en will be described. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G4en (G4e), and the counter circuit 403 counts the number of pulses of the clock signal pCNTckn4 in the count period tn04en, and outputs the count value cn04en at that time. I do. The count value cn04en is a digital value obtained by converting the signal level Vn0 of the N signal Vn from analog to digital using the reference signal G4en. At this time, the count value cn04en becomes the same as the count value cn04es. As described above, by using the clock signals pCNTcks4 and pCNTckn4, it is possible to eliminate the error of the count value due to the delay and rounding of the reference signal G4e.

  As shown in FIG. 8, the delay amount s1d of the reference signal G1es and the delay amount s4d of the reference signal G4es are different from each other. The delay amount n1d of the reference signal G1en and the delay amount n4d of the reference signal G4en are different from each other. The reference signal G1es is delayed from the reference signal G4es by a delay amount r1d. The delay amount r1d is a difference between the delay amount s1d and the delay amount s4d.

  In the operation of the area 601, it is possible to set the optimum delay amount n1d of the clock signal pCNTckn1 for the ramp wave G1e. Similarly, in the operation of the area 602, it is possible to set the optimum delay amount n4d of the clock signal pCNTckn4 for the ramp wave G4e.

  However, in the operation of the region 603, which of the reference signals G1e and G4e is used is determined for each column signal processing unit 203 of each column according to the comparison result between the S signal in the period t6 and the determination signal Vjd. Therefore, the counter control line pCNT connected to the counter circuit 403 can supply both the clock signal for the reference signal G1e and the clock signal for the ramp wave G4e.

  FIG. 9 is a diagram illustrating a configuration example of the counter circuit 403 of the column signal processing unit 203 according to the present embodiment. The counter circuit 403 has a count C circuit 501 and a switch circuit 502, and is connected to a counter control line pCNT and a switch control line pSwC. The switch control line pSwC is connected to the comparator 402 in FIG. The counter control line pCNT has clock signal lines pCNTck1 and pCNTck4, a switch control line pSwCk, and a counter control line pCNTctr. The clock signal line pCNTck1 transmits the clock signal pCNTcks1 or pCNTckn1 in FIG. The clock signal line pCNTck4 transmits the clock signal pCNTcks4 or pCNTckn4 of FIG.

  The count C circuit 501 is connected to the comparator 402 and the latch circuit 404. The count C circuit 501 performs the operation of a normal counter circuit. That is, the count C circuit 501 starts the counting operation in accordance with the generation of the pulse of the clock signal output from the switch circuit 502, and outputs the count value at that time to the latch circuit 404 when the comparison result signal of the comparator 402 is inverted. . The count C circuit 501 selects start and stop of the count operation and selection of up / down of the count by controlling the counter control line pCNTctr.

  The switch circuit 502 is connected to the switch control lines pSwCk and pSwC, and connects one of the clock signal lines pCNTck1 and pCNTck4 to the count C circuit 501 under control via the switch control lines pSwCk and pSwC.

  First, the operation of column signal processing section 203 when N signal Vn is lower than signal level Vn1 will be described. As an example, a case where the N signal Vn is at the signal level Vn0 will be described. In the period t2, the switch circuit 502 outputs the clock signal pCNTckn1 to the count C circuit 501 via the clock signal line pCNTck1 according to the signal on the switch control line pSwCk. The timing section 211 generates the reference signal G1e. The reference signal G1e is in a dull state. Therefore, the timing unit 211 outputs the clock signal pCNTckn1 with the delay amount n1d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G1e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTckn1 in the count period tn01en, and outputs the count value cn01en at that time. The arithmetic circuit 405 stores the count value cn01en.

  Next, in the period t3, the switch circuit 502 outputs the clock signal pCNTckn4 to the count C circuit 501 via the clock signal line pCNTck4 according to the signal on the switch control line pSwCk. The timing section 211 generates the reference signal G4e. The reference signal G4e is in a dull state. Therefore, the timing unit 211 outputs the clock signal pCNTckn4 with the delay amount n4d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G4e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTckn4 in the count period tn04en, and outputs the count value cn04en at that time. The arithmetic circuit 405 stores the count value cn04en.

  After the period t4, the processing differs depending on whether the pixel signal Vsig is the S signal VsigL or VsigH. First, a case where the pixel signal Vsig is the S signal VsigL will be described. In the period t6, the comparator 402 outputs a low level to the switch control line pSwC because the S signal VsigL is smaller than the determination signal Vjd. In the period t7, since the switch control line pSwC is at the low level, the switch circuit 502 outputs the clock signal pCNTcks1 to the count C circuit 501 via the clock signal line pCNTck1. The reference signal G1e is in a dull state. Therefore, the timing unit 211 outputs the clock signal pCNTcks1 of the delay amount s1d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the S signal VsigL with the reference signal G1e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks1 in the count period ts1es, and outputs the count value cs1es at that time. The arithmetic circuit 405 stores the count value cs1es. Then, the arithmetic circuit 405 outputs the result of subtraction of the count value cn01en from the count value cs1es to the signal processing unit 13 via the output line 261 as the pixel value of the pixel 200. That is, the arithmetic circuit 405 calculates the difference between the count value cs1es and the count value cn01en, and outputs the calculation result as the pixel value of the pixel 200.

  Next, a case where the pixel signal Vsig is the S signal VsigH will be described. In the period t6, the comparator 402 outputs a high level to the switch control line pSwC because the S signal VsigH is larger than the determination signal Vjd. In the period t7, since the switch control line pSwC is at the high level, the switch circuit 502 outputs the clock signal pCNTcks4 to the count C circuit 501 via the clock signal line pCNTck4. The reference signal G4e is in a dull state. Therefore, the timing unit 211 outputs the clock signal pCNTcks4 of the delay amount s4d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the S signal VsigH with the reference signal G4e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks4 in the count period ts4es, and outputs the count value cs4es at that time. The arithmetic circuit 405 stores the count value cs4es. Then, the arithmetic circuit 405 subtracts the count value cn04en from the count value cs4es, and outputs a value obtained by quadrupling the result of the subtraction to the signal processing unit 13 via the output line 261 as a pixel value of the pixel 200. That is, the arithmetic circuit 405 calculates a value that is four times the difference between the count value cs4es and the count value cn04en, and outputs the calculation result as the pixel value of the pixel 200.

  The pulse generation of the clock signal pCNTckn1 is started after the delay amount n1d (after the first time) from the level change start time of the reference signal G1e generated by the timing unit 211 in the period t2. The pulse generation of the clock signal pCNTckn4 starts after a delay amount n4d (after the second time) from the level change start time of the reference signal G4e generated in the period t3 by the timing unit 211. The pulse generation of the clock signal pCNTcks1 is started after the delay amount s1d (after the third time) from the level change start time of the reference signal G1e generated by the timing unit 211 in the period t7. The pulse generation of the clock signal pCNTcks4 starts after a delay amount s4d (fourth time) from the level change start time of the reference signal G4e generated in the period t7 by the timing unit 211. The delay amounts n1d, n4d, s1d, and s4d are different from each other.

  The timing of the level change start of the reference signal G1e generated by the timing unit 211 in the period t7 is the same as the timing of the level change start of the reference signal G4e generated by the timing unit 211 in the period t7. The level of the reference signal G1e generated by the timing section 211 in the periods t2 and t7 at the start of the level change is the same as the level of the reference signal G4e generated by the timing section 211 in the periods t3 and t7 at the start of the level change. .

  Next, a case where the N signal Vn is equal to or higher than the signal level Vn1 and lower than the signal level Vn4 will be described. As an example, a case where the N signal Vn is at the signal level Vn1 will be described. In the period t2, the switch circuit 502 outputs the clock signal pCNTcks1 to the count C circuit 501 via the clock signal line pCNTck1 according to the signal on the switch control line pSwCk. The reference signal G1e is in a delay state. Therefore, the timing unit 211 outputs the clock signal pCNTcks1 of the delay amount s1d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the signal level Vn1 of the N signal Vn with the reference signal G1e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks1 in the count period tn11es, and outputs the count value cn11es at that time. The arithmetic circuit 405 stores the count value cn11es.

  In the period t3, the switch circuit 502 outputs the clock signal pCNTckn4 to the count C circuit 501 via the clock signal line pCNTck4 according to the signal on the switch control line pSwCk. The reference signal G4e is in a dull state. Therefore, the timing unit 211 outputs the clock signal pCNTckn4 with the delay amount n4d to the count C circuit 501 via the switch circuit 502. Here, the delay amount n4d is a time from the level change start time of the reference signal G4e to the intersection of the reference signal G4e and the signal level Vn1. The comparator 402 compares the signal level Vn1 of the N signal Vn with the reference signal G4e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTckn4 and outputs the count value cn14en at that time. The arithmetic circuit 405 stores the count value cn14en.

  In the periods t6 and t7, the column signal processing unit 203 performs the same processing as in the case of the signal level Vn0. However, when the pixel signal Vsig is the S signal VsigL, the arithmetic circuit 405 determines the result of subtracting the count value cn11es from the count value cs1es as the pixel value of the pixel 200 via the output line 261. 13 is output. When the pixel signal Vsig is the S signal VsigH, the arithmetic circuit 405 subtracts the count value cn14en from the count value cs4es and sets the value obtained by quadrupling the result of the subtraction as the pixel value of the pixel 200 as the output line. 261 to the signal processing unit 13.

  Next, the operation of column signal processing section 203 when N signal Vn is equal to or higher than signal level Vn4 will be described. As an example, a case where the N signal Vn is at the signal level Vn4 will be described. In the period t2, the switch circuit 502 outputs the clock signal pCNTcks1 to the count C circuit 501 via the clock signal line pCNTck1 according to the signal on the switch control line pSwCk. The reference signal G1e is in a delay state. Therefore, the timing unit 211 outputs the clock signal pCNTcks1 of the delay amount s1d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the signal level Vn4 of the N signal Vn with the reference signal G1e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks1 and outputs the count value cn41es at that time. The arithmetic circuit 405 stores the count value cn41es.

  In the period t3, the switch circuit 502 outputs the clock signal pCNTcks4 to the count C circuit 501 via the clock signal line pCNTck4 according to the signal on the switch control line pSwCk. The reference signal G4e is in a delay state. Therefore, the timing unit 211 outputs the clock signal pCNTcks4 of the delay amount s4d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the signal level Vn4 of the N signal Vn with the reference signal G4e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks4 in the count period tn44es, and outputs the count value cn44es at that time. The arithmetic circuit 405 stores the count value cn44es.

  In the periods t6 and t7, the column signal processing unit 203 performs the same processing as in the case of the signal level Vn0. However, when the pixel signal Vsig is the S signal VsigL, the arithmetic circuit 405 determines the result of subtracting the count value cn41es from the count value cs1es as the pixel value of the pixel 200 via the output line 261. 13 is output. When the pixel signal Vsig is the S signal VsigH, the arithmetic circuit 405 subtracts the count value cn44es from the count value cs4es and quadruples the result of the subtraction as the pixel value of the pixel 200, and outputs the resultant signal to the output line. 261 to the signal processing unit 13.

  Here, the N signal Vn is measured in advance to determine whether the N signal Vn is lower than the signal level Vn1, higher than the signal level Vn1 and lower than the signal level Vn4, or higher than the signal level Vn4. Is determined by

  The delay amounts s1d, s4d, n1d, and n4d may be measured and set in advance. For example, the image sensor 12 measures the delay amounts of the reference signals G1e and G4e during the vertical blanking period VBLK in the photographing operation, and sets the delay amounts of the clock signals pCNTcks1, pCNTcks4, pCNTckn1, and pCNTckn4.

  As described above, in the present embodiment, the delay amounts of the clock signals pCNTcks1, pCNTcks4, pCNTckn1, and pCNTckn4 corresponding to the delay amounts of the reference signals G1e and G4e are set. As a result, it is possible to obtain a good image signal in which the signal unevenness due to the AD conversion of the AD conversion circuit has been eliminated.

  Further, the delay amounts of the clock signals pCNTcks1, pCNTcks4, pCNTckn1, and pCNTckn4 are set for the rounding of the waveform that occurs at the rise of the reference signals G1e and G4e. As a result, it is possible to obtain a good image signal in which signal unevenness due to a rounded waveform is eliminated.

  Further, the delay amounts of the clock signals pCNTcks1, pCNTckn1, pCNTcks4, and pCNTckn4 corresponding to the reference signals G1e and G4e having different rates of change are set. As a result, A / D conversion with a wide dynamic range and high resolution can be performed, and a good image signal in which signal unevenness has been eliminated can be obtained.

(Second embodiment)
FIG. 10 is a timing chart illustrating a control method of the column signal processing unit 203 according to the second embodiment of the present invention. The reference signals G1e and G4e are rounded and delayed with respect to the reference signals G1 and G4, respectively. This embodiment has the same configuration and operation as the first embodiment. Hereinafter, the points of this embodiment different from the first embodiment will be described.

  10, the rising portions of the reference signals G1e and G4e in the regions 601 to 603 in FIG. In FIG. 10, the rising position of the reference signal G1es and the rising position of the reference signal G4es are set to be simultaneously. In FIG. 8, the rising position of the reference signal G1e (G1) and the rising position of the reference signal G4e (G4) are set to be the same.

  The reference signal G4e having a large change rate has a larger current driving capability of the reference signal generation circuit in the timing section 211 than the reference signal G1e having a small change rate. Therefore, the reference signal G1e has a larger delay amount than the reference signal G4e. Therefore, in FIG. 10, the reference signal G4e (G4) is generated with a delay amount r4d with respect to the reference signal G1e (G1). The delay amount r4d can be obtained from the difference between the delay amounts s1d and s4d.

  By setting the rising positions of the reference signals G1es and G4es at the same time, the clock signals pCNTcks1 and pCNTcks4 become the same. Therefore, the clock signals pCNTcks1 and pCNTcks4 can be made common. Thus, the counter circuit 403 in FIG. 9 can be simplified.

  The pulse generation time of the clock signal pCNTcks1 is a time delayed by the delay amount s1d from the level change start time of the reference signal G1e (G1). The pulse generation time of the clock signal pCNTcks4 is a time delayed by the delay amount s4d from the level change start time of the reference signal G4e (G4). The pulse generation time of the clock signal pCNTckn1 is a time delayed by the delay amount n1d from the level change start time of the reference signal G1e (G1). The pulse generation time of the clock signal pCNTckn4 is a time delayed by the delay amount n4d with respect to the level change start time of the reference signal G4e (G4).

  FIG. 11 is a diagram illustrating a configuration example of the counter circuit 403 according to the present embodiment. The counter circuit 403 has a count C circuit 501 and is connected to a counter control line pCNT. The counter control line pCNT has a clock signal line pCNTckx and a counter control line pCNTctr. The clock signal line pCNTckx transmits the clock signal pCNTcks1, pCNTckn1, or pCNTckn4 of FIG. Count C circuit 501 is connected to comparator 402 and latch circuit 404, and performs the operation of a normal counter circuit. The count C circuit 501 starts the count operation in accordance with the generation of the pulse of the clock signal on the clock signal line pCNTckx, and outputs the count value to the latch circuit 404 when the comparison result signal of the comparator 402 determines. The count C circuit 501 selects start and stop of the count operation and selection of up / down of the count by controlling the counter control line pCNTctr.

  The counter circuit 403 in FIG. 11 does not require the switch circuit 502, the clock signal line pCNTck4, and the switch control lines pSwCk and pSwC, and therefore, can reduce the number of circuits and wirings and simplify control as compared with the counter circuit 403 in FIG. It becomes possible. The details of the clock signal line pCNTckx will be described later.

  First, the operation of column signal processing section 203 when N signal Vn is lower than signal level Vn1 will be described. As an example, a case where the N signal Vn is at the signal level Vn0 will be described. In the period t2, the timing unit 211 outputs the clock signal pCNTckn1 with the delay amount n1d to the count C circuit 501 via the clock signal line pCNTckx. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G1e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTckn1 in the count period tn01en, and outputs the count value cn01en at that time. The arithmetic circuit 405 stores the count value cn01en.

  In the period t3, the timing section 211 outputs the clock signal pCNTckn4 with the delay amount n4d to the count C circuit 501 via the clock signal line pCNTckx. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G4e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTckn4 in the count period tn04en, and outputs the count value cn04en at that time. The arithmetic circuit 405 stores the count value cn04en.

  In the period t7, the timing unit 211 outputs the clock signal pCNTcks1 with the delay amount s1d to the count C circuit 501 via the clock signal line pCNTckx regardless of the level determination result of the S signal in the period t6. Note that the clock signal pCNTcks1 is the same signal as the clock signal pCNTcks4. Further, the timing section 211 generates the reference signals G1e and G4e such that the rising positions of the reference signals G1es and G4es are simultaneously.

  First, a case where the pixel signal Vsig is the S signal VsigL will be described. At time t7, the comparator 402 compares the S signal VsigL with the reference signal G1e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks1 in the count period ts1es, and outputs the count value cs1es at that time. The arithmetic circuit 405 stores the count value cs1es. Then, the arithmetic circuit 405 outputs the result of subtraction of the count value cn01en from the count value cs1es to the signal processing unit 13 via the output line 261 as the pixel value of the pixel 200.

  Next, a case where the pixel signal Vsig is the S signal VsigH will be described. At time t7, the comparator 402 compares the S signal VsigH with the reference signal G4e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks1 in the count period ts4es, and outputs the count value cs4es at that time. The arithmetic circuit 405 stores the count value cs4es. Then, the arithmetic circuit 405 subtracts the count value cn04en from the count value cs4es, and outputs a value obtained by quadrupling the result of the subtraction to the signal processing unit 13 via the output line 261 as a pixel value of the pixel 200.

  The timing of starting the level change of the reference signal G1e generated in the period t7 by the timing unit 211 is earlier than the timing of starting the level change of the reference signal G4e generated in the period t7 by the timing unit 211. The level of the reference signal G1e generated by the timing section 211 in the periods t2 and t7 at the start of the level change is the same as the level of the reference signal G4e generated by the timing section 211 in the periods t3 and t7 at the start of the level change. .

  Next, a case where the N signal Vn is equal to or higher than the signal level Vn1 and lower than the signal level Vn4 will be described. As an example, a case where the N signal Vn is at the signal level Vn1 will be described. In the period t2, the timing section 211 outputs the clock signal pCNTcks1 with the delay amount s1d to the count C circuit 501 via the clock signal line pCNTckx. The comparator 402 compares the signal level Vn1 of the N signal Vn with the reference signal G1e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks1 in the count period tn11es, and outputs the count value cn11es at that time. The arithmetic circuit 405 stores the count value cn11es.

  In the period t3, the timing section 211 outputs the clock signal pCNTckn4 with the delay amount n4d to the count C circuit 501 via the clock signal line pCNTckx. Here, the delay amount n4d is a time from the level change start time of the reference signal G4e to the intersection of the reference signal G4e and the signal level Vn1. The comparator 402 compares the signal level Vn1 of the N signal Vn with the reference signal G4e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTckn4 and outputs the count value cn14en at that time. The arithmetic circuit 405 stores the count value cn14en.

  In the period t7, the column signal processing unit 203 performs the same processing as in the case of the signal level Vn0. However, when the pixel signal Vsig is the S signal VsigL, the arithmetic circuit 405 determines the result of subtracting the count value cn11es from the count value cs1es as the pixel value of the pixel 200 via the output line 261. 13 is output. When the pixel signal Vsig is the S signal VsigH, the arithmetic circuit 405 subtracts the count value cn14en from the count value cs4es and sets the value obtained by quadrupling the result of the subtraction as the pixel value of the pixel 200 as the output line. 261 to the signal processing unit 13.

  Next, the operation of column signal processing section 203 when N signal Vn is equal to or higher than signal level Vn4 will be described. As an example, a case where the N signal Vn is at the signal level Vn4 will be described. In the period t2, the timing section 211 outputs the clock signal pCNTcks1 with the delay amount s1d to the count C circuit 501 via the clock signal line pCNTckx. The comparator 402 compares the signal level Vn4 of the N signal Vn with the reference signal G1e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks1 and outputs the count value cn41es at that time. The arithmetic circuit 405 stores the count value cn41es.

  In the period t3, the timing unit 211 outputs the clock signal pCNTcks4 having the delay amount s4d to the count C circuit 501 via the clock signal line pCNTckx. The comparator 402 compares the signal level Vn4 of the N signal Vn with the reference signal G4e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks4 in the count period tn44es, and outputs the count value cn44es at that time. The arithmetic circuit 405 stores the count value cn44es.

  In the period t7, the column signal processing unit 203 performs the same processing as in the case of the signal level Vn0. However, when the pixel signal Vsig is the S signal VsigL, the arithmetic circuit 405 determines the result of subtracting the count value cn41es from the count value cs1es as the pixel value of the pixel 200 via the output line 261. 13 is output. When the pixel signal Vsig is the S signal VsigH, the arithmetic circuit 405 subtracts the count value cn44es from the count value cs4es and quadruples the result of the subtraction as the pixel value of the pixel 200, and outputs the resultant signal to the output line. 261 to the signal processing unit 13.

  As described above, the present embodiment can obtain the same effects as those of the first embodiment. Also, in the present embodiment, only one clock signal line pCNTckx is provided by adjusting the rising positions (level change start times) of the reference signals G1es and G4es. Wiring can be reduced and control can be simplified.

(Third embodiment)
FIG. 12 is a timing chart illustrating a control method of the column signal processing unit 203 according to the third embodiment of the present invention. The reference signals G1e and G4e are rounded and delayed with respect to the reference signals G1 and G4, respectively. This embodiment has the same configuration and operation as the first embodiment. Hereinafter, the points of this embodiment different from the first embodiment will be described. 12, the rising portions of the reference signals G1e and G4e in the regions 601 to 603 in FIG.

  The signal level Vr0 is an initial signal level of the reference signals G1e and G4e, and is, for example, 0V. The reference signal G1e is generated such that the signal level at which the rounding of the reference signal G1e is eliminated becomes Vr0. Further, the reference signal G4e is generated such that the signal level at which the rounding of the reference signal G4e is eliminated becomes Vr0. For this purpose, the level change start signal level Vr1 of the reference signal G1e may be set to -Vn1, and the level change start signal level Vr4 of the reference signal G4e may be set to -Vn4. This makes it possible to perform analog-to-digital conversion of the pixel signal Vsig using the reference signals G1e and G4e that are not affected by rounding.

  The clock signal pCNTcks1 is delayed by a delay amount s1d from the level change start time of the reference signal G1e. The delay amount s1d is a period from when the level change of the reference signal G1e starts to when the rounding of the reference signal G1e is eliminated.

  The clock signal pCNTcks4 is delayed by a delay amount s4d from the level change start time of the reference signal G4e. The delay amount s4d is a period from the level change start time of the reference signal G4e until the rounding of the reference signal G4e is eliminated. The level change start time of the reference signal G4e is the same as the level change start time of the reference signal G1e. The delay amounts s1d and s4d can be measured and set in advance.

  Here, the signal level Vn0 shows an example of the potential of the N signal Vn, and is lower than the signal level Vs in FIG. The relationship among the reference signals G1, G1e, and G1es is the same as in FIG. Similarly, the relationship among the reference signals G4, G4e and G4es is the same as in FIG.

  Next, the operation of the column signal processing unit 203 will be described. The imaging element 12 clamps the initial potential of the pixel signal Vsig and the initial signal level Vr0 of the signal Vrmp in advance in the comparator 402 as an operation of matching the reference of the comparison between the pixel signal Vsig and the signal Vrmp input to the comparator 402. Keep it. As an example, a description will be given assuming that the N signal Vn is at the signal level Vn0.

  In the period t2, the switch circuit 502 outputs the clock signal pCNTcks1 to the count C circuit 501 via the clock signal line pCNTck1 according to the signal on the switch control line pSwCk. The reference signal G1e is in a delay state. Therefore, the timing unit 211 outputs the clock signal pCNTcks1 of the delay amount s1d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G1e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks1 in the count period tn01es, and outputs the count value cn01es at that time. The arithmetic circuit 405 stores the count value cn01es.

  Next, in the period t3, the switch circuit 502 outputs the clock signal pCNTcks4 to the count C circuit 501 via the clock signal line pCNTck4 according to the signal on the switch control line pSwCk. The reference signal G4e is in a delay state. Therefore, the timing unit 211 outputs the clock signal pCNTcks4 of the delay amount s4d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the signal level Vn0 of the N signal Vn with the reference signal G4e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks4 in the count period tn04es, and outputs the count value cn04es at that time. The arithmetic circuit 405 stores the count value cn04es.

  After the period t4, the processing differs depending on whether the pixel signal Vsig is the S signal VsigL or VsigH. First, a case where the pixel signal Vsig is the S signal VsigL will be described. In the period t6, the comparator 402 outputs a low level to the switch control line pSwC because the S signal VsigL is smaller than the determination signal Vjd. In the period t7, since the switch control line pSwC is at the low level, the switch circuit 502 outputs the clock signal pCNTcks1 to the count C circuit 501 via the clock signal line pCNTck1. The reference signal G1e is in a delay state. Therefore, the timing unit 211 outputs the clock signal pCNTcks1 of the delay amount s1d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the S signal VsigL with the reference signal G1e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks1 in the count period ts1es, and outputs the count value cs1es at that time. The arithmetic circuit 405 stores the count value cs1es. Then, the arithmetic circuit 405 outputs the result of subtraction of the count value cn01es from the count value cs1es to the signal processing unit 13 via the output line 261 as the pixel value of the pixel 200.

  Next, a case where the pixel signal Vsig is the S signal VsigH will be described. In the period t6, the comparator 402 outputs a high level to the switch control line pSwC because the S signal VsigH is larger than the determination signal Vjd. In the period t7, since the switch control line pSwC is at the high level, the switch circuit 502 outputs the clock signal pCNTcks4 to the count C circuit 501 via the clock signal line pCNTck4. The reference signal G4e is in a delay state. Therefore, the timing unit 211 outputs the clock signal pCNTcks4 of the delay amount s4d to the count C circuit 501 via the switch circuit 502. The comparator 402 compares the S signal VsigH with the reference signal G4e, and the count C circuit 501 counts the number of pulses of the clock signal pCNTcks4 in the count period ts4es, and outputs the count value cs4es at that time. The arithmetic circuit 405 stores the count value cs4es. Then, the arithmetic circuit 405 subtracts the count value cn04es from the count value cs4es, and outputs a value obtained by quadrupling the result of the subtraction to the signal processing unit 13 via the output line 261 as a pixel value of the pixel 200.

  The level Vr1 of the reference signal G1e generated by the timing unit 211 in the periods t2 and t7 at the start of the level change is larger than the level Vr4 of the reference signal G4e generated by the timing unit 211 in the periods t3 and t7 at the start of the level change.

  The level Vr0 of the reference signal G1e input to the comparator 402 in the periods t2 and t7 at the start of the level change is higher than the level Vr1 of the reference signal G1e generated by the timing unit 211 in the periods t2 and t7 at the start of the level change. The level Vr0 of the reference signal G4e input by the comparator 402 in the periods t3 and t7 at the start of the level change is larger than the level Vr4 of the reference signal G4e generated by the timing unit 211 in the periods t3 and t7 at the start of the level change. . The level Vr0 of the reference signal G1e input to the comparator 402 in the periods t2 and t7 at the start of the level change is the same as the level Vr0 of the reference signal G4e input to the comparator 402 in the periods t3 and t7 at the start of the level change. .

  The timing of the level change start of the reference signal G1e generated by the timing unit 211 in the period t7 is the same as the timing of the level change start of the reference signal G4e generated by the timing unit 211 in the period t7.

  As described above, in the present embodiment, the delay amounts of the clock signals pCNTcks1 and pCNTcks4 corresponding to the delay amounts of the reference signals G1e and G4e are set. As a result, it is possible to obtain a good image signal in which the signal unevenness due to the AD conversion of the AD conversion circuit has been eliminated.

  Further, the delay amounts of the clock signals pCNTcks1 and pCNTcks4 corresponding to the reference signals G1e and G4e having different rates of change are set. As a result, A / D conversion with a wide dynamic range and high resolution can be performed, and a good image signal in which signal unevenness has been eliminated can be obtained.

  Further, with respect to the rounding of the waveform occurring at the rise of the reference signals G1e and G4e, the rounded signal level Vr0 is set to the initial signal level of the ramp signal lines Vrmp1 and Vrmp4. Thus, the comparator 402 can compare the pixel signals Vsig with the reference signals G1e and G4e that are not affected by rounding.

  In the present embodiment, the reference signals G1e and G4e need only be considered by considering only the delay while avoiding the influence of rounding. Therefore, compared to the first embodiment, the two clock signals pCNTcks1 and pCNTcks4 are compared. Control can be simplified.

  It should be noted that each of the above-described embodiments is merely an example of a concrete example for carrying out the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features.

  The imaging element 12 is applicable to a digital camera, a video camera, a smartphone, a tablet, an industrial camera, a medical camera, a vehicle-mounted camera, and the like.

12 image sensor, 200 pixels, 203 column signal processing section, 211 timing section, 231 column signal line, 402 comparator, 403 counter circuit, 404 latch circuit, 405 arithmetic circuit

Claims (18)

A pixel including photoelectric conversion means for converting light into electric charges,
Generating means for generating a first reference signal changing at a first change rate and a second reference signal changing at a second change rate larger than the first change rate;
Analog-to-digital conversion means for converting the output signal of the pixel from analog to digital,
The analog-to-digital conversion means,
In the first period, the output signal of the pixel based on the reset release of the pixel is compared with the first reference signal, and counting is performed on the basis of the first clock signal. Generating a first digital value obtained by converting the output signal of the pixel from analog to digital;
In a second period different from the first period, the output signal of the pixel based on the reset release of the pixel is compared with the second reference signal, and counting is performed based on a second clock signal. Generating a second digital value obtained by converting the output signal of the pixel based on the reset release of the pixel from analog to digital,
In a third period different from the first and second periods, when the output signal of the pixel based on the charge converted by the photoelectric conversion unit is smaller than the determination signal, the pixel is converted by the photoelectric conversion unit. By comparing the output signal of the pixel based on the charge with the first reference signal and counting based on a third clock signal, the output signal of the pixel based on the charge converted by the photoelectric conversion unit is calculated. A third digital value converted from analog to digital is generated, and if the output signal of the pixel based on the charge converted by the photoelectric conversion means is larger than the determination signal, the charge converted by the photoelectric conversion means is generated. By comparing the output signal of the pixel based on the second reference signal with the second reference signal and counting based on a fourth clock signal, the change is performed by the photoelectric conversion unit. The output signal of the pixel based on the charges to generate a fourth digital value converted from analog to digital,
The first clock signal starts pulse generation after a first time from a level change start time of the first reference signal generated in the first period by the generation unit,
The second clock signal starts to generate a pulse after a second time from a level change start time of the second reference signal generated in the second period by the generation unit,
The third clock signal starts pulse generation at a third time after a level change start time of the first reference signal generated by the generation unit in the third period,
An image pickup apparatus, wherein the pulse generation of the fourth clock signal is started at a fourth time after a level change start time of the second reference signal generated by the generation unit in the third period. .   The imaging apparatus according to claim 1, wherein the first to fourth times are different from each other. The first time and the third time are the same as each other;
The imaging apparatus according to claim 1, wherein the first time, the second time, and the fourth time are different from each other. The first time and the third time are the same as each other;
The second time and the fourth time are the same as each other,
The imaging apparatus according to claim 1, wherein the first time and the second time are different from each other.   The level change start timing of the first reference signal generated by the generation unit in the third period is the timing of the level change start of the second reference signal generated by the generation unit in the third period. The imaging device according to claim 1, wherein the imaging device is the same as the imaging device.   The level when the level of the first reference signal generated by the generation unit in the third period starts changing is the level when the level of the second reference signal generated by the generation unit in the third period starts. The imaging apparatus according to any one of claims 1 to 5, wherein the level is the same as the level of (i).   The imaging device according to claim 1, wherein the third clock signal and the fourth clock signal are the same signal.   The imaging apparatus according to claim 7, wherein the first clock signal, the second clock signal, and the third clock signal are different from each other.   The level change start timing of the first reference signal generated by the generation unit in the third period is the timing of the level change start of the second reference signal generated by the generation unit in the third period. The imaging device according to claim 1, wherein the imaging device is different from the imaging device.   The level when the level of the first reference signal generated by the generation unit in the third period starts to change is the level when the level of the second reference signal generated by the generation unit in the third period starts to change. The image pickup apparatus according to claim 7, wherein the level is the same as that of the image pickup apparatus. The first time and the third time are mutually the same,
The imaging device according to claim 1, wherein the second time and the fourth time are the same as each other.   The imaging apparatus according to claim 11, wherein the first time and the second time are different from each other.   The level when the level of the first reference signal generated by the generation unit in the third period starts to change is the level when the level of the second reference signal generated by the generation unit in the third period starts to change. The imaging device according to claim 1, wherein the imaging device has a different level. The level at the start of the level change of the first reference signal input by the analog-to-digital converter in the third period is the level change of the first reference signal generated by the generation unit in the third period. Unlike the starting level,
The level at the start of the level change of the second reference signal input by the analog-to-digital converter in the third period is the level change of the second reference signal generated by the generator in the third period. 14. The imaging apparatus according to claim 1, wherein the level is different from the level at the start.   The level of the first reference signal input by the analog-to-digital converter in the third period at the start of the level change is the level of the second reference signal input by the analog-to-digital converter in the third period. The imaging apparatus according to claim 14, wherein the level is the same as the level at the start of the level change.   The level change start timing of the first reference signal generated by the generation unit in the third period is the timing of the level change start of the second reference signal generated by the generation unit in the third period. The imaging device according to any one of claims 11 to 15, wherein: The second rate of change is a first factor times the first rate of change;
When an output signal of the pixel based on the electric charge converted by the photoelectric conversion unit is smaller than the determination signal, a difference between the third digital value and the first digital value is calculated, and the photoelectric conversion unit When the output signal of the pixel based on the electric charge converted by the above is larger than the determination signal, a value obtained by multiplying the difference between the fourth digital value and the second digital value by the first coefficient is used. The imaging device according to claim 1, further comprising a calculation unit configured to perform a calculation. A pixel including photoelectric conversion means for converting light into electric charges,
A method for controlling an imaging apparatus, comprising: a first reference signal that changes at a first rate of change; and a generation unit that generates a second reference signal that changes at a second rate of change that is greater than the first rate of change. hand,
In the first period, the analog-to-digital converter compares the output signal of the pixel based on the reset release of the pixel with the first reference signal, and counts based on a first clock signal. Generating a first digital value obtained by converting the output signal of the pixel based on the reset release of the pixel from analog to digital;
In the second period different from the first period, the analog-to-digital converter compares the output signal of the pixel based on the reset release of the pixel with the second reference signal, and outputs a second clock signal. Generating a second digital value obtained by converting the output signal of the pixel based on the reset release of the pixel from analog to digital by counting based on
In the third period different from the first and second periods, the output signal of the pixel based on the charge converted by the photoelectric conversion unit is smaller than the determination signal by the analog-to-digital conversion unit. By comparing the output signal of the pixel based on the electric charge converted by the photoelectric conversion means with the first reference signal and counting based on a third clock signal, the charge is converted into the electric charge converted by the photoelectric conversion means. Generating a third digital value obtained by converting the output signal of the pixel based on the analog to digital, and when the output signal of the pixel based on the charge converted by the photoelectric conversion unit is larger than the determination signal, An output signal of the pixel based on the charge converted by the conversion unit is compared with the second reference signal, and counting is performed based on a fourth clock signal. And a, and a step of generating a fourth digital value converted from analog to digital output signals of the pixels based on the electric charge converted by said photoelectric conversion means,
The first clock signal starts pulse generation after a first time from a level change start time of the first reference signal generated in the first period by the generation unit,
The second clock signal starts to generate a pulse after a second time from a level change start time of the second reference signal generated in the second period by the generation unit,
The third clock signal starts pulse generation at a third time after a level change start time of the first reference signal generated by the generation unit in the third period,
An image pickup apparatus, wherein the pulse generation of the fourth clock signal is started at a fourth time after a level change start time of the second reference signal generated by the generation unit in the third period. Control method.

Images