JP2020057884A - Imaging apparatus and electronic apparatus - Google Patents

Abstract

To provide an imaging apparatus capable of expanding a dynamic range while reducing generation of a dark current due to interface defects under a gate of a transfer transistor.SOLUTION: The imaging apparatus includes: a first mode in which the number of times the comparison result is inverted is counted using a saturation counter and connection means connects an output terminal and an input terminal; and a second mode in which counting is performed until a comparison result is inverted using a clock counter and the connection means does not connect the output terminal and the input terminal. In the first mode, a transfer unit and a reset unit are turned on by inverting the comparison result, and after a photoelectric conversion element and floating diffusion capacitance are reset, the transfer unit and the reset unit are turned off again.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an imaging device, and particularly to a configuration and driving of the imaging device.

  2. Description of the Related Art Imaging devices such as CMOS image sensors are widely used in imaging devices such as digital still cameras and digital video cameras. In recent years, an image sensor having an AD converter for each pixel has been proposed (Patent Document 1). In this configuration, the amount of light that can be input is not limited by the storage capacity, so that the dynamic range can be expanded.

  Patent Literature 1 proposes a circuit for AD-converting a charge generated by a photoelectric conversion element. When the voltage of the storage capacitor connected in parallel with the photoelectric conversion element reaches a predetermined value, the voltage of the storage capacitor is returned to the reset voltage. The AD conversion is performed by counting the number of resets and outputting the number of resets.

  A transfer transistor is arranged between the photoelectric conversion element and the storage capacitor, and the transfer transistor is turned off during a period in which the voltage of the storage capacitor is returned to the reset voltage.

  On the other hand, the transfer transistor is turned on during a period in which the signal charge generated by the photoelectric conversion element is being transferred to the storage capacitor. Therefore, when the amount of charge generated by the photoelectric conversion element is small, the time during which the transfer transistor is turned on during the accumulation period becomes long.

JP 2015-173432 A

  However, as the time during which the transfer transistor is turned on becomes longer, dark current increases due to electrons generated by interface defects below the gate of the transfer transistor. For this reason, the image quality is deteriorated due to the influence of noise due to the increased dark current.

  An object of the present invention is to provide an imaging apparatus capable of expanding a dynamic range while reducing generation of a dark current due to an interface defect below a gate of a transfer transistor in order to solve such a problem. is there.

In order to achieve the above object, an imaging device according to the present invention includes:
A photoelectric conversion element that generates a charge according to luminance,
A floating diffusion capacitance to which charges generated in the photoelectric conversion element are transferred,
A reset unit for resetting the voltage of the floating diffusion capacitance,
A transfer unit that transfers the charge generated by the photoelectric conversion element to the floating diffusion capacitance,
A comparison signal generation circuit that generates a comparison signal;
A comparator for comparing the voltage of the floating diffusion capacitor with the voltage of the comparison signal;
Connection means for selectively connecting an output terminal of the comparator and an input terminal of the transfer unit and the reset unit;
A clock counter that counts until the result of comparison between the voltage of the floating diffusion capacitance and the voltage of the comparison signal is inverted,
A comparison is made between the voltage of the floating diffusion capacitor, which changes due to the charge transferred from the photoelectric conversion element, and the voltage of the comparison signal in a state where the transfer unit is turned off, and the saturation is performed to count the number of times the comparison result is inverted. A counter,
A memory unit for recording a value counted by the saturation counter and the clock counter,
Count the number of times the comparison result is inverted using the saturation counter,
A first mode for connecting the output terminal and the input terminal,
Count until the comparison result is inverted using the clock counter,
The connection means has a second mode in which the output terminal and the input terminal are not connected,
In the first mode, the transfer unit and the reset unit are turned on by inverting the comparison result, and after the photoelectric conversion element and the floating diffusion capacitance are reset, the transfer unit and the reset unit are turned off again. It is characterized by that.

  According to the present invention, it is possible to provide an imaging device capable of expanding a dynamic range while reducing generation of dark current due to an interface defect below a gate of a transfer transistor.

FIG. 2 is an equivalent circuit diagram of a pixel unit according to the first embodiment of the present invention. 6 is a timing chart illustrating a flow of a process performed by a pixel unit. FIG. 3 is another equivalent circuit diagram of the pixel unit according to the first embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration example of an electronic device. FIG. 9 is an equivalent circuit diagram of a pixel unit according to a second embodiment of the present invention. It is a conceptual diagram of an imaging device by a 2nd embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is an equivalent circuit diagram of the pixel unit 100 according to the first embodiment of the present invention. The pixel unit 100 photoelectrically converts the received subject image, further converts the electric signal into a digital signal, and outputs the digital signal. The pixel portion 100 includes a photodiode 101, a transfer transistor 102, a floating diffusion capacitor 103, a reset transistor 104, a source follower 115, a comparator 105, a transfer switch 106, a reset switch 107, an output selection switch 108, a comparison signal generation circuit 109, a signal It includes a selection switch 110, a saturation counter 111, a clock counter 112, a clock switch 113, and a memory unit 114.

  The photodiode 101 generates and accumulates signal charges corresponding to the received light. ON / OFF of the transfer transistor 102 is controlled by a signal from a transfer switch 106 described later, and the signal charge accumulated in the photodiode 101 is transferred to the floating diffusion capacitor 103. The floating diffusion capacitance 103 is a capacitance electrically connected to a gate electrode of a source follower 115 and a transfer transistor 102 described later.

  ON / OFF of the reset transistor 104 is controlled by a signal from a reset switch 107 described later, and resets unnecessary signal charges existing in the photodiode 101 and the floating diffusion capacitor 103. The source follower 115 converts the signal charge transferred to the floating diffusion capacitor 103 into a voltage and outputs the voltage to the comparator 105.

  The comparator 105 compares the voltage VR of the reference signal or the voltage VS of the slope signal supplied from the later-described comparison signal generation circuit 109 with the voltage VFD of the floating diffusion capacitor 103, and outputs the comparison result (VCOMP). The output of the comparator 105 is supplied to a transfer switch 106, a reset switch 107, and an output selection switch 108 as selection means.

  The transfer switch 106 is controlled by the signal ETX, and supplies either the output of the comparator 105 or the signal PTX to the transfer transistor 102. The reset switch 107 is controlled by the signal ERES, and supplies either the output of the comparator 105 or the signal PRES to the reset transistor 104. Here, when the signal ETX or the signal ERES is “L”, ON / OFF of the transfer transistor 102 and the reset transistor 104 is switched according to VCOMP. The output selection switch 108 is controlled by the signal EREF, and supplies the output of the comparator 105 to a saturation counter 111 or a clock counter 112 described later.

  The comparison signal generation circuit 109 generates a reference signal and a slope signal which are comparison signals for comparison with the voltage VFD. These signals are supplied to a signal selection switch 110 described later. The signal selection switch 110, which is a selection unit, is controlled by the signal EREF, and supplies one of the reference signal and the slope signal supplied from the comparison signal generation circuit 109 to the comparator 105.

  The saturation counter 111 compares the voltage VFD with the voltage VR of the reference signal by the comparator 105, and counts and records the number of times that the voltage VFD is determined to be smaller than the voltage VR. The saturation counter 111 supplies the recorded value (CNTS) to the memory unit 114. The clock counter 112 is supplied with a clock from a clock switch 113 described later, and performs a counting operation using the clock. Further, the clock counter 112 compares the voltage VFD with the voltage VS of the slope signal by the comparator 105, and records a count value when it is determined that the voltage VS is smaller than the voltage VFD. In addition, the clock counter 112 supplies the recorded count value to the memory unit 114. The clock switch 113 is controlled by the signal EREF and supplies a clock to the clock counter 112. The memory unit 114 performs an operation on the values supplied from the saturation counter 111 and the clock counter 112, and outputs the result outside the pixel unit.

  FIG. 2 is a timing chart for explaining the flow of processing of the pixel unit 100 according to the present invention. With reference to FIGS. 1 and 2, a series of operations from converting a signal charge generated in the pixel unit 100 into a digital signal and outputting the digital signal to the outside of the pixel unit will be described. 2A shows the case where the intensity of light incident on the photodiode 101 is low, and FIG. 2B shows the case where the intensity of light incident on the photodiode 101 is high.

  First, an operation example when the intensity of light incident on the photodiode 101 is low will be described with reference to FIG. In FIG. 2A, the signal ERES is set to “H” and the signal PRES is supplied to the reset transistor 104 before the signal charge is accumulated in the photodiode 101. Further, the signal PTX and the signal PRES are set to “H”, and the transfer transistor 102 and the reset transistor 104 are turned on. As a result, unnecessary signal charges of the photodiode 101 and the floating diffusion capacitor 103 are reset.

  At time t200, the signal PRES is set to “L”, the reset transistor 104 is turned off, and the reset state is released. Then, the photodiode 101 generates signal charges and starts accumulating the signal charges. Further, the signals ERES and ETX are set to “L”, and the output of the comparator 105 is supplied to the gates of the transfer transistor 102 and the reset transistor 104. The signal EREF becomes “L”, and the signal selection switch 110 supplies a reference signal from the comparison signal generation circuit 109 to the comparator 105. Similarly, the output selection switch 108 supplies the comparison result VCOMP of the comparator 105 to the saturation counter 111. The comparator 105 starts comparing the voltage VR of the reference signal with the voltage VFD of the floating diffusion capacitor 103.

  At this time, the transfer transistor 102 is turned off by applying a negative voltage to the gate of the transfer transistor 102. By applying a negative voltage, holes are induced below the gate of the transfer transistor 102. The induced holes are combined with electrons generated by interface defects below the gate. As a result, the number of electrons generated in the interface defect that causes the dark current is reduced. Therefore, by applying a negative voltage to the gate of the transfer transistor 102 to turn off the transfer transistor 102, generation of dark current can be reduced.

  Since the transfer transistor 102 is turned off, the signal charge accumulated in the photodiode 101 is not transferred to the floating diffusion capacitance 103. However, depending on the intensity of incident light, the amount of signal charges generated by the photodiode 101 exceeds the amount of charges that can be accumulated by the photodiode 101 itself. The signal charge generated exceeding the amount of charge that can be stored moves to the floating diffusion capacitor 103 via the transfer transistor 102.

  At time t201, signal charges generated in excess of the amount of charge that can be accumulated in the photodiode 101 itself move to the floating diffusion capacitor 103. As a result, the voltage VFD starts to gradually decrease from the voltage in the reset state.

  At time t202, when the voltage VFD falls below the voltage VR, the comparison result VCOMP becomes “H”, and the result is supplied to the transfer transistor 102, the reset transistor 104, and the saturation counter 111. The transfer transistor 102 and the reset transistor 104 are turned on, and the signal charges of the photodiode 101 and the floating diffusion capacitor 103 are reset. The saturation counter 111 counts according to the comparison result VCOMP.

  At time t203, the voltages of the photodiode 101 and the floating diffusion capacitance 103 are reset. Then, the photodiode 101 again generates a signal charge and starts accumulation. The comparator 105 compares the reset voltage VFD with the voltage VR. As a result of the comparison, VCOMP becomes “L”, and the transfer transistor 102 and the reset transistor 104 are turned off.

  At a time t204, the signal ERES is set to “H”, and the signal PRES is supplied to the reset transistor 104. Further, the signal PRES is set to “H”, and the reset transistor 104 is turned on. As a result, the signal charges existing in the floating diffusion capacitance 103 are reset. The signal ETX is set to “H”, and the transfer switch 106 supplies the signal PTX to the transfer transistor 102. At this time, the signal PTX is set to “L”.

  Due to the operation (first mode) from time t200 to time t204, the saturation counter 111 supplies the CNTS to the memory unit 114. When the time t204 ends, the generation and accumulation (accumulation time) of the signal charge in the photodiode 101 ends.

  At time t205, the signal PRES is set to “L”, the reset transistor 104 is turned off, and the reset state is released. Further, the signal EREF is set to “H”, and the signal selection switch 110 supplies a slope signal from the comparison signal generation circuit 109 to the comparator 105. The clock switch 113 supplies a clock to the clock counter 112. The clock counter 112 starts a count operation using the supplied clock. The comparator 105 and the clock counter 112 are connected via the output selection switch 108. Then, the comparator 105 starts comparing the voltage VFD with the voltage VS, and supplies the result to the clock counter 112.

  At time t206, when the voltage VFD exceeds the voltage VS, the comparison result VCOMP becomes “H”. At the same time, the clock counter 112 supplies the count value at this time (hereinafter referred to as N value) to the memory unit 114. With this processing, it is possible to obtain an AD conversion result according to the level of the voltage VFD. The N value is a value obtained by AD-converting the voltage when the reset state is released, and this value includes a reset noise component.

  At time t207, since the voltage VS of the slope signal has reached a certain value, the comparison between the voltage VFD and the voltage VS ends. Further, the clock supplied to the clock counter 112 stops, and the clock counter 112 also stops counting.

  From time t208 to time t209, the signal PTX becomes “H”, the transfer transistor 102 is turned on, and the signal charge accumulated in the photodiode 101 is transferred to the floating diffusion capacitor 103.

  At time t210, comparison signal generation circuit 109 supplies a slope signal to comparator 105. Further, a clock is supplied to the clock counter 112 to start a counting operation. Comparator 105 starts comparing voltage VFD with voltage VS, and supplies the result to clock counter 112.

  At time t211, when the voltage VFD exceeds the voltage VS, the comparison result VCOMP becomes “H”. At the same time, the clock counter 112 supplies the count value at this time (hereinafter referred to as an S value) to the memory unit 114. An AD conversion result according to the level of voltage VFD can be obtained.

  The S value includes a light component (LS), a reset noise component, and a noise component due to dark current (NDC). This NDC is determined by the increase and decrease of electrons generated by interface defects below the gate of the transistor. In the NDC, there is a component generated when the transfer transistor 102 is turned on during a period from time t200 to time t204.

  In the above-described driving, the transfer transistor 102 is turned off from time t200 to time t202 and from time t203 to time t204 from time t200 to time t204 when the signal charge generated in the photodiode 101 is accumulated. As a result, the time during which the transfer transistor 102 is turned on is shortened, and the number of electrons generated by the interface defect under the gate can be reduced. As a result, NDC included in the S value can be reduced.

At time t212, since the slope signal VS has reached a certain value (a value lower than time t206), the comparison between the voltage VFD and the voltage VS ends. Further, the clock supplied to the clock counter 112 stops, and the clock counter 112 also stops counting. After the operation (second mode) from time t205 to time t212 ends, the memory unit 114 subtracts the N value obtained at time t206 from the S value obtained at time t211. By this subtraction, a value obtained by removing the reset noise component from the S value can be obtained. Then, at time t204, the CNTS and the subtracted S value are combined so that the CNTS supplied by the saturation counter 111 is arranged on the most significant bit side. The pixel unit 100 outputs the combined value (hereinafter, referred to as a digital signal) to the outside of the pixel unit. The output digital signal (DOUT) is
DOUT = (CNTS × EC) + (LS + NDC)
Value. EC has a value corresponding to the amount of charge that can be accumulated in the photodiode 101 when the transfer transistor 102 is turned off. In the case of FIG. 2A, from time t200 to time t204, the time during which the transfer transistor 102 is turned on is limited to the reset period of the floating diffusion capacitor 103, so that the dark current generated by the interface defect under the gate of the transfer transistor 102 is reduced. A reduced digital signal can be generated.

  Next, an operation example when the intensity of light incident on the photodiode 101 is high will be described with reference to FIG. The operation from time t220 to time t223 is the same as the operation from time t200 to time t203 in FIG.

  The above operation is repeated from time t224 to time t229, and the saturation counter 111 counts the number of times that the amount of charge that the photodiode 101 can store is exceeded. The operation at time t230 is the same as that at time t204 in FIG. By the operation from the time t220 to the time t230, the saturation counter 111 supplies the CNTS to the memory unit 114.

  When the time t230 ends, the generation and accumulation (accumulation time) of the signal charge in the photodiode 101 ends. In the case of FIG. 2B, the operation from time t220 to time t230 is the first mode.

  The operation from time t231 to time t238, which is the second mode, is the same as the operation from time t205 to time 212 in FIG. The memory unit 114 removes the reset noise component by subtracting the N value obtained at time t232 from the S value obtained at time t237. Then, the CNTS and the subtracted S value are combined so that the CNTS supplied by the saturation counter 111 is arranged on the most significant bit side. The pixel unit 100 outputs a digital signal (DOUT) outside the pixel unit.

  In the case of FIG. 2B, the time for turning on the transfer transistor 102 is longer than that of FIG. 2A, so that the NDC increases. However, the ratio of the NDC to the entire output digital signal is sufficiently small, so this is not a problem.

  As described above, by performing the processing described with reference to FIGS. 1 and 2, the imaging device shortens the time during which the transfer transistor 102 is turned on, and reduces the generation of dark current due to an interface defect below the gate of the transfer transistor 102. A digital signal with an expanded dynamic range can be obtained.

  Note that the following relationship is established between the times in the timing chart of FIG. For example, when the frequency of the clock supplied to the clock counter 112 is 1 GHz and the resolution of the AD conversion of the pixel unit 100 is 12 bits, the total time of acquiring the S value and the N value in the second mode is within 10 μsec. .

  On the other hand, when an image of a subject having a light amount LV12 is taken using the pixel portion 100 and a lens having an aperture value of F5.6, when the first mode is set to 100 ms or more, the amount of signal charges generated in the photodiode 101 is increased. Exceeds the amount of charge that can be accumulated by the photodiode 101 itself. Therefore, the time of the second mode is sufficiently shorter than the time of the first mode. Therefore, in the second mode, the amount of signal charge generated by the photodiode 101 exceeds the amount of charge that can be accumulated by the photodiode 101 itself, and the voltage VFD of the floating diffusion capacitor 103 rarely changes.

  FIG. 3 is a diagram illustrating another example of an equivalent circuit of the pixel unit 100. The pixel portion 300 of this example further includes an overflow drain transistor 301 in addition to the circuit configuration of the pixel portion 100 shown in FIG. ON / OFF of the overflow drain transistor 301 is controlled by the signal POF, and the signal drain generated by the photodiode 101 is discharged.

  In the pixel portion 100 of FIG. 1, when the intensity of light incident on the photodiode 101 is high as shown in FIG. 2B, the light is generated by the photodiode 101 in the second mode in which the S value and the N value are acquired. The amount of the generated signal charge exceeds the amount of charge that can be stored in the photodiode 101 itself. As a result, the voltage VFD of the floating diffusion capacitance 103 changes.

  In order to suppress this change, the signal POF is set to “H” and the overflow drain transistor 301 is turned on while the pixel unit 300 in FIG. 3 is acquiring the S value and the N value. As a result, signal charges generated and accumulated in the photodiode 101 are discharged, and a change in the voltage VFD is suppressed. The period during which the signal POF is set to “H” is performed from time t204 to time t212 in FIG. 2A, and from time t230 to time t238 in FIG. 2B. By operating the overflow drain transistor 301 in this manner, it is possible to suppress the voltage VFD from changing during the second mode.

  By providing the overflow drain transistor 301, for example, when there is a subject having a higher light intensity than the target subject at the time of shooting, the signal charges generated and accumulated in the photodiode 101 during the second mode are discharged, A change in voltage VFD can be suppressed. Note that as an operation of the overflow drain transistor 301, the signal POF is set to “H” before the time t200 in FIG. 2A and the time t220 in FIG. 2B, and unnecessary signal charges accumulated in the photodiode 101 are reduced. You may make it discharge | emit.

  In the pixel portion 100 of the present invention, as shown in FIG. 2, the signal charge exceeding the charge amount that can be accumulated by the photodiode 101 itself moves to the floating diffusion capacitor 103, so that the voltage VFD changes. The photodiodes 101 forming the pixel portion 100 have variations in sensitivity and variations in the amount of charge (EC) that can be accumulated. Due to these variations, the time when the voltage VFD becomes lower than the voltage VR, that is, the time t201 in FIG. 2A and the times t222, t225, and t228 in FIG. A method for reducing the influence of this variation will be described.

  FIG. 4 is a block diagram illustrating a configuration example of an electronic apparatus including an imaging device including the pixel unit 100 illustrated in FIG. The electronic device 400 includes a lens 401, an imaging device 402, a DSP 403, and a correction function memory 404.

  The lens 401 forms a subject image on the imaging device 402. The lens 401 has an aperture that changes the aperture diameter and determines an aperture value for adjusting the exposure amount. In the imaging device 400, the pixel units 100 are two-dimensionally arranged in a row direction and a column direction. Each pixel unit 100 outputs a digital signal by subjecting the subject image to photoelectric conversion and AD conversion. The DSP 403 performs a correction process using a correction function described later, various image processes, and a compression process on the digital signal supplied from the imaging device 402.

  The correction function memory 404 stores a correction function for correcting a digital signal output from each pixel unit 100. The correction function memory 404 supplies a correction function to the DSP 403 in response to a request from the DSP 403. The correction function can be changed or added by the DSP 403.

  Next, processing for performing correction using a correction function will be described. The imaging device 402 receives incident light through a lens 401. The pixel unit 100 supplies a digital signal corresponding to the emitted light to the DSP 403. The DSP 403 evaluates the level of the supplied digital signal. The DSP 403 selects a correction function to be used for correction from a plurality of correction functions recorded in the correction function memory 404 according to the evaluated level. The correction function memory 404 supplies the selected correction function to the DSP 403. The DSP 403 corrects the digital signal using the supplied correction function. This makes it possible to generate a digital signal in which variation in each pixel portion is reduced.

  Next, a method of generating a correction function will be described. Incident light having a uniform intensity is incident on each pixel unit 100 of the imaging device 402. The DSP 403 calculates an average value of the digital signals output from the respective pixel units 100. A correction function is generated based on the average value. For example, when the level of the digital signal output from the pixel unit 100 has a difference from the average value, the correction value is determined so as to eliminate the difference. This correction value is recorded in the correction function memory 404 as a correction function. The processing for generating the correction function is performed by changing the light intensity, thereby generating a correction function corresponding to the level of the digital signal. Thereby, it is possible to generate a plurality of correction functions according to the level of the digital signal.

  Here, the generation of the correction function may be performed according to the temperature at the time of shooting, or may be performed according to the drive mode of the imaging device. When the correction function is generated according to the temperature, for example, the electronic device 400 includes a thermometer. The temperature at the time of photographing is acquired by the thermometer, and a correction function is generated based on the acquired temperature information. When generating the correction function according to the drive mode of the imaging device, for example, the correction function may be generated according to the exposure time of the drive mode at the time of shooting a still image, or each time the frame rate of the drive mode is set at the time of shooting a moving image. May be generated.

  By performing the above-described configuration and processing, the imaging device according to the present invention can expand the dynamic range while reducing the occurrence of dark current due to interface defects below the gate of the transfer transistor. Here, the method of generating the correction function is an example, and the correction function may be generated by another method.

(Second embodiment)
FIG. 5 is an equivalent circuit diagram of the pixel unit 100 according to the second embodiment of the present invention. Differences from the configuration of the pixel unit 100 of the first embodiment shown in FIG. 1 will be described. The photoelectric converter 500 includes a photodiode 101, a transfer transistor 102, a floating diffusion capacitor 103, a reset transistor 104, a transfer switch 106, a reset switch 107, and a source follower 115. The comparison unit 501 includes a comparator 105, a comparison signal generation circuit 109, and a signal selection switch 110. The signal processing unit 502 includes an output selection switch 108, a saturation counter 111, a clock counter 112, a clock switch 113, and a memory unit 114.

  Although the equivalent circuit diagram of FIG. 5 is configured based on the pixel unit 100 illustrated in FIG. 1, the equivalent circuit diagram may be configured based on the pixel unit 300 illustrated in FIG. In this case, an overflow drain transistor 301 is added to the photoelectric conversion unit 500.

  FIG. 6 is a conceptual diagram of an imaging device including the pixel unit 100 described in FIG. The imaging device 600 includes a photoelectric conversion substrate 601, a digital conversion substrate 602, and a signal processing substrate 603, and has a structure in which the respective substrates are stacked. On the photoelectric conversion substrate 601, the digital conversion substrate 602, and the signal processing substrate 603, a photoelectric conversion unit 500, a comparison unit 501, and a signal processing unit 502 are two-dimensionally arranged in a row direction and a column direction, respectively. Although not shown in FIG. 6, the respective substrates are electrically connected by vias or micro bumps.

  By electrically coupling the respective substrates, the comparison unit 501 of the digital conversion substrate 602 compares the signal charge generated in the photoelectric conversion unit 500 of the photoelectric conversion substrate 601 with the reference signal or the slope signal. Then, the signal processing unit 502 of the signal processing board 603 converts the signal charge into a digital signal by using the comparison result of the comparison unit 501, and outputs the digital signal to the outside of the imaging device.

  The imaging device of the present invention includes the pixel unit of the first embodiment, and can increase the dynamic range while reducing the generation of dark current due to interface defects below the gate of the transfer transistor. In the present embodiment, the comparison unit 501 and the signal processing unit 502 are arranged on different substrates, but may be arranged on the same substrate according to their respective circuit areas. When the area of the photodiode 101 that performs photoelectric conversion is increased, a circuit element included in the photoelectric conversion unit 500 may be provided on a substrate other than the photoelectric conversion unit 601 such as the digital conversion substrate 602.

  As described above, the imaging device according to the present invention can expand the dynamic range while reducing the occurrence of dark current due to the interface defect below the gate of the transfer transistor. As described above, the preferred embodiments of the present invention have been described, but the present invention is not limited to these embodiments, and various modifications and changes can be made within the scope of the gist. Note that, in the imaging device of the present embodiment, the voltage VFD is compared with the voltage VR or the voltage VS using one comparator, but a configuration including two comparators may be employed. In this case, the first comparator compares the voltage VFD with the voltage VR, and the second comparator compares the voltage VFD with the voltage VS. Further, although the reference signal and the slope signal are generated from one comparison signal generation circuit, each signal may be generated by a separate comparison signal generation circuit.

100 pixel unit, 101 photodiode, 102 transfer transistor,
103 floating diffusion capacity,
104 reset transistor, 105 comparator,
106 transfer switch, 107 reset switch,
108 output selection switch, 109 comparison signal generation circuit,
110 signal selection switch, 111 saturation counter,
112 clock counter, 113 clock switch,
114 memory unit, 115 source follower

Claims (6)

A photoelectric conversion element that generates a charge according to luminance,
A floating diffusion capacitance to which charges generated in the photoelectric conversion element are transferred,
A reset unit for resetting the voltage of the floating diffusion capacitance,
A transfer unit that transfers the charge generated by the photoelectric conversion element to the floating diffusion capacitance,
A comparison signal generation circuit that generates a comparison signal;
A comparator for comparing the voltage of the floating diffusion capacitor with the voltage of the comparison signal;
Connection means for selectively connecting an output terminal of the comparator and an input terminal of the transfer unit and the reset unit;
A clock counter that counts until the result of comparison between the voltage of the floating diffusion capacitance and the voltage of the comparison signal is inverted,
A comparison is made between the voltage of the floating diffusion capacitor, which changes due to the charge transferred from the photoelectric conversion element, and the voltage of the comparison signal in a state where the transfer unit is turned off, and the saturation is performed to count the number of times the comparison result is inverted. A counter,
A memory unit for recording a value counted by the saturation counter and the clock counter,
Count the number of times the comparison result is inverted using the saturation counter,
A first mode for connecting the output terminal and the input terminal,
Count until the comparison result is inverted using the clock counter,
The connection means has a second mode in which the output terminal and the input terminal are not connected,
In the first mode, the transfer unit and the reset unit are turned on by inverting the comparison result, and after the photoelectric conversion element and the floating diffusion capacitance are reset, the transfer unit and the reset unit are turned off again. An imaging device, comprising: The comparison signal generation circuit generates a reference signal that does not change with time and a slope signal that changes with time,
The imaging device, a signal selection unit that supplies one of the reference signal or the slope signal to the comparator as the comparison signal,
Output selection means for supplying a comparison result to one of the saturation counter and the clock counter,
In the first mode, the signal selection unit supplies the reference signal to the comparator, and the output selection unit supplies a comparison result to the saturation counter,
In the second mode, the signal selection means supplies the slope signal to the comparator,
2. The imaging apparatus according to claim 1, wherein the output selection unit supplies a comparison result to the clock counter. Further comprising a charge discharging unit for discharging charges generated by the photoelectric conversion element,
3. The imaging device according to claim 1, wherein in the second mode, the charge discharging unit discharges charges generated in the photoelectric conversion element. 4.   The imaging device according to claim 1, wherein the photoelectric conversion element and the memory unit are provided on different substrates. A photoelectric conversion substrate including the photoelectric conversion element,
A digital conversion board comprising the comparator,
A signal processing board including the memory unit,
The imaging device according to any one of claims 1 to 4, wherein the imaging device is electrically connected to each other. An imaging device according to any one of claims 1 to 5,
A correction function memory for recording a plurality of correction functions for correcting the digital signal output by the imaging device,
A correction processing circuit that performs correction by using the plurality of correction functions on the digital signal output from the imaging device,
The correction processing circuit selects a correction function to be used for correction from among the plurality of correction functions recorded in the correction function memory according to the level of the digital signal output by the imaging device, and uses the selected correction function. An electronic device for correcting a digital signal.