JP2020052097A - Video signal processor, dither pattern generation method, and dither pattern generation program - Google Patents

Abstract

To provide a video signal processor with which it is possible to extend gradation with high quality.SOLUTION: A storage device (ROM 30) stores a three-dimensional dither pattern consisting of horizontal direction dot counts H × vertical direction line counts V × frame direction F dot counts. Each value from the minimum to the maximum value of an n-bit dither value is written to the address of the storage device that corresponds to each dot. When each value of dither value is written to the storage device, a process of finding a spatio-temporal density value that indicates the sparse-dense degree of an already written address in a three-dimensional area centering around each target address to which a new dither value is writable and a process of selecting an address, among the whole target address, that has the minimum spatio-temporal density value and writing a dither value are repeated. The processes are carried out so that the target address is hardly selected as an address having the minimum spatio-temporal density value, in accordance with the number of already written addresses in the three-dimensional area.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a video signal processing device, a dither pattern generation method, and a dither pattern generation program.

  With m and n being predetermined integers, a video signal having the first number of gradations of (m + n) bits may be input to a display that can express only the second number of gradations of m bits. In this case, the first number of gradations can be expressed in a pseudo manner by performing the n-bit multi-gradation processing on the m-bit video signal. As one of the pseudo multi-gradation processing, a video signal called FRC (Frame Rate Control) for reducing the number of bits after adding dither data having a dither pattern repeated at a plurality of frame periods to the video signal There is processing.

JP 2000-56726 A

  2. Description of the Related Art A general video signal processing apparatus performs pseudo multi-grayscale processing on a video signal by adding different dither patterns each composed of four dots of two horizontal lines and two vertical lines to the video signal in a four-frame cycle. According to the video signal processing device that adds dither data of a 4-dot dither pattern in a 4-frame cycle, it is possible to expand the gray scale of 2 bits in a pseudo manner.

  In order to make the number of bits to be expanded larger than 2 bits, the size of the block of the dither pattern should be larger than 4 dots, and the frame period for adding dither data of different dither patterns should be longer than 4 frames. . However, if dither data having a large dither pattern and a long frame period is added to the video signal, side effects are likely to occur. Therefore, there is a demand for a dither pattern in which side effects due to the addition of dither data are unlikely to occur and the gradation can be extended with high quality.

  The present invention provides a video signal processing apparatus and a dither pattern generation method in which a block of a dither pattern has a size exceeding 4 dots, side effects due to addition of dither data are less likely to occur, and gradation can be extended with high quality. And a dither pattern generation program.

  In the present invention, the number of dots in the horizontal direction is H, the number of lines in the vertical direction is V, and the number of lines in the frame direction is F. The number of H × V dots is a number exceeding 4, and is composed of the number of H × V dots. The two-dimensional block is one two-dimensional dither pattern in which each dot is set to a dither value that is one of n bits, and the two-dimensional dither pattern is a number F in the frame direction. And a storage device for storing dither data having a three-dimensional dither pattern composed of three-dimensional blocks arranged in the following manner, and a two-dimensional dither pattern having a number F in the frame direction are sequentially selected in a frame cycle F, An adder for adding a selected dither pattern for each two-dimensional block consisting of the number of H × V dots in a frame of the input video signal having the first number of bits, and an output of the adder And a lower bit reduction unit that outputs a video signal having a second bit number obtained by reducing the lower n bits of the first bit number. Each value from the minimum value to the maximum value of the n-bit dither value is written in the address of the storage device corresponding to each dot of the three-dimensional block of numbers, and the n-bit dither value is written in the storage device. When each dither value is written, the number of written addresses in which a dither value has already been written in a three-dimensional predetermined area centered on each target address to which a new dither value can be written. And a second process for calculating a spatio-temporal density value indicating the degree of density of the written address in a three-dimensional predetermined area centered on each of the target addresses. And a third process that makes it difficult for the target address to be selected as an address having the smallest spatio-temporal density value in accordance with the number of written addresses obtained by the first process; and And a fourth process of selecting the address having the smallest spatio-temporal density value from all the target addresses, and selecting the address having the smallest spatio-temporal density value by the fourth process. By repeating the fifth process of writing the dither value to the target address, the video signal processing device in which each value of the n-bit dither value is assigned to each dot of the three-dimensional block provide.

  In the present invention, the number of dots in the horizontal direction is H, the number of lines in the vertical direction is V, and the number of lines in the frame direction is F. The number of H × V dots is a number exceeding 4, and is composed of the number of H × V dots. The block is one two-dimensional dither pattern in which each dot is set to a dither value that is one of n bits, and the two-dimensional dither pattern is arranged in the frame direction by a number F. This is a dither pattern generation method for generating a three-dimensional dither pattern composed of a three-dimensional block, and an address in a storage device corresponding to each dot of a three-dimensional block consisting of H × V × F dots. Of the three-dimensional predetermined area centered on each target address to which a new dither value can be written, the number of written addresses to which a dither value has already been written is determined. A spatio-temporal density value indicating the degree of density of the written address in a three-dimensional predetermined area centered on the address is obtained, and the target address is calculated according to the obtained number of written addresses. The spatial density value is processed so as to be less likely to be selected as the smallest address, and the target address is processed so that the spatio-temporal density value is less likely to be selected as the smallest address. Processing for selecting an address having the smallest spatio-temporal density value, writing a dither value to the target address selected as the address having the smallest spatio-temporal density value, and calculating the number of written addresses; Calculating the target address, making it difficult for the target address to be selected as the address having the smallest spatio-temporal density value; The process of selecting the address having the smallest degree value and the process of writing a dither value to the target address selected as the address having the smallest spatio-temporal density value are repeated for each dot of the three-dimensional block. By writing each value from the minimum value to the maximum value of the n-bit dither value to an address in the storage device in an arbitrary order, the dither data having the three-dimensional dither pattern is stored in the storage device. A method for generating a dither pattern to be stored is provided.

  According to the present invention, the number of dots in the horizontal direction is H, the number of lines in the vertical direction is V, and the number of lines in the frame direction is F. The block composed of numbers is one two-dimensional dither pattern in which a dither value, which is one of n bits, is set for each dot, and the two-dimensional dither pattern is represented by a number F in the frame direction. This is a dither pattern generation program for executing a process of generating a three-dimensional dither pattern composed of an arranged three-dimensional block. Each dither pattern has a number of H × V × F dots. Among the addresses in the corresponding storage device, a document in which a dither value has already been written in a three-dimensional predetermined area centered on each target address to which a new dither value can be written. A first process for obtaining the number of embedded addresses, and a second process for obtaining a spatio-temporal density value indicating the degree of density of written addresses in a three-dimensional predetermined area centered on each of the target addresses. And a third process that makes it difficult for the target address to be selected as the address having the smallest spatio-temporal density value in accordance with the number of written addresses obtained in the first process; and And a fourth process of selecting the address having the smallest spatio-temporal density value from all the target addresses, and selecting the address having the smallest spatio-temporal density value in the fourth process. A fifth process of writing a dither value to the target address thus set and the first to fifth processes are repeated, and an address in the storage device corresponding to each dot of the three-dimensional block is set to n bits. And writing a dither value from the minimum value to the maximum value of the dither value of the bit in an arbitrary order, thereby causing the storage device to store the dither data having the three-dimensional dither pattern. A dither pattern generation program is provided.

  According to the video signal processing apparatus, the dither pattern generation method, and the dither pattern generation program of the present invention, a block of a dither pattern has a size exceeding 4 dots, and a side effect due to addition of dither data hardly occurs, and high quality is achieved. The gradation can be extended.

It is a block diagram showing a video signal processing device of each embodiment. FIG. 4 is a diagram illustrating an example of a dither pattern having an 8-frame period. 4 is a flowchart illustrating processing that is a premise of processing executed by a dither pattern generation method or a dither pattern generation program according to each embodiment. FIG. 9 is a diagram conceptually illustrating a process of sequentially writing dither values at addresses having the smallest spatio-temporal density values in the storage device. 5 is a flowchart illustrating a process executed by a dither pattern generation method or a dither pattern generation program according to the first embodiment. It is a figure showing an example of a three-dimensional field centering on a target address in a 1st and 2nd embodiment. It is a flowchart which shows the process performed by the dither pattern generation method or the dither pattern generation program of 2nd Embodiment. It is a figure showing other examples of a three-dimensional field centering on a target address in a 2nd embodiment. It is a figure showing an example of a three-dimensional field centering on a target address in a 3rd embodiment. It is a flowchart which shows the process performed by the dither pattern generation method or the dither pattern generation program of 4th Embodiment.

  Hereinafter, a video signal processing device, a dither pattern generation method, and a dither pattern generation program of each embodiment will be described with reference to the accompanying drawings. The configuration of the video signal processing device of each embodiment is common. The configuration and operation of a video signal processing device common to the embodiments will be described with reference to FIG.

  In FIG. 1, the video signal processing device according to each embodiment includes a timing generation unit 10, a dither pattern generation unit 20, a RAM 30, adders 41 to 43, and lower bit reduction units 51 to 53. As an example, the video signal input to the video signal processing device is a 12-bit R signal, a G signal, and a B signal. The video signal processing device of each embodiment outputs a 4-bit R signal, G signal, and B signal by adding a dither pattern described later to the R signal, G signal, and B signal, and then reducing the lower 8 bits. I do.

  The timing generator 10 includes a frame counter 11 that counts frames based on the vertical synchronization signal, a vertical counter 12 that counts the number of lines in the vertical direction based on the vertical synchronization signal and the horizontal synchronization signal, and a A horizontal counter 13 for counting the number of dots in the horizontal direction. Note that the vertical counter 12 resets the count value with the vertical synchronization signal and counts up using the horizontal synchronization signal as a trigger.

  The RAM 30 combines the lower 3 bits of the frame count value generated by the frame counter 11, the lower 4 bits of the vertical count value generated by the vertical counter 12, and the lower 4 bits of the horizontal count value generated by the horizontal counter 13. The read address of 11 bits is supplied. The RAM 30 is an example of a storage device.

  The dither pattern generation unit 20 generates a dither pattern by executing the dither pattern generation method of each embodiment. The dither pattern generation unit 20 may be a central processing unit (CPU) or a computer that executes the dither pattern generation program of each embodiment to generate a dither pattern.

  As shown in FIG. 2, the dither pattern generation unit 20 generates a dither pattern having an eight-frame period composed of 256 dots of 16 horizontal dots and 16 vertical lines as an example. The dither patterns having a period of eight frames are referred to as dither patterns Dp1 to Dp8. The dither patterns Dp1 to Dp8 have different dither patterns. The dither patterns Dp1 to Dp8 each composed of a two-dimensional block are arranged in the frame direction, and the entire dither pattern Dp1 to Dp8 forms a dither pattern composed of three-dimensional blocks.

  Each dot of the dither patterns Dp1 to Dp8 can be specified by 2048 addresses that can be expressed by 11 bits. Therefore, the dither pattern generation unit 20 generates an 11-bit write address and supplies it to the RAM 30. In each embodiment, the number of extension bits is eight in order to reduce a 12-bit video signal to four bits. Therefore, the dither pattern generation unit 20 generates dither data in which an 8-bit dither value is assigned to each dot of the dither patterns Dp1 to Dp8. That is, the dither value of each dot is any value from 0 to 255.

  The RAM 30 has 2048 addresses, and the 2048 addresses correspond to each dot of a three-dimensional block composed of the dither patterns Dp1 to Dp8. The dither pattern generation unit 20 generates a dither value for each dot of the dither patterns Dp1 to Dp8, and writes each dither value to an address specified by a write address. Therefore, the RAM 30 holds dither data having dither patterns Dp1 to Dp8 in which a dither value is assigned to each dot.

  When the video signal processing device is started, the dither pattern generation unit 20 generates dither data having dither patterns Dp1 to Dp8 and writes the dither data into the RAM 30. The dither data held in the RAM 30 is read by the above 11-bit read address and supplied to the adders 41 to 43.

  In FIG. 1, a RAM is used as a storage device for holding dither data having dither patterns Dp1 to Dp8, but a ROM in which dither patterns Dp1 to Dp8 generated by dither pattern generation unit 20 are written in advance is used. Is also good. The type of the storage device is not limited. When a ROM is used as the storage device, the dither pattern generation unit 20 is provided outside the video signal processing device.

  The adders 41 to 43 add 8-bit dither data to the input 12-bit R signal, G signal, and B signal. The dither pattern of the dither data added to the R signal, the G signal, and the B signal is sequentially selected from the dither patterns Dp1 to Dp8 according to the read address. The adders 41 to 43 make the horizontal 16 dots and the vertical 16 lines 256 dots in each frame one block, and add dither data of the selected two-dimensional dither pattern to each block.

  The lower bit reduction units 51 to 53 limit overflow of the outputs of the adders 41 to 43, reduce the lower 8 bits, and output the upper 4 bits of the R, G, and B signals.

  For example, it is assumed that the lower 8 bits of the 12-bit R signal, G signal, and B signal are 128 and the dither data to be added is any of 0 to 127. In this case, since the addition result by the adders 41 to 43 is 255 or less, it does not carry over to the upper bits. It is assumed that the lower bits of the 12-bit R signal, G signal, and B signal are 128, and the dither data to be added is any of 128 to 255. In this case, since the addition result by the adders 41 to 43 is 256 or more, it is moved up to the upper bit.

  If the frequencies of the dither values 0 to 255 of the dither data are uniform, the probability of the case where the dither data does not carry over to the upper bits and the case of carrying up the dither data becomes 50%: 50%. Therefore, the lower bit reduction units 51 to 53 reduce the lower 8 bits of 128 and output the upper 4 bits originally included in the input R signal, G signal, and B signal as they are. The probability of outputting 4 bits is 50%: 50%. Thereby, 0.5 is expressed on average.

  In the above description, the case where the lower 8 bits are 128 is taken as an example. However, since the lower 8 bits are any value from 0 to 255, the following is considered as a whole from 0 to 255. The frequency at which the dither data having the dither value 0 to 255 is added to the lower 8 bits 0 to 255 of the 12-bit R signal, G signal, and B signal, and the lower 8 bits are moved up to the upper bits is 0/256. ~ 255/256. That is, by the processing of the adders 41 to 43 and the lower bit reduction units 51 to 53, it is possible to extend the bits by 8 bits.

  Although the R signal, the G signal, and the B signal output from the lower bit reduction units 51 to 53 are 4 bits, a 12-bit gradation number is represented in a pseudo manner by 8-bit bit expansion.

  Next, a description will be given of what kind of dither patterns Dp1 to Dp8 are required in order to hardly cause side effects due to the addition of the dither data and to extend the gradation to high quality.

The conditions required for the dither patterns Dp1 to Dp8 are:
Condition 1: dither values 0 to 255 are distributed as uniformly as possible in one dither pattern;
Condition 2: the dither value in the frame direction at each position of the dither patterns Dp1 to Dp8 is a value that is dispersed as much as possible;
It is.

More preferable conditions are, in addition to the conditions 1 and 2,
Condition 3: a block boundary is not visually recognized in a frame of the R signal, the G signal, and the B signal to which the dither pattern is added, and there is almost no visual discomfort at the block boundary.
Condition 4: In the frame direction of the R signal, the G signal, and the B signal to which the three-dimensional blocks including the dither patterns Dp1 to Dp8 are added, the boundary of the frame period of the dither pattern is hardly recognized, and the period in the frame direction Gender (specifically, flicker interference) can hardly be recognized,
It is.

  A specific generation method for generating the dither patterns Dp1 to Dp8 so as to satisfy at least the above conditions 1 and 2 will be described with reference to FIGS. FIG. 3 and FIG. 4 show processing that is a premise of the processing executed by the dither pattern generation method or the dither pattern generation program of each embodiment.

  In FIG. 3, the dither pattern generation unit 20 writes the dither value 0 to all the 2048 addresses of the RAM 30 in step S1. In step S2, the dither pattern generation unit 20 resets the counter, sets the count value to 0, and sets the dither value to 255. In step S3, the dither pattern generation unit 20 calculates a spatiotemporal density value at an address having a dither value of 0, and searches for an address having the smallest spatiotemporal density value.

  The spatio-temporal density value means that when a new dither value is to be written to an address in the RAM 30, the dither value already exists in a three-dimensional predetermined area centered on each address where a new dither value can be written. Is a value indicating the degree of density of the address at which is written (hereinafter, the written address). The details of the spatiotemporal density value will be described later. The address at which a new dither value can be written is an address at which a dither value 0 is written. In the example shown in FIG. 3, since the dither value 0 is written in advance to all the addresses of the RAM 30, the dither value can be written to all the addresses at first, and the dither value is repeated by repeating the subsequent steps. Written sequentially.

  In step S4, the dither pattern generation unit 20 writes the dither value to the address of the RAM 30 obtained in step S3. In step S4, first, 255 is written as the dither value. The dither pattern generation unit 20 increments the count value by 1 in step S5, and determines whether the count value is 8 in step S6. If the count value is not 8 (NO), the dither pattern generation unit 20 repeats the processing of steps S3 to S6. That is, the dither value 255 is written into the RAM 30 at the eight addresses sequentially obtained in step S3.

  If the count value is 8 in step S6 (YES), the dither pattern generation unit 20 resets the counter to 0 in step S7 and decrements the dither value by 1 in step S7. The dither pattern generation unit 20 determines whether or not the dither value is 0 in step S8. If the dither value is not 0 (NO), the dither pattern generation unit 20 repeats the processing of steps S3 to S8.

  That is, the dither value 254 is written to the RAM 30 eight times, then the dither value 253 is written eight times, and so on until the dither value 1 is written eight times. As a result, dither data having a dither pattern composed of three-dimensional blocks is stored in the RAM 30.

  Since the dither value 0 has been written in advance, if the dither value is 0 in step S8 (YES), the dither pattern generation unit 20 ends the processing.

  By the above processing, each of the dither values 0 to 255 is written to the 2048 addresses of the RAM 30 eight times. Since the number of addresses in the RAM 30 is 2048 and the number of extension bits is 8 bits, each of the dither values 0 to 255 is written to each of 2048/8 = 8 times in order to equally allocate the dither values to 2048 addresses.

  FIG. 4 conceptually shows a process of sequentially writing dither values at addresses having the smallest spatiotemporal density values. In FIG. 4, 2048 addresses of the RAM 30 are shown in one dimension. By selecting the address having the smallest spatio-temporal density value, an address is selected from a three-dimensionally coarse area where a written address does not exist as much as possible, and a new dither value is written.

  In FIG. 4, first, eight dither values 255 are written in the RAM 30. Since the eight dither values 255 are sequentially selected and written in the addresses having the smallest spatio-temporal density value from the 2048 addresses, the eight dither values 255 are uniformly distributed in one dither pattern and in the frame direction. . In FIG. 4, a dither value 0 is written in the address of the blank portion.

  Next, eight dither values 254 are written to the RAM 30. Similarly, since the eight dither values 254 are sequentially selected and written with the address having the smallest spatio-temporal density value among the remaining 2040 addresses, the eight dither values 254 are stored in one dither pattern and in the frame direction. Disperse almost uniformly.

  Thereafter, similarly, from the dither value 253 to the dither value 1, the address which remains at the dither value 0 and at which a new dither value can be written, and then the address with the smallest spatio-temporal density value is selected in order, and each dither value is selected. Is written. By the above processing, the above conditions 1 and 2 are achieved.

  As a comparative example, it is conceivable that an address at which a dither value is to be written is randomly selected using a pseudo-random number generated by a pseudo-random number generator. However, the pseudo-random number generator may continuously generate adjacent addresses or adjacent addresses, and cannot satisfy the conditions 1 and 2.

  In the example shown in FIG. 3, the dither value 0 is written to all the 2048 addresses of the RAM 30 in step S1 and the respective dither values are written in descending order from the dither value 255 to the dither value 1; This is an example. The order of writing each value from the minimum value to the maximum value of the 8-bit dither value to the address of the RAM 30 is arbitrary.

  A preferred method of calculating a spatiotemporal density value to achieve the above conditions 3 and 4 will be described. The address of the RAM 30 is represented by (f, v, h). f is the position of the frame of the dither patterns Dp1 to Dp8, and f = 0 to 7. v is a line position of 16 vertical lines, and v = 0 to 15. h is a dot position of 16 horizontal dots, and h = 0 to 15.

  The dither pattern generation unit 20 performs a filtering process using a three-dimensional low-pass filter (hereinafter, three-dimensional LPF) with data of a written address other than dither value 0 being 1 and data of other addresses being 0. The LPF is, for example, a Gaussian filter. More specifically, the dither pattern generation unit 20 performs a three-dimensional convolution operation on the kernel function of the three-dimensional LPF and the data of the address based on Expression (1) to obtain a spatiotemporal density value D (f, v, h). Is calculated.

  In equation (1), K (i, j, k) is a kernel function of the three-dimensional LPF. i, j, and k are ranges in the frame direction of a three-dimensional region centered on an address (f, v, h) for which a spatiotemporal density value D (f, v, h) is to be calculated; This is a number that determines the range in the vertical direction and the range in the horizontal direction. As an example, i = −4 to 4, j = −8 to 8, and k = −8 to 8, and the three-dimensional region may be a predetermined region.

  The kernel function K (i, j, k) when a Gaussian filter is used as the three-dimensional LPF is as shown in Expression (2). In Expression (2), σ is a standard deviation, and a specific numerical value may be a design value.

  Each block of the dither patterns Dp1 to Dp8 is repeatedly used in the frame, and three-dimensional blocks of the dither patterns Dp1 to Dp8 are repeatedly used in the frame direction. The remainder of a by b is expressed as mod (a, b). Therefore, mod (f + i + 8, 8) is the first remainder when (f + i + 8) is divided by 8, which is the frame period of the dither pattern, and mod (v + i + 16, 16) is (v + i + 16), which is the period (number of lines) in the vertical direction. Mod (h + i + 16, 16) means the third remainder when (h + i + 16) is divided by 16 which is the horizontal period (number of dots).

  Q (f, v, h) is 1 when a dither value other than dither value 0 is written to address (f, v, h) of RAM 30, and when the initial value of dither value 0 remains unchanged. This is a function that returns 0 (hereinafter, function Q). The addresses obtained by mod (f + i + 8, 8), mod (v + j + 16, 16), and mod (h + k + 16, 16) are (f ', v', h ').

  Therefore, Q (mod (f + i + 8,8), mod (v + j + 16,16), mod (h + k + 16,16)) in the equation (1) indicates that the address (f ′, v ′, h ′) has a dither value other than dither value 0. This means returning 1 when a value is written and returning 0 when the dither value remains 0.

  As described above, when calculating the spatiotemporal density value D (f, v, h) at each address, the values of (f + i + 8), (v + j + 16), and (h + k + 16) are respectively used for the frame period, the number of lines, and the number of dots of the dither pattern. 1 or 0 is assigned to each address obtained by performing the remainder operation. Then, 1 or 0 of each address is multiplied by the kernel function K (i, j, k) of the three-dimensional LPF to obtain a spatiotemporal density value D (f, v, h). In step S3 in FIG. 3, an address having the smallest spatiotemporal density value D (f, v, h) is searched.

  If the address with the smallest spatio-temporal density value is searched for and the dither value is written without using the remainder operation, the addresses at the upper, lower, left, and right ends in the frame are easily selected as the addresses with the smallest spatio-temporal density value. Further, in the frame direction, an address located in the dither pattern Dp1 or Dp8, which is an end in the frame direction, is likely to be selected as an address having the smallest spatiotemporal density value.

  Then, the boundaries of the blocks in the frame are visually recognized, and a visual discomfort is likely to occur at the boundaries of the blocks. In addition, the boundary of the frame period of the three-dimensional block composed of the dither patterns Dp1 to Dp8 is visually recognized, and is easily recognized as flicker interference.

  By using the remainder operation in the function Q, it is possible to prevent the addresses at the upper, lower, left, and right ends in the dither pattern from being easily selected as the address having the smallest spatiotemporal density value. Further, it is possible to avoid that an address located in the dither pattern at the end in the frame direction is likely to be selected as an address having the smallest spatiotemporal density value. Thereby, the above conditions 3 and 4 are achieved.

  By the way, i, j, and k that determine a three-dimensional region in which 1 or 0 obtained by the function Q is multiplied by the kernel function K (i, j, k) are represented by i = −p to p, j = − q to q, k = -rr to r. p, q, and r are predetermined numbers. The number of dither patterns in the frame direction (frame period) is generalized to F, the number of lines in the vertical direction is V, and the number of dots in the horizontal direction is H. F, V, and H are predetermined numbers. By these generalizations, equation (1) can be represented by equation (3).

  In the present embodiment described above, the number H of dots in the horizontal direction of the three-dimensional block of the dither pattern is 16, the number V of lines in the vertical direction is 16, and the number F in the frame direction is 8, but the present invention is not limited to this. Not done. The number of H × V dots of one dither pattern is a number exceeding four. The verification by the present inventors has confirmed that not only H = 16 and V = 16 but also H = 32 and V = 32 can realize very high-quality multi-gradation with less side effects.

  It has been experimentally confirmed that the number F in the frame direction is preferably 4 to 8 when the frame rate of the video signal is 50 to 60 fps (frame per second), and preferably 8 to 16 when the frame rate is 100 to 120 fps. Have been. The dither pattern generation unit 20 may be configured to switch the number F in the frame direction according to the frame rate of the video signal. When the video signal processing device illustrated in FIG. 1 is used in a display device that can switch the frame rate when displaying a video signal, the dither pattern generation unit 20 switches the number F in the frame direction according to the frame rate. Is preferred.

  When the storage device is constituted by a ROM, a number F of dither data in the frame direction corresponding to a plurality of frame rates may be stored in the ROM, or a number F of dither data in the frame direction corresponding to each frame rate may be stored in the ROM. A plurality of stored ROMs may be provided.

  Assuming that H = 16, V = 16, F = 8, and the bit number (extended bit number) n of the dither value is 8, the capacity of the RAM 30 may be 2048 × 8 bits. Assuming that H = 32, V = 32, F = 8, and n = 8, the capacity of the RAM 30 may be 8192 × 8 bits. In any case, the capacity of the RAM 30 is relatively small.

  When H = 32, V = 32, F = 8, and n = 8, each of the dither values 0 to 255 is written to the 8192 addresses of the RAM 30 32 times from 8192/256. In step S6 of FIG. 3, it may be determined whether the count value is 32.

  By the processing shown in FIG. 3 described above, each dither value is written into the RAM 30 so as to be distributed almost uniformly in one dither pattern and in the frame direction. However, in practice, the same dither value may be written to addresses vertically and horizontally adjacent to each other in one dither pattern. Also, the same dither value may be written to an address adjacent in the frame direction.

  Second, each embodiment can reduce the probability that the same dither value is written in one dither pattern or at an adjacent address in the frame direction, and can distribute each dither value more uniformly in one dither pattern and in the frame direction. Will be described.

<First embodiment>
FIG. 5 shows a process in which the dither pattern generation unit 20 generates a dither pattern by executing the dither pattern generation method of the first embodiment or the dither pattern generation program of the first embodiment.

  In FIG. 5, the dither pattern generation unit 20 writes the dither value 0 to all the 2048 addresses of the RAM 30 in step S11. In step S12, the dither pattern generation unit 20 resets the counter, sets the count value to 0, and sets the dither value to 255.

  In step S13, the dither pattern generation unit 20 sequentially sets each of the 2048 addresses in the RAM 30 as a target address, and if a dither value other than the dither value 0 is written in an adjacent address of each target address, the target Set the address as an excluded address.

  As shown in FIG. 6, the address adjacent to the target address is an address located on the left, right, upper, or lower side of the target address in each of the dither patterns Dp1 to Dp8, or an address before and after adjacent in the frame direction. . In FIG. 6, an address Atgt surrounded by a thick solid line is an arbitrary target address located in the dither pattern Dpi which is one of the dither patterns Dp1 to Dp8. The left, right, upper, lower, front and rear addresses of the target address Atgt shown in FIG. 6 constitute a three-dimensional predetermined area centered on the target address Atgt.

  It is preferable that the dither pattern generation unit 20 changes the condition for setting the target address as the exclusion address according to the number of written addresses. As an example, if the number of written addresses is equal to or less than ア ド レ ス of all addresses, the dither pattern generation unit 20 determines whether the number of addresses left, right, up, down, before, and after the target address is one. If at least one dither value other than the dither value 0 is written, the target address is set as the excluded address.

  If the number of written addresses exceeds 1/8 of all addresses and is 1/4 or less, the dither pattern generation unit 20 determines the position of the target address on the left and right, above and below, before and after. If a dither value other than the dither value 0 is written to at least one set of addresses among the addresses to be processed, the target address is set as the excluded address.

  If the number of written addresses exceeds １ ／ of all addresses, the dither pattern generation unit 20 does not set the target address as an exclusion address regardless of the state of the adjacent address of the target address.

  In the first embodiment, when the number of target addresses to which dither values are written is equal to or less than the first number, the dither pattern generation unit 20 determines that the number of written addresses is at least the second number. , The target address is excluded from the addresses for which the spatio-temporal density value is to be obtained. Here, the first number is 1/8 of all addresses, and the second number is 1.

  When the number of target addresses to which the dither value has been written exceeds the first number and is equal to or less than the third number, the dither pattern generation unit 20 determines that the number of written addresses is at least the fourth number. If so, the target address is excluded from the addresses for which the spatiotemporal density value is to be obtained. Here, the third number is 1/4 of all addresses, and the fourth number is 2. However, the fourth number 2 in the first embodiment is two addresses located symmetrically with respect to the target address.

  In step S14, the dither pattern generation unit 20 calculates a spatio-temporal density value at an address having a dither value of 0, excluding the exclusion address set in step S13, and searches for an address having the smallest spatio-temporal density value. I do.

  In the first embodiment, if a dither value other than the dither value 0 is written to an address adjacent to the target address, the dither value is excluded even if the spatio-temporal density value at the target address is minimum. The density value is no longer selected as the lowest address. The process of setting an exclusion address in the first embodiment is a process of ultimately making it difficult to select a target address in which a dither value other than dither value 0 is written in an adjacent address as an address having the smallest spatio-temporal density value. It is.

  In step S15, the dither pattern generation unit 20 writes the dither value to the address of the RAM 30 obtained in step S14. In step S15, first, 255 is written as the dither value. The dither pattern generation unit 20 increments the count value by 1 in step S16, and determines whether the count value is 8 in step S17. If the count value is not 8 (NO), the dither pattern generation unit 20 repeats the processing of steps S13 to S17.

  If the count value is 8 in step S17 (YES), the dither pattern generation unit 20 resets the counter to 0 in step S18 and decrements the dither value by 1 in step S18. The dither pattern generation unit 20 determines whether or not the dither value is 0 in step S19. If the dither value is not 0 (NO), the dither pattern generation unit 20 repeats the processing of steps S13 to S19.

  If the dither value is 0 in step S19 (YES), the dither pattern generation unit 20 ends the processing.

  In FIG. 5, step S13 includes a first process for calculating the number of written addresses in a three-dimensional area centered on the target address. Step S14 includes a second process of obtaining a spatiotemporal density value indicating the degree of density of the written address in a three-dimensional area centered on the target address. The three-dimensional area in step S13 and the three-dimensional area in step S14 need not be the same.

  Step S13 includes a third process that makes it difficult for the target address to be selected as the address having the smallest spatio-temporal density value according to the number of written addresses obtained by the first process. Step S14 includes a fourth process of selecting the address having the smallest spatio-temporal density value among all the target addresses after executing the third process. Step S15 is a fifth process of writing the dither value to the target address selected as the address having the smallest spatial density value.

  The dither pattern generation unit 20 executes the sixth process of repeating steps S13 to S19 including the first to fifth processes following steps S11 and S12, thereby storing the RAM 30 from the dither value 255 to the dither value 0. Up to eight dither values can be written. Thus, dither data having a three-dimensional dither pattern is stored in the RAM 30.

<Second embodiment>
FIG. 7 illustrates a process in which the dither pattern generation unit 20 generates a dither pattern by executing the dither pattern generation method of the second embodiment or the dither pattern generation program of the second embodiment.

  7, the dither pattern generation unit 20 writes the dither value 0 to all the 2048 addresses of the RAM 30 in step S21. In step S22, the dither pattern generation unit 20 resets the counter, sets the count value to 0, and sets the dither value to 255.

  In step S23, the dither pattern generation unit 20 sequentially sets each of the 2048 addresses of the RAM 30 as a target address, and if a dither value other than the dither value 0 is written in an adjacent address of each target address, the target Set a predetermined coefficient to the address. As shown in FIG. 6, the address adjacent to the target address is an address located on the left, right, above, or below the target address in each of the dither patterns Dp1 to Dp8, or an address before and after in the frame direction.

  As shown in FIG. 8, in each of the dither patterns Dp1 to Dp8, an address located in a diagonal direction of the target address (diagonally upper right, lower right, lower left, or lower left) may be added to the adjacent address. . In FIG. 8, the left, right, upper, lower, right diagonally upper, right diagonally lower, left diagonally upper, left diagonally lower, front and rear addresses of the target address Atgt are three-dimensional with the target address Atgt as a center. A predetermined area.

  It is preferable that the dither pattern generation unit 20 varies the coefficient value of the coefficient set to the target address according to the number of written addresses. As an example, if the number of written addresses is equal to or less than ア ド レ ス of all addresses, the dither pattern generation unit 20 determines whether the number of addresses left, right, up, down, before, and after the target address is one. If at least one dither value other than 0 is written, the first coefficient having the first coefficient value is set at the target address. The first coefficient value is a number exceeding 1, for example, 1.1.

  When adding an address located diagonally to the target address to the adjacent address, the dither pattern generation unit 20 adds a coefficient to the target address when a dither value other than dither value 0 is written to the address adjacent to the target address in the diagonal direction. Set. The coefficient value at this time is preferably set to a coefficient value smaller than 1.1.

  If the number of written addresses exceeds 1/8 of all addresses and is 1/4 or less, the dither pattern generation unit 20 determines the position of the target address on the left and right, above and below, before and after. If a dither value other than the dither value 0 is written in at least one set of addresses among the addresses to be processed, a second coefficient having a second coefficient value larger than the first coefficient value is written to the target address. Set. The second coefficient value is a number larger than the first coefficient value, for example, 1.2.

  When adding an address located in the diagonal direction of the target address to the adjacent address, the dither pattern generation unit 20 dithers the dither pattern to the set of the diagonally upper right and diagonally lower left, or the diagonally lower right and diagonally upper left of the target address. If a dither value other than the value 0 is written, a coefficient is set at the target address. The coefficient value at this time is preferably smaller than 1.2 and larger than 1.1.

  If the number of written addresses exceeds １ ／ of all addresses, the dither pattern generation unit 20 does not set a coefficient in the target address regardless of the state of the adjacent address of the target address.

  In the second embodiment, when the number of target addresses to which dither values are written is equal to or smaller than the first number, the dither pattern generation unit 20 determines that the number of written addresses is at least the second number. , The first coefficient is set to the target address. Here, the first number is 1/8 of all addresses, and the second number is 1.

  When the number of target addresses to which the dither value has been written exceeds the first number and is equal to or less than the third number, the dither pattern generation unit 20 determines that the number of written addresses is at least the fourth number. If there is, the second coefficient is set to the target address. Here, the third number is 1/4 of all addresses, and the fourth number is 2. However, the fourth number 2 in the second embodiment is two addresses located symmetrically with respect to the target address.

  In step S24, the dither pattern generation unit 20 calculates the spatiotemporal density value at the address where the dither value is 0, and multiplies the calculated spatiotemporal density value by the coefficient at the address where the coefficient is set. Search for the address with the smallest spatiotemporal density value.

  In the second embodiment, if a dither value other than the dither value 0 is written in the address adjacent to the target address, a coefficient having a coefficient value exceeding 1 is set in the target address. As a result, the spatio-temporal density value of the target address is multiplied by the coefficient value to increase the spatio-temporal density value, so that it is difficult for the spatio-temporal density value to be selected as the smallest address.

  In step S25, the dither pattern generation unit 20 writes the dither value to the address of the RAM 30 obtained in step S24. The dither pattern generation unit 20 increments the count value by 1 in step S26, and determines whether the count value is 8 in step S27. If the count value is not 8 (NO), the dither pattern generation unit 20 repeats the processing of steps S23 to S27.

  If the count value is 8 in step S27 (YES), the dither pattern generation unit 20 resets the counter to 0 in step S28 and decrements the dither value by 1 in step S28. The dither pattern generation unit 20 determines whether the dither value is 0 in step S29. If the dither value is not 0 (NO), the dither pattern generation unit 20 repeats the processing of steps S23 to S29.

  If the dither value is 0 in step S29 (YES), the dither pattern generation unit 20 ends the processing.

  In FIG. 7, step S23 includes a first process for calculating the number of written addresses in a three-dimensional area centered on the target address. Step S24 includes a second process of obtaining a spatio-temporal density value indicating a degree of density of a written address in a three-dimensional area centered on the target address. The three-dimensional area in step S23 and the three-dimensional area in step S24 need not be the same.

  Steps S23 and S24 include a third process that makes it difficult for the target address to be selected as the address having the smallest spatio-temporal density value in accordance with the number of written addresses obtained by the first process. Step S24 includes a fourth process of selecting the address having the smallest spatiotemporal density value among all the target addresses after executing the third process. Step S25 is a fifth process of writing the dither value to the target address selected as the address having the smallest spatial density value.

  The dither pattern generation unit 20 executes the sixth process of repeating steps S23 to S29 including the first to fifth processes following steps S21 and S22, thereby storing the RAM 30 from the dither value 255 to the dither value 0. Up to eight dither values can be written. Thus, dither data having a three-dimensional dither pattern is stored in the RAM 30.

<Third embodiment>
In the first and second embodiments described above, the address adjacent to the target address is defined as shown in FIG. 6 or FIG. 8, but may be defined as shown in FIG. In FIG. 9, the p × p address of p in the horizontal and vertical directions centering on the target address Atgt and the p × p address located before and after the target address Atgt adjacent and in the frame direction are the target address. A three-dimensional predetermined area around Atgt is configured. p is an integer of 3 or more.

  In the third embodiment, as in the first embodiment, when the number of target addresses to which dither values are written is equal to or smaller than the first number, the dither pattern generation unit 20 determines that the number of written addresses is at least If it is the second number, the target address may be excluded from the addresses for which the spatio-temporal density value is to be obtained. The second number may be set appropriately.

  When the number of target addresses to which the dither value has been written exceeds the first number and is equal to or less than the third number, the dither pattern generation unit 20 determines that the number of written addresses is at least the fourth number. If so, the target address may be excluded from the addresses for which the spatio-temporal density value is to be obtained. The fourth number may be set appropriately.

  Furthermore, in the third embodiment, as in the second embodiment, when the number of target addresses to which dither values are written is equal to or smaller than the first number, the dither pattern generation unit 20 determines the number of written addresses. Is at least the second number, the first coefficient may be set to the target address. When the number of target addresses to which the dither value has been written exceeds the first number and is equal to or less than the third number, the dither pattern generation unit 20 determines that the number of written addresses is at least the fourth number. If so, the second coefficient may be set for the target address.

  The second number or the fourth number in the third embodiment does not have to be a number obtained by combining two addresses located symmetrically with respect to the target address. The number of written addresses at any position among the 26 addresses located around the target address may be the second number or the fourth number.

  Next, a description will be given of a process of the fourth embodiment that can reduce the amount of calculation in the dither pattern generation unit 20.

<Fourth embodiment>
In FIG. 10, the dither pattern generation unit 20 writes the dither value 0 to all the 2048 addresses of the RAM 30 in step S41. In step S22, the dither pattern generation unit 20 resets the counter, sets the count value to 0, and sets the dither value to 255.

  In step S43, the dither pattern generation unit 20 calculates a spatio-temporal density value at an address having a dither value of 0 in an address at a current frame value, and searches for an address having the smallest spatio-temporal density value. The frame value is a count value for selecting any one of the dither patterns Dp1 to Dp8 having a period of eight frames.

  In step S44, the dither pattern generation unit 20 writes the dither value to the address of the RAM 30 obtained in step S43. The dither pattern generation unit 20 increments the frame value by 3 in step S45. If the value obtained by incrementing the frame value by 3 is 8 or more, the dither pattern generation unit 20 decrements the frame value by 8.

  The dither pattern generation unit 20 increments the count value by 1 in step S46, and determines whether the count value is 8 in step S47. If the count value is not 8 (NO), the dither pattern generation unit 20 repeats the processing of steps S43 to S47.

  If the count value is 8 in step S47 (YES), the dither pattern generation unit 20 resets the counter to 0 in step S48 and decrements the dither value by 1 in step S48. In step S49, the dither pattern generation unit 20 determines whether the dither value is 0. If the dither value is not 0 (NO), the dither pattern generation unit 20 repeats the processing of steps S43 to S49.

  If the dither value is 0 in step S49 (YES), the dither pattern generation unit 20 ends the processing.

  According to the fourth embodiment shown in FIG. 10, the process of searching for the address with the smallest spatio-temporal density value and the process of writing the dither value at the address with the smallest spatio-temporal density value are performed in a three-dimensional manner. This is performed for each two-dimensional block in a simple block. Therefore, the amount of calculation in the process of searching for the address having the smallest spatio-temporal density value is ８.

  In the example shown in FIG. 10, the frame value circulates in the order of 0 → 3 → 6 → 1 → 4 → 7 → 2 → 5 → 0 over a period of eight frames. This is a first traveling example. The method of circulating the frame values is not limited to the first circulating example. As a second traveling example, the traveling may be performed in the order of 0 → 5 → 2 → 7 → 4 → 1 → 6 → 3 → 0... As a third traveling example, 0 → 1 → 2 → 3 → 4 → It is also possible to go around in the order of 5 → 6 → 7 → 0. The order in which the two-dimensional block is circulated in the frame direction may be any order.

  According to the fourth embodiment, a side effect due to the addition of dither data is less likely to occur, and a dither pattern capable of expanding the gradation with high quality can be generated with a small amount of calculation.

  The fourth embodiment may be combined with the first to third embodiments. By combining the fourth embodiment with the first to third embodiments, in addition to the effect that each dither value can be more uniformly dispersed within one dither pattern and in the frame direction, the amount of calculation can be reduced. It has the effect of being able to.

  The present invention is not limited to the embodiment described above, and can be variously modified without departing from the gist of the present invention. The first bit number of the input video signal and the second bit number of the output video signal are not limited to 12 bits and 4 bits, respectively, and the number of extension bits is not limited to 8 bits.

Reference Signs List 10 timing generation unit 20 dither pattern generation unit 30 RAM (storage device)
41 to 43 Adder 51 to 53 Lower bit reduction unit

Claims (9)

The number of dots in the horizontal direction is H, the number of lines in the vertical direction is V, and the number of lines in the frame direction is F. The number of H × V dots is a number exceeding 4, and is a two-dimensional number of H × V dots. The block is one two-dimensional dither pattern in which each dot is set to a dither value that is one of n bits, and the two-dimensional dither pattern is arranged in the frame direction by a number F. A storage device for storing dither data having a three-dimensional dither pattern composed of dimensional blocks;
A number F of two-dimensional dither patterns in the frame direction are sequentially selected in the frame period F, and for each two-dimensional block consisting of the number of H × V dots in the frame of the input video signal having the first number of bits. An adder for adding the selected dither pattern;
A lower bit reduction unit that performs a limit process on an overflow in an output of the adder and outputs a video signal having a second bit number obtained by reducing lower n bits of the first bit number;
With
At the address of the storage device corresponding to each dot of the three-dimensional block having the number of dots of H × V × F, each value from the minimum value to the maximum value of the n-bit dither value is written,
When each value of the n-bit dither value is written to the storage device, the dither value is already written in a three-dimensional predetermined area centered on each target address to which a new dither value can be written. First processing for determining the number of written addresses that have been written;
A second process of calculating a spatio-temporal density value indicating a degree of density of a written address in a three-dimensional predetermined area centered on each of the target addresses;
A third process that makes it difficult for the target address to be selected as the address having the smallest spatiotemporal density value, in accordance with the number of written addresses obtained by the first process;
A fourth process of selecting the address having the smallest spatio-temporal density value among all the target addresses after executing the third process;
A fifth process of writing a dither value to the target address selected as the address having the smallest space-time density value by the fourth process;
Is repeated to thereby assign each value of the n-bit dither value to each dot of the three-dimensional block.   The predetermined area in the first processing includes at least an address located above, below, left, and right of the target address in the two-dimensional dither pattern and a previous address adjacent to the target address in a frame direction. The video signal processing device according to claim 1, wherein the video signal processing device is an area including an address and a subsequent address.   The predetermined area in the first processing is a p × p address of p in the horizontal direction and p in the vertical direction centering on the target address in the two-dimensional dither pattern, where p is an integer of 3 or more. 2. The video signal processing device according to claim 1, wherein the video signal processing device is an area including: a p × p address located before and after the target address adjacent in the frame direction.   The video signal processing device according to any one of claims 1 to 3, wherein the third process is a process of excluding the target address from a target address for which the spatiotemporal density value is calculated.   4. The method according to claim 1, wherein the third process is a process of multiplying the space-time density value by a coefficient so as to increase the space-time density value obtained at the target address. 5. Video signal processing device. When the number of the target addresses where the dither value is written is less than or equal to a first number among all the addresses corresponding to each dot of the three-dimensional block, the number is obtained by the first processing. If the number of written addresses is at least a second number, the target address is excluded from the addresses for which the spatiotemporal density value is to be obtained,
If the number of the target addresses in which the dither value is written is more than the first number and equal to or less than a third number among all the addresses, the written address obtained by the first processing 5. The video signal processing device according to claim 4, wherein if the number is at least a fourth number larger than the second number, the target address is excluded from the addresses for which the spatiotemporal density value is to be obtained. When the number of the target addresses where the dither value is written is less than or equal to a first number among all the addresses corresponding to each dot of the three-dimensional block, the number is obtained by the first processing. If the number of written addresses is at least a second number, multiply the spatiotemporal density value determined at the target address by a first coefficient;
If the number of the target addresses in which the dither value is written is more than the first number and equal to or less than a third number among all the addresses, the written address obtained by the first processing If the number is at least a fourth number larger than the second number, the spatiotemporal density value obtained at the target address is multiplied by a second coefficient larger than the first coefficient. The video signal processing device according to the above. The number of dots in the horizontal direction is H, the number of lines in the vertical direction is V, and the number of lines in the frame direction is F. The number of H × V dots is greater than 4, and a block consisting of H × V dots is A two-dimensional dither pattern in which a dither value that is any one of n bits is set, and the two-dimensional dither pattern is a three-dimensional block in which a number F is arranged in the frame direction. A dither pattern generation method for generating a three-dimensional dither pattern composed of
Of the addresses in the storage device corresponding to each dot of the three-dimensional block having the number of H × V × F dots, a three-dimensional predetermined centering on each target address at which a new dither value can be written. Find the number of written addresses in the area where the dither value has already been written,
In a three-dimensional predetermined area centered on each of the target addresses, a spatio-temporal density value indicating the degree of density of the written address is obtained,
According to the determined number of written addresses, the target address is processed such that the space-time density value is hardly selected as the smallest address,
After processing the target address so that the space-time density value is less likely to be selected as the smallest address, of all the target addresses, select the address with the smallest space-time density value,
Write a dither value to the target address selected as the smallest address space-time density value,
A process of calculating the number of written addresses, a process of calculating the spatiotemporal density value, a process of making the target address difficult to be selected as the address having the smallest spatiotemporal density value, and a process of minimizing the spatiotemporal density value. The process of selecting an address and the process of writing a dither value to the target address selected as the address having the smallest spatio-temporal density value are repeated, and the process in the storage device corresponding to each dot of the three-dimensional block is repeated. The dither data having the three-dimensional dither pattern is stored in the storage device by writing the respective values from the minimum value to the maximum value of the n-bit dither value in an arbitrary order at the address of Method. In the computer, the number of dots in the horizontal direction is H, the number of lines in the vertical direction is V, and the number of lines in the frame direction is F. The number of H × V dots is a number exceeding 4, and the block is composed of the number of H × V dots. Is a two-dimensional dither pattern in which each dot is set to any one of n-bit dither values. The three-dimensional pattern in which the two-dimensional dither patterns are arranged in a number F in the frame direction. A dither pattern generation program for executing a process of generating a three-dimensional dither pattern composed of typical blocks,
Of the addresses in the storage device corresponding to each dot of the three-dimensional block having the number of dots of H × V × F, a three-dimensional predetermined centering on each target address at which a new dither value can be written. A first process for calculating the number of written addresses in which the dither value has already been written in the area of
A second process of calculating a spatio-temporal density value indicating a degree of density of a written address in a three-dimensional predetermined area centered on each of the target addresses;
A third process that makes it difficult for the target address to be selected as the address having the smallest spatio-temporal density value in accordance with the number of written addresses obtained in the first process;
A fourth process of selecting the address having the smallest spatio-temporal density value among all the target addresses after executing the third process;
A fifth process of writing a dither value to the target address selected as the address having the smallest spatiotemporal density value in the fourth process;
By repeating the first to fifth processes, an address in the storage device corresponding to each dot of the three-dimensional block is set to an arbitrary value from the minimum value to the maximum value of the n-bit dither value. A sixth process of storing dither data having the three-dimensional dither pattern in the storage device by writing in order;
A dither pattern generation program that executes

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