JP2020043154A - Semiconductor device and manufacturing method therefor, and power conversion device - Google Patents

Semiconductor device and manufacturing method therefor, and power conversion device Download PDF

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JP2020043154A
JP2020043154A JP2018167478A JP2018167478A JP2020043154A JP 2020043154 A JP2020043154 A JP 2020043154A JP 2018167478 A JP2018167478 A JP 2018167478A JP 2018167478 A JP2018167478 A JP 2018167478A JP 2020043154 A JP2020043154 A JP 2020043154A
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power
semiconductor element
semiconductor device
metal
metal sintered
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翔 熊田
Sho Kumada
翔 熊田
祥久 内田
Yoshihisa Uchida
祥久 内田
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Mitsubishi Electric Corp
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    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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Abstract

To provide a technology capable of improving the reliability of a semiconductor device.SOLUTION: The semiconductor device includes: a semiconductor element 4 for electric power which is a semiconductor element; metal sinter members 7e, 7g; and a metal wire 6 which is a wiring member. The metal sinter members 7e, 7g are disposed on a major surface of the semiconductor element 4 for electric power. The metal wire 6 is coupled to the semiconductor element 4 for electric power through the metal sinter members 7e, 7g. A part of the metal wire 6 is embedded into the metal sinter members 7e, 7g under a spaced state from the major surface of the semiconductor element 4 for electric power.SELECTED DRAWING: Figure 3

Description

本発明は、半導体装置、及び、半導体装置の製造方法、並びに、電力変換装置に関する。   The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and a power conversion device.

半導体装置のうちの電力用半導体装置は、産業用機器から家電及び情報端末まで幅広い機器の主電力（パワー）の制御に用いられており、特に、輸送機器等に用いられる電力用半導体装置には、高い信頼性が求められている。そこで、従来のシリコン（Ｓｉ）を用いた半導体素子に代えて、炭化珪素（ＳｉＣ）等のワイドバンドギャップ半導体を用いた半導体素子を電力用半導体素子として備えた電力用半導体装置の開発が進められており、高パワー密度化及び高温動作化が進められている。   Power semiconductor devices among semiconductor devices are used for controlling main power (power) of a wide range of devices from industrial devices to home appliances and information terminals. , High reliability is required. Therefore, development of a power semiconductor device including a semiconductor element using a wide band gap semiconductor such as silicon carbide (SiC) as a power semiconductor element instead of a conventional semiconductor element using silicon (Si) has been advanced. Therefore, higher power density and higher temperature operation are being promoted.

従来の電力用半導体装置において、電力用半導体素子と、回路基板及び外部電極との接続には、一般的にアルミニウム（Ａｌ）を主材料とする金属ワイヤを、超音波圧着または超音波圧着により接合するウェッジボンディング法が用いられる。しかしながら、電力用半導体装置の動作時に電力用半導体素子が発熱すると、電力用半導体素子と金属ワイヤとの間の熱膨張係数の差異に起因して熱応力が発生する。この熱応力などにより、金属ワイヤが電力用半導体素子から剥離してしまうことがあり、電力用半導体装置の寿命が金属ワイヤ接合の疲労寿命により決定されてしまうことがあった。このような問題に対して、特許文献１には、電力用半導体素子のゲート電極及びエミッタ電極が、緩衝板を介して金属配線と接合する技術が開示されている。   In a conventional power semiconductor device, a metal wire mainly composed of aluminum (Al) is generally bonded by ultrasonic pressure bonding or ultrasonic pressure bonding to connect a power semiconductor element to a circuit board and external electrodes. A wedge bonding method is used. However, when the power semiconductor element generates heat during operation of the power semiconductor device, thermal stress is generated due to a difference in thermal expansion coefficient between the power semiconductor element and the metal wire. The metal wire may be separated from the power semiconductor element due to the thermal stress or the like, and the life of the power semiconductor device may be determined by the fatigue life of the metal wire bonding. To cope with such a problem, Patent Literature 1 discloses a technique in which a gate electrode and an emitter electrode of a power semiconductor element are bonded to metal wiring via a buffer plate.

特開２０１２−２８６７４号公報JP 2012-28674 A

特許文献１の技術によれば、緩衝板によって、金属ワイヤを超音波接合する際の荷重及び超音波エネルギーによる半導体素子へのダメージを低減できるので、Ａｌワイヤよりも高強度で接合部の信頼性向上が期待できる銅（Ｃｕ）ワイヤを使用できる。しかしながら、緩衝板を備えるため、電気抵抗の増大により発熱が大きくなってしまうという新たな問題が生じる。   According to the technology of Patent Document 1, the buffer plate can reduce the damage to the semiconductor element due to the load and ultrasonic energy at the time of ultrasonic bonding of the metal wires. A copper (Cu) wire that can be expected to be improved can be used. However, the provision of the buffer plate causes a new problem that heat generation increases due to an increase in electric resistance.

そこで、本発明は、上記のような問題点を鑑みてなされたものであり、半導体装置の信頼性を高めることが可能な技術を提供することを目的とする。   Therefore, the present invention has been made in view of the above problems, and has as its object to provide a technology capable of improving the reliability of a semiconductor device.

本発明に係る半導体装置は、半導体素子と、前記半導体素子の主面上に配設された金属焼結材と、前記金属焼結材によって前記半導体素子と接合された配線部材とを備え、前記配線部材の一部分は、前記半導体素子の前記主面と離間された状態で前記金属焼結材に埋設されている。   A semiconductor device according to the present invention includes a semiconductor element, a metal sintered material disposed on a main surface of the semiconductor element, and a wiring member joined to the semiconductor element by the metal sintered material. A part of the wiring member is buried in the metal sintered material while being separated from the main surface of the semiconductor element.

本発明によれば、配線部材が金属焼結材によって半導体素子と接合され、配線部材の一部分が、半導体素子の主面と離間された状態で金属焼結材に埋設されるので、半導体装置の信頼性を高めることができる。   According to the present invention, the wiring member is joined to the semiconductor element by the metal sintered material, and a part of the wiring member is embedded in the metal sintered material while being separated from the main surface of the semiconductor element. Reliability can be improved.

実施の形態１に係る電力用半導体装置の主要部の構成を示す上面図である。FIG. 2 is a top view illustrating a configuration of a main part of the power semiconductor device according to the first embodiment; 実施の形態１に係る電力用半導体装置の主要部の構成を示す断面図である。FIG. 2 is a cross-sectional view showing a configuration of a main part of the power semiconductor device according to the first embodiment. 実施の形態１に係る電力用半導体装置の主要部の構成を示す拡大断面図である。FIG. 2 is an enlarged sectional view showing a configuration of a main part of the power semiconductor device according to the first embodiment. 実施の形態１に係る電力用半導体装置の主要部の構成を示す拡大断面図である。FIG. 2 is an enlarged sectional view showing a configuration of a main part of the power semiconductor device according to the first embodiment. 実施の形態２に係る電力変換装置を適用した電力変換システムの構成を示すブロック図である。FIG. 13 is a block diagram illustrating a configuration of a power conversion system to which the power conversion device according to Embodiment 2 is applied.

＜実施の形態１＞
図１は、本発明の実施の形態１に係る半導体装置である電力用半導体装置１２の主要部の構成を示す上面図であり、図２は、図１のＡ−Ａ線に沿った断面図である。図１及び図２に示すように、電力用半導体装置１２は、基板２と、接合部材３と、半導体素子である電力用半導体素子４と、それぞれが配線部材である複数の金属ワイヤ６と、金属焼結材である金属焼結体７ｅ，７ｇとを備える。 <First Embodiment>
FIG. 1 is a top view showing a configuration of a main part of a power semiconductor device 12 which is a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line AA of FIG. It is. As shown in FIGS. 1 and 2, the power semiconductor device 12 includes a substrate 2, a joining member 3, a power semiconductor element 4 that is a semiconductor element, and a plurality of metal wires 6 each of which is a wiring member. Metal sintered bodies 7e and 7g, which are metal sintered materials.

基板２は、セラミックからなる絶縁基板２ａと、絶縁基板２ａに配設された回路パターン２ｂ，２ｃ，２ｄ，２ｅとを備える。回路パターン２ｂ，２ｃ，２ｄは、絶縁基板２ａの上面に配設され、回路パターン２ｅは、絶縁基板２ａの下面に配設される。   The substrate 2 includes an insulating substrate 2a made of ceramic and circuit patterns 2b, 2c, 2d, and 2e provided on the insulating substrate 2a. The circuit patterns 2b, 2c, 2d are provided on the upper surface of the insulating substrate 2a, and the circuit pattern 2e is provided on the lower surface of the insulating substrate 2a.

電力用半導体素子４の下面は、回路パターン２ｂと接合部材３によって接合されている。電力用半導体素子４は、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistor）、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）、ＦＷＤ（Free Wheeling Diode）、及び、ＳＢＤ（Schottky Barrier Diode）の少なくともいずれか１つを含み、かつ珪素（Ｓｉ）を含む。   The lower surface of the power semiconductor element 4 is joined to the circuit pattern 2b by the joining member 3. The power semiconductor element 4 includes, for example, at least one of an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a FWD (Free Wheeling Diode), and an SBD (Schottky Barrier Diode). And silicon (Si).

電力用半導体素子４の上面には、エミッタ電極４ｅとゲート電極４ｇとが離間して配設されている。エミッタ電極４ｅ及びゲート電極４ｇは、例えばスパッタ法により成膜された厚さ５μｍのアルミニウム（Ａｌ）を主材料とする膜と、その上に無電解めっき法により成膜された厚さ１０μｍのニッケル（Ｎｉ）を主材料とする膜と、その上にフラッシュめっき法により成膜された厚さ０．０５μｍの金（Ａｕ）を主材料とする膜とからなる３層構造を有する。このようなエミッタ電極４ｅ及びゲート電極４ｇによれば、金属焼結体７ｅ，７ｇと良好な接合を得ることができる。   On the upper surface of the power semiconductor element 4, an emitter electrode 4e and a gate electrode 4g are arranged apart from each other. The emitter electrode 4e and the gate electrode 4g are made of, for example, a film mainly made of aluminum (Al) having a thickness of 5 μm formed by a sputtering method and nickel having a thickness of 10 μm formed thereon by an electroless plating method. It has a three-layer structure consisting of a film mainly composed of (Ni) and a film mainly composed of gold (Au) having a thickness of 0.05 μm formed thereon by flash plating. According to such an emitter electrode 4e and a gate electrode 4g, good bonding with the metal sintered bodies 7e and 7g can be obtained.

金属焼結体７ｅ，７ｇは、電力用半導体素子４の主面である上面に配設されたエミッタ電極４ｅ及びゲート電極４ｇ上にそれぞれ配設されている。金属焼結体７ｅ，７ｇの厚さは例えば５０μｍである。   The metal sintered bodies 7e and 7g are provided on the emitter electrode 4e and the gate electrode 4g provided on the upper surface which is the main surface of the power semiconductor element 4, respectively. The thickness of the metal sintered bodies 7e and 7g is, for example, 50 μm.

複数の金属ワイヤ６の一部分である一端は、金属焼結体７ｅ，７ｇによってエミッタ電極４ｅ及びゲート電極４ｇと接合されている。また、複数の金属ワイヤ６の別部分である他端は、超音波接合処理、または、荷重のみによる圧着によって、回路パターン２ｃ，２ｄと接合されている。本実施の形態１では、金属ワイヤ６は、Ａｕワイヤ、銀（Ａｇ）ワイヤ、または、銅（Ｃｕ）ワイヤを含むが、これに限ったものではない。   One end which is a part of the plurality of metal wires 6 is joined to the emitter electrode 4e and the gate electrode 4g by metal sintered bodies 7e and 7g. The other end, which is another part of the plurality of metal wires 6, is joined to the circuit patterns 2c and 2d by an ultrasonic joining process or by crimping only with a load. In the first embodiment, the metal wire 6 includes an Au wire, a silver (Ag) wire, or a copper (Cu) wire, but is not limited thereto.

図３及び図４は、それぞれ図２の点線枠Ｌ及び点線枠Ｒ内の拡大断面図である。なお、図３、図４に示される破線は、複数の金属ワイヤ６の一端の下端の位置を示す。図３及び図４に示すように、複数の金属ワイヤ６の一端は、エミッタ電極４ｅ及びゲート電極４ｇと離間された状態で金属焼結体７ｅ，７ｇに埋設されている。なお、金属焼結体７ｅ，７ｇ内には、複数の空隙１０が含まれている。   FIG. 3 and FIG. 4 are enlarged cross-sectional views in the dotted frame L and the dotted frame R of FIG. 2 respectively. Note that the broken lines shown in FIGS. 3 and 4 indicate the positions of the lower ends of the one ends of the plurality of metal wires 6. As shown in FIGS. 3 and 4, one ends of the plurality of metal wires 6 are embedded in the metal sintered bodies 7e and 7g while being separated from the emitter electrode 4e and the gate electrode 4g. Note that a plurality of voids 10 are included in the metal sintered bodies 7e and 7g.

次に、本実施の形態１に係る電力用半導体装置１２の製造方法について説明する。まず、回路パターン２ｂ〜２ｅを有する基板２を準備する。そして、焼結性金属粒子と分散材とを混錬した金属ペーストを、スクリーン印刷またはディスペンスによって回路パターン２ｂ上に供給する。その後、金属ペースト上の所定の位置に電力用半導体素子４を加圧搭載し、電力用半導体素子４の裏面全面に当該金属ペーストを広げる。それから上記金属ペーストと同様に、焼結前の金属焼結体７ｅ，７ｇである金属ペーストを、エミッタ電極４ｅ及びゲート電極４ｇ上に供給する。   Next, a method for manufacturing the power semiconductor device 12 according to the first embodiment will be described. First, the substrate 2 having the circuit patterns 2b to 2e is prepared. Then, a metal paste obtained by kneading the sinterable metal particles and the dispersant is supplied onto the circuit pattern 2b by screen printing or dispensing. Thereafter, the power semiconductor element 4 is mounted under pressure on a predetermined position on the metal paste, and the metal paste is spread over the entire back surface of the power semiconductor element 4. Then, similarly to the above-mentioned metal paste, a metal paste which is a metal sintered body 7e, 7g before sintering is supplied onto the emitter electrode 4e and the gate electrode 4g.

次に、金属ワイヤ６の一端を、エミッタ電極４ｅ及びゲート電極４ｇと離間された状態でエミッタ電極４ｅ及びゲート電極４ｇ上の金属ペーストに埋める。その後、金属ワイヤ６の他端を超音波接合処理などによって回路パターン２ｃ，２ｄに接合する。それから、これまでに構成された一体品を２００℃以上の温度で加熱して、各金属ペースト中の焼結性金属粒子を焼結させることによって、接合部材３及び金属焼結体７ｅ，７ｇを形成する。この際、焼結性金属粒子のネッキングの形成と、分散材の揮発とが起こることによって、接合部材３及び金属焼結体７ｅ，７ｇ内に空隙１０が形成される。   Next, one end of the metal wire 6 is buried in a metal paste on the emitter electrode 4e and the gate electrode 4g while being separated from the emitter electrode 4e and the gate electrode 4g. After that, the other end of the metal wire 6 is bonded to the circuit patterns 2c and 2d by an ultrasonic bonding process or the like. Then, the joint member 3 and the metal sintered bodies 7e and 7g are heated by heating the integrally formed product at a temperature of 200 ° C. or more to sinter the sinterable metal particles in each metal paste. Form. At this time, the formation of necking of the sinterable metal particles and the volatilization of the dispersing material occur, so that the voids 10 are formed in the joining member 3 and the metal sintered bodies 7e and 7g.

接合部材３によって電力用半導体素子４と回路パターン２ｂとが接合され、金属焼結体７ｅ，７ｇによってエミッタ電極４ｅ及びゲート電極４ｇと複数の金属ワイヤ６とが接合される。以上によって、本実施の形態１に係る電力用半導体装置１２が完成する。   The power semiconductor element 4 and the circuit pattern 2b are joined by the joining member 3, and the emitter electrodes 4e and the gate electrode 4g and the plurality of metal wires 6 are joined by the metal sintered bodies 7e and 7g. Thus, the power semiconductor device 12 according to the first embodiment is completed.

＜実施の形態１のまとめ＞
本実施の形態１に係る電力用半導体装置１２では、緩衝板を用いずに、金属焼結体７ｅ，７ｇを介して金属ワイヤ６を電力用半導体素子４に接合する。これにより、緩衝板と緩衝板を搭載する工程とを省略できるため、従来の電力用半導体装置よりも材料コスト及び製造コストの低減が期待できる。 <Summary of Embodiment 1>
In the power semiconductor device 12 according to the first embodiment, the metal wire 6 is joined to the power semiconductor element 4 via the metal sintered bodies 7e and 7g without using the buffer plate. As a result, the buffer plate and the step of mounting the buffer plate can be omitted, so that a reduction in material cost and manufacturing cost can be expected as compared with the conventional power semiconductor device.

また本実施の形態１では、金属ワイヤ６の一部分が金属焼結体７ｅ，７ｇに埋設されている。これにより、金属ワイヤ６と金属焼結体７ｅ，７ｇとの接合面積が拡大して強固な接合を実現することができるので、接合部の信頼性を高めることができる。なお、金属ワイヤ６のうちワイヤ径の半分以上の部分が金属焼結体７ｅ，７ｇに埋まり、かつ、金属ワイヤ６の一部が金属焼結体７ｅ，７ｇから露出されていることが望ましい。金属焼結体７ｅ，７ｇの厚さは、金属ワイヤ６の直径の半分以上であることが望ましい。   Further, in the first embodiment, a part of the metal wire 6 is embedded in the metal sintered bodies 7e and 7g. As a result, the bonding area between the metal wire 6 and the metal sintered bodies 7e and 7g can be increased and a strong bonding can be realized, so that the reliability of the bonding portion can be improved. It is desirable that a portion of the metal wire 6 having a half or more of the wire diameter be buried in the metal sintered bodies 7e and 7g, and that a part of the metal wire 6 be exposed from the metal sintered bodies 7e and 7g. It is desirable that the thickness of the metal sintered bodies 7 e and 7 g be at least half the diameter of the metal wire 6.

また本実施の形態１では、金属ワイヤ６のうち、金属焼結体７ｅ，７ｇに埋設された一部分は、電力用半導体素子４の主面から離間されている。これにより、超音波接合処理などによる衝撃が金属ワイヤ６から電力用半導体素子４に伝わることによる電力用半導体素子４へのダメージを抑制することができる。この結果、一般的なワイヤボンディングを用いて電力用半導体装置１２を形成することができる。以上により、信頼性に優れた電力用半導体素子４を実現することができる。   In the first embodiment, a part of the metal wire 6 buried in the metal sintered bodies 7 e and 7 g is separated from the main surface of the power semiconductor element 4. Accordingly, it is possible to suppress damage to the power semiconductor element 4 due to transmission of an impact due to an ultrasonic bonding process or the like from the metal wire 6 to the power semiconductor element 4. As a result, the power semiconductor device 12 can be formed using general wire bonding. As described above, the power semiconductor element 4 having excellent reliability can be realized.

また本実施の形態１では、金属ワイヤ６は、Ａｕワイヤ、Ａｇワイヤ、または、Ｃｕワイヤを含む。これらのワイヤは、Ａｌワイヤよりも再結晶温度が高く、電力用半導体素子４の高温動作に耐えることが可能である。このため、より信頼性に優れた電力用半導体素子４を実現することができる。   In the first embodiment, the metal wire 6 includes an Au wire, an Ag wire, or a Cu wire. These wires have a higher recrystallization temperature than the Al wire and can withstand the high-temperature operation of the power semiconductor element 4. For this reason, it is possible to realize the power semiconductor element 4 having higher reliability.

＜変形例＞
実施の形態１では、電力用半導体素子４がＳｉによって構成されていたが、これに限ったものではない。例えば、電力用半導体素子４は、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって構成されてもよい。ワイドバンドギャップ半導体としては、例えば、炭化珪素、窒化ガリウム系材料又はダイヤモンドがある。このようなワイドバンドギャップ半導体によって構成されたスイッチング素子やダイオード素子等の半導体素子は、耐電圧性が高く、許容電流密度も高い。このため、スイッチング素子やダイオード素子の小型化が可能であり、これら小型化されたスイッチング素子やダイオード素子を用いることにより、これらの素子を組み込んだ半導体モジュールの小型化が可能となる。また耐熱性も高いため、ヒートシンクの放熱フィンの小型化や、水冷部の空冷化が可能であるので、半導体モジュールの一層の小型化が可能になる。さらに電力損失が低いため、スイッチング素子やダイオード素子の高効率化が可能であり、延いては半導体モジュールの高効率化が可能になる。なお、スイッチング素子及びダイオード素子の両方がワイドバンドギャップ半導体によって構成されていることが望ましいが、いずれか一方の素子がワイドバンドギャップ半導体よって構成されていても、上記の効果をある程度得ることができる。 <Modification>
In the first embodiment, the power semiconductor element 4 is made of Si, but is not limited to this. For example, the power semiconductor element 4 may be formed of a wide band gap semiconductor having a larger band gap than silicon. Examples of the wide band gap semiconductor include silicon carbide, a gallium nitride-based material, and diamond. Semiconductor elements such as switching elements and diode elements formed of such a wide band gap semiconductor have high withstand voltage and high allowable current density. Therefore, it is possible to reduce the size of the switching element and the diode element, and by using the reduced switching element and the diode element, it is possible to reduce the size of a semiconductor module incorporating these elements. In addition, since the heat resistance is high, the size of the heat radiation fins of the heat sink can be reduced, and the air cooling of the water cooling section can be achieved. Further, since the power loss is low, the efficiency of the switching element and the diode element can be increased, and thus the efficiency of the semiconductor module can be increased. It is desirable that both the switching element and the diode element are made of a wide band gap semiconductor. However, even if one of the elements is made of a wide band gap semiconductor, the above effects can be obtained to some extent. .

＜実施の形態２＞
本発明の実施の形態２に係る電力変換装置は、実施の形態１に係る電力用半導体装置を有する主変換回路を備えた電力変換装置である。以上で説明した電力用半導体装置は特定の電力変換装置に限定されるものではないが、以下、本実施の形態２として、三相のインバータに、実施の形態１に係る電力用半導体装置を適用した場合について説明する。 <Embodiment 2>
A power converter according to a second embodiment of the present invention is a power converter including a main conversion circuit having the power semiconductor device according to the first embodiment. Although the power semiconductor device described above is not limited to a specific power converter, hereinafter, a power semiconductor device according to the first embodiment is applied to a three-phase inverter as a second embodiment. A description will be given of the case in which this is done.

図５は、本実施の形態２に係る電力変換装置を適用した電力変換システムの構成を示すブロック図である。   FIG. 5 is a block diagram illustrating a configuration of a power conversion system to which the power conversion device according to the second embodiment is applied.

図５に示す電力変換システムは、電源１００、電力変換装置２００、負荷３００から構成される。電源１００は、直流電源であり、電力変換装置２００に直流電力を供給する。電源１００は種々の電源で構成することが可能であり、例えば、直流系統、太陽電池、蓄電池で構成されてもよいし、交流系統に接続された整流回路やＡＣ／ＤＣコンバータで構成されてもよい。また、電源１００は、直流系統から出力される直流電力を所定の電力に変換するＤＣ／ＤＣコンバータによって構成されてもよい。   The power conversion system illustrated in FIG. 5 includes a power supply 100, a power conversion device 200, and a load 300. Power supply 100 is a DC power supply, and supplies DC power to power conversion device 200. The power supply 100 can be composed of various power supplies, and may be composed of, for example, a DC system, a solar cell, or a storage battery, or may be composed of a rectifier circuit or an AC / DC converter connected to an AC system. Good. Further, power supply 100 may be configured by a DC / DC converter that converts DC power output from a DC system into predetermined power.

電力変換装置２００は、電源１００と負荷３００との間に接続された三相のインバータであり、電源１００から供給された直流電力を交流電力に変換し、負荷３００に交流電力を供給する。電力変換装置２００は、図５に示すように、直流電力を交流電力に変換して出力する主変換回路２０１と、主変換回路２０１を制御する制御信号を主変換回路２０１に出力する制御回路２０３とを備えている。   The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts DC power supplied from the power supply 100 into AC power, and supplies AC power to the load 300. As shown in FIG. 5, power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs the same, and a control circuit 203 that outputs a control signal for controlling main conversion circuit 201 to main conversion circuit 201. And

負荷３００は、電力変換装置２００から供給された交流電力によって駆動される三相の電動機である。なお、負荷３００は特定の用途に限られるものではなく、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車や電気自動車、鉄道車両、エレベーター、もしくは、空調機器向けの電動機として用いられる。   Load 300 is a three-phase electric motor driven by AC power supplied from power conversion device 200. The load 300 is not limited to a specific application, but is a motor mounted on various electric devices, and is used as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner, for example.

以下、電力変換装置２００の詳細を説明する。主変換回路２０１は、スイッチング素子と還流ダイオードとを備えており（図示せず）、スイッチング素子がスイッチングすることによって、電源１００から供給される直流電力を交流電力に変換し、負荷３００に供給する。主変換回路２０１の具体的な回路構成には種々の構成があるが、本実施の形態２に係る主変換回路２０１は２レベルの三相フルブリッジ回路であり、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列された６つの還流ダイオードとから構成することができる。主変換回路２０１の各スイッチング素子及び各還流ダイオードの少なくともいずれか１つは、上述した実施の形態１に係る電力用半導体装置が適用された半導体モジュール２０２によって構成される。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相（Ｕ相、Ｖ相、Ｗ相）を構成する。そして、各上下アームの出力端子、すなわち主変換回路２０１の３つの出力端子は、負荷３００に接続される。   Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes a switching element and a free wheel diode (not shown). The switching element performs switching to convert DC power supplied from the power supply 100 into AC power and supply the AC power to the load 300. . Although there are various specific configurations of the main conversion circuit 201, the main conversion circuit 201 according to the second embodiment is a two-level three-phase full-bridge circuit, and includes six switching elements and respective switching elements. And six freewheeling diodes in antiparallel to the element. At least one of each switching element and each freewheel diode of the main conversion circuit 201 is configured by the semiconductor module 202 to which the power semiconductor device according to the above-described first embodiment is applied. The six switching elements are connected in series for every two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.

駆動回路２０２は、主変換回路２０１のスイッチング素子を駆動する駆動信号を生成し、主変換回路２０１のスイッチング素子の制御電極に供給する。具体的には、駆動回路２０２は、後述する制御回路２０３からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以上の電圧信号（オン信号）であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以下の電圧信号（オフ信号）となる。   The drive circuit 202 generates a drive signal for driving the switching element of the main conversion circuit 201, and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, the drive circuit 202 outputs a drive signal for turning on the switching element and a drive signal for turning off the switching element to the control electrode of each switching element in accordance with a control signal from the control circuit 203 described later. I do. When the switching element is maintained in the ON state, the drive signal is a voltage signal (ON signal) higher than the threshold voltage of the switching element. When the switching element is maintained in the OFF state, the drive signal is lower than the threshold voltage of the switching element. Signal (off signal).

制御回路２０３は、負荷３００に所望の電力が供給されるよう主変換回路２０１のスイッチング素子を制御する。具体的には、制御回路２０３は、負荷３００に供給すべき電力に基づいて主変換回路２０１の各スイッチング素子がオン状態となるべき時間（オン時間）を算出する。例えば、制御回路２０３は、出力すべき電圧に応じてスイッチング素子のオン時間を変調するＰＷＭ（Pulse Width Modulation）制御によって主変換回路２０１を制御することができる。そして、制御回路２０３は、各時点においてオン状態となるべきスイッチング素子にはオン信号を、オフ状態となるべきスイッチング素子にはオフ信号が出力されるよう、主変換回路２０１が備える駆動回路に制御指令（制御信号）を出力する。駆動回路は、この制御信号に従い、各スイッチング素子の制御電極にオン信号又はオフ信号を駆動信号として出力する。   The control circuit 203 controls the switching elements of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, the control circuit 203 calculates a time (on time) in which each switching element of the main conversion circuit 201 is to be in an on state based on the power to be supplied to the load 300. For example, the control circuit 203 can control the main conversion circuit 201 by PWM (Pulse Width Modulation) control that modulates the ON time of the switching element according to the voltage to be output. Then, the control circuit 203 controls the drive circuit included in the main conversion circuit 201 to output an ON signal to the switching element to be turned ON and an OFF signal to the switching element to be turned OFF at each time. Outputs a command (control signal). The drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to the control signal.

以上のような本実施の形態２に係る電力変換装置では、主変換回路２０１のスイッチング素子及び還流ダイオードの少なくともいずれか１つとして、実施の形態１に係る電力用半導体装置を適用するため、信頼性を高めることができる。   In the power converter according to the second embodiment as described above, since the power semiconductor device according to the first embodiment is applied as at least one of the switching element and the free wheel diode of the main conversion circuit 201, the reliability is improved. Can be enhanced.

以上で説明した本実施の形態２では、２レベルの三相インバータに、実施の形態１に係る電力用半導体装置を適用する例を説明したが、本実施の形態２は、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態２では、実施の形態１に係る電力用半導体装置は、２レベルの電力変換装置であるとしたが、３レベルやマルチレベルの電力変換装置であっても構わないし、単相負荷に電力を供給する場合には単相のインバータに上記電力用半導体装置を適用しても構わない。また、直流負荷等に電力を供給する場合にはＤＣ／ＤＣコンバータやＡＣ／ＤＣコンバータに上記電力用半導体装置を適用することも可能である。   In the second embodiment described above, an example is described in which the power semiconductor device according to the first embodiment is applied to a two-level three-phase inverter. However, the second embodiment is limited to this. Instead, it can be applied to various power converters. In the second embodiment, the power semiconductor device according to the first embodiment is a two-level power converter, but may be a three-level or multi-level power converter, or may be a single-phase load. When power is supplied to the power semiconductor device, the power semiconductor device may be applied to a single-phase inverter. When supplying power to a DC load or the like, the power semiconductor device can be applied to a DC / DC converter or an AC / DC converter.

また、本実施の形態２に係る電力変換装置は、上述した負荷が電動機の場合に限定されるものではなく、例えば、放電加工機やレーザー加工機、又は誘導加熱調理器や非接触給電システムの電源装置として用いることもでき、さらには太陽光発電システムや蓄電システム等のパワーコンディショナーとして用いることも可能である。   Further, the power conversion device according to the second embodiment is not limited to the case where the load is an electric motor, for example, an electric discharge machine, a laser machine, or an induction heating cooker or a non-contact power supply system. It can be used as a power supply device, and can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

なお、本発明は、その発明の範囲内において、各実施の形態及び各変形例を自由に組み合わせたり、各実施の形態及び各変形例を適宜、変形、省略したりすることが可能である。   In the present invention, each embodiment and each modified example can be freely combined, and each embodiment and each modified example can be appropriately modified or omitted within the scope of the invention.

４ 電力用半導体素子、６ 金属ワイヤ、７ｅ，７ｇ 金属焼結体、１２ 電力用半導体装置、２００ 電力変換装置、２０１ 主変換回路、２０３ 制御回路。   Reference Signs List 4 power semiconductor element, 6 metal wire, 7e, 7g metal sintered body, 12 power semiconductor device, 200 power conversion device, 201 main conversion circuit, 203 control circuit.

Claims (5)

半導体素子と、
前記半導体素子の主面上に配設された金属焼結材と、
前記金属焼結材によって前記半導体素子と接合された配線部材と
を備え、
前記配線部材の一部分は、前記半導体素子の前記主面と離間された状態で前記金属焼結材に埋設されている、半導体装置。 A semiconductor element;
A metal sintered material disposed on a main surface of the semiconductor element,
A wiring member joined to the semiconductor element by the metal sintered material,
A semiconductor device, wherein a part of the wiring member is buried in the metal sintered material while being separated from the main surface of the semiconductor element. 請求項１に記載の半導体装置であって、
前記配線部材は、Ａｕワイヤ、Ａｇワイヤ、または、Ｃｕワイヤを含む、半導体装置。 The semiconductor device according to claim 1, wherein:
The semiconductor device, wherein the wiring member includes an Au wire, an Ag wire, or a Cu wire. 請求項１または請求項２に記載の半導体装置であって、
前記半導体素子は、ワイドバンドギャップ半導体を含む、半導体装置。 The semiconductor device according to claim 1 or 2, wherein:
The semiconductor device, wherein the semiconductor element includes a wide band gap semiconductor. 請求項１から請求項３のうちのいずれか１項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路と
を備える、電力変換装置。 A main conversion circuit, comprising: the semiconductor device according to claim 1, wherein the main conversion circuit converts input power and outputs the converted power.
And a control circuit for outputting a control signal for controlling the main conversion circuit to the main conversion circuit. （ａ）半導体素子の主面上に、焼結前の金属焼結材を塗布する工程と、
（ｂ）配線部材の一部分を、前記半導体素子の前記主面と離間された状態で前記金属焼結材に埋める工程と、
（ｃ）前記工程（ｂ）の後に、前記配線部材の別部分に超音波接合処理を行う工程と、
（ｄ）前記工程（ｃ）の後に、前記金属焼結材を加熱して焼結することによって、前記配線部材を前記半導体素子に接合する工程と
を備える、半導体装置の製造方法。 (A) applying a metal sintered material before sintering on the main surface of the semiconductor element;
(B) a step of burying a part of the wiring member in the metal sintered material while being separated from the main surface of the semiconductor element;
(C) performing an ultrasonic bonding process on another portion of the wiring member after the step (b);
(D) bonding the wiring member to the semiconductor element by heating and sintering the metal sintered material after the step (c).
JP2018167478A 2018-09-07 2018-09-07 Semiconductor device and manufacturing method therefor, and power conversion device Pending JP2020043154A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021240748A1 (en) * 2020-05-28 2021-12-02 三菱電機株式会社 Semiconductor device, method for producing same, and electric power converter
JP7176662B1 (en) * 2021-11-04 2022-11-22 三菱電機株式会社 Semiconductor equipment and power conversion equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021240748A1 (en) * 2020-05-28 2021-12-02 三菱電機株式会社 Semiconductor device, method for producing same, and electric power converter
JP7391210B2 (en) 2020-05-28 2023-12-04 三菱電機株式会社 Semiconductor device and its manufacturing method, and power conversion device
JP7176662B1 (en) * 2021-11-04 2022-11-22 三菱電機株式会社 Semiconductor equipment and power conversion equipment
WO2023079640A1 (en) * 2021-11-04 2023-05-11 三菱電機株式会社 Semiconductor device and power conversion apparatus

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