JP2020038758A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2020038758A5 JP2020038758A5 JP2018164352A JP2018164352A JP2020038758A5 JP 2020038758 A5 JP2020038758 A5 JP 2020038758A5 JP 2018164352 A JP2018164352 A JP 2018164352A JP 2018164352 A JP2018164352 A JP 2018164352A JP 2020038758 A5 JP2020038758 A5 JP 2020038758A5
- Authority
- JP
- Japan
- Prior art keywords
- outer bank
- display device
- bank
- sealing layer
- inorganic sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007789 sealing Methods 0.000 claims 10
- 239000000758 substrate Substances 0.000 claims 9
- 230000000873 masking Effects 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000009751 slip forming Methods 0.000 claims 1
Claims (7)
前記表示領域の外側に形成され、断面が凸形状の外側バンクと、
前記表示領域において前記複数の自発光素子を覆う無機封止層と、を含み、
前記無機封止層は、前記外側バンクの前記表示領域側の側面に形成され、前記外側バンクの頂部の少なくとも一部分には形成されていない
ことを特徴とする表示装置。 An element substrate having a display area in which a plurality of self-luminous elements are formed, and
An outer bank formed outside the display area and having a convex cross section,
Including the inorganic sealing layer covering the plurality of self-luminous elements in the display region,
A display device characterized in that the inorganic sealing layer is formed on a side surface of the outer bank on the display region side, and is not formed on at least a part of the top of the outer bank.
前記外側バンクは、前記素子基板の端部に形成されており、
前記無機封止層は、前記素子基板の端部には形成されておらず、
前記素子基板の上面と前記外側バンクの上面との距離は、前記素子基板の上面と前記無機封止層の上面との距離よりも大きい、
ことを特徴とする表示装置。 In the display device according to claim 1,
The outer bank is formed at an end portion of the element substrate.
The inorganic sealing layer is not formed at the end of the device substrate, and the inorganic sealing layer is not formed.
The distance between the upper surface of the element substrate and the upper surface of the outer bank is larger than the distance between the upper surface of the element substrate and the upper surface of the inorganic sealing layer.
A display device characterized by that.
前記外側バンクは、前記素子基板の端部に沿って連続的に形成されている
ことを特徴とする表示装置。 In the display device according to claim 2,
A display device characterized in that the outer bank is continuously formed along an end portion of the element substrate.
前記表示領域から離れている接触領域において回路基板と接触する配線を更に含み、
前記外側バンクは、前記表示領域と、前記接触領域との間の位置に形成されており、
前記無機封止層は、前記外側バンクの前記接触領域側の側面には形成されていない
ことを特徴とする表示装置。 In the display device according to any one of claims 1 to 3.
Further including wiring that comes into contact with the circuit board in the contact area away from the display area.
The outer bank is formed at a position between the display area and the contact area.
A display device characterized in that the inorganic sealing layer is not formed on the side surface of the outer bank on the contact region side.
前記外側バンクの前記側面に形成される前記無機封止層の厚さは、前記頂部に向かって徐々に薄くなっている
ことを特徴とする表示装置。 In the display device according to any one of claims 1 to 4.
A display device characterized in that the thickness of the inorganic sealing layer formed on the side surface of the outer bank gradually decreases toward the top.
前記表示領域と前記外側バンクとの間に形成され、断面が凸形状の中間バンクを更に含み、
前記外側バンクの頂部は、前記中間バンクの頂部よりも上方に位置し、
前記無機封止層は、前記複数の自発光素子と前記中間バンクとを連続的に覆うように形成されており、前記外側バンクの頂部の少なくとも一部分には形成されていない
ことを特徴とする表示装置。 In the display device according to any one of claims 1 to 5.
An intermediate bank formed between the display area and the outer bank and having a convex cross section is further included.
The top of the outer bank is located above the top of the intermediate bank.
The inorganic sealing layer is formed so as to continuously cover the plurality of self-luminous elements and the intermediate bank, and is not formed on at least a part of the top of the outer bank. Device.
前記表示領域の外側に断面が凸状の外側バンクを形成する外側バンク形成工程と、
前記外側バンクの上に、開口が形成されたマスクを配置するマスク工程と、
前記マスク工程よりも後に、前記複数の自発光素子を覆う無機封止層を、前記表示領域と、前記外側バンクの頂部の少なくとも一部分を除く前記表示領域側の側面に形成する無機封止層形成工程と、
を含み、
前記外側バンクは、前記素子基板の上面と前記外側バンクの上面との距離が前記素子基板の上面と前記無機封止層の上面との距離よりも大きくなるように形成される、
ことを特徴とする表示装置の製造方法。 A process of preparing an element substrate in which a plurality of self-luminous elements are formed in a display area, and
An outer bank forming step of forming an outer bank having a convex cross section on the outside of the display area,
A masking step of arranging a mask having an opening formed on the outer bank,
After the masking step, the inorganic sealing layer for covering the plurality of self-luminous elements is formed on the display region and the side surface on the display region side except for at least a part of the top of the outer bank. Process and
Only including,
The outer bank is formed so that the distance between the upper surface of the element substrate and the upper surface of the outer bank is larger than the distance between the upper surface of the element substrate and the upper surface of the inorganic sealing layer.
A method of manufacturing a display device, characterized in that.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018164352A JP7178216B2 (en) | 2018-09-03 | 2018-09-03 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE |
PCT/JP2019/021314 WO2020049811A1 (en) | 2018-09-03 | 2019-05-29 | Display device and display device manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018164352A JP7178216B2 (en) | 2018-09-03 | 2018-09-03 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2020038758A JP2020038758A (en) | 2020-03-12 |
JP2020038758A5 true JP2020038758A5 (en) | 2021-10-28 |
JP7178216B2 JP7178216B2 (en) | 2022-11-25 |
Family
ID=69723072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018164352A Active JP7178216B2 (en) | 2018-09-03 | 2018-09-03 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP7178216B2 (en) |
WO (1) | WO2020049811A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022067770A1 (en) | 2020-09-30 | 2022-04-07 | 京东方科技集团股份有限公司 | Display panel and display device |
CN117561559A (en) * | 2021-07-26 | 2024-02-13 | 夏普显示科技株式会社 | Method for manufacturing display device |
KR20240025337A (en) * | 2022-08-18 | 2024-02-27 | 엘지디스플레이 주식회사 | Display device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7109653B2 (en) * | 2002-01-15 | 2006-09-19 | Seiko Epson Corporation | Sealing structure with barrier membrane for electronic element, display device, electronic apparatus, and fabrication method for electronic element |
KR101978783B1 (en) * | 2012-11-09 | 2019-05-15 | 엘지디스플레이 주식회사 | Flexible organic electroluminescent device and method for fabricating the same |
KR102663900B1 (en) * | 2016-05-26 | 2024-05-08 | 삼성디스플레이 주식회사 | Organic light emitting display device and method for manufacturing the same |
US10743425B2 (en) * | 2016-10-31 | 2020-08-11 | Lg Display Co., Ltd. | Display device and method for manufacturing the same |
KR20180060851A (en) * | 2016-11-29 | 2018-06-07 | 엘지디스플레이 주식회사 | Organic light emitting display device |
JP2018113104A (en) * | 2017-01-06 | 2018-07-19 | 株式会社ジャパンディスプレイ | Display device and manufacturing method of display device |
-
2018
- 2018-09-03 JP JP2018164352A patent/JP7178216B2/en active Active
-
2019
- 2019-05-29 WO PCT/JP2019/021314 patent/WO2020049811A1/en active Application Filing
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2020038758A5 (en) | ||
JP2020532043A5 (en) | ||
JP2018066819A5 (en) | ||
JP2017098020A5 (en) | ||
JP2017210657A5 (en) | ||
JP2015069854A5 (en) | ||
JP2013153069A5 (en) | ||
JP2014235959A5 (en) | ||
JP2011124160A5 (en) | ||
JP2012074443A5 (en) | ||
JP2016018759A5 (en) | ||
JP2016009791A5 (en) | Semiconductor device | |
JP2020073726A5 (en) | ||
JP2017092477A5 (en) | ||
JP2018181668A5 (en) | ||
SG196825A1 (en) | Reliable interconnect for semiconductor device | |
JP2013093386A5 (en) | ||
JP2007142382A5 (en) | ||
JP6571414B2 (en) | Semiconductor device | |
JP2016096246A5 (en) | Method for forming solder resist on flexible printed wiring board and printed wiring board | |
JP2017044533A5 (en) | ||
JP2015195272A5 (en) | ||
SG11201808293UA (en) | Method for manufacturing semiconductor device | |
JP2015156471A5 (en) | ||
JP2018160491A5 (en) |