JP2020027905A - Laminated body and manufacturing method thereof - Google Patents

Abstract

To provide a laminated body of an electrode-p-type gallium-based semiconductor having low resistance and good quality ohmic contact, and a manufacturing method thereof.SOLUTION: A laminated body includes a p-type III-V compound semiconductor layer 11 including Ga such as GaN or GaN mixed crystal, an electrode 13, and a contact resistance reducing layer 12 provided between the p-type III-V compound semiconductor layer 11 and the electrode 13, and including an oxide containing Ru or an oxynitride containing Ru, and having the film thickness from 10 nm to 1 μm. The contact resistance reducing layer 12 is formed by a sputtering method, and the film forming temperature is lower than 600°C.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a laminate and a method for producing the same.

In order to realize an optical device (Photo-related devices) using a gallium nitride semiconductor such as a light emitting diode and a laser diode, it is very important to form a high-quality ohmic contact between the semiconductor and the electrode. is there.
Conventionally, in a p-type gallium nitride semiconductor, a thin film electrode structure based on nickel (Ni), that is, a metal thin film of nickel / gold (Ni / Au) has been widely used as a thin film electrode structure for forming an ohmic contact. Have been. Recently, various ohmic contact metal systems such as Ni / Pt / Au, Pt / Ni / Au, and Pd / Au have been developed.

However, even now, there is a problem to be solved in order to form a high-quality ohmic contact in a p-type gallium nitride semiconductor. In particular, hydrogen (H) of ammonia (NH ₃ ), which is an atmospheric gas used when forming a p-type gallium nitride semiconductor, is combined with Mg, which is a p-type dopant, to provide an electrically insulating Mg—H composite. Since the body is formed, the effective carrier concentration decreases and the surface resistance increases. As a result, there is a problem that it is difficult to form a high-quality ohmic contact. In addition, since carrier (hole) injection is reduced, it becomes difficult to manufacture a high-quality optical device.
Therefore, a method for realizing high-quality ohmic contact has been required.

  Patent Document 1 discloses that a p-type gallium nitride-based compound semiconductor doped with a p-type impurity is subjected to a heat treatment together with a metal or an alloy capable of absorbing hydrogen, such as Zr, to thereby provide a p-type gallium nitride-based compound having a high carrier concentration. It is described that a semiconductor is formed and an ohmic contact with a metal is formed by increasing the carrier concentration of the semiconductor. However, since it is essential to heat-treat the semiconductor at 400 ° C. or higher, there is a concern that the semiconductor may be damaged by heat.

  Patent Document 2 describes that an ohmic contact is formed by sequentially depositing a thin film of nickel, a gold-zinc alloy, and gold (Ni / Au-Zn / Au) on gallium nitride. However, since this method also requires heat treatment near the melting point of the metal, there is a concern that the semiconductor may be damaged by heat.

  Further, it has been proposed to use a conductive oxide such as indium tin oxide (ITO) or ZnO, or a conductive nitride such as TiN as an ohmic contact layer formed between a semiconductor and an electrode. I have. However, since the work functions of conductive oxides and nitrides are small and difficult to adjust, a large voltage drop occurs at the interface between the ohmic contact layer and the semiconductor (Schottky contact). As a result, there has been a problem that the operating voltage of the semiconductor element is increased.

JP 2001-35796 A JP 2011-199319 A

  An object of the present invention is to provide a stacked body of an electrode and a p-type gallium-based semiconductor having low resistance and high quality ohmic contact.

According to the present invention, the following laminates and the like are provided.
1. A semiconductor layer containing a p-type III-V compound containing gallium, an electrode, and a contact resistance reducing layer containing an oxide containing Ru or an oxynitride containing Ru between the semiconductor layer and the electrode; A laminate.
2. 2. The laminate according to 1, wherein the semiconductor layer includes GaN or a mixed crystal including GaN.
3. The electrodes, Ni, Pd, Pt, Rh , Zn, In, Sn, Ag, Au, Mo, metal selected from Ti and _{Al, ITO, SnO 2, ZnO} , In 2 O 3, Ga 2 O 3, At least one selected from the group consisting of an oxide selected from RhO ₂ , NiO, CoO, PdO, PtO, CuAlO ₂ and CuGaO ₂ , a nitride selected from TiN, TaN and SiNx, and a poly-Si 3. The laminate according to 1 or 2, including:
4. 4. The laminate according to 3, wherein the electrode has a laminate structure of two or more layers, and each layer of the laminate structure includes at least one selected from the group consisting of the metal, the oxide, and the nitride.
5. The laminate according to any one of claims 1 to 4, wherein the contact resistance reducing layer has a thickness of 10 nm or more and 1 μm or less.
A semiconductor device including the laminate according to any one of 6.1 to 5.
7. Forming a contact resistance reducing layer containing an oxide containing Ru or an oxynitride containing Ru on a semiconductor layer containing a p-type III-V compound containing gallium, and then contacting the contact resistance reducing layer. A method for manufacturing a laminate, which forms an electrode.
8. 8. The method according to 7, wherein the semiconductor layer contains GaN or a mixed crystal containing GaN.
9. The electrode is made of a metal selected from Ni, Pd, Pt, Rh, Zn, In, Sn, Ag, Au, Mo, Ti and Al, ITO, SnO ₂ , ZnO, In ₂ O ₃ , Ga ₂ O ₃ , RhO ₂ , NiO, CoO, PdO, PtO, an oxide selected from CuAlO ₂ and CuGaO ₂ , a nitride selected from TiN, TaN and SiNx, and at least one selected from the group consisting of poly-Si 9. The production method according to 7 or 8, comprising:
10. The manufacturing method according to any one of 7 to 9, wherein a film forming temperature of the contact resistance reducing layer is set to less than 600 ° C.
11. The method according to any one of claims 7 to 10, wherein the contact resistance reducing layer is formed by a sputtering method using at least one selected from O ₂ , Ar, and N ₂ as a sputtering gas.
12. Said electrode is formed by a sputtering method using at least one sputtering gas selected from O _2, Ar and N _2, The process according to any one of 7-11.

  ADVANTAGE OF THE INVENTION According to this invention, the laminated body of an electrode and a p-type gallium-based semiconductor which has a low resistance and good quality ohmic contact can be provided.

It is an outline sectional view of a layered product concerning one embodiment of the present invention. It is a schematic structure figure of a light emitting diode concerning one embodiment of the present invention. FIG. 9 is a schematic configuration diagram of a light emitting diode according to another embodiment of the present invention. FIG. 9 is a schematic configuration diagram of a light emitting diode according to another embodiment of the present invention. It is a schematic sectional drawing of the laminated body produced in the Example and the comparative example.

The stacked body according to one embodiment of the present invention includes a semiconductor layer containing a p-type III-V compound containing gallium, an electrode, and an oxide containing Ru or between the semiconductor layer and the electrode. It has a contact resistance reduction layer containing an oxynitride containing Ru.
FIG. 1 is a schematic sectional view of a laminate according to one embodiment of the present invention.
The laminate 1 has a configuration in which a semiconductor layer 11, a contact resistance reduction layer 12, and an electrode 13 are laminated in this order. By interposing the contact resistance reducing layer 12 containing an oxide containing Ru or an oxynitride containing Ru between the semiconductor layer 11 and the electrode 13, a good ohmic contact with low resistance can be formed.

In this embodiment, the semiconductor layer contains a p-type group III-V compound containing gallium. Examples of the compound include GaN, InGaN, AlGaN, AlInGaN, and the like. The semiconductor layer preferably contains GaN or a mixed crystal containing GaN.
Known Mg and the like can be used as the p-type dopant.

The semiconductor layer can be formed, for example, by epitaxial growth on a supporting substrate for forming the semiconductor layer. The support substrate is not particularly limited as long as it can form a semiconductor layer. For example, GaN, InGaN, AlGaN, AlN, InN, SiC, Si, and sapphire can be suitably used.
Further, the semiconductor layers can be formed over different materials. For example, GaN can be used for the surface in contact with the contact resistance reduction layer, and Si can be used for the supporting substrate.

  The thickness of the semiconductor layer can be appropriately adjusted so that desired electric characteristics can be obtained. For example, a range of 10 nm to 2 mm is preferable.

  Whether the semiconductor layer is a p-type semiconductor or an n-type semiconductor is determined by Hall effect measurement. When the Hall effect measurement is difficult due to high resistance, the presence or absence of an acceptor-derived peak (385 to 400 nm) by photoluminescence (PL) and the acceptor element (Mg or the like) are determined by secondary ion mass spectrometry (SIMS). The contents of the donor elements (such as Si) are compared, and a determination is made as to which of them contains one or more digits.

The contact resistance reducing layer is a layer containing an oxide containing Ru or an oxynitride containing Ru, and preferably contains RuOx such as RuO ₂ . The contact resistance reducing layer is formed between the electrode and the semiconductor layer so as to be in contact with a part or the entire surface of the semiconductor layer. The fact that the contact resistance reducing layer contains an oxide containing Ru or an oxynitride containing Ru can be confirmed by, for example, SIMS.
It is preferable that the contact resistance reducing layer essentially consists of an oxide containing Ru or an oxynitride containing Ru. For example, at least 90% by weight, at least 95% by weight, or at least 99% by weight may be an oxide containing Ru or an oxynitride containing Ru. Further, the contact resistance reducing layer may consist of only the contact resistance reducing layer. In this case, it may contain unavoidable impurities.

  The thickness of the contact resistance reducing layer can be appropriately adjusted so as to obtain a desired contact resistance reducing effect. For example, the range is preferably from 1 nm to 10 μm, and more preferably from 10 nm to 1 μm. The cross-sectional shape such as the thickness can be confirmed by, for example, a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

  The contact resistance reducing layer may be an amorphous layer or a polycrystalline layer. Further, a layer in which an amorphous component and a crystalline component are mixed may be used. The crystallinity of the contact resistance reduction layer can be determined from a TEM lattice image.

The electrical resistivity (25 ° C.) of the contact resistance reducing layer is preferably 1 × 10 ⁻¹ Ωm or less. When it is 1 × 10 ⁻¹ Ωm or less, for example, when used as an electrode of a semiconductor device, the conductivity is sufficient and the current injection efficiency is high.
The electric resistivity of the contact resistance reducing layer is a measured value of a sample in which a single contact resistance reducing layer is formed on a glass substrate. The electric resistivity can be measured by, for example, a Hall effect measuring device.

The electrode is not particularly limited as long as it can be formed on the surface of the contact resistance reduction layer on the side opposite to the semiconductor layer. For example, metals such as Ni, Pd, Pt, Rh, Zn, In, Sn, Ag, Au, Mo, Ti, and Al, ITO, SnO ₂ , ZnO, In ₂ O ₃ , Ga ₂ O ₃ , RhO ₂ , NiO _{, CoO, PdO, PtO, CuAlO} 2, CuGaO oxides such as _2, TiN, TaN, nitrides such as SiNx, poly-Si (polysilicon) can be mentioned.
When light is extracted through an electrode, the electrode is preferably a transparent conductive oxide or a transparent conductive nitride having light transmittance.

  The electrode may be a single layer or a laminate of two or more layers. For example, a layer containing Ni may be formed in contact with the contact resistance reduction layer, and an Au layer may be stacked on the Ni layer to prevent oxidation. Further, each layer constituting the electrode may include at least one selected from the group consisting of the above-mentioned metals, oxides, and nitrides.

  The thickness of the electrode can be appropriately adjusted so as to obtain desired electric characteristics. For example, a range of 10 nm to 10 μm is preferable.

  The laminate of this embodiment forms, for example, a contact resistance reduction layer containing an oxide containing Ru or an oxynitride containing Ru on a semiconductor layer containing a p-type III-V compound containing gallium, And a step of forming an electrode in contact with the contact resistance reducing layer.

In the above manufacturing method, the method for forming the semiconductor layer, the contact resistance reducing layer, and the electrode is not particularly limited. For example, metal organic chemical vapor deposition (MOVPE), resistance heating evaporation, electron beam evaporation, sputter deposition, atomic layer deposition (ALD) deposition, thermal CVD, parallel plate plasma CVD deposition, magnetic field micro Wave plasma CVD film formation, inductively coupled plasma CVD film formation, and spin coating method can be used.
In the case of sputtering film formation, reactive sputtering of a metal target in an atmosphere containing oxygen can also be suitably used. Thereby, the film formation rate is improved as compared with sputtering using an insulator target.

  From the viewpoint of reducing thermal damage to the semiconductor layer, the deposition temperature of the contact resistance reduction layer is preferably lower than 600 ° C, more preferably 400 ° C or lower.

From the viewpoint of reducing thermal damage to the semiconductor layer, the contact resistance reducing layer is preferably formed by a sputtering method using at least one selected from O ₂ , Ar, and N ₂ as a sputtering gas.
Similarly, the electrode is preferably formed by a sputtering method using at least one selected from O ₂ , Ar, and N ₂ as a sputtering gas.

The laminate of the present embodiment can be used as a constituent member of a semiconductor device such as a light emitting diode and a laser diode. For example, a good ohmic contact can be formed at the interface between the electrode of a short-wavelength light emitting diode and a laser diode using a gallium nitride semiconductor and emitting short wavelength light emitting diodes and laser diodes and a semiconductor layer.
Hereinafter, a specific example of a light emitting diode as a semiconductor device using the stacked body of the present embodiment will be described with reference to the drawings. Note that the semiconductor device of the present invention is not limited to the following example.

FIG. 2 is a schematic configuration diagram of a light emitting diode according to one embodiment of the present invention.
In the light-emitting diode 2, an n-type GaN-based semiconductor layer 21 is laminated on a substrate 20, and an electrode 23 (cathode) is partially provided near an end on the semiconductor layer 21, The light emitting layer 22 is formed in a portion other than the electrode 23 and its periphery. The light emitting diode 2 has a structure in which the laminate 1 (semiconductor layer (p-type GaN-based semiconductor layer) 11, contact resistance reducing layer 12, and electrode (anode) 13) of the present invention is formed on the light emitting layer 22.

FIG. 3 is a schematic configuration diagram of a light emitting diode according to another embodiment of the present invention.
The light emitting diode 3 includes an electrode 23 (cathode), a substrate 20, an n-type GaN-based semiconductor layer 21, a light-emitting layer 22, and a laminate 1 (semiconductor layer (p-type GaN-based semiconductor layer) 11, It has a structure in which the resistance reduction layer 12 and the electrode (anode) 13) are stacked in this order.

FIG. 4 is a schematic configuration diagram of a light emitting diode according to another embodiment of the present invention.
The light-emitting diode 4 includes a substrate 20, an electrode 23 (cathode), an n-type GaN-based semiconductor layer 21, a light-emitting layer 22, and a laminate 1 (semiconductor layer (p-type GaN-based semiconductor layer) 11, It has a structure in which the resistance reduction layer 12 and the electrode (anode) 13) are stacked in this order.

  In the light emitting diodes 2 to 4, when a voltage is applied between the electrode 13 and the electrode 23, holes are injected into the semiconductor layer 11 and electrons are injected into the n-GaN-based semiconductor layer 21. Light is emitted by the recombination of the injected holes and electrons in the light emitting layer 22.

The constituent members of the above-described embodiments are not particularly limited, and known members can be used. Further, it can be manufactured by applying a known film forming technique.
According to the present invention, a semiconductor device having high-quality ohmic contact having excellent current-voltage characteristics and low contact resistance can be obtained.

Example 1
FIG. 5 is a schematic cross-sectional view of the laminates manufactured in the examples and the comparative examples.
A p-type GaN semiconductor layer 11 was formed on a single-crystal n-type GaN semiconductor substrate serving as the support substrate 30 by metal organic chemical vapor deposition (MOVPE). The substrate 30 on which the p-type GaN semiconductor layer 11 was formed was placed in an ultrasonic bath (ultrasonic bath), and washed with trichloroethylene for 5 minutes, acetone for 5 minutes, methanol for 5 minutes, and finally with distilled water for 5 minutes. . Thereafter, activation annealing was performed at 750 ° C. for 5 minutes in an oxygen atmosphere.
The activation-annealed substrate 30 was set together with an area mask in a sputtering apparatus (E-200-S, manufactured by Anelva), a Ru target having a diameter of 2 inches was used, O ₂ was used as a sputtering gas, and output was performed at 25 ° C. Ruthenium oxide (RuO _x ) as the contact resistance reducing layer 12 was formed to a thickness of 100 nm on the p-type GaN semiconductor layer 11 at DC 50 W.
Then, the electrode 13 was set in an EB vapor deposition apparatus (manufactured by ULVAC, Inc.) together with an area mask, and Au serving as the electrode 13 was formed to a thickness of 200 nm on RuO _x to produce a p-GaN / RuO _x / Au laminate. The temperature rose from 25 ° C. to 80 ° C. due to radiant heat during the film formation for vapor deposition.
About the obtained laminated body, the specific resistance was measured using the specific resistance / Hall measuring system (ResiTest8300 by Toyo Technica). The specific resistance was 9.81 × 10 ⁻¹ Ωcm.

In addition, the laminate obtained in Example 1 was placed in a rapid heating furnace, and was annealed by heating at 525 ° C. for 5 minutes in an air or oxygen atmosphere. The specific resistance after annealing was 1.69 × 10 ⁻¹ Ωcm.
Table 1 shows the structure of the laminate and the measurement results of the specific resistance.

Comparative Example 1
The electrode was formed as a laminate of Ni and Au without forming the contact resistance reducing layer 12 (RuO _x ) of Example 1. Specifically, the substrate with the p-type GaN semiconductor that had been activated and annealed in the same manner as in Example 1 was set together with an area mask in an EB vapor deposition apparatus (manufactured by ULVAC, Inc.). 20 nm of Ni was deposited as an electrode on the p-type GaN semiconductor layer, and 200 nm of Au was formed on Ni to form a p-GaN / Ni / Au laminate. The temperature rose from 25 ° C. to 80 ° C. due to radiant heat during the film formation for vapor deposition.
The obtained laminate was evaluated in the same manner as in Example 1. Table 1 shows the measurement results.

Comparative Example 2
In the contact resistance reducing layer 12 of the first embodiment, IrO _x was used instead of RuO _x . Specifically, in the same manner as in Example 1, the substrate with the activated p-type GaN semiconductor was set together with an area mask in a sputtering apparatus (E-200-S, manufactured by Anelva) and an Ir target having a diameter of 2 inches was set. And IrO _x was formed to a thickness of 100 nm on the p-type GaN semiconductor layer at 25 ° C. with an output of DC 50 W using O ₂ as a sputtering gas.
Next, it was set in an EB vapor deposition apparatus (manufactured by ULVAC, Inc.), and a 200 nm film of Au was formed on IrO _x to produce a p-GaN / IrO _x / Au laminate.
The obtained laminate was evaluated in the same manner as in Example 1. Table 1 shows the measurement results.

In Example 1 using RuO _x to the contact resistance reducing layer, small specific resistance as compared with Comparative Example 1 using Ni and Au in the electrode, it can be confirmed that by forming a high quality ohmic contact. Also, it can be confirmed that a high-quality ohmic contact is formed even in comparison with Comparative Example 2 in which an oxide of Ir which is the same platinum group as that of Ru for the contact resistance reducing layer is used.

  The laminate according to one embodiment of the present invention can be used as a constituent member of a semiconductor device such as a light emitting diode and a laser diode.

Reference Signs List 1 laminated body 11 semiconductor layer (semiconductor layer containing p-type III-V compound containing gallium)
12 contact resistance reducing layer 13 electrode 2,3,4 light emitting diode (semiconductor device)
Reference Signs List 20 substrate 21 n-type GaN-based semiconductor layer 22 light-emitting layer 23 electrode 30 support substrate

Claims (12)

A semiconductor layer containing a p-type III-V compound containing gallium;
Electrodes and
A laminate comprising, between the semiconductor layer and the electrode, a contact resistance reduction layer containing an oxide containing Ru or an oxynitride containing Ru.   The laminate according to claim 1, wherein the semiconductor layer includes GaN or a mixed crystal including GaN. The electrodes, Ni, Pd, Pt, Rh , Zn, In, Sn, Ag, Au, Mo, metal selected from Ti and _{Al, ITO, SnO 2, ZnO} , In 2 O 3, Ga 2 O 3, At least one selected from the group consisting of an oxide selected from RhO ₂ , NiO, CoO, PdO, PtO, CuAlO ₂ and CuGaO ₂ , a nitride selected from TiN, TaN and SiNx, and a poly-Si The laminate according to claim 1, comprising:   The laminate according to claim 3, wherein the electrode has a laminate structure of two or more layers, and each layer of the laminate structure includes at least one selected from the group consisting of the metal, the oxide, and the nitride. body.   The laminate according to any one of claims 1 to 4, wherein the contact resistance reducing layer has a thickness of 10 nm or more and 1 m or less.   A semiconductor device comprising the laminate according to claim 1. Forming a contact resistance reduction layer containing an oxide containing Ru or an oxynitride containing Ru on a semiconductor layer containing a p-type III-V compound containing gallium;
Next, an electrode is formed so as to be in contact with the contact resistance reducing layer.   The method according to claim 7, wherein the semiconductor layer includes GaN or a mixed crystal including GaN. The electrodes, Ni, Pd, Pt, Rh , Zn, In, Sn, Ag, Au, Mo, metal selected from Ti and _{Al, ITO, SnO 2, ZnO} , In 2 O 3, Ga 2 O 3, At least one selected from the group consisting of an oxide selected from RhO ₂ , NiO, CoO, PdO, PtO, CuAlO ₂ and CuGaO ₂ , a nitride selected from TiN, TaN and SiNx, and a poly-Si The manufacturing method according to claim 7, comprising:   The method according to claim 7, wherein a film forming temperature of the contact resistance reducing layer is less than 600 ° C. 10. The method according to claim 7, wherein the contact resistance reducing layer is formed by a sputtering method using at least one selected from O ₂ , Ar, and N ₂ as a sputtering gas. The manufacturing method according to claim 7, wherein the electrode is formed by a sputtering method using at least one selected from O ₂ , Ar, and N ₂ as a sputtering gas.

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