JP2020021987A - Imaging apparatus and electronic apparatus - Google Patents

Abstract

To achieve photographing by a global shutter system without reducing a saturation signal charge amount.SOLUTION: The imaging apparatus includes: a pixel including a photoelectric conversion section for converting received light into a charge and a retaining part for retaining a charge transferred from the photoelectric conversion section; a floating diffusion shared among a plurality of pixels and retaining the charge transferred from the retaining part; and a pressure rising line for raising the pressure of the floating diffusion. This technique is applicable to, for example, a photographing device executing photographing by a global shutter system.SELECTED DRAWING: Figure 3

Description

  The present technology relates to an imaging device and an electronic device, and for example, relates to an imaging device and an electronic device that are preferably applied when capturing images using a global shutter method.

  2. Description of the Related Art Imaging elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCDs (Charge Coupled Devices) are widely used in digital still cameras and digital video cameras.

  For example, light incident on a CMOS image sensor is photoelectrically converted in a PD (Photodiode) included in a pixel. Then, the charge generated in the PD is transferred to an FD (Floating Diffusion) via a transfer transistor, and is converted into a pixel signal of a level corresponding to the amount of received light.

  By the way, a conventional CMOS image sensor generally employs a method of sequentially reading pixel signals from each pixel row by row, that is, a so-called rolling shutter method, and therefore, an image may be distorted due to a difference in exposure timing. Was.

  Therefore, for example, Japanese Patent Application Laid-Open No. H11-157572 discloses a CMOS system having a function of simultaneously reading out pixel signals from all pixels by providing a charge holding portion in each pixel, a so-called global shutter method, and having a simultaneous electronic shutter function for all pixels. An image sensor is disclosed. By employing the global shutter method, the exposure timing is the same for all pixels, and it is possible to avoid the occurrence of distortion in the image.

JP 2008-103647 A

  By the way, in recent years, there has been a demand for miniaturization of solid-state imaging devices, and there is a tendency that individual pixel sizes are reduced. In addition, by adopting the global shutter method, in the case of a configuration in which a charge holding unit is provided in a pixel, there is a possibility that the size of the photodiode is reduced and the saturated charge amount (Qs) is reduced.

  The present technology has been made in view of such a situation, and is to enable photographing by a global shutter method without reducing the saturation signal charge amount.

  An imaging device according to one aspect of the present technology is a pixel including a photoelectric conversion unit that converts received light into electric charge, and a holding unit that holds electric charge transferred from the photoelectric conversion unit, and is shared by a plurality of the pixels. A floating diffusion for holding the charge transferred from the holding unit; and a booster line for boosting the floating diffusion.

  An electronic device according to one aspect of the present technology is shared by a plurality of pixels including a pixel including a photoelectric conversion unit that converts received light into electric charge, and a holding unit that holds electric charge transferred from the photoelectric conversion unit. The imaging device includes a floating diffusion that holds the charges transferred from the holding unit, a booster line that boosts the floating diffusion, and a processing unit that processes a signal from the imaging device.

  In an imaging device according to an aspect of the present technology, a pixel including a photoelectric conversion unit that converts received light into electric charge and a holding unit that holds electric charge transferred from the photoelectric conversion unit is shared by a plurality of pixels. , A floating diffusion for holding the charges transferred from the holding unit, and a booster line for boosting the floating diffusion.

  An electronic apparatus according to one aspect of the present technology is configured to include the imaging device.

  Note that the imaging device and the electronic device may be independent devices, or may be internal blocks constituting one device.

  According to the embodiments of the present technology, it is possible to perform imaging using the global shutter method without reducing the saturation signal charge amount.

  Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

FIG. 3 is a diagram illustrating a configuration of an image sensor. FIG. 3 is a cross-sectional view illustrating a configuration of a pixel. FIG. 2 is a plan view illustrating a configuration of a pixel. It is a top view showing other composition of a pixel. It is a top view showing other composition of a pixel. It is a top view showing other composition of a pixel. It is a top view showing other composition of a pixel. It is a top view showing other composition of a pixel. FIG. 3 is a diagram for describing an FD boosting wiring. FIG. 3 is a diagram for describing an FD boosting wiring. FIG. 3 is a diagram for describing an FD boosting wiring. FIG. 3 is a diagram for describing an FD boosting wiring. FIG. 3 is a circuit diagram illustrating a configuration of a pixel. FIG. 3 is a diagram for explaining an operation of a pixel. FIG. 3 is a cross-sectional view illustrating a configuration of a pixel. FIG. 7 is a diagram for explaining transition of a potential of a pixel. FIG. 7 is a diagram for explaining transition of a potential of a pixel. FIG. 3 is a diagram for explaining an operation of a pixel. FIG. 3 is a diagram for describing the position and shape of a pixel wiring. FIG. 3 is a circuit diagram illustrating a configuration of a pixel. FIG. 3 is a diagram for describing the position and shape of a pixel wiring. FIG. 3 is a diagram for describing the position and shape of a pixel wiring. FIG. 3 is a diagram for describing the position and shape of a pixel wiring. FIG. 3 is a diagram for describing the position and shape of a pixel wiring. FIG. 2 is a plan view illustrating a configuration of a pixel. FIG. 3 is a cross-sectional view illustrating a configuration of a pixel. It is a top view showing other composition of a pixel. It is a figure for explaining FD conversion wiring. FIG. 3 is a diagram for describing the position and shape of a pixel wiring. FIG. 3 is a circuit diagram illustrating a configuration of a pixel. FIG. 3 is a circuit diagram illustrating a configuration of a pixel. FIG. 3 is a diagram for describing the position and shape of a pixel wiring. FIG. 3 is a diagram for describing the position and shape of a pixel wiring. FIG. 3 is a diagram for describing the position and shape of a pixel wiring. FIG. 3 is a diagram for describing the position and shape of a pixel wiring. FIG. 2 is a diagram for describing a configuration of an electronic device. It is a figure showing an example of the schematic structure of an endoscope operation system. FIG. 3 is a block diagram illustrating an example of a functional configuration of a camera head and a CCU. It is a block diagram showing an example of a schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of a vehicle exterior information detection part and an imaging part.

  Hereinafter, an embodiment for implementing the present technology (hereinafter, referred to as an embodiment) will be described.

<Configuration of imaging device>
FIG. 1 is a block diagram showing a configuration example of a CMOS (Complementary Metal Oxide Semiconductor) image sensor as an image sensor to which the present invention is applied.

  The CMOS image sensor 30 includes a pixel array unit 41, a vertical drive unit 42, a column processing unit 43, a horizontal drive unit 44, and a system control unit 45. The pixel array section 41, the vertical drive section 42, the column processing section 43, the horizontal drive section 44, and the system control section 45 are formed on a semiconductor substrate (chip) not shown.

  In the pixel array section 41, unit pixels (pixels 50 in FIG. 2) each having a photoelectric conversion element that generates and accumulates a photocharge of a charge amount corresponding to the incident light amount are two-dimensionally arranged in a matrix. In the following, the photocharge having a charge amount corresponding to the incident light amount may be simply described as “charge”, and the unit pixel may be simply described as “pixel”.

  Further, in the pixel array section 41, a pixel drive line 46 is formed for each row in the pixel array in a matrix along the left-right direction (pixel arrangement direction of the pixel row) in the figure, and a vertical signal line 47 is provided for each column. Are formed along the vertical direction in the figure (the arrangement direction of the pixels in the pixel column). One end of the pixel drive line 46 is connected to an output end of the vertical drive unit 42 corresponding to each row.

  The CMOS image sensor 30 further includes a signal processing unit 48 and a data storage unit 49. The signal processing unit 48 and the data storage unit 49 may be processed by an external signal processing unit provided on a substrate different from the CMOS image sensor 30, for example, a DSP (Digital Signal Processor) or software, or may be the same as the CMOS image sensor 30. It may be mounted on a substrate.

  The vertical drive unit 42 is a pixel drive unit that includes a shift register, an address decoder, and the like, and drives each pixel of the pixel array unit 41 simultaneously for all pixels or in units of rows. Although the specific configuration of the vertical drive unit 42 is not shown, the vertical drive unit 42 has a read-out scanning system, a sweep-out scanning system, or a batch sweep-out and batch transfer.

  The readout scanning system selectively scans the unit pixels of the pixel array unit 41 in row units in order to read out signals from the unit pixels. In the case of the row driving (rolling shutter operation), in the sweeping, the sweeping scan is performed on the readout row on which the readout scanning is performed by the readout scanning system earlier than the readout scanning by the shutter speed time. In the case of global exposure (global shutter operation), batch sweeping is performed earlier than batch transfer by the shutter speed time.

  By this sweeping, unnecessary charges are swept out (reset) from the photoelectric conversion elements of the unit pixels in the readout row. Then, by sweeping out (resetting) the unnecessary charges, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discarding the photoelectric charge of the photoelectric conversion element and newly starting exposure (starting accumulation of the photoelectric charge).

  The signal read out by the readout operation by the readout scanning system corresponds to the amount of light incident after the immediately preceding readout operation or the electronic shutter operation. In the case of row driving, a period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is a photocharge accumulation period (exposure period) in the unit pixel. In the case of global exposure, a period from batch sweeping to batch transfer is an accumulation period (exposure period).

  Pixel signals output from each unit pixel of the pixel row selected and scanned by the vertical driving unit 42 are supplied to the column processing unit 43 through each of the vertical signal lines 47. The column processing unit 43 performs a predetermined signal processing on a pixel signal output from each unit pixel of the selected row through the vertical signal line 47 for each pixel column of the pixel array unit 41, and performs a pixel processing after the signal processing. Temporarily.

  Specifically, the column processing unit 43 performs at least noise removal processing, for example, CDS (Correlated Double Sampling) processing as signal processing. By the correlated double sampling by the column processing unit 43, fixed pattern noise peculiar to pixels, such as reset noise and variation in the threshold value of the amplification transistor, is removed. The column processing unit 43 may have, for example, an AD (analog-digital) conversion function in addition to the noise removal processing, and output the signal level as a digital signal.

  The horizontal drive unit 44 includes a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 43. The pixel signals subjected to the signal processing in the column processing unit 43 are sequentially output to the signal processing unit 48 by the selective scanning by the horizontal driving unit 44.

  The system control unit 45 includes a timing generator or the like that generates various timing signals. The system control unit 45 includes a vertical driving unit 42, a column processing unit 43, and a horizontal driving unit 44 based on various timing signals generated by the timing generator. Drive control is performed.

  The signal processing section 48 has at least an addition processing function, and performs various signal processing such as addition processing on the pixel signal output from the column processing section 43. The data storage unit 49 temporarily stores data necessary for the signal processing in the signal processing unit 48.

<Structure of unit pixel>
Next, a specific structure of the unit pixels 50 arranged in a matrix in the pixel array unit 41 of FIG. 1 will be described. FIG. 2 is a diagram illustrating a cross-sectional configuration example of the pixel 50.

  The pixel 50a illustrated in FIG. 2 includes a charge holding unit in order to realize a global shutter. As shown in FIG. 2, the pixel 50a has a configuration in which a wiring layer 61, an oxide film 62, a semiconductor substrate 63, a light shielding layer 64, a color filter layer 65, and an on-chip lens 66 are stacked in this order from the lower side of FIG. Have been. In the pixel 50a, a region where the PD 51 is formed on the semiconductor substrate 63 is a PD region 67, and a region where the charge holding unit 54 is formed on the semiconductor substrate 63 is a charge holding region 68.

  In the image sensor 30, incident light is applied to a back surface (a surface facing upward in FIG. 2) opposite to the surface of the semiconductor substrate 63 on which the wiring layer 61 is provided. This is a so-called back-illuminated CMOS image sensor. Here, the description will be continued with a back-illuminated CMOS image sensor as an example, but the present technology can also be applied to a front-illuminated image sensor.

  The wiring layer 61 is supported by, for example, a substrate support member (not shown) disposed below the wiring layer 61, and includes a plurality of wirings 71 for reading charges of the PD 51 formed on the semiconductor substrate 63. It is configured to be embedded in the interlayer insulating film 72.

  In the wiring layer 61, a TRX gate 73 constituting a transfer transistor is arranged in a region between the PD 51 and the charge holding unit 54 via an oxide film 62 with respect to the semiconductor substrate 63. When a predetermined voltage is applied to the TRX gate 73, the charge stored in the PD 51 is transferred to the charge holding unit 54.

  The wiring layer 61 has a four-layer structure of the wiring layers 61-1 to 61-4 in the example shown in FIG. The wiring layer 61-1 is stacked on the semiconductor substrate 63, the wiring layer 61-2 is stacked on the wiring layer 61-1, the wiring layer 61-3 is stacked on the wiring layer 61-2, and the wiring layer 61-1. 4 is stacked on the wiring layer 61-3. The wiring pattern of each of the wiring layers 61-1 to 61-4 will be described later.

  The oxide film 62 has an insulating property, and insulates the surface side of the semiconductor substrate 63. An N-type region forming the PD 51 and an N-type region forming the charge holding unit 54 are formed on the semiconductor substrate 63.

  A surface pinning layer 74-1 is formed on the back side of the PD 51 and the charge holding unit 54, and a surface pinning layer 74-2 is formed on the surface side of the PD 51 and the charge holding unit 54. Further, in the semiconductor substrate 63, an inter-pixel separation region 75 for separating the pixel 50a from another adjacent pixel 50a is formed so as to surround the periphery of the pixel 50a.

  The light-shielding layer 64 is formed by embedding a light-shielding portion 76 made of a material having a light-shielding property in a high-dielectric-constant material film 77. For example, the light shielding portion 76 is formed of a material such as tungsten (W), aluminum (Al), or copper (Cu), and is connected to GND (not shown). The high dielectric constant material film 77 is formed of a material such as silicon dioxide (SiO2), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), and zirconium dioxide (ZrO2).

  The light-shielding portion 76 is disposed so as to be embedded in a vertical groove formed in the semiconductor substrate 63 so as to surround the lid portion 76A disposed so as to cover the semiconductor substrate 63 and the PD 51 and the charge holding portion 54. Buried portion 76B. That is, the cover 76A is formed substantially parallel to each layer constituting the pixel 50a, and the embedded portion 76B is formed to a predetermined depth so as to extend in a direction substantially orthogonal to the cover 76A. I have.

  Here, the buried portion 76 </ b> B of the light shielding portion 76 is formed in the inter-pixel separation region 75 so as to surround the PD 51 and the charge holding portion 54, and for example, forms the periphery of the charge holding portion 54. Or a structure formed between the PD 51 and the charge holding unit 54. That is, it is sufficient that the buried portion 76B is formed at least between the PD 51 and the charge holding portion 54, and the PD 51 and the charge holding portion 54 are separated by the buried portion 76B.

  The light-shielding portion 76 has an opening 76C for allowing light to enter the PD 51. That is, the opening 76 </ b> C is formed in a region corresponding to the PD 51, and the other regions, for example, the region where the charge holding unit 54 and the FD 55 are formed are shielded by the light shielding unit 76.

  Further, in the example shown in FIG. 2, the light shielding portion 76 is formed such that a part of the buried portion 76 </ b> B penetrates the semiconductor substrate 63. That is, the buried portion 76 </ b> B of the light shielding portion 76 penetrates the semiconductor substrate 63 in a region other than the region between the PD 51 and the charge holding portion 54, that is, in a region other than a region serving as a transfer path for transferring charges from the PD 51 to the charge holding portion 54. It is formed as follows.

  In other words, a region between the PD 51 and the charge holding unit 54 cannot be used as a light shielding unit because it is used for transferring charges. However, by forming the buried unit 76B outside the region, the same pixel 50a is formed. Of light from other than the PD 51 into the charge holding unit 54 can be effectively suppressed.

  In the color filter layer 65, a filter that transmits light of a corresponding color is disposed for each pixel 50a. For example, a filter that transmits green, blue, and red light is provided in a so-called Bayer array for each pixel 50a. Be placed. The on-chip lens 66 is a small lens for condensing incident light incident on the pixel 50a on the PD 51.

<Layout on semiconductor substrate>
FIG. 3 is a plan view when the pixel 50 shown in FIG. 2 is viewed from below (the lower side in FIG. 2). Since the present technology is particularly effective in a configuration in which a predetermined transistor is shared by a plurality of pixels, FIG. 3 is a plan view in the case where a predetermined transistor and the like are shared by four 2 × 2 pixels. In the plan views shown in FIG. 3 and subsequent drawings, the light-shielding portion 76 is not shown, but a penetrating light-shielding portion 76 and a non-penetrating light-shielding portion 76 are formed around the PD 56 and the charge holding portion 54. .

  FIG. 3 illustrates four pixels 50 a-1 to 50 a-4 arranged in the pixel array unit 41. The pixel 50a-1 is arranged at the upper left in the figure, the pixel 50a-2 is arranged at the lower left in the figure, the pixel 50a-3 is arranged at the upper right in the figure, and the pixel 50a-4 is arranged at the lower right in the figure. Are located. Since the pixels 50a have basically the same configuration, the description will be continued with the pixel 50a-1 arranged at the upper left in the drawing as an example.

  The OFD 121 is arranged on the lower left side of the pixel 50a-1. OFD121 represents a drain connected to the reset gate of PD51. The OFD 121 is connected to the PD 51 via the OFG gate 122.

  Above the PD 51, a charge holding unit 54 is arranged. When the pixel 50a is viewed from below (on the side of the wiring layer 61), a TRX gate 73 is arranged in a region where the charge holding unit 54 is arranged. The TRX gate 73 is provided to control the transfer of charges from the PD 51 to the charge holding unit 54.

  On the right side of the charge holding region 68 in the drawing, a floating diffusion region 125 (FD 125) is arranged via a TRX gate 73. The TRG gate 124 is provided to transfer charges from the charge holding unit 54 to the FD 125.

  The FD 125-1 is disposed between the pixel 50a-1 and the pixel 50a-3, and the FD 125-2 is disposed between the pixel 50a-2 and the pixel 50a-4. The FD 125-1 and the FD 125-2 are connected by the FD wiring 126. The FD 125-1 and the FD 125-2 function as one FD by being connected by the FD wiring 126. The FD 125-1 and FD 125-2 functioning as one FD are shared by the pixels 50a-1 to 50a-4.

  Between the pixel 50a-1 and the pixel 50a-3, a reset transistor 131 (described as RST in the drawing) and an amplification transistor 132 are arranged. Further, between the pixels 50a-2 and 50a-4, a selection transistor 133 (denoted as SEL in the drawing) is disposed. Although not shown in FIG. 3, a configuration in which the conversion efficiency switching transistor is disposed between the pixel 50a-2 and the pixel 50a-4 may be employed. The configuration having the conversion efficiency switching transistor will be described later. In addition, as shown in FIG. 3, when the configuration is such that the conversion efficiency switching transistor is not provided, a dummy may be arranged to ensure symmetry.

  In the example shown in FIG. 3, the four pixels 50a share a reset transistor 131, an amplification transistor 132, and a selection transistor 133.

  As described above, by using a structure in which a transistor is shared by a plurality of pixels, a region assigned to one transistor can be increased. Since the region allocated to one transistor can be widened, a structure in which the distance between the source and the drain of the transistor can be widened and a structure in which leakage is prevented can be performed.

  In addition, a structure in which a plurality of pixels share a transistor can be downsized.

  In the configuration of the shared pixel shown in FIG. 3, the reset transistor 131, the amplification transistor 132, and the selection transistor 133 are arranged in the vertical direction, and when the FD wiring 126 is set as a symmetric axis, the PD 51, the charge holding unit 54, the OFD 121 Are arranged symmetrically.

  The present technology can be applied to the left-right symmetric structure shown in FIG. 3 and also to the up-down symmetric structure shown in FIG. FIG. 4 is a plan view showing another example of the arrangement of the pixels 50. The pixel 50b-1 is arranged at the upper left in FIG. 4, the pixel 50b-2 is arranged at the lower left in the figure, the pixel 50b-3 is arranged at the upper right in the figure, and the pixel 50b-4 is arranged at the lower right in the figure. Is arranged.

  The FD125-1 is disposed between the pixel 50b-3 and the pixel 50b-4, the FD125-2 is disposed between the pixel 50b-1 and the pixel 50b-2, and the FD125-1 and the FD125-2 are connected to the FD wiring 126. Connected by The PD 51, the charge holding unit 54, the OFD 121, and the like are arranged vertically symmetrically with the FD wiring 126 as a symmetry axis.

  A reset transistor 131 and an amplification transistor 132 are arranged between the pixels 50b-3 and 50b-4, and a selection transistor 133 is arranged between the pixels 50b-1 and 50b-2. In the configuration of the shared pixel shown in FIG. 4, a reset transistor 131, an amplification transistor 132, and a selection transistor 133 are arranged in the horizontal direction in the figure.

  As shown in FIG. 4, the present technology can be applied to a case where pixels are vertically symmetrically arranged.

  Although the configuration shown in FIGS. 3 and 4 shows a case where a predetermined transistor and the like are shared by four pixels of 2 × 2, the configuration can be applied to a case where a predetermined transistor and the like are shared by two pixels.

  FIG. 5 is a plan view showing an example of the arrangement of the pixels 50c when two pixels are shared. The pixel 50c-1 is arranged on the left side in FIG. 5, and the pixel 50c-2 is arranged on the right side in the figure.

  An FD 125, a reset transistor 131, an amplification transistor 132, and a selection transistor 133 are arranged between the pixels 50c-1 and 50c-2 arranged in the horizontal direction in the drawing. The FD 125 and the amplification transistor 132 are connected by the FD wiring 126.

  The PD 51, the charge holding unit 54, the OFD 121, and the like are arranged symmetrically with respect to the FD wiring 126 using the FD wiring 126 as a symmetry axis. The present technology is a two-pixel sharing shown in FIG. 5 and can be applied to a left-right symmetric structure, and as shown in FIG. 6, can be applied to a two-pixel sharing and vertically symmetric structure.

  FIG. 6 is a plan view illustrating another example of the arrangement of the pixels 50. The pixel 50d-1 is arranged on the upper side in FIG. 6, and the pixel 50d-2 is arranged on the lower side in the figure. An FD 125, a reset transistor 131, an amplification transistor 132, and a selection transistor 133 are arranged between the pixels 50d-1 and 50d-2 arranged in the vertical direction in the figure. The FD 125 and the amplification transistor 132 are connected by the FD wiring 126.

  The PD 51, the charge holding unit 54, the OFD 121, and the like are arranged vertically symmetrically with the FD wiring 126 as a symmetry axis. The present technology is a two-pixel shared structure shown in FIG. 5 and can be applied to a left-right symmetric structure, and as shown in FIG. 6, a two-pixel shared and vertically symmetric structure can be applied.

  Further, in two-pixel sharing in which two pixels arranged in the vertical direction share a predetermined transistor or the like, a configuration in which the charge holding unit 54 is arranged at a position shifted by a half pitch with respect to the PD 51 may be adopted.

  FIG. 7 is a plan view showing another example of the arrangement of the pixels 50. The pixel 50e-1 is arranged on the upper side in FIG. 7, and the pixel 50e-2 is arranged on the lower side in the figure. In the arrangement example shown in FIG. 7, the OFD 121 and the OFG gate 122 are arranged on the lower right side of the pixel 50e-1.

  The charge holding unit 54 is disposed at the upper left side of the PD 51 and at a position shifted from the PD 51 by a half pitch. When the pixel 50e is viewed from below (on the side of the wiring layer 61), a TRX gate 73 is disposed in a region where the charge holding unit 54 is disposed. A TRG gate 124 is disposed above the center of the TRX gate 73 in the drawing. Further, an FD 125 is formed on the upper side of the center of the TRG gate 124 in the drawing.

  The pixel 50e-2 has the same configuration as the pixel 50e-1. The FD125-1 is arranged in the pixel 50e-1, and the FD125-2 is arranged in the pixel 50e-2. FD125-1 and FD125-2 are connected by FD wiring 126.

  A reset transistor 131 and an amplification transistor 132 are disposed between the pixel 50e-1 and the pixel 50e-2, and a selection transistor 133 is disposed above the pixel 50e-1 in the drawing. In the example illustrated in FIG. 7, the two pixels 50e share a reset transistor 131, an amplification transistor 132, and a selection transistor 133.

  When attention is paid to the pixel 50e-1, the destination where the charge accumulated in the PD 51 included in the pixel 50e-1 is transferred is below the TRX gate 73 arranged on the upper left side of the pixel 50e-1 in the drawing. This is the charge holding unit 54 that is formed. Similarly, when attention is paid to the pixel 50e-2, the destination to which the charge accumulated in the PD 51 included in the pixel 50e-2 is transferred is the TRX gate 73 arranged on the upper left side of the pixel 50e-2 in the drawing. This is the charge holding unit 54 formed below.

  The PD 51 and the charge holding unit 54 are arranged at positions shifted by a half pitch. By arranging the charge holding unit 54 at a position shifted by a half pitch with respect to the PD 51, the TRG gate 124 can be arranged at the center of the charge holding unit 54 (TRX gate 73). Since the TRG gate 124 is located at the center of the charge holding unit 54, the transfer length in the charge holding unit 54 can be shortened, and the transfer efficiency can be improved.

  FIG. 7 shows an example in which the long side of the PD 51 is arranged in the horizontal direction, the charge holding unit 54 is arranged on the long side of the PD 51, and is arranged at a position shifted by a half pitch, as shown in FIG. In addition, the present technology can be applied to a case where the long sides of the PD 51 are arranged in the vertical direction, the charge holding units 54 are arranged on the long sides of the PD 51, and are arranged at positions shifted by a half pitch.

  FIG. 8 is a plan view illustrating another example of the arrangement of the pixels 50. As in the arrangement example shown in FIG. 7, the pixels 50f-1 and 50f-2 are arranged in the vertical direction. In the arrangement example shown in FIG. 8, the OFD 121 and the OFG gate 122 are arranged below the pixel 50f.

  A charge holding unit 54 (TRX gate 73) is arranged at a position on the right side of the PD 51 in the figure, which is shifted by a half pitch from the PD 51. The TRG gate 124 is arranged on the right side of the center of the TRX gate 73 in the drawing. Further, an FD 125 is formed on the right side of the center of the TRG gate 124 in the drawing.

  The pixel 50f-2 has the same configuration as the pixel 50f-1. The FD125-1 is arranged in the pixel 50f-1, and the FD125-2 is arranged in the pixel 50f-2. FD125-1 and FD125-2 are connected by FD wiring 126.

  A configuration for boosting the FD described below can be applied to the configuration shown in FIGS. Although not shown in FIGS. 3 to 8, for example, the present invention can be applied to a configuration in which the FD 125 and the reset transistor 131 are shared by eight pixels, and the application of the present technology is shown in FIGS. 3 to 8. The description is not limited to the above configuration.

<Configuration for boosting FD>
The pixel 50 as described above has a global shutter structure in which the charge stored in the PD 51 is temporarily stored in the charge holding unit 54. A pixel having the charge holding unit 54 tends to have a smaller area that can contribute to securing the saturated charge amount (Qs), compared to a pixel having a structure without the charge holding unit 54. In a pixel including the charge holding unit 54, if the potential is deepened so as to secure the saturated charge amount, the dynamic range of the FD 125 may be secured and the pumping characteristics may be deteriorated.

  As described below, a wiring for boosting the FD 125 is arranged near the FD wiring 126, and by boosting the FD 125, a dynamic range of the FD 124 is secured and deterioration of the pumping characteristics is suppressed.

  In the following description, among the configurations of the pixel 50 shown in FIGS. 3 to 8, the configuration for boosting the FD 125 will be described by taking the configuration shown in FIG. 3 as an example.

  FIG. 9 is a diagram illustrating a four-pixel shared pixel structure having a configuration in which the FD 125 is boosted. In FIG. 9, the PD 51, the FD 125, and the FD wiring 126 are shown for explanation, but the TRX gate 73 and the like are also arranged as shown in FIG.

  The PD 51 and the FD 125 constituting the pixel 50 shown in FIG. 9 are formed in the semiconductor substrate 63 (FIG. 2). The FD wiring 126 connecting the FD 125-1 and the FD 125-2 is formed in the wiring layer 61. Here, the case where the FD wiring 126 is formed in the wiring layer 61-1 constituting the wiring layer 61 will be described as an example, and the description will be continued.

  When four pixels 50-1 to 50-4 are defined as one shared unit, two FDs 125 (two FD regions) are formed in the semiconductor substrate 63 in one shared unit, and the two FD regions are located at the bottom. It is configured to be connected by the FD wiring 126 formed in the stacked wiring layer 61-1. The FD 125 and the FD wiring 126 are connected by a via formed in the vertical direction (from the semiconductor substrate 63 to the wiring layer 61-1).

  As shown in FIG. 9, the FD boost wiring 301 is formed in parallel with the FD wiring 126. The FD boost wiring 301 is formed in the same layer as the FD wiring 126, that is, in this case, in the wiring layer 61-1. The FD boost wiring 301 is formed so as to have a portion that is at least partially parallel to the FD wiring 126.

  Although the FD wiring 126 and the FD boosting wiring 301 are shown in a linear shape for explanation in FIG. May be formed in a shape of a combination of straight lines having the angles of (a polygonal line), or may be formed in a shape other than a straight line, for example, a shape including an arc shape. An example of a specific layout will be described later.

  As shown in FIG. 9, at least a part is formed in a linear shape in which the FD wiring 126 and the FD boosting wiring 301 are parallel to each other. The portion of the FD boosting wiring 301 which is parallel and has a linear shape may be equal in length to the length of the FD wiring 126, may be formed short, or may be formed long. Is also good.

  The thickness of the FD boost wiring 301 may be equal to the thickness of the FD wiring 126, or may be formed to be thin or thick. As described above, the length, thickness, shape, and the like of the FD boost wiring 301 are appropriately designed according to the length, thickness, and shape of the FD wiring 126.

  Further, as shown in FIG. 9, one FD boosting wiring 301 can be formed on the right side of the FD wiring 126. As shown in FIG. 10, one FD boost wiring 301 is formed on the right side of the FD wiring 126 (referred to as FD boost wiring 301-1), and one is formed on the left side (referred to as FD boost wiring 301-2). Configuration. Hereinafter, when there is no need to individually distinguish the FD boost wiring 301-1 and the FD boost wiring 301-2, they are simply described as the FD boost wiring 301.

  As shown in FIG. 10, when the FD boost wiring 301-1 and the FD boost wiring 301-2 are formed on the left and right sides of the FD wiring 126, respectively, the FD boost wiring 301-1 and the FD boost wiring 301-2 are connected to the FD wiring. It is formed symmetrically with 126 as the axis of symmetry. In addition, it is also possible to make it formed asymmetrically. For example, an asymmetric configuration in which the FD boosting wiring 301-1 is formed on the upper right side of the FD wiring 126 and the FD boosting wiring 301-2 is formed on the lower left side of the FD wiring 126 may be used.

  Although the FD boost wirings 301-1 and 301-2 are illustrated in FIGS. 9 and 10 as being arranged at positions avoiding the FD 125 and the PD 51, they may be arranged at overlapping positions. However, the interval between the FD wiring 126 and the FD boosting wiring 301 is preferably within the range of 100 to 420 nm. When the interval is less than 100 nm, high precision is required when forming the FD wiring 126 and the FD boosting wiring 301, and it is difficult to form them.

  On the other hand, if the interval is 420 nm or more, it is difficult to appropriately boost the FD 125 even if the FD boosting wiring 301 is formed, or another wiring is provided between the FD wiring 126 and the FD boosting wiring 301. It may be difficult to properly boost the FD 125 because another wiring is formed between them.

  In addition, if 420 nm or more is provided between the FD wiring 126 and the FD boosting wiring 301 and no other wiring is formed between them, the miniaturization of the pixel will be hindered.

  Therefore, the interval between the FD wiring 126 and the FD boosting wiring 301 is formed in the range of 100 to 420 nm. It is to be noted that such numerical values are merely examples, and do not indicate limitations.

  The FD wiring 126 and the FD boost wiring 301 shown in FIGS. 9 and 10 are respectively formed in the wiring layer 61-1. In other words, the FD wiring 126 and the FD boosting wiring 301 are formed in the same layer. As shown in FIG. 11, the FD wiring 126 and the FD boosting wiring 301 can be formed in different layers.

  The upper part of FIG. 11 is an enlarged plan view of a portion of the FD wiring 126 in one shared unit of four pixels, and the lower part of FIG. 11 is a cross-sectional view taken along a line AA ′ in the plan view. It is. As in the case described above, the FD 125-1 and the FD 125-2 are connected by the FD wiring 126. The FD wiring 126 is formed on the wiring layer 61-1 as shown in the figure below.

  The FD wiring 126 is formed on the wiring layer 61-1, and the FD boosting wiring 301-3 is formed on the wiring layer 61-2 laminated immediately below the wiring layer 61-1. The relationship between the FD wiring 126 and the FD boost wiring 301-3 is the same as the relationship between the FD wiring 126 and the FD boost wiring 301-1 (or the FD boost wiring 301-2). That is, at least a part is formed in a linear shape in which the FD wiring 126 and the FD boosting wiring 301-3 are parallel to each other.

  The portion of the FD boost wiring 301-3 which is parallel and has a linear shape may have a length equal to the length of the FD wiring 126, may be formed short, or may be formed long. May be. The thickness of the FD boosting wiring 301-3 may be equal to the thickness of the FD wiring 126, or may be formed to be thin or thick. As described above, the length, thickness, shape, and the like of the FD boost wiring 301 are appropriately designed according to the length, thickness, and shape of the FD wiring 126.

  As illustrated in FIG. 11, by forming the FD wiring 126 and the FD boosting wiring 301-3 in different layers, the FD boosting wiring 301-3 can have a structure also serving as a shield to the FD wiring 126. .

  As shown in FIGS. 9 to 11, an FD boosting wiring 301 for boosting the FD 125 is formed in the same layer or a different layer from the FD wiring 126 and in the vicinity of the FD wiring 126.

  Note that here, the FD wiring 126 is described as the FD wiring 126 and the FD wiring 126 is a wiring, but the FD wiring 126 itself also has a function of accumulating charges transferred from the PD 51, Functions as FD125. Therefore, although the FD wiring 126 is described, the FD wiring 126 is not a simple wiring, and the FD wiring 126 also forms a part of the FD 125.

  That is, according to the present technology, the FD boosting wiring 301 for boosting the FD 125 is formed near the FD 125 near the FD 125. Here, when the FD 125 is shared between the pixels, the FD regions are formed in different regions of the semiconductor substrate 63 and connected by wiring, so that the FD boost wiring 126 is formed near the wiring (FD wiring 126). Examples have been given.

  Further, as shown in FIG. 12, a configuration can be employed in which the FD boost wiring 126 is connected to a part of the amplification transistor 132 to which the FD 125 is connected. Referring to the pixel of one sharing unit shown in FIG. 12, an FD boost wiring 301-4 is formed so as to be connected to the amplification transistor 132 shared by the pixels 50-1 to 50-4.

  The amplification transistor gate, which is a part of the amplification transistor 132, is formed in the wiring layer 61-1. FD boost wiring 301-4 is formed so as to be connected to the gate of the amplification transistor. The FD boost wiring 301-4 may have a line shape. Alternatively, it is formed so as to be in contact with the amplification transistor gate at a point, for example, a via, to be connected to the wiring connected to the FD boosting power supply provided in another layer, and to be connected to the amplification transistor gate at the point. The FD boosting wiring 301-4 may be used as the part where the FD voltage is increased.

  Here, a circuit diagram of one pixel 50 is shown in FIG. 13, and a description will be added that the FD 125 can be boosted by configuring the FD boost wiring 301-4 to be in contact with the amplification transistor gate.

  The pixel 50 includes a PD 51, a first transfer transistor 73 (a transfer transistor including a TRX gate 73), a charge holding unit 54, a second transfer transistor 124 (a transfer transistor including a TRG gate 124), an FD 125, and an amplifying transistor 132. A transistor 133, a reset transistor 131, and a discharge transistor 121 (OFG 121) are provided.

  The PD 51 is a photoelectric conversion unit that converts incident light into electric charges by photoelectric conversion and accumulates the charges, and has an anode terminal grounded and a cathode terminal connected to the first transfer transistor 73 and the discharge transistor 121. .

  The first transfer transistor 73 is driven according to the transfer signal TRX supplied from the vertical drive circuit 13, and when the first transfer transistor 73 is turned on, the charge stored in the PD 51 is transferred to the charge holding unit 54. .

  The charge holding unit 54 temporarily holds the charge transferred from the PD 51 via the first transfer transistor 73.

  The second transfer transistor 124 is driven according to a transfer signal TRG supplied from the vertical drive circuit 13, and when the second transfer transistor 124 is turned on, the charge stored in the charge holding unit 54 is transferred to the FD 125. .

  The FD 125 is a floating diffusion region having a predetermined storage capacitance connected to the gate electrode of the amplification transistor 132 and stores the charge transferred from the charge holding unit 54.

  The amplification transistor 132 outputs a pixel signal of a level (that is, the potential of the FD 125) corresponding to the charge stored in the FD 125 to the vertical signal line 47 via the selection transistor 133. That is, with the configuration in which the FD 125 is connected to the gate electrode of the amplification transistor 132, the FD 125 and the amplification transistor 132 function as a conversion unit that converts the charge generated in the PD 51 into a pixel signal of a level corresponding to the charge.

  The selection transistor 133 is driven according to a selection signal SEL supplied from the vertical driving unit 42 (FIG. 1). When the selection transistor 133 is turned on, a pixel signal output from the amplification transistor 132 can be output to the vertical signal line 47. State.

  The reset transistor 131 is driven according to a reset signal RST supplied from the vertical drive unit 42. When the reset transistor 131 is turned on, the electric charge accumulated in the FD 125 is discharged to the reset power supply Vrst, and the FD 125 is reset.

  The discharge transistor 121 is arranged in series between the PD 51 and the overflow drain OFD (discharge unit). Further, the discharge transistor 121 is driven according to a discharge signal OFG supplied from the vertical drive unit 42.

  As described above, the FD 125 is connected to the gate electrode of the amplification transistor 132. Accordingly, the FD 125 is boosted by connecting the FD boost wiring 301-4 to a portion connected to the gate electrode of the amplification transistor 132 or a part of the wiring connecting the FD 125 and the gate electrode of the amplification transistor 132. be able to.

  If any one of the FD boost wirings 301-1 to 301-4 shown in FIGS. 9 to 13 is formed, a configuration in which the FD 125 is boosted can be employed. Further, a plurality of FD boost wirings 301-1 to 301-4 may be formed. For example, as illustrated in FIG. 10, a pixel in which the FD boost wiring 301-1 and the FD boost wiring 301-2 are formed, or a pixel in which the FD 301-3 is formed may be used. it can.

  Further, a structure including one or more of the FD boost wirings 301-1 to 301-3 and the FD boost wiring 301-4 connected to the gate electrode of the amplification transistor 132 may be employed.

  With the provision of the plurality of FD boost wirings 301, a configuration can be provided in which the FD 125 can be boosted more efficiently.

  The FD boost wiring 301 is formed in another layer (in the case of the configuration shown in FIG. 2, any of the wiring layers 61-2 to 61-4) and connected to a voltage source that supplies a predetermined voltage. Connected to the wiring. The timing at which a voltage is applied to the FD boost wiring 301 will be described with reference to the timing chart of FIG.

  In FIG. 14, a control signal that is turned on (High) when a voltage is applied to the FD boost wiring 301 is represented as a signal FDB, and a control signal that is turned on (High) when the second transfer transistor 124 transfers electric charge. Is a signal TRG, a control signal turned on (High) when the reset transistor 131 performs a reset operation is expressed as a signal RST, and a control signal turned on (High) when the selection transistor 133 is selected is a signal TRG. Expressed as SEL.

  In the read operation for the pixel 50, unnecessary charges are swept out (reset) from the photoelectric conversion elements of the unit pixels in the readout row. At the time of this reset operation, the signal SEL is set to a high state, and the signal RST is set to a high state for a predetermined time. By the reset operation, a noise signal is obtained.

  After the noise signal is obtained, exposure is started, and charges are accumulated in the PD 51. Although not shown in FIG. 14, after the exposure is completed, the charge is transferred from the PD 51 to the charge holding unit 54, and the charge is accumulated in the charge holding unit 54. The transfer of the charge from the PD 51 to the charge holding unit 54 is performed simultaneously for all the pixels, thereby realizing a global shutter.

  When transferring the charge accumulated in the charge holding unit 54 to the FD 125, the signal TRG for controlling the second transfer transistor 124 is set to High, and the signal FOB for controlling the voltage to the FD boost wiring 301 is set to High. When charge is transferred from the charge holding unit 54 to the FD 125 by the operation of the second transfer transistor 124, a voltage is applied to the FD boost wiring 301, so that the FD 125 is boosted.

  At a time point shortly after the signal TRG is returned to the low state, the signal FOB is returned to the low state. The charge transferred to the FD 125 is supplied to the column processing unit 43 (FIG. 1) as a data signal via the vertical signal line 47. The pixel value of the pixel 50 is calculated by executing processing such as removal of a noise signal from the data signal in the column processing unit 43.

  As described above, when charges are transferred to the FD 125, a voltage is applied to the FD boost wiring 301, and the FD 125 is boosted. Therefore, according to the present technology, it is possible to secure the boost amount and increase the conversion efficiency. It is also effective in securing a dynamic range and reducing noise.

<When applied to a vertical transistor>
In the pixel 50 including the above-described FD boost wiring 301, a transistor that performs reading can be configured as a vertical transistor. FIG. 15 is a cross-sectional view of the pixel 50 in a case where the second transfer transistor 124 that reads out charges from the charge holding unit 54 is formed of a vertical transistor.

  The pixel 50 shown in FIG. 15 is different from the pixel 50 shown in FIG. 2 in that a vertical transistor is added, and the other parts are the same. The read gate 331 constituting the second transfer transistor 124 is formed up to a position reaching the inside of the charge holding unit 54. That is, the readout gate 331 for reading out the charge from the charge holding portion 54 is formed in the vertical direction and the horizontal direction with respect to the charge holding portion 54, and the readout gate 331 formed in the vertical direction is in contact with the charge holding portion 54. Is formed.

  By using such a vertical transistor, the modulation power can be improved and the potential can be deepened. On the other hand, when the FD boosting wiring 301 is not formed and the FD 125 is not boosted, the pumping from the FD 125 may be weak. This will be described with reference to FIG.

  16, FD represents the FD 125, TRG represents the second transfer transistor 124, MEM represents the charge holding unit 54, and PD represents the PD 51. FIG. 16A illustrates a change in potential when the second transfer transistor 124 is not a vertical transistor, and FIG. 16B illustrates a change in potential when the second transfer transistor 124 is a vertical transistor. 16C shows a change in potential when the second transfer transistor 124 is a vertical transistor and boosting by the FD boosting wiring 301 is performed.

  Referring to FIG. 16A, at time T1, the second transfer transistor 124 and the charge holding unit 54 are in a low state. At time T2, when the second transfer transistor 124 is set to the high state, the potential under the gate of the second transfer transistor 124 becomes shallow, but a barrier is generated, and the charge from the charge holding unit 54 to the FD 125 is reduced. Transfers can be hindered.

  Referring to FIG. 16B, the second transfer transistor 124 and the charge holding unit 54 are in the low state, similarly to the time T1 in FIG. 16A. At the time T2, when the second transfer transistor 124 is set to a high state, the modulation power is improved and a barrier-free state can be obtained because the transistor is a vertical transistor. However, there is a possibility that the charge may be left under the gate and deep under the gate.

  Referring to FIG. 16C, when the second transfer transistor 124 and the charge holding unit 54 are in the low state, as in the case of the time T1 in FIG. 16A, predetermined charges are accumulated in the FD 125. In the state in which the second transfer transistor 124 is in the high state and the voltage is applied to the FD boosting wiring 301 at time T2, the FD 125 is boosted. When the FD 125 is boosted, the potential of the FD 125 is deepened. Therefore, as in the case of the time T2 in FIG. 16B, even if the area under the gate is deepened, the FD 125 can be further deepened, thereby preventing a situation in which charges remain under the gate. Can be.

  As described above, even when a vertical transistor is used, the FD boost wiring 301 is formed and the FD 125 is boosted, so that the boost amount and the conversion efficiency can be secured, the dynamic range can be secured, and the noise can be reduced. Can be reduced.

<When applied to reading by CCD method>
The present invention can be applied to an image sensor that reads out the pixel 50 including the above-described FD boost wiring 301 by a CCD method. The reading by the CCD method is a method of reading out the electric charges (signals) accumulated in the PD 51 by moving electric charges one after another by using electric coupling between adjacent elements.

  FIG. 17 is a diagram for explaining a change in potential at the time of reading by the CCD method. In the example shown in FIG. 17, two charge holding portions 54 (denoted by MEM in the drawing) are formed, and the charges are discharged in the order of the PD 51, the first charge holding portion 54, the second charge holding portion 54, and the FD 125. This shows the case of moving. At time T1, when the first charge holding unit 54, the second charge holding unit 54, and the second transfer transistor 124 are in a low state, predetermined charges are accumulated in the FD 125.

  In such a state, when the second charge holding unit 54 and the second transfer transistor 124 are set to the high state at the time T2, the potential of the second charge holding unit 54 is deeper than that of the FD 125. Become. When such a state occurs, charges may flow backward from the FD 125 to the second charge holding unit 54.

  At time T3 after time T2, the second charge holding unit 54 is returned to the low state, and the second transfer transistor 124 is maintained at the high state. At this time, when a voltage is applied to the FD boosting wiring 301, the FD 125 is boosted, so that the potential of the FD 125 can be made deeper than the potential of the charge holding unit 54.

  In order to prevent the charge from flowing backward, the FD 125 is boosted to have a potential deeper than that of the charge holding unit 54. The structure in which the above-described FD boosting wiring 301 is formed can cope with the boosting of the FD 125.

  Therefore, by applying the present technology also to reading by the CCD method, it is possible to secure a boosting amount and increase conversion efficiency, secure a dynamic range, and reduce noise.

  The operation of the pixel 50 to which the vertical transistor and the CCD method are applied will be described with reference to FIG.

  FIG. 18A shows the timing of the high and low states of each control signal when transferring the charge from the PD 51 to the charge holding unit 54, and FIG. 18B shows the charge from the charge holding unit 54 to the FD 125. It shows the timing of the High and Low states of each control signal when transferring. 18, FOB, TRG, RST, and SEL are the same as those in FIG. In FIG. 18, TRX is a control signal for controlling the first transfer transistor 73, and represents a control signal that is turned on (High) when the charge is transferred from the PD 51 to the charge holding unit 54.

  Referring to FIG. 18A, the FD 125 is reset by setting the signal TRG and the signal RST to a high state. After the reset, the signal FOB, the signal TRX, and the signal TRG are set to a high state, so that a predetermined voltage is applied to the FD boosting wiring 301 and the FD 125 is boosted, and the signal from the PD 51 to the charge holding unit 54 is increased. The transfer of the charge is performed, and the transfer of the charge from the charge holding unit 54 to the FB 125 is performed.

  Since reading of charges from the PD 51 to the charge holding unit 54 is performed simultaneously for all pixels, the signal SEL remains in a low state. Referring to FIG. 18B, since the charge stored in the charge storage unit 54 is sequentially transferred for each pixel, the signal SEL to the selection transistor 133 of the pixel to be read is in a high state. To be. When the signal SEL is set to the high state, the signal RST is also set to the high state, and the reset transistor 131 is turned on for a certain period.

  When the charge is transferred from the charge holding unit 54 to the FD 125, the signal FOB, the signal TRX, and the signal TRG are set to a high state. Therefore, a predetermined voltage is applied to the FD boost wiring 301, and the charge is transferred from the PD 51 to the charge holding unit 54 while the FD 125 is boosted, and the charge is transferred from the charge holding unit 54 to the FB 125. Will be

  By repeating such operations sequentially, the charges accumulated in the PD 51 are sequentially transferred to the charge holding unit 54 and the FD 125. In addition, when the charge is transferred, the FD 125 is boosted, so that it is possible to secure the boosting amount, increase the conversion efficiency, secure the dynamic range, and reduce the noise.

  When it is desired to suppress the pumping at the time of reset, the reset operation may be performed after a floating state is once created. When the CCD method is applied to the vertical transistor, a voltage is applied to the FD boost wiring 301 once at a timing when the FD 125 becomes a floating state so as to boost the FD 125 in order to completely reset the charge holding unit 54. good.

<Specific wiring shape>
Hereinafter, examples of specific shapes of the FD wiring 126 and the FD boosting wiring 301 will be described. As described above, the shape and the arrangement position of the FD boosting wiring 301 are set according to the arrangement of the PD 51 and the charge holding unit 54 and the relation with other wirings. Therefore, a specific example of the arrangement and shape of the PD 51, the charge holding unit 54, and other wirings will be described below, and the shape and arrangement position of the FD boosting wiring 301 will be described.

  FIG. 19 is a plan view of the semiconductor substrate 63, showing a specific example of the arrangement position and shape of the PD 51 and the like. FIG. 20 is a circuit diagram corresponding to the configuration shown in FIG. FIG. 19 is a diagram when four pixels arranged in 2 × 2 are set as one sharing unit. Pixel 50-0 is arranged at the lower left, pixel 50-1 is arranged at the lower right, pixel 50-2 is arranged at the upper left, and pixel 50-3 is arranged at the upper right.

  The pixel 50-1 includes the PD2. 19 to 24, common reference numerals are used, and reference numerals different from the reference numerals used in the above description are given so that connection relations such as wiring of each layer can be easily understood. PD0 included in the pixel 50-0 corresponds to the PD51 in the above description. Similarly, the other parts are the same as those described above except for the reference numerals, and the description thereof will be appropriately omitted.

  OFG and OFG are formed on the left side of PD0 of the pixel 50-0, and TRY0, TRX0, and TRG0 are formed on the upper side. Although not shown in FIG. 19, MEM0 (corresponding to the charge holding unit 54) is formed in a region where TRY0 and TRX0 are formed.

  The PD0, OFD, OFG, PD0, TRY0, TRX0, TRG0, and MEM0 formed in the pixel 50-0 are connected as shown in the circuit diagram of FIG. The circuit configuration of one pixel has been described with reference to FIG. 13 and will not be described here.

  In the configuration shown in FIGS. 19 and 20, TRY0 is added. TRY0 functions as a gate for preventing charge from flowing back from the charge holding unit 54 to the PD 51 (MEM0 to PD0 in the pixel 50-0 shown in FIGS. 19 and 20), and is shown in FIGS. As described above, it is provided between PD0 and TRX0.

  TRY0 (which is appropriately described as a third transfer transistor) is provided, and TRY0 is turned on when transferring charges from PD0 to MEM0, and then turned off so that charges do not flow back to PD0. The backflow of charges can be prevented.

  Further, TRY0 can be configured to have a memory function of accumulating charges. As shown in the circuit diagram of FIG. 20, MEM0 is formed between TRY0 and TRX0 and between TRX0 and TRG0. The charge holding unit 54 is formed of two charge holding units 54, one of which is formed between TRY0 and TRX0, and can have a memory function of TRY0.

  Similarly to the pixel 50-0, the pixel 50-1 is formed with PD1, OFD, OFG, TRY0, TRX1, TRG1, and MEM1. In the pixel 50-2, PD2, OFD, OFG, TRY1, TRX2, TRG2, and MEM2 are formed. In the pixel 50-3, PD3, OFD, OFG, TRY1, TRX3, TRG3, and MEM3 are formed.

  Similarly to the case described with reference to FIG. 3 and the like, the arrangement of the PD and the like shown in FIG. 19 is such that the pixels arranged on the left and right, for example, the pixel 50-0 and the pixel 50-1 are symmetrical. The pixels arranged vertically, for example, the pixel 50-0 and the pixel 50-2 are arranged to have periodic symmetry.

  The periodic symmetry refers to, for example, one pixel such that TRX0 is arranged above PD0 in the pixel 50-0, and TRX2 is similarly arranged above PD2 in the pixel 50-2. Means that the same thing is arranged at the same position when viewed within.

  Further, as shown in FIG. 19, SEL (corresponding to the selection transistor 133) and FD (corresponding to FD125) are formed between the pixel 50-0 and the pixel 50-1. An AMP (corresponding to the amplification transistor 132), an RST (corresponding to the reset transistor 131), and an FD are formed between the pixel 50-2 and the pixel 50-3.

  Since SEL, FD, AMP, and RST are shared by the pixels 50-0 to 50-3, TRG0, TRG1, TRG2, and TRG3 are connected to FD and AMP as shown in FIG. . The circuit diagram shown in FIG. 20 shows a configuration when eight VSLs (corresponding to the vertical signal lines 47) are simultaneously read. That is, as shown in FIG. 20, eight VSLs are formed, and one of the VSLs is connected to the SEL.

  Here, for example, TRY0 is formed in each of the pixels 50-0 and 50-1, but TRY0 of the pixel 50-0 and TRY0 of the pixel 50-1 are connected to a TRY0 wiring (FIG. 23) described later. ing. That is, TRYs connected to the same wiring are given the same reference numerals (in the case of TRY0, 0 corresponds to the reference numeral). The other parts are the same.

  FIG. 21 is a diagram illustrating an arrangement and a shape of wirings and the like wired in the wiring layer 61-1 laminated on the semiconductor substrate 63 illustrated in FIG. In the wiring layer 61-1, a light-shielding film made of, for example, a metal is formed at the position of the PD formed on the semiconductor substrate 63.

  Further, for example, in the portion of the semiconductor substrate 63 shown in FIG. 19 where the TRY0 of the pixel 50-0 is formed, the gate of the TRY0 is formed in the wiring layer 61-1. Similarly, in the wiring layer 61-1, a gate of the TRX0 is formed in a portion where the TRX0 of the pixel 50-0 of the semiconductor substrate 63 shown in FIG. 19 is formed. In the wiring layer 61-1, the gate of the TRG0 is formed in the portion of the semiconductor substrate 63 shown in FIG. 19 where the TRG0 of the pixel 50-0 is formed.

  In the wiring layer 61-1, gates for TRY, TRX, and TRG formed in the other pixels 50-1 to 50-3 are also formed at corresponding positions. The gates of the selection transistor (SEL), the amplification transistor (AMP), and the reset transistor (RST) are also formed in the wiring layer 61-1.

  Further, the FD wiring 126 connecting the FD formed on the semiconductor substrate 63 is also formed on the wiring layer 61-1. The FD wiring 126 (a line described as FD in the drawing) is, for example, shown in FIG. 3 as an example in which the FD wiring 126 is formed in a linear shape. It is formed so as to connect the FD formed at the upper part and the FD formed at the lower part in the figure.

  The FD wiring 126 shown in FIG. 21 has a pattern formed so as to avoid the VDD wiring connected to the AMP. The VDD wiring is connected to a via described as VDD formed above AMP in FIG. As described above, in the patterns such as the PD and the wiring illustrated in FIGS. 19 and 21, the FD wiring 126 is formed in a shape that partially bypasses the other wiring in relation to the other wiring.

  The FD boost wiring 301 (the line described as FDB in the drawing) is formed near and parallel to the FD wiring 126. The FD boost wiring 301 is formed so as to have a part at least partially parallel to the FD wiring 126.

  FIG. 22 is a diagram illustrating an arrangement and a shape of wirings and the like wired on the wiring layer 61-2 laminated on the wiring layer 61-1 illustrated in FIG. The wiring for connecting the wiring formed in the wiring layer 61-1 to the wiring of the wiring layer 61-3 or the wiring layer 61-4 is formed in the wiring layer 61-2.

  Since the example shown in FIG. 22 shows a case where the FD boosting wiring 301-3 is formed in another layer described with reference to FIG. 11, the FD boosting wiring 301 (see FIG. In the figure, a line described as FDB) is formed. That is, the examples shown in FIGS. 21 and 22 are configured to include the FD boosting wiring 301-1 described with reference to FIG. 9 and the FD boosting wiring 301-3 described with reference to FIG. Is shown.

  As described with reference to FIG. 11, the FD boost wiring 301 formed in the wiring layer 61-2 different from the wiring layer 61-1 in which the FD wiring 126 is formed has substantially the same position as the FD wiring 126. Are formed in substantially the same shape.

  FIG. 23 is a diagram illustrating an arrangement and a shape of wirings and the like wired in the wiring layer 61-3 stacked on the wiring layer 61-2 illustrated in FIG. A signal line through which a control signal flows is formed in the wiring layer 61-3.

  In the wiring layer 61-3 shown in FIG. 23, control signal lines are formed in a linear shape in the horizontal direction in the figure. The upper part in the figure is connected to the OFD regions formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22) by vertical vias. The signal line OFD is formed.

  TRG3 regions (gates) formed on the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22) are provided below the OFD signal line in the drawing. And a signal line TRG3 connected by a vertical via is formed. The signal line TRG3 is a signal line through which a signal for controlling the second transfer transistor (TRG3) of the pixel 50-3 (FIG. 19) flows.

  Below the signal line TRG3 in the drawing, TRG2 regions (gates) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22), respectively. And a signal line TRG2 connected by a vertical via is formed. The signal line TRG2 is a signal line through which a signal for controlling the second transfer transistor (TRG2) of the pixel 50-2 (FIG. 19) flows.

  On the lower side of the signal line TRG2 in the drawing, TRX3 regions (gates) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22), respectively. And a signal line TRX3 connected by a vertical via is formed. The signal line TRX3 is a signal line through which a signal for controlling the first transfer transistor (TRX3) of the pixel 50-3 (FIG. 19) flows.

  On the lower side of the signal line TRX3 in the drawing, TRX2 regions (gates) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22), respectively. And a signal line TRX2 connected by a vertical via is formed. The signal line TRX2 is a signal line through which a signal for controlling the first transfer transistor (TRX2) of the pixel 50-2 (FIG. 19) flows.

  Below the signal line TRX2 in the figure, the TRY1 region (gate) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22), respectively. And a signal line TRY1 connected by a vertical via is formed. The signal line TRY1 is a signal line for passing a signal for controlling the third transfer transistor (TRY1) of the pixel 50-3 and the pixel 50-2 (FIG. 19).

  RST regions (gates) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22) are provided below the signal line TRY1 in the drawing. And a signal line RST connected by a vertical via is formed. The signal line RST is a signal line for passing a signal for controlling the reset transistor (RST) shared by the pixels 50-0 to 50-4 (FIG. 19).

  VDD regions (wirings) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22) are provided below the signal line RST in the drawing. And a signal line VDD connected by a vertical via is formed. The signal line VDD is a signal line that supplies a predetermined voltage VDD to a predetermined portion of the pixels 50-0 to 50-4 (FIG. 19).

  Below the signal line VDD in the drawing, FDB regions (wirings) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22), respectively. And a signal line FDB connected by a vertical via is formed. The signal line FDB is a signal line that supplies a predetermined voltage to the FD boost wiring 301 (FDB).

  The wirings so far (the wirings in the upper half in the drawing) are mainly signal lines related to the pixels 50-2 and 50-3 arranged in the upper part of the 2 × 2 four pixels. This is a signal line related to a transistor disposed between the pixel 50-2 and the pixel 50-3.

  In the lower side of the signal line FDB in the drawing, the VSS regions (comparatively formed) in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22) are formed. And a signal line VSS connected by a vertical via is formed. The signal line VSS is a signal line that supplies a predetermined voltage VSS to a predetermined portion of the pixels 50-0 to 50-4 (FIG. 19). Note that the voltage VDD is a positive voltage and the voltage VSS is a negative voltage.

  TRG1 regions (gates) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22) are provided below the signal line VSS in the figure. And a signal line TRG1 connected by a vertical via is formed. The signal line TRG1 is a signal line through which a signal for controlling the second transfer transistor (TRG1) of the pixel 50-1 (FIG. 19) flows.

  Below the signal line TRG1 in the drawing, TRG0 regions (gates) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22), respectively. And a signal line TRG0 connected by a vertical via is formed. The signal line TRG0 is a signal line through which a signal for controlling the second transfer transistor (TRG0) of the pixel 50-0 (FIG. 19) flows.

  TRX1 regions (gates) formed on the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22) are provided below the signal line TRG0 in the drawing. And a signal line TRX1 connected by a vertical via is formed. The signal line TRX1 is a signal line through which a signal for controlling the first transfer transistor (TRX1) of the pixel 50-1 (FIG. 19) flows.

  On the lower side of the signal line TRX1 in the drawing, TRX0 regions (gates) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22), respectively. And a signal line TRX0 connected by a vertical via is formed. The signal line TRX0 is a signal line for passing a signal for controlling the first transfer transistor (TRX0) of the pixel 50-0 (FIG. 19).

  Below the signal line TRX0 in the figure, the TRY0 region (gate) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22), respectively. And a signal line TRY0 connected by a vertical via is formed. The signal line TRY0 is a signal line for passing a signal for controlling the third transfer transistor (TRY0) of the pixel 50-1 and the pixel 50-0 (FIG. 19).

  On the lower side of the signal line TRY0 in the figure, OFG regions formed respectively in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22), A signal line OFG connected by a mold via is formed.

  SEL regions (gates) formed in the semiconductor substrate 63 (FIG. 19), the wiring layer 61-1 (FIG. 21), and the wiring layer 61-2 (FIG. 22) are provided below the signal line OFG in the drawing. And a signal line SEL connected by a vertical via is formed. The signal line SEL is a signal line for passing a signal for controlling the selection transistor (SEL) shared by the pixels 50-0 to 50-4 (FIG. 19).

  The wiring in the lower half of the figure is a signal line mainly related to the lower pixel 50-1 and the lower pixel 50-0 of the 2 × 2 four pixels. This is a signal line related to the transistor arranged between 50-0.

  Thus, signal lines are formed in the wiring layer 61-3.

  Here, when attention is paid to the signal line FDB wired in the wiring layer 61-3 shown in FIG. 23 and the FD wiring 126 (FD boosting wiring 301), a case where the signal line FDB and the FD wiring 126 are orthogonal to each other The structure may be parallel to the above.

  Since the FD wiring 126 shown in FIGS. 3, 5, 7, and 8 is formed in the vertical direction in the figure, in the pixel employing these structures, it is formed in the horizontal direction in FIG. And the signal line FDB. In this case, since the FD boost wiring 301 is also formed in the same direction as the FD wiring 126, the FD boost wiring 301 and the signal line FDB also have a structure orthogonal to each other.

  On the other hand, since the FD wiring 126 shown in FIGS. 4 and 6 is formed in the horizontal direction in the drawing, in the pixel employing these structures, the signal line formed in the horizontal direction in FIG. The structure is parallel to the FDB. In this case, since the FD boost wiring 301 is also formed in the same direction as the FD wiring 126, the FD boost wiring 301 and the signal line FDB also have a parallel structure.

  FIG. 24 is a diagram showing the arrangement and shape of the wiring and the like wired in the wiring layer 61-4 laminated on the wiring layer 61-3 shown in FIG. Vertical signal lines are formed in the wiring layer 61-4.

  As described with reference to the circuit diagram of FIG. 20, when eight vertical signal lines are formed, the vertical signal lines VSL0 to VSL7 are formed in the wiring layer 61-4 in the vertical direction in the drawing. . Referring to FIG. 19 again, a via VSLout for outputting an output from the selection transistor to the vertical signal line is formed below the selection transistor (SEL), and this via VSLout is formed in the wiring layer 61-2 (FIG. 22). ) Is connected to the signal line VSL of the wiring layer 61-3 (FIG. 23) via a wiring described as VSL.

  The signal line VSL of the wiring layer 61-3 is formed below the signal line SEL, and is formed in a horizontal linear shape like other signal lines. This signal line VLS is connected to any one of the vertical signal lines VSL0 to VSL7 of the wiring layer 61-4 by a via.

  The positions and shapes of the wirings described above are merely examples, and do not limit the description.

  In the examples shown in FIGS. 19 to 23, TRY as the third transfer transistor has TRY0 formed in each of the pixels 50-0 and 50-1. This TRY0 is connected to one signal line TRY0. ing. TRY1 is formed in each of the pixels 50-2 and 50-3, and this TRY1 is connected to one signal line TRY1.

  The third transfer transistor (TRY) is a transistor used when transferring charges from the PD 51 (PD0 to PD3) to the charge holding unit 54 (MEM0 to MEM3). In the case of the global shutter method, the operation from the PD 51 to the charge holding unit 54 is performed simultaneously for all pixels. Therefore, the control of the third transfer transistor (TRY) can be performed by the same control for all pixels. If the same control is applied to all the pixels, a configuration in which a signal line TRY shared by all the pixels is formed is also possible.

  As described above, the pixels arranged in the horizontal direction, for example, in the example shown in FIG. 19, the pixel 50-0 and the pixel 50-1 share the signal line TRY0, and the pixel 50-2 and the pixel 50-3. With the configuration sharing the signal line TRY1, the same control can be performed on the pixels 50 arranged in the horizontal direction, and different control can be performed on the pixels 50 arranged in the vertical direction. It becomes possible.

  By enabling such operations, it becomes possible to perform read control for each row. It is also possible to perform control such as changing the exposure time for each row. Note that, as described above, a configuration in which the signal line TRY shared by all the pixels is formed is also possible. By using the signal line TRY shared by all the pixels, the number of signal lines can be reduced. Can be. Therefore, when a small space is required, the signal line TRY may be configured to be shared in both the horizontal direction and the vertical direction.

<When a vertical transistor is applied>
As described with reference to FIGS. 15 and 16, the modulation power is read by reading out the transistor from which the charge is read from the charge holding unit 54 by using the vertical transistor having the gate reaching the inside of the silicon substrate. Reading can be performed with the potential improved and the potential deepened.

  Such a vertical transistor can be applied to reading from a photodiode (PD), and by applying to reading from a PD, the modulation power can be improved and the potential can be deepened even in the reading. The reading can be performed in the state in which the reading is performed.

  With reference to FIGS. 25 and 26, a structure of the pixel 50 in the case where a vertical transistor is applied to reading from a PD will be described. FIG. 25 is the same as the plan view of the semiconductor substrate 63 shown in FIG. 19, except that a line segment ABC is added to the pixel 50-3. FIG. 26 is a cross-sectional view taken along the line ABC.

  Referring to FIGS. 25 and 26, FD, TRG3, TRX3, TRY1, and PD3 are arranged in order from the point A side in the portion of the line segment ABC. Note that FD, TRG3, TRX3, TRY1, and PD3 use the same reference numerals as those shown in FIGS.

  A TRG3 is formed between the FD and the MEM3, and the TRG3 is formed by a vertical transistor. As described with reference to FIG. 15, the vertical transistor is formed in the vertical direction and the horizontal direction with respect to the MEM3, and the portion formed in the vertical direction is formed by digging into silicon. .

  Similarly, TRY1 is formed between PD3 and MEM3, and this TRY1 is formed of a vertical transistor, is formed vertically and horizontally with respect to MEM3, and is formed vertically. The portion is formed by being dug into silicon.

  TRY1 is a transistor used when transferring charges from PD3 to MEM3. By configuring TRY1 with a vertical transistor, charges can be read from PD3 in a state where the modulation power is improved and the potential is deepened.

  As described above, the transistor (TRY) for reading from the PD3 (photodiode 51) and the transistor (TRG) for reading from the MEM3 (charge holding unit 54) are each configured by a vertical transistor, so that Reading from the diode 51 and reading from the charge holding portion 54 can be performed in a state where the modulation power is improved and the potential is deepened.

  Therefore, the saturation (dynamic range) of the photodiode 51 and the charge holding unit 54 can be improved.

  Forming a transistor for reading from the photodiode 51 with a vertical transistor is applicable to the above-described embodiment and the embodiment described below.

<Configuration Having Conversion Efficiency Switching Transistor>
Next, a pixel having a change efficiency switching transistor (a pixel group in a sharing unit) will be described. FIG. 27 is a diagram illustrating a configuration of a pixel group of one sharing unit including the conversion efficiency switching transistor 401.

  The configuration of the pixel group of one sharing unit shown in FIG. 27 is basically the same as that of the pixel group of one sharing unit shown in FIG. 3 except that a conversion efficiency switching transistor 401 is added. The description is omitted.

  When the conversion efficiency switching transistor 401 is turned on, the floating diffusion region of the FD 125 is expanded, the capacity of the FD 125 is increased, and the conversion efficiency is reduced.

  FIG. 28 is a diagram showing a pixel structure of four pixels sharing having a configuration for boosting the FD 125 as in FIG. Although the PD 51, the FD 125, and the FD wiring 126 are shown in FIG. 28 for the sake of explanation, the TRX gate 73 and the like are also arranged as shown in FIG.

  FD125-1 and FD125-2 are connected by FD wiring 126. The FD boost wiring 301-1 is formed on the right side of the FD wiring 126, and the FD boost wiring 301-2 is formed on the left side. Such a configuration is similar to the configuration shown in FIG.

  Further, in the configuration shown in FIG. 28, FD conversion wiring 411 is formed outside FD boosting wiring 301. A conversion efficiency switching transistor 401 (denoted as FDG in the figure) is formed below the FD 125-2.

  When the conversion efficiency switching transistor 401 is off, the FD wiring 126 and the FD conversion wiring 411 are in a disconnected state, and the FD 125 has a capacitance of FD125-1, FD125-2, and FD wiring 126. This is the state of the combined capacity.

  When the conversion efficiency switching transistor 401 is turned on, the FD wiring 126 and the FD conversion wiring 411 are in a connected state, and the capacitance of the FD 125 is FD125-1, FD125-2, FD wiring 126, and FD conversion. It becomes a state of the capacity of the combined wiring 411.

  When the conversion efficiency switching transistor 401 is on, the floating diffusion region of the FD 125 is enlarged by the amount of the FD conversion wiring 411, and the conversion efficiency is reduced.

  In a pixel including the conversion efficiency switching transistor 401 and the FD conversion wiring 411, the FD 125 may be boosted by the FD boosting wiring 301 when the conversion efficiency switching transistor 401 is off. Further, when the conversion efficiency switching transistor 401 is on, the FD 125 may be boosted by the FD boost wiring 301. Further, regardless of whether the conversion efficiency switching transistor 401 is on or off, the boosting of the FD 125 by the FD boosting wiring 301 may be performed.

  When the conversion efficiency switching transistor 401 is on, the floating diffusion region of the FD 125 expands and the conversion efficiency decreases, so that the FD 125 is boosted by the FD boosting wiring 301 so that the conversion is performed. It is possible to prevent the efficiency from decreasing.

  When the FD boosting wiring 301 boosts the FD 125 regardless of whether the conversion efficiency switching transistor 401 is on or off, the FD boosting wiring 301 for boosting the FD 125 when the conversion efficiency switching transistor 401 is on is provided. Alternatively, a separate wiring may be provided as a wiring different from the FD boost wiring 301 for boosting the FD 125 when the conversion efficiency switching transistor 401 is off.

  For example, when the FD boost wiring 301-1 and the FD boost wiring 301-2 are formed as shown in FIG. 27, when the conversion efficiency switching transistor 401 is off, the boosting of the FD 125 by the FD boost wiring 301-1 is not performed. When the conversion efficiency switching transistor 401 is on, the FD 125 may be boosted by the FD boost wiring 301-1 and the FD boost wiring 301-2.

  Further, the voltage applied to the FD boosting wiring 301 may be controlled to be different between when the conversion efficiency switching transistor 401 is on and when it is off.

<Specific wiring shape>
Next, an example of a specific shape of the FD wiring 126 and the FD boosting wiring 301 in a pixel having the conversion efficiency switching transistor 401 will be described. FIG. 29 is a plan view of the semiconductor substrate 63, showing a specific example of the arrangement position and shape of the PD 51 and the like. FIGS. 30 and 31 are circuit diagrams corresponding to the configuration shown in FIG.

  FIG. 29 is a diagram when four pixels arranged in 2 × 2 are set as one sharing unit. Pixel 50-0 is arranged at the lower left, pixel 50-1 is arranged at the lower right, pixel 50-2 is arranged at the upper left, and pixel 50-3 is arranged at the upper right. The basic arrangement and shape are the same as those of the pixel shown in FIG. 19, and are different in that a conversion efficiency switching transistor 401 is added to the pixel shown in FIG.

  The conversion efficiency switching transistor 401 (denoted as FDG in FIG. 29) is formed between the pixel 50-0 and the pixel 50-1. SEL (corresponding to the selection transistor 133), AMP (corresponding to the amplification transistor 132), RST (corresponding to the reset transistor 131), and FD (corresponding to FD125) are provided between the pixel 50-2 and the pixel 50-3. Is formed.

  In each pixel 50, PD, OFD, OFG, TRY, TRX, and TRG are formed. In the region where TRY and TRX are formed, MEM (corresponding to the charge holding unit 54) is formed.

  PD, OFD, OFG, TRY, TRY, TRG, and MEM formed in the pixel 50 are connected as shown in the circuit diagrams of FIGS. The circuit configuration of one pixel has been described with reference to FIG. 13 and will not be described here. However, in the pixel configuration shown in FIG. 29 and subsequent figures, TRY is exemplified for a case where it is formed for each pixel and controlled so as to be controlled for each pixel.

  In the circuit diagrams shown in FIGS. 30 and 31, FD1 represents a portion corresponding to the FD125, and FD2 represents the FD conversion wiring 411. When the conversion efficiency switching transistor 401 is turned on, the FD1 and the FD2 function as one FD.

  FIG. 32 is a diagram illustrating an arrangement and a shape of wiring and the like wired in the wiring layer 61-1 stacked on the semiconductor substrate 63 illustrated in FIG. In the wiring layer 61-1, a light-shielding film made of, for example, a metal is formed at the position of the PD formed on the semiconductor substrate 63.

  In the wiring layer 61-1, a TRY gate is formed in a portion of the semiconductor substrate 63 shown in FIG. 29 where the TRY of the pixel 50 is formed. Similarly, a gate of TRX and a gate of TRG are formed in the wiring layer 61-1. Further, the gate of the conversion efficiency switching transistor 401 (FDG) is also formed in the wiring layer 61-1.

  Further, vias are formed in the wiring layer 61-1 to connect the FD region formed in the semiconductor substrate 63 to the FD wiring 126 formed in the wiring layer 61-2. Further, an FD conversion wiring 411 (a wiring described as FD2 in FIG. 32) is formed in the wiring layer 61-1.

  FIG. 33 is a diagram illustrating an arrangement and a shape of wirings and the like wired in the wiring layer 61-2 laminated on the wiring layer 61-1 illustrated in FIG. In the wiring layer 61-2, an FD wiring 126 (a wiring described as FD1 in the drawing) for connecting a region of the FD 125 formed on the semiconductor substrate 63 is formed. An FD boosting wiring 301 (a wiring described as FOB in FIG. 33) is formed in a shape close to and parallel to the FD wiring 126. The example shown in FIG. 33 shows an example in which the FD boost wiring 301 is formed on the left and right with the FD wiring 126 as the center.

  FIG. 34 is a diagram illustrating an arrangement and a shape of wirings and the like wired in a wiring layer 61-3 stacked on the wiring layer 61-2 illustrated in FIG. Control signal lines are formed in the wiring layer 61-3 in the horizontal direction (horizontal direction) in the drawing. Similarly to the wiring layer 61-3 of the pixel without the conversion efficiency switching transistor 401 shown in FIG. 23, the control signal lines include the signal line OFD, the signal line OFG, the signal line TRY, the signal line TRX, the signal line RST, and the signal line. A line VDD, a signal line VSS, and a signal line SEL are formed. Further, a signal line FDG for supplying a signal for controlling the conversion efficiency switching transistor 401 is also formed. Since TRY is provided for each pixel, TRY0 to TRY3 are also formed.

  FIG. 35 is a diagram illustrating the arrangement and shape of the wiring and the like wired in the wiring layer 61-4 stacked on the wiring layer 61-3 illustrated in FIG. Vertical signal lines are formed in the wiring layer 61-4. Vertical signal lines VSL0 to VSL3 are formed in the wiring layer 61-4 in the vertical direction (vertical direction) in the drawing.

  The positions and shapes of the wirings described above are merely examples, and do not limit the description.

  According to the present technology, a charge holding unit that temporarily accumulates charges from a PD is provided, and when photographing is performed using the global shutter method, the amount of boost of the FD can be secured and the conversion efficiency can be improved. Further, according to the present technology, in a configuration in which a plurality of pixels share an FD, a wiring for boosting the FD is formed in the vicinity of a wiring connecting the FD to be shared, thereby securing a boost amount of the FD. Configuration.

  According to the present technology, it is possible to secure a dynamic range and reduce noise.

<Electronic equipment>
The present technology is not limited to application to an imaging device, but includes an imaging device such as a digital still camera or a video camera, a mobile terminal device having an imaging function such as a mobile phone, and a copy using the imaging device for an image reading unit. The present invention can be applied to all electronic devices using an imaging device for an image capturing unit (photoelectric conversion unit), such as a device. It should be noted that there is also a case where the imaging device is a module type mounted on an electronic device, that is, a camera module.

  FIG. 36 is a block diagram illustrating a configuration example of an imaging device that is an example of the electronic device of the present disclosure. As illustrated in FIG. 36, an imaging device 600 according to the present disclosure includes an optical system including a lens group 601 and the like, an imaging element 602, a DSP circuit 603 serving as a camera signal processing unit, a frame memory 604, a display device 605, a recording device 606, An operation system 607 and a power supply system 608 are provided.

  A DSP circuit 603, a frame memory 604, a display device 605, a recording device 606, an operation system 607, and a power supply system 608 are connected to each other via a bus line 609. The CPU 610 controls each unit in the imaging device 600.

  The lens group 601 captures incident light (image light) from a subject and forms an image on an imaging surface of the imaging element 602. The image sensor 602 converts the amount of incident light formed on the imaging surface by the lens group 601 into an electric signal in pixel units and outputs the signal as a pixel signal. As the image sensor 602, the image sensor (image sensor) according to the above-described embodiment can be used.

  The display device 605 includes a panel-type display device such as a liquid crystal display device or an organic EL (electro luminescence) display device, and displays a moving image or a still image captured by the image sensor 602. The recording device 606 records a moving image or a still image captured by the image sensor 602 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation system 607 issues an operation command for various functions of the imaging apparatus under an operation by the user. The power supply system 608 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 603, the frame memory 604, the display device 605, the recording device 606, and the operation system 607 to these supply targets.

  Such an imaging device 600 is applied to a video camera, a digital still camera, and a camera module for a mobile device such as a mobile phone. In the imaging device 600, the imaging device according to the above-described embodiment can be used as the imaging device 602.

<Example of application to endoscopic surgery system>
The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

  FIG. 37 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology (the present technology) according to the present disclosure may be applied.

  FIG. 37 illustrates a state in which an operator (doctor) 11131 performs an operation on a patient 11132 on a patient bed 11133 using the endoscopic surgery system 11000. As shown, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, and a support arm device 11120 that supports the endoscope 11100. And a cart 11200 on which various devices for endoscopic surgery are mounted.

  The endoscope 11100 includes a lens barrel 11101 having a region of a predetermined length from the distal end inserted into the body cavity of the patient 11132, and a camera head 11102 connected to a proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100 which is configured as a so-called rigid endoscope having a hard lens barrel 11101 is illustrated. However, the endoscope 11100 may be configured as a so-called flexible endoscope having a soft lens barrel. Good.

  An opening in which the objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the distal end of the lens barrel by a light guide that extends inside the lens barrel 11101, and the objective The light is radiated toward the observation target in the body cavity of the patient 11132 via the lens. In addition, the endoscope 11100 may be a direct view scope, a perspective view scope, or a side view scope.

  An optical system and an image sensor are provided inside the camera head 11102, and the reflected light (observation light) from the observation target is focused on the image sensor by the optical system. The observation light is photoelectrically converted by the imaging element, and an electric signal corresponding to the observation light, that is, an image signal corresponding to the observation image is generated. The image signal is transmitted to a camera control unit (CCU: Camera Control Unit) 11201 as RAW data.

  The CCU 11201 is configured by a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and the like, and controls the operations of the endoscope 11100 and the display device 11202 overall. Further, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal for displaying an image based on the image signal, such as a development process (demosaicing process).

  The display device 11202 displays an image based on the image signal on which image processing has been performed by the CCU 11201 under the control of the CCU 11201.

  The light source device 11203 includes, for example, a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when imaging an operation part or the like.

  The input device 11204 is an input interface to the endoscopic surgery system 11000. The user can input various information and input instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction or the like to change imaging conditions (type of irradiation light, magnification, focal length, and the like) by the endoscope 11100.

  The treatment tool control device 11205 controls driving of the energy treatment tool 11112 for cauterizing, incising a tissue, sealing a blood vessel, and the like. The insufflation device 11206 is used to inflate the body cavity of the patient 11132 for the purpose of securing the visual field by the endoscope 11100 and securing the working space of the operator. Send. The recorder 11207 is a device that can record various types of information related to surgery. The printer 11208 is a device capable of printing various types of information on surgery in various formats such as text, images, and graphs.

  The light source device 11203 that supplies the endoscope 11100 with irradiation light at the time of imaging the operation site can be configured by, for example, a white light source including an LED, a laser light source, or a combination thereof. When a white light source is configured by a combination of the RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high accuracy, so that the light source device 11203 adjusts the white balance of the captured image. It can be carried out. In this case, the laser light from each of the RGB laser light sources is radiated to the observation target in a time-division manner, and the driving of the image pickup device of the camera head 11102 is controlled in synchronization with the irradiation timing. It is also possible to capture the image obtained in a time-division manner. According to this method, a color image can be obtained without providing a color filter in the image sensor.

  The driving of the light source device 11203 may be controlled so as to change the intensity of light to be output at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change of the light intensity, an image is acquired in a time-division manner, and the image is synthesized, so that a high dynamic image without so-called blackout and whiteout is obtained. An image of the range can be generated.

  In addition, the light source device 11203 may be configured to be able to supply light in a predetermined wavelength band corresponding to special light observation. In the special light observation, for example, by utilizing the wavelength dependence of the absorption of light in the body tissue, by irradiating light in a narrower band than the irradiation light (ie, white light) at the time of normal observation, the surface of the mucous membrane is exposed. A so-called narrow band imaging (Narrow Band Imaging) for photographing a predetermined tissue such as a blood vessel with high contrast is performed. Alternatively, in the special light observation, fluorescence observation in which an image is obtained by fluorescence generated by irradiating excitation light may be performed. In fluorescence observation, body tissue is irradiated with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and Irradiation with excitation light corresponding to the fluorescence wavelength of the reagent can be performed to obtain a fluorescence image. The light source device 11203 can be configured to be able to supply narrowband light and / or excitation light corresponding to such special light observation.

  FIG. 38 is a block diagram illustrating an example of a functional configuration of the camera head 11102 and the CCU 11201 illustrated in FIG.

  The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are communicably connected to each other by a transmission cable 11400.

  The lens unit 11401 is an optical system provided at a connection with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102, and enters the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

  The imaging unit 11402 includes an imaging element. The number of imaging elements constituting the imaging unit 11402 may be one (so-called single-panel type) or plural (so-called multi-panel type). When the imaging unit 11402 is configured as a multi-panel type, for example, an image signal corresponding to each of RGB may be generated by each imaging element, and a color image may be obtained by combining the image signals. Alternatively, the imaging unit 11402 may be configured to include a pair of imaging elements for acquiring right-eye and left-eye image signals corresponding to 3D (Dimensional) display. By performing the 3D display, the operator 11131 can more accurately grasp the depth of the living tissue in the operative part. Note that when the imaging unit 11402 is configured as a multi-plate system, a plurality of lens units 11401 may be provided for each imaging element.

  Further, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101 immediately after the objective lens.

  The driving unit 11403 is configured by an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. Thus, the magnification and the focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

  The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

  In addition, the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. The control signal includes, for example, information indicating that the frame rate of the captured image is specified, information that specifies the exposure value at the time of imaging, and / or information that specifies the magnification and focus of the captured image. Contains information about the condition.

  Note that the above-described imaging conditions such as the frame rate, the exposure value, the magnification, and the focus may be appropriately designated by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. Good. In the latter case, a so-called AE (Auto Exposure) function, an AF (Auto Focus) function, and an AWB (Auto White Balance) function are mounted on the endoscope 11100.

  The camera head control unit 11405 controls driving of the camera head 11102 based on a control signal from the CCU 11201 received via the communication unit 11404.

  The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

  Further, the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by electric communication, optical communication, or the like.

  The image processing unit 11412 performs various types of image processing on an image signal that is RAW data transmitted from the camera head 11102.

  The control unit 11413 performs various controls related to the imaging of the operative site and the like by the endoscope 11100 and the display of a captured image obtained by imaging the operative site and the like. For example, the control unit 11413 generates a control signal for controlling driving of the camera head 11102.

  In addition, the control unit 11413 causes the display device 11202 to display a captured image in which an operation unit or the like is shown, based on the image signal on which the image processing is performed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 detects a shape, a color, or the like of an edge of an object included in the captured image, and thereby detects a surgical tool such as forceps, a specific living body site, bleeding, a mist when using the energy treatment tool 11112, and the like. Can be recognized. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition result to superimpose and display various types of surgery support information on the image of the operative site. By superimposing the operation support information and presenting it to the operator 11131, the burden on the operator 11131 can be reduced, and the operator 11131 can reliably perform the operation.

  A transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electric signal cable corresponding to electric signal communication, an optical fiber corresponding to optical communication, or a composite cable thereof.

  Here, in the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

  Although the endoscopic surgery system has been described as an example here, the technology according to the present disclosure may be applied to, for example, a microscopic surgery system and the like.

<Example of application to moving objects>
The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on any type of mobile object such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.

  FIG. 39 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a moving object control system to which the technology according to the present disclosure may be applied.

  Vehicle control system 12000 includes a plurality of electronic control units connected via communication network 12001. In the example shown in FIG. 39, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and a vehicle-mounted network I / F (interface) 12053 are illustrated.

  The drive system control unit 12010 controls operations of devices related to the drive system of the vehicle according to various programs. For example, the driving system control unit 12010 includes a driving force generating device for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting driving force to wheels, and a steering angle of the vehicle. It functions as a control mechanism such as a steering mechanism for adjusting and a braking device for generating a braking force of the vehicle.

  The body control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a head lamp, a back lamp, a brake lamp, a blinker, and a fog lamp. In this case, a radio wave or various switch signals transmitted from a portable device replacing the key may be input to the body control unit 12020. The body control unit 12020 receives the input of these radio waves or signals and controls a door lock device, a power window device, a lamp, and the like of the vehicle.

  Out-of-vehicle information detection unit 12030 detects information outside the vehicle on which vehicle control system 12000 is mounted. For example, an imaging unit 12031 is connected to the outside-of-vehicle information detection unit 12030. The out-of-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle, and receives the captured image. The out-of-vehicle information detection unit 12030 may perform an object detection process or a distance detection process of a person, a vehicle, an obstacle, a sign, a character on a road surface, or the like based on the received image.

  The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of received light. The imaging unit 12031 can output an electric signal as an image or can output the information as distance measurement information. The light received by the imaging unit 12031 may be visible light or non-visible light such as infrared light.

  The in-vehicle information detection unit 12040 detects information in the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the status of the driver. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 determines the degree of driver fatigue or concentration based on the detection information input from the driver state detection unit 12041. The calculation may be performed, or it may be determined whether the driver has fallen asleep.

  The microcomputer 12051 calculates a control target value of the driving force generation device, the steering mechanism or the braking device based on the information on the inside and outside of the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, and the drive system control unit A control command can be output to 12010. For example, the microcomputer 12051 realizes an ADAS (Advanced Driver Assistance System) function including a vehicle collision avoidance or a shock mitigation, a following operation based on a distance between vehicles, a vehicle speed maintaining operation, a vehicle collision warning, a vehicle lane departure warning, and the like. Cooperative control for the purpose.

  Further, the microcomputer 12051 controls the driving force generation device, the steering mechanism, the braking device, and the like based on the information about the surroundings of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, so that the driver 120 It is possible to perform cooperative control for automatic driving or the like in which the vehicle travels autonomously without depending on the operation.

  Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information on the outside of the vehicle obtained by the outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of preventing glare such as switching a high beam to a low beam. It can be carried out.

  The sound image output unit 12052 transmits at least one of a sound signal and an image signal to an output device capable of visually or audibly notifying a passenger of the vehicle or the outside of the vehicle of information. In the example of FIG. 39, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

  FIG. 40 is a diagram illustrating an example of an installation position of the imaging unit 12031.

  In FIG. 40, the vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

  The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper portion of a windshield in the vehicle compartment of the vehicle 12100. The imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the passenger compartment mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100. The imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, and the like.

  Note that FIG. 40 shows an example of the imaging range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates 13 shows an imaging range of an imaging unit 12104 provided in a rear bumper or a back door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing image data captured by the imaging units 12101 to 12104.

  At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements or an imaging element having pixels for detecting a phase difference.

  For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 calculates a distance to each three-dimensional object in the imaging ranges 12111 to 12114 and a temporal change of the distance (relative speed with respect to the vehicle 12100). , It is possible to extract, as a preceding vehicle, a three-dimensional object that travels at a predetermined speed (for example, 0 km / h or more) in a direction substantially the same as that of the vehicle 12100, which is the closest three-dimensional object on the traveling path of the vehicle 12100. it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured before the preceding vehicle and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for automatic driving or the like in which the vehicle travels autonomously without depending on the operation of the driver.

  For example, the microcomputer 12051 converts the three-dimensional object data relating to the three-dimensional object into other three-dimensional objects such as a motorcycle, a normal vehicle, a large vehicle, a pedestrian, a telephone pole, and the like based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle, and when the collision risk is equal to or more than the set value and there is a possibility of collision, via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver through forced driving and avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.

  At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian exists in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed by, for example, extracting a feature point in an image captured by the imaging units 12101 to 12104 as an infrared camera, and performing a pattern matching process on a series of feature points indicating the outline of the object to determine whether the object is a pedestrian. Is performed according to a procedure for determining When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a rectangular contour for emphasis to the recognized pedestrian. The display unit 12062 is controlled so that is superimposed. Further, the sound image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

  In this specification, the system represents the entire device including a plurality of devices.

  It should be noted that the effects described in this specification are merely examples and are not limited, and may have other effects.

  Note that embodiments of the present technology are not limited to the above-described embodiments, and various changes can be made without departing from the gist of the present technology.

Note that the present technology can also have the following configurations.
(1)
A photoelectric conversion unit that converts received light into electric charges,
A holding unit that holds the charge transferred from the photoelectric conversion unit; and
A floating diffusion that is shared by the plurality of pixels and holds the charge transferred from the holding unit;
And a booster line for boosting the floating diffusion.
(2)
The imaging device according to (1), which performs imaging using a global shutter method.
(3)
The imaging device according to (1) or (2), wherein the booster line is formed in a shape in which at least a part thereof is parallel to a vicinity of a connection wiring connecting the plurality of floating diffusions.
(4)
The imaging device according to (3), wherein the boosting line and the connection wiring are formed in the same layer.
(5)
The imaging device according to (3), wherein the boosting line and the connection wiring are formed in different layers.
(6)
The imaging device according to any one of (1) to (5), wherein the boost line is connected to a gate of an amplification transistor that outputs a voltage signal corresponding to a potential of the floating diffusion.
(7)
The imaging device according to any one of (1) to (6), further including a switching unit configured to switch a capacity of the floating diffusion.
(8)
A read gate for reading out electric charges from the holding unit,
The imaging device according to any one of (1) to (7), wherein the read gate is formed in a vertical direction and a horizontal direction with respect to the photoelectric conversion unit.
(9)
The imaging device according to any one of (1) to (8), wherein the reading of the charge from the photoelectric conversion unit is performed by a CCD method.
(10)
The imaging device according to any one of (3) to (9), wherein a control line that controls application of a predetermined voltage to the boost line and the connection line are orthogonal to each other.
(11)
The imaging device according to any one of (3) to (9), wherein a control line that controls application of a predetermined voltage to the boost line and the connection line are parallel.
(12)
A photoelectric conversion unit that converts received light into electric charges,
A holding unit that holds the charge transferred from the photoelectric conversion unit; and
A floating diffusion that is shared by the plurality of pixels and holds the charge transferred from the holding unit;
An electronic apparatus comprising: an imaging device including: a boosting line that boosts the floating diffusion; and a processing unit that processes a signal from the imaging device.

  Reference Signs List 30 image sensor, 41 pixel array section, 42 vertical drive section, 43 column processing section, 44 horizontal drive section, 45 system control section, 46 pixel drive line, 47 vertical signal line, 48 signal processing section, 49 data storage section, 50 Pixel, 54 charge holding section, 61 wiring layer, 62 oxide film, 63 semiconductor substrate, 64 light shielding layer, 65 color filter layer, 66 on-chip lens, 67 PD area, 68 charge holding area, 71 wiring, 72 interlayer insulating film, 73 TRX gate, 74 surface pinning layer, 75 inter-pixel separation region, 76 light shielding portion, 77 high dielectric constant material film, 121 discharge transistor, 122 OFG gate, 124 second transfer transistor, 125 floating diffusion region, 126 FD boost wiring , 131 Reset Transient , 132 amplifying transistor, 133 selection transistor, 301 FD boost wiring, 331 read gate, 401 conversion efficiency switching transistor, 411 FD conversion wiring

Claims (12)

A photoelectric conversion unit that converts received light into electric charges,
A holding unit that holds the charge transferred from the photoelectric conversion unit; and
A floating diffusion that is shared by the plurality of pixels and holds the charge transferred from the holding unit;
And a booster line for boosting the floating diffusion. The imaging device according to claim 1, wherein imaging is performed by a global shutter method. 2. The imaging device according to claim 1, wherein the boosting line is formed in a shape in which at least a part thereof is parallel to a vicinity of a connection wiring connecting the plurality of floating diffusions. 3. The imaging device according to claim 3, wherein the boosting line and the connection wiring are formed in the same layer. The imaging device according to claim 3, wherein the boosting line and the connection wiring are formed in different layers. The imaging device according to claim 1, wherein the boost line is connected to a gate of an amplification transistor that outputs a voltage signal corresponding to a potential of the floating diffusion. The imaging device according to claim 1, further comprising a switching unit configured to switch a capacity of the floating diffusion. A read gate for reading out electric charges from the holding unit,
The imaging device according to claim 1, wherein the read gate is formed in a vertical direction and a horizontal direction with respect to the photoelectric conversion unit. The imaging device according to claim 1, wherein the reading of the charge from the photoelectric conversion unit is performed by a CCD method. The imaging device according to claim 3, wherein a control line that controls application of a predetermined voltage to the boost line and the connection line are orthogonal to each other. The imaging device according to claim 3, wherein a control line that controls application of a predetermined voltage to the boost line and the connection line are parallel. A photoelectric conversion unit that converts received light into electric charges,
A holding unit that holds the charge transferred from the photoelectric conversion unit; and
A floating diffusion that is shared by the plurality of pixels and holds the charge transferred from the holding unit;
An imaging device comprising: a boosting line for boosting the floating diffusion;
A processing unit that processes a signal from the imaging device.

Images