JP2020013833A - Semiconductor device - Google Patents

Abstract

To provide a thin semiconductor device, while preventing a bonding wire from short-circuiting with other conductor.SOLUTION: A semiconductor device disclosed herein includes a semiconductor element, a bonding wire, and an insulating substrate. The bonding wire is connected with a first electrode on the principal surface of the semiconductor element. The insulating substrate is facing the principal surface and the bonding wire. On the face of the insulating substrate opposing the principal surface of the semiconductor element, a conductor pattern of a prescribed thickness is formed and connected with a second electrode on the principal surface of the semiconductor element. In the region of the insulating substrate facing the bonding wire, the insulating substrate is exposed, and a wire guide part for regulating the position of the bonding wire is provided. By this regulation, the bonding wire does not short-circuit with other conductor, even if the distance between the insulating substrate and the semiconductor element is shortened. In other words, the semiconductor element can be made thinner, while preventing the bonding wire from short-circuiting with other conductor.SELECTED DRAWING: Figure 1

Description

  The technology disclosed in this specification relates to a semiconductor device.

  Patent Literature 1 discloses a semiconductor device in which a semiconductor element is mounted on a wiring board. The semiconductor element has a first electrode and a second electrode on its main surface. Here, the main surface of the semiconductor element means a wide surface of the flat semiconductor element. The first electrode is a small current electrode such as a gate electrode or a sense emitter electrode. The second electrode is a main electrode such as a collector electrode or an emitter electrode. A bonding wire is connected to the first electrode. A wiring board is connected to the second electrode via a copper block. The wiring board also faces the bonding wires. The copper block is provided to secure a space between the semiconductor element and the wiring board so that the bonding wire does not short-circuit with another conductor.

JP-A-2004-311905

  2. Description of the Related Art In recent years, electronic devices on which semiconductor devices are mounted have been reduced in size, particularly thinned. Therefore, semiconductor devices are also required to be thin. In the semiconductor device of Patent Document 1, if the space between the semiconductor element and the wiring substrate can be reduced, the thickness can be reduced. However, when the space between the semiconductor substrate and the wiring substrate is reduced, the bonding wire is likely to short-circuit with another conductor. The present specification provides a thinned semiconductor device while preventing a bonding wire from being short-circuited with another conductor.

  The semiconductor device disclosed in this specification includes a semiconductor element, a bonding wire, and an insulating substrate. A first electrode and a second electrode are provided on a main surface of the semiconductor element. The first electrode is typically a small current control electrode, such as a gate electrode. The second electrode is a main electrode through which a large current flows, such as a collector electrode. The bonding wire is connected to the first electrode. The insulating substrate faces the main surface and the bonding wires. A conductor pattern having a predetermined thickness is formed on a surface of the insulating substrate facing the main surface of the semiconductor element, and the conductor pattern is connected to the second electrode. The insulating substrate is exposed in a region of the insulating substrate facing the bonding wires, and a wire guide portion for regulating the position of the bonding wire is provided in the region.

  In the semiconductor device disclosed in this specification, the distance between the semiconductor element and the insulating substrate is the smallest when the distance is only about the thickness of the conductor pattern. Accordingly, the thickness of the semiconductor device can be reduced. On the other hand, in such a narrow space, the bonding wires may come into contact with the insulating substrate. The bonding wire that has come into contact with the insulating substrate may be pushed by the insulating substrate, change its position, and come into contact with another conductor. However, in the semiconductor device disclosed in this specification, since the wire guide regulates the position of the bonding wire, even if the distance between the insulating substrate and the semiconductor element is shortened, the bonding wire is short-circuited with another conductor. Can be prevented. That is, the semiconductor device disclosed in this specification can achieve a reduction in thickness while preventing a bonding wire from being short-circuited to another conductor. An example of another conductor is another adjacent bonding wire, and an example of a wire guide is a wall separating adjacent bonding wires or a groove in which each bonding wire is locked.

  The details and further improvements of the technology disclosed in this specification will be described in the following “Detailed description of the invention”.

It is a top view of the semiconductor device of an example. FIG. 2 is a sectional view taken along the line II-II in FIG. 1. FIG. 3 is a cross-sectional view along the line III-III in FIG. 2. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1 in a modified example of a wire guide unit. FIG. 5 is a sectional view taken along line VV in FIG. 4.

  A semiconductor device 10 according to an embodiment will be described with reference to the drawings. As described below, the semiconductor device 10 of the present embodiment is a semiconductor device having a double-sided cooling structure. The semiconductor device 10 of the present embodiment can be used for a power conversion circuit such as a converter and an inverter in an electric vehicle such as an electric vehicle, a hybrid vehicle, and a fuel cell vehicle. However, the use of the semiconductor device 10 is not particularly limited. The semiconductor device 10 can be widely used for various devices and circuits.

  The components constituting the semiconductor device 10 will be described with reference to FIGS. The semiconductor device 10 includes a front semiconductor element 20a and a rear semiconductor element 20b, an upper insulating substrate 12, a lower insulating substrate 32, a resin package 11, and a copper spacer 17. The front semiconductor element 20a and the rear semiconductor element 20b are sandwiched between the upper insulating substrate 12 and the lower insulating substrate 32 from above and below, and the whole is sealed inside the resin package 11. The front semiconductor element 20a and the rear semiconductor element 20b are so-called power semiconductor elements for a power circuit. The front semiconductor element 20a includes a control pad (hereinafter, referred to as a first electrode 21a), a collector electrode (hereinafter, referred to as a second electrode 23a), and an emitter electrode (hereinafter, referred to as a third electrode 24a). ,have. The first electrode 21a and the second electrode 23a are located on one principal surface (first principal surface) of the front semiconductor element 20a, and the third electrode 24a is located on the other principal surface (second principal surface) of the front semiconductor element 20a. ) Is located. The rear semiconductor element 20b also has a first electrode 21b, a second electrode 23b, and a third electrode 24b, like the front semiconductor element 20a. The first electrode 21b and the second electrode 23b are located on one main surface (first main surface) of the rear semiconductor element 20b, and the third electrode 24b is located on the other main surface (second main surface) of the rear semiconductor element 20b. Main surface). Note that FIG. 1 is a plan view of the semiconductor device 10 viewed from the + Z direction of the coordinate system in the figure. However, in order to facilitate understanding, the package 11 that seals the semiconductor elements 20a and 20b is indicated by a virtual line. Is shown. In FIG. 1, the insulating substrate 12 located in front of the semiconductor elements 20 a and 20 b is also indicated by phantom lines, and upper main surface conductive patterns 25 a and 25 b provided on one surface of the insulating substrate 12 (details will be described later). ) Are shown in gray. Upper backside conductor patterns 35a and 35b (details described later) provided on the other surface of the insulating substrate 12 are not shown.

  The upper insulating substrate 12 and the lower insulating substrate 32 are so-called DBC (Direct Bonding Copper) substrates. The upper insulating substrate 12 has upper main surface conductor patterns 25a and 25b on the main surfaces of the front semiconductor element 20a and the rear semiconductor element 20b and on a surface (hereinafter, referred to as a lower surface) opposed to bonding wires 26a and 26b (described below). Is formed. The upper main surface conductor patterns 25a and 25b are separated from each other on the lower surface of the upper insulating substrate 12, and are insulated from each other. As shown in FIG. 3, the upper insulating substrate 12 also has upper back side patterns 35a and 35b formed on the surface opposite to the upper main surface conductive patterns 25a and 25b. The upper main surface conductive patterns 35a and 35b are separated from each other on the upper surface of the upper insulating substrate 12, and are insulated from each other. The upper main surface conductor patterns 25a and 25b and the upper back surface patterns 35a and 35b are insulated from each other by the upper insulating substrate 12.

  In the lower insulating substrate 32, lower main surface conductor patterns 45a and 45b are formed on a surface facing the second main surface of the front semiconductor element 20a and the rear semiconductor element 20b. As shown in FIG. 3, the lower insulating substrate 32 is further formed with lower back surface conductor patterns 55a and 55b on the surface opposite to the lower main surface conductor patterns 45a and 45b. The lower main surface conductor patterns 45a and 45b are insulated from each other, and the lower back surface conductor patterns 55a and 55b are also insulated from each other. The lower main surface conductor patterns 45a and 45b and the lower back surface conductor patterns 55a and 55b are insulated from each other by the lower insulating substrate 12.

  The semiconductor device 10 further includes a plurality of power terminals 14, 15, 16 and a plurality of control terminals 18, 19 as external connection terminals. The plurality of power terminals 14, 15, 16 and the plurality of control terminals 18, 19 are external connection terminals for electrically connecting the semiconductor elements 20a, 20b to another device. These external connection terminals extend from the inside of the resin package 11 to the outside.

  The connection structure of the components constituting the semiconductor device 10 will be described. In the semiconductor device 10, the four first electrodes 21a of the front semiconductor element 20a and the four control terminals 18 are connected using four bonding wires 26a. Further, an upper main surface conductor pattern 25 a connected to the second electrode 23 a of the front semiconductor element 20 a is connected to the power terminal 14. Further, the lower main surface conductor pattern 45a of the lower insulating substrate 32 is connected to the third electrode 23a of the front semiconductor element 20a. The lower main surface conductor pattern 45a extends to the center of the semiconductor device 10. The lower main surface conductor pattern 45a is connected to the copper spacer 17, and the copper spacer 17 is connected to the upper main surface conductor pattern 25b of the upper insulating substrate 12. That is, the front semiconductor element 20 a and the rear semiconductor element 20 b are connected in series via the copper spacer 17. Similarly to the front semiconductor element 20a, the second electrode 23b of the rear semiconductor element 20b is connected to the upper main conductor pattern 25b, and the upper main conductor pattern 25b is connected to the power terminal 16. Further, in the semiconductor device 10, the four first electrodes 21b of the front semiconductor element 20b and the four control terminals 19 are connected by using four bonding wires 26b. The lower main surface conductor pattern 45b connected to the third electrode 23b of the rear semiconductor element 20b is connected to the power terminal 15.

  With reference to FIG. 2, a joining structure of components constituting the semiconductor device 10 will be described. FIG. 2 is a cross section taken along line II-II in FIG. As described above, the front semiconductor element 20a is sandwiched between the upper insulating substrate 12 and the lower insulating substrate 32. The upper main surface conductor pattern 25a of the upper insulating substrate 12 is joined to the second electrode 23a of the front semiconductor element 20a. For this joining, soldering is employed, and a solder layer 27 is formed between the front semiconductor element 20a and the upper main surface conductor pattern 25a. The lower main surface conductor pattern 45a of the lower insulating substrate 32 is joined to the third electrode 24a of the front semiconductor element 20a. This bonding also employs soldering, and a solder layer 28 is formed between the front semiconductor element 20a and the lower main surface conductor pattern 45a. The upper main surface conductive pattern 25a of the upper insulating substrate 12 and the power terminal 14 are joined. Soldering is also used for this bonding, and a solder layer 29 is formed between the upper main surface conductive pattern 25a and the power terminal 14. The whole is sealed with a resin package 11. Note that a similar bonding method is adopted for the rear semiconductor element 20b.

  The upper back surface conductive pattern 35 a of the upper insulating substrate 12 is exposed on the upper surface 11 a of the resin package 11. Thus, the upper back surface conductive pattern 35a of the upper insulating substrate 12 not only constitutes a part of the electric circuit of the semiconductor device 10, but also functions as a heat radiating plate for releasing heat of the front semiconductor element 20a and the like to the outside. I have. Similarly, the lower back surface conductive pattern 55 a of the lower insulating substrate 32 is exposed on the lower surface 11 b of the resin package 11. Thus, the lower back surface conductive pattern 55a of the lower insulating substrate 32 not only constitutes a part of the electric circuit of the semiconductor device 10, but also serves as a heat radiating plate for releasing heat of the front semiconductor element 20a and the like to the outside. It is functioning. As shown in FIG. 3, the upper back surface conductive pattern 35 b of the upper insulating substrate 12 and the lower back surface conductive pattern 55 b of the lower insulating substrate 32 are exposed on both upper and lower surfaces 11 a and 11 b of the resin package 11. Accordingly, the upper back surface conductor pattern 35b of the upper insulation substrate 12 and the lower back surface conductor pattern 55b of the lower insulation substrate 32 not only constitute a part of the electric circuit of the semiconductor device 10, but also form the rear side semiconductor element 20b. It also functions as a heat radiating plate for releasing the heat of the outside. By adopting such a structure, the semiconductor device 10 of the present embodiment is configured such that, for example, a cooler is brought into contact with the upper surface 11a and the lower surface 11b of the resin package 11 so that the front semiconductor element 20a as a heating element and the rear side The semiconductor element 20b can be cooled from both upper and lower surfaces of the resin package 11. That is, the semiconductor device 10 has a double-sided cooling structure.

  The front semiconductor element 20a and the rear semiconductor element 20b in this embodiment are vertical semiconductor elements. Further, they are the same kind of semiconductor elements, specifically, an RC-IGBT (Reverse Conducting IGBT) element incorporating an IGBT (Insulated Gate Bipolar Transistor) and a diode.

  As described above, the upper insulating substrate 12 in this embodiment is a DBC substrate. The upper insulating substrate 12 is made of, for example, a ceramic such as aluminum oxide, silicon nitride, aluminum nitride, or the like. The upper main surface conductor patterns 25a and 25b and the upper back surface conductor patterns 35a and 35b are each made of copper. I have. However, the upper insulating substrate 12 is not limited to a DBC substrate. The upper insulating substrate 12 is not limited to ceramic and may be made of another insulator. The upper main surface conductor patterns 25a and 25b and the upper rear surface conductor patterns 35a and 35b are not limited to copper, but may be formed of another conductor. Also, the bonding structure between the upper main surface conductor patterns 25a and 25b and the upper rear surface conductor patterns 35a and 35b in the upper insulating substrate 12 is not particularly limited.

  Like the upper insulating substrate 12, the lower insulating substrate 32 in this embodiment is also a DBC substrate. The lower insulating substrate 32 is made of, for example, a ceramic such as aluminum oxide, silicon nitride, or aluminum nitride, and each of the lower main conductor patterns 45a and 45b and the lower back conductor patterns 55a and 55b is made of copper. Have been. However, the lower insulating substrate 32 is not limited to a DBC substrate. The lower insulating substrate 32 is not limited to ceramic, and may be made of another insulator. The lower main surface conductor patterns 45a and 45b and the lower back surface conductor patterns 55a and 55b are not limited to copper, and may be formed of another conductor. The bonding structure between the lower main surface conductor patterns 45a and 45b and the lower back surface conductor patterns 55a and 55b in the lower insulating substrate 32 is not particularly limited.

  Further, the resin package 11 in the embodiment is made of an epoxy resin, but is not particularly limited, and another thermosetting resin may be used. Further, the plurality of power terminals 14, 15, 16 and the plurality of control terminals 18, 19 are made of copper, but other metal materials can be used. Further, the copper spacer 17 in this embodiment is made of a copper-molybdenum alloy. However, the copper spacer 17 is not limited to the copper-molybdenum alloy, and may be formed of another conductor such as pure copper or another copper alloy. Although the bonding wires 26a and 26b are configured by gold wires in the embodiment, the bonding wires 26a and 26b are not particularly limited, and other metals (such as aluminum and copper) may be used.

  The semiconductor device 10 of the present embodiment includes wire guides 12a and 12b that regulate the positions of the bonding wires 26a and 26b. The wire guides 12a and 12b prevent each of the plurality of bonding wires 26a and 26b from being short-circuited with another conductor. Hereinafter, the wire guide portions 12a and 12b will be described.

  As shown in FIGS. 2 and 3, the wire guide portion 12 a is a plurality of ridges provided on the lower surface of the upper insulating substrate 12. A conductive pattern is not provided in a region on the lower surface of the upper insulating substrate 12 facing the bonding wires 26a, and the insulating substrate is exposed, and the wire guide portion 12a is provided in that region. Each ridge extends substantially parallel to each bonding wire 26a. Further, the height of the wire guide portion 12a is substantially the same as the diameter of the bonding wire 26a. One bonding wire 26a passes between adjacent ridges. Therefore, the wire guide portion 12a can regulate the position of the bonding wire 26a.

  Here, the curved shape of the bonding wire 26a will be described. The bonding wire 26a is joined to the first electrode 21a of the front semiconductor element 20a and the control terminal 18 by wire bonding. Here, the wire bonding is a wire bonding method generally used in a semiconductor device. The length of the bonding wire 26a is slightly longer than the distance between the first electrode 21a and the control terminal 18 so that the wire is not cut in the wire bonding step. Therefore, the bonding wire 16a draws a loop between the first electrode 21a and the control terminal 18. Each bonding wire 26a is bent in a direction approaching the upper insulating substrate 12 in a wire bonding step so as not to contact an adjacent bonding wire.

  In an attempt to reduce the size and thickness of the semiconductor device 10, the bonding wires 26a approach the upper insulating substrate 12, and the distance between adjacent bonding wires 26a is reduced. Then, there is a possibility that the bonding wire 26a is short-circuited by contact with the conductor pattern provided on the upper insulating substrate 12 or the adjacent bonding wire. Therefore, in the semiconductor device 10 of the embodiment, the short circuit is prevented by providing the wire guide portion 12a in the exposed region of the upper insulating substrate 12 to regulate the position of the bonding wire 26a.

  As shown in FIG. 2, the distance between the front semiconductor element 20a and the upper insulating substrate 12 is equal to the thickness of the upper main surface conductive pattern 25a. The thickness of the upper main surface conductive pattern 25a is not so large, for example, 0.3 mm. Therefore, when attaching the upper insulating substrate 12 to the front semiconductor element 20a to which the bonding wires 26a are joined in the assembling process, the upper insulating substrate 12 may come into contact with the bonding wires 26a. The bonding wire 26a pressed by the upper insulating substrate 12 tends to move in a direction approaching the adjacent bonding wire 26a, but since the ridge (wire guide portion 12a) regulates the position of the bonding wire 26a, the bonding wire 26a is pressed. Does not significantly deviate from the initial position. That is, the wire guide portion 12a prevents the bonding wire 26a from being short-circuited to an adjacent bonding wire.

  The resin (resin package 11) is filled around the bonding wire 26a. If the bonding wire 26a is deformed by the pressure of the resin filled during the manufacturing process and the resin package 11 is formed while being short-circuited with other conductors, the short-circuit cannot be eliminated. Such a semiconductor device is discarded as a defective product. By regulating the position of the bonding wire 26a by the wire guide portion 12a, deformation of the bonding wire 26a is prevented, and short-circuit is prevented. As a result, the production yield of the semiconductor device 10 is improved.

  As described above, in the semiconductor device 10 disclosed in this specification, the wire guide portion 12a regulates the position of the bonding wire 26a. Therefore, even if the distance between the upper insulating substrate 12 and the front semiconductor element 20a is reduced, it is possible to prevent the bonding wire 26a from being short-circuited with another conductor. That is, the semiconductor device 10 disclosed in this specification can achieve a reduction in thickness while preventing the bonding wire 26a from being short-circuited to another conductor. Note that the wire guide portion 12b also regulates the position of the bonding wire 26b connected to the first electrode 21b of the rear semiconductor element 20b.

  A modification of the wire guide will be described with reference to FIGS. The wire guide portion may be a groove as shown in FIGS. 4 and 5 instead of the ridge as described above. Hereinafter, the wire guide portions 12c and 12d which are modified examples of the wire guide portion will be described. As shown in FIG. 4, the wire guide portion 12c is a plurality of grooves, and each groove extends along a corresponding bonding wire 26a. The depth of the groove is substantially the same as the diameter of the bonding wire 26a. One bonding wire 26a passes through each groove. In other words, the wire guide portion 12c holds the bonding wire 26a. The groove-shaped wire guide portion 12c can also regulate the position of the bonding wire 26a similarly to the wire guide portion 12a described above. Therefore, even if the distance between the upper insulating substrate 12 and the front semiconductor element 20a is reduced, it is possible to prevent the bonding wire 26a from being short-circuited with another conductor. The wire guide portion 12d similarly regulates the position of the bonding wire 26b connected to the first electrode 21b of the rear semiconductor element 20b.

  Points to keep in mind regarding the technology described in the embodiment will be described. 3 and 5 show the cross-sectional shape of the wire guide that regulates the position of the bonding wire 26a. However, the cross-sectional shape of the wire guide is not limited to the shapes disclosed in FIGS. The wire guide may be a ridge or a groove having a semicircular cross section, for example. The corners of the ridges or grooves of the wire guide portion 12a may be chamfered.

  Further, in the semiconductor device 10 according to the present embodiment, the wire guide portion is configured by the upper insulating substrate. However, the shape of the wire guide portion for regulating the position of the bonding wire 26a as described above may be formed as a separate component and attached to the upper insulating substrate to form the wire guide portion.

  In the semiconductor device 10 of the present embodiment, a front semiconductor element 20a and a rear semiconductor element 20b are provided. In addition, four bonding wires 26a and 26b are provided, and four control terminals 18 and 19 are also set. However, the number and specific configuration are not particularly limited. Further, although the semiconductor device 10 in the present embodiment has the double-sided cooling structure as described above, the technology disclosed in this specification is not limited to the semiconductor device having the double-sided cooling structure. Further, the technology disclosed in this specification is not limited to the semiconductor device in the embodiment, that is, the RC-IGBT device.

  As described above, specific examples of the present invention have been described in detail, but these are merely examples, and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings can simultaneously achieve a plurality of objects, and has technical utility by achieving one of the objects.

10: Semiconductor device 11: Resin package 11a: Resin package upper surface 11b: Resin package lower surface 12: Upper insulating substrates 12a, 12b, 12c, 12d: Wire guide portions 14, 15, 16: Power terminals 17: Copper spacers 18, 19 : Control terminals 20a, 20b: semiconductor elements 21a, 21b: control pad (first electrode)
23a, 23b: collector electrode (second electrode)
24a, 24b: emitter electrode (third electrode)
25a, 25b: Upper main surface conductor patterns 26a, 26b: Bonding wires 27, 28, 29: Solder layer 32: Lower insulating substrate 35a, 35b: Upper rear surface conductor patterns 45a, 45b: Lower main surface conductor patterns 55a, 55b. : Lower backside conductor pattern

Claims (2)

A semiconductor element having a first electrode and a second electrode on a main surface;
A bonding wire connected to the first electrode;
An insulating substrate facing the main surface and the bonding wires, a conductive pattern having a predetermined thickness is formed on a surface facing the main surface, and the conductive pattern is connected to the second electrode;
With
The insulating substrate is exposed in a region of the insulating substrate facing the bonding wires,
A semiconductor device, wherein a wire guide for regulating a position of the bonding wire is provided in the region. Each of the plurality of bonding wires is connected to each of the plurality of first electrodes,
2. The semiconductor device according to claim 1, wherein the wire guide portion is a wall separating the adjacent bonding wires or a groove in which each bonding wire is locked. 3.