JP2020005259A - Semiconductor device - Google Patents

Abstract

An object of the present invention is to suppress the influence of crosstalk between oscillation signals having different frequencies. A semiconductor device (1) includes a first circuit section to which power is supplied from at least a first power supply system, and a second circuit section to which power is supplied from a second power supply system different from the first power supply system. and a circuit unit. The first circuit section includes a first buffer to which power is supplied from the first power supply system and to which the first oscillation signal generated by the first oscillation signal generation circuit is input. The first buffer controls whether to output one oscillation signal to the second circuit unit based on the first control signal. The second buffer is supplied with power from the second power supply system and receives the second oscillation signal generated by the second oscillation signal generating circuit from the second circuit section. The second buffer controls whether or not to output the input second oscillation signal to the first processing unit to which power is supplied from the first power supply system, based on the second control signal. . [Selection drawing] Fig. 1

Description

  Embodiments of the present invention relate to a semiconductor device.

  In wireless communication, MIMO (Multiple Input and Multiple Output) has been proposed as a standard for performing communication using a plurality of channels on both a transmitting side and a receiving side. Further, research and development for the practical use of multi-user MIMO in which MIMO is partially made multi-user has been actively performed.

  In order to realize such a communication environment, two oscillation signals having frequencies close to an IQ signal generator for generating an IQ modulation signal required for a transmitter or a receiver in one semiconductor device. Need to be supplied. However, if two transmission lines of oscillation signals having frequencies close to each other are run in parallel, a problem of crosstalk between the transmission lines occurs.

  Further, it is necessary to provide a changeover switch for switching and supplying two oscillation signals to a plurality of IQ signal generators. Even in this changeover switch, a problem of crosstalk between adjacent changeover switches is required. Occurs.

Patent No. 4627033

  An object of the present embodiment is to provide a semiconductor device in which the influence of crosstalk between oscillation signals having different frequencies is suppressed.

  The semiconductor device according to the present embodiment includes a first circuit unit to which power is supplied from a first power supply system, and a second circuit to which power is supplied from a second power supply system different from the first power supply system. And at least a part. The first circuit unit is a first buffer to which power is supplied from the first power supply system and to which the first oscillation signal generated by the first oscillation signal generation circuit is input. A first buffer capable of controlling whether or not to output the one oscillation signal to the second circuit unit based on the control signal of (a), a power supplied from a second power supply system, and a second oscillation A second buffer that receives the second oscillation signal generated by the signal generation circuit from the second circuit unit, and converts the second oscillation signal that is input based on the second control signal into the first buffer; And a second buffer capable of controlling whether or not to output to the first processing unit to which power is supplied from the power supply system.

FIG. 3 is a layout diagram of a power supply system in the semiconductor device according to the first embodiment. 2A and 2B are a circuit diagram and a block diagram illustrating a part of a circuit configuration in the semiconductor device according to the first embodiment. FIG. 9 is a diagram for explaining a circuit state when a second oscillation signal generated by a second oscillation signal generation circuit is supplied to first to fourth circuit units. The first oscillation signal generated by the first oscillation signal generation circuit is supplied to the first circuit section, and the second oscillation signal generated by the second oscillation signal generation circuit is supplied to the second to fourth signals. FIG. 4 is a diagram for explaining a circuit state when the circuit is supplied to the circuit section of FIG. The first oscillation signal generated by the first oscillation signal generation circuit is supplied to the first and second circuit units, and the second oscillation signal generated by the second oscillation signal generation circuit is supplied to the third oscillation unit. FIG. 14 is a diagram for explaining a circuit state when the circuit is supplied to the fourth to fourth circuit units. The first oscillation signal generated by the first oscillation signal generation circuit is supplied to the first to third circuit units, and the second oscillation signal generated by the second oscillation signal generation circuit is output to the fourth oscillation signal generator. FIG. 4 is a diagram for explaining a circuit state when the circuit is supplied to the circuit section of FIG. FIG. 3 is a diagram for explaining a circuit state when a first oscillation signal generated by a first oscillation signal generation circuit is supplied to first to fourth circuit units. FIG. 4 is a diagram illustrating an example of a specific circuit configuration of a buffer that can individually control whether to output an input signal based on a control signal. FIG. 2 is a block circuit diagram for functionally explaining the semiconductor device according to the first embodiment. FIG. 3 is a diagram illustrating a modification of the semiconductor device according to the first embodiment, and is a diagram corresponding to FIG. 2. FIG. 6 is a diagram illustrating another modified example of the semiconductor device according to the first embodiment, and is a diagram corresponding to FIG. 2. FIGS. 7A and 7B are a circuit diagram and a block diagram illustrating a part of a circuit configuration in a semiconductor device according to a second embodiment. FIGS. FIG. 9 is a diagram for explaining a circuit state in a case where a first oscillation signal is supplied to first to fourth circuit units or a case where a second oscillation signal is supplied to the first to fourth circuit units. is there. When the first oscillation signal is supplied to the first circuit portion and the second oscillation signal is supplied to the second to fourth circuit portions, or when the second oscillation signal is supplied to the first circuit portion. FIG. 9 is a diagram for explaining a circuit state when the first oscillation signal is supplied to the second to fourth circuit units. When the first oscillation signal is supplied to the first and second circuit units and the second oscillation signal is supplied to the third and fourth circuit units, or when the second oscillation signal is supplied to the first to second circuit units. FIG. 9 is a diagram for explaining a circuit state in a case where a first oscillation signal is supplied to a second circuit portion and a first oscillation signal is supplied to third and fourth circuit portions. FIG. 13 is a diagram illustrating a modification of the semiconductor device according to the second embodiment, and is a diagram corresponding to FIG. 12. FIG. 13 is a diagram illustrating another modified example of the semiconductor device according to the second embodiment, and is a diagram corresponding to FIG. 12.

  Hereinafter, a semiconductor device according to an embodiment will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals, and repeated description will be made only when necessary.

[First Embodiment]
The semiconductor device according to the first embodiment is provided with a plurality of circuit units having different power supply systems, each circuit unit receiving a buffer that outputs an oscillation signal to an adjacent circuit unit, and receiving an oscillation signal from the adjacent circuit unit. By providing buffers and operating these buffers on the power supply system of each circuit unit, crosstalk between different oscillation signals is suppressed. This will be described in more detail below.

  FIG. 1 is a layout diagram of a power supply system in a semiconductor device 1 according to the present embodiment. As shown in FIG. 1, the semiconductor device 1 according to the present embodiment has a plurality of power supply systems. Specifically, power supply circuits 20 to 26 that receive power supply from power supply 10, first oscillation signal generation circuit 30 that receives power supply from power supply circuit 20, and power supply circuits 21 to 24 respectively receive power supply The power supply circuit includes first to fourth circuit units 40 to 43 that receive power, a second oscillation signal generation circuit 31 that receives power from the power supply circuit 25, and a control circuit 50 that receives power from the power supply circuit 26. It is configured.

  The power supply 10 is a power supply source provided outside the semiconductor device 1 and includes, for example, a primary battery such as an alkaline manganese dry battery, a secondary battery such as a lithium ion battery, a DC-converted household power supply, and the like. .

  The power supply circuits 20 to 26 stabilize the power supplied from the power supply 10 and perform voltage conversion and the like as necessary, and perform the first and second oscillation signal generation circuits 30 and 31 and the first to fourth oscillation signal generation circuits. A power supply system for supplying the circuit units 40 to 43 and the control circuit 50 is formed. Further, the power supply circuits 20 to 26 have a role of interrupting the signals generated in the circuits provided in the different power supply systems so as not to affect each other. For example, even if the voltage of the power supply system of the power supply circuit 21 fluctuates due to the operation of the first circuit unit 40, the voltage of the power supply system of another power supply circuit is not affected. Have been.

  The first and second oscillation signal generation circuits 30 and 31 generate oscillation signals used in the first to fourth circuit units 40 to 43. Specifically, the first oscillation signal generation circuit 30 generates a first oscillation signal having a first frequency and supplies the first oscillation signal to the first to fourth circuit units 40 to 43. The second oscillation signal generation circuit 31 generates a second oscillation signal having a second frequency different from the first frequency and supplies the second oscillation signal to the first to fourth circuit units 40 to 43.

  The control circuit 50 performs overall control of various operations performed in the semiconductor device 1. In the present embodiment, in particular, a control signal for controlling the first and second oscillation signal generation circuits 30 and 31 is generated, and the first to fourth circuit units 40 to 43 are controlled. To generate a control signal.

  When the semiconductor device 1 is used for communication, it is common practice to provide a plurality of power supply systems in this way to reduce signal interference between different systems. Note that the number of power supply systems varies depending on the specifications of the semiconductor device 1, communication standards, and the like.

  FIG. 2 is a circuit diagram and a block diagram illustrating a part of the circuit configuration in the semiconductor device 1 according to the present embodiment.

  As shown in FIG. 2, the first oscillation signal generation circuit 30 generates a first oscillation signal of a first frequency and outputs the first oscillation signal to the first circuit unit 40. In the present embodiment, for example, the first frequency is 2 GHz, and an oscillation signal of 2 GHz is input to the first circuit unit 40.

  On the other hand, the second oscillation signal generation circuit 31 generates a second oscillation signal of the second frequency and outputs the second oscillation signal to the fourth circuit unit 43. In the present embodiment, for example, the second frequency is 5 GHz, and an oscillation signal of 5 GHz is input to the fourth circuit unit 43. Note that 2 GHz and 5 GHz are merely examples relating to the first frequency and the second frequency. For example, the first frequency is 5.50 GHz and the second frequency is 5.52 GHz. In the present embodiment, the case where the first frequency of the oscillation signal and the second frequency of the second oscillation signal are closer to each other is also within the assumed range.

  The first circuit section 40 includes an IQ signal generator 60, a transmitter 70, and a receiver 80. The IQ signal generator 60 is a circuit that generates an I signal, which is an in-phase component, and a Q signal, which is a quadrature component, used for modulation and demodulation.

  The transmitter 70 is a circuit that generates a transmission wave by orthogonally modulating a transmission signal using the I signal and the Q signal generated by the IQ signal generator 60. The generated transmission wave is output from an antenna or the like (not shown).

  The receiver 80 is a circuit that performs quadrature demodulation of a reception wave received via an antenna or the like using the I signal and the Q signal generated by the IQ signal generator 60 to generate a reception signal. The generated reception signal is used in the semiconductor device 1 for various processes.

  The IQ signal generator 60, the transmitter 70, and the receiver 80 are examples of a first processing unit of the first circuit unit 40 in the present embodiment, and operate by power supplied from a power supply system of the power supply circuit 21. I do. Further, the first circuit unit 40 may include, as a first processing unit, a circuit that performs other processing in addition to the IQ signal generator 60, the transmitter 70, and the receiver 80.

  Similarly to the first circuit unit 40, the second circuit unit 41 includes an IQ signal generator 61, a transmitter 71, and a receiver 81 as a second processing unit, and the third circuit unit 42 includes The third processing unit includes an IQ signal generator 62, a transmitter 72, and a receiver 82, and the fourth circuit unit 43 includes an IQ signal generator 63, a transmitter 73, and a receiver as fourth processing units. 83.

  Further, the first circuit section 40 includes a capacitor 90a, a buffer 90b, a capacitor 90c, a buffer 90d, a capacitor 90e, and a buffer in addition to the IQ signal generator 60, the transmitter 70, and the receiver 80. 90f, a capacitor 90g, a capacitor 90h, and a buffer 90i.

  The output of the first oscillation signal in the first oscillation signal generation circuit 30 is connected to the buffer 90b via the capacitor 90a. Therefore, the first oscillation signal of the first frequency is input from the first oscillation signal generation circuit 30 to the buffer 90b. Here, in the present embodiment, “input” refers to a case where a signal is indirectly input via another element or the like and a case where a signal is directly input without passing through another element or the like. Is used to mean both.

  The output of the buffer 90b is connected to the input of the buffer 90d via the capacitor 90c, and is connected to the input of the buffer 90i via the capacitor 90h. Further, the output of the buffer 90f is also connected to the input of the buffer 90i via the capacitor 90g. Then, the output of the buffer 90i is input to the IQ signal generator 60.

  The buffers 90b, 90d, and 90f are buffers that can individually control whether to output an input signal based on a control signal. These control signals are individually generated by the control circuit 50 shown in FIG. 1 and input to the buffers 90b, 90d, and 90f, respectively. That is, the buffers 90b, 90d, and 90f, to which the control signal for instructing to output the input signal is input, buffer and output the input oscillation signal. On the other hand, the input control signal is not output to the buffers 90b, 90d, and 90f to which the control signal instructing not to output the input signal is input.

  The buffer 90i does not need to be a buffer that can individually control whether to output an input signal based on a separate control signal. That is, a buffer that outputs the input signal non-selectively is sufficient. However, similarly to the buffers 90b, 90d, and 90f, the buffer 90i may be configured by a buffer capable of individually controlling whether to output an input signal based on a separate control signal. In this case, a control signal for instructing to output the input signal is constantly input to the buffer 90i during operation.

  The buffers 90b, 90d, 90f, and 90i operate on the power supplied from the first power supply system, which is the power supply system of the power supply circuit 21, similarly to the IQ signal generator 60, the transmitter 70, and the receiver 80. .

  The second circuit unit 41 also includes a capacitor 91a, a buffer 91b, a capacitor 91c, a buffer 91d, a capacitor 91e, and a buffer 91f in addition to the above-described IQ signal generator 61, transmitter 71, and receiver 81. , A capacitor 91g, a capacitor 91h, a buffer 91i, a capacitor 91j, and a buffer 91k.

  The capacitor 91a, the buffer 91b, the capacitor 91c, the buffer 91d, the buffer 91e, the buffer 91f, the capacitor 91g, the capacitor 91h, and the buffer 91i in the second circuit unit 41 are the same as the capacitor 90a and the buffer 90b in the first circuit unit 40 described above. Capacitor 90c, buffer 90d, capacitor 90e, buffer 90f, capacitor 90g, capacitor 90h, and buffer 90i respectively correspond.

  Further, the output of the buffer 91f is connected to the input of the buffer 91i via a capacitor 91j in addition to being connected to the input of the buffer 91i via a capacitor 91g. The buffer 91k is a buffer that can individually control whether to output an input signal based on a control signal, similarly to the buffers 91b, 91d, and 91f.

  The output of the buffer 90d of the first circuit unit 40, the input of the buffer 90f of the first circuit unit 40 via the capacitor 90e, the input of the buffer 91b of the second circuit unit 41 via the capacitor 91a, The output of the buffer 91k of the second circuit unit 41 is commonly connected. That is, the transmission path between the buffer 90d and the buffer 91b and the transmission path between the buffer 91k and the buffer 90f are shared and become one. Here, when the oscillation signal exchanged between the first circuit unit 40 and the second circuit unit 41 is a single-phase signal, there is one physical signal line in one transmission line. When the oscillation signal exchanged between the first circuit unit 40 and the second circuit unit 41 is a differential signal, there are two physical signal lines in one transmission line.

  The buffers 91b, 91d, 91f, 91k, and 91i use the power supplied from the second power supply system, which is the power supply system of the power supply circuit 22, similarly to the IQ signal generator 61, the transmitter 71, and the receiver 81. Operate.

  The third circuit unit 42 has a configuration similar to that of the second circuit unit 41. In addition to the above-described IQ signal generator 62, transmitter 72, and receiver 82, a capacitor 92a, a buffer 92b, and a capacitor 92c , A buffer 92d, a capacitor 92e, a buffer 92f, a capacitor 92g, a capacitor 92h, a buffer 92i, a capacitor 92j, and a buffer 92k.

  The capacitor 92a, the buffer 92b, the capacitor 92c, the buffer 92d, the buffer 92e, the buffer 92f, the capacitor 92g, the capacitor 92h, the buffer 92i, the capacitor 92j, and the buffer 92k in the third circuit unit 42 are the same as those in the second circuit unit 41 described above. Capacitor 91a, buffer 91b, capacitor 91c, buffer 91d, capacitor 91e, buffer 91f, capacitor 91g, capacitor 91h, buffer 91i, capacitor 91j, and buffer 91k, respectively.

  The output of the buffer 91d of the second circuit unit 41, the input of the buffer 91f via the capacitor 91e of the second circuit unit 41, and the input of the buffer 92b via the capacitor 92a of the third circuit unit 42 , And the output of the buffer 92k of the third circuit section 42 are commonly connected. That is, the transmission path between the buffer 91d and the buffer 92b and the transmission path between the buffer 92k and the buffer 91f are shared and become one.

  The buffers 92b, 92d, 92f, 92k, and 92i use the power supplied from the third power supply system, which is the power supply system of the power supply circuit 23, similarly to the IQ signal generator 62, the transmitter 72, and the receiver 82. Operate.

  The fourth circuit unit 43 includes a capacitor 93a, a buffer 93b, a capacitor 93e, a buffer 93f, a capacitor 93g, and a capacitor 93h, in addition to the IQ signal generator 63, the transmitter 73, and the receiver 83 described above. , A buffer 93i, a capacitor 93j, and a buffer 93k.

  The capacitor 93a, the buffer 93b, the capacitor 93e, the buffer 93f, the capacitor 93g, the capacitor 93h, the buffer 93i, the capacitor 93j, and the buffer 93k in the fourth circuit 43 are the same as the capacitor 92a and the buffer 92b in the third circuit 42 described above. A capacitor 92e, a buffer 92f, a capacitor 92g, a capacitor 92h, a buffer 92i, a capacitor 92j, and a buffer 92k correspond to each other.

  However, the output of the second oscillation signal in the second oscillation signal generation circuit 31 is connected to the input of the buffer 93f via the capacitor 93e. For this reason, the second oscillation signal of the second frequency is input from the second oscillation signal generation circuit 31 to the buffer 93f.

  The output of the buffer 92d of the third circuit unit 42, the input of the buffer 92f via the capacitor 92e of the third circuit unit 42, and the input of the buffer 93b via the capacitor 93a of the fourth circuit unit 43 , And the output of the buffer 93k of the fourth circuit section 43 are commonly connected. That is, the transmission path between the buffer 92d and the buffer 93b and the transmission path between the buffer 93k and the buffer 92f are shared and become one.

  The buffers 93b, 93f, 93k, and 93i operate on the power supplied from the fourth power supply system, which is the power supply system of the power supply circuit 24, similarly to the IQ signal generator 63, the transmitter 73, and the receiver 83. .

  A capacitor is connected to the input of each buffer, which is provided to cut off the DC component of the signal by the capacitor. That is, the DC components of the first oscillation signal and the second oscillation signal are cut off by each capacitor.

  The above is the circuit configuration of the semiconductor device 1 according to the present embodiment. Next, the operation of the semiconductor device 1 will be described.

  FIG. 3 is a diagram for explaining a circuit state when the second oscillation signal generated by the second oscillation signal generation circuit 31 is supplied to the first to fourth circuit units 40 to 43. In this embodiment, this state is referred to as a first mode.

  As shown in FIG. 3, in the first mode, a control signal of an instruction not to output the input signal is input to buffers 90b, 90d, 91b, 91d, 92b, 92d, and 93d, and buffer 90f , 91k, 91f, 92k, 92f, 93k, and 93f receive control signals for instructing to output the input signals.

  Therefore, the first oscillation signal generated by the first oscillation signal generation circuit 30 is cut off by the buffer 90b and is not supplied to any of the first to fourth circuit units 40 to 43. On the other hand, the second oscillation signal generated by the second oscillation signal generation circuit 31 passes through the buffers 93f, 93k, 92f, 92k, 91f, 91k, and 90f in order, and the first to fourth circuit units 40 To IQ signal generators 60 to 63.

  FIG. 4 shows a case where the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the first circuit section 40 and the second oscillation signal generated by the second oscillation signal generation circuit 31 is generated. Is a diagram for describing a circuit state in a case where is supplied to the second to fourth circuit units 41 to 43. In the present embodiment, this state is referred to as a second mode.

  As shown in FIG. 4, in the second mode, a control signal for instructing not to output the input signal is input to the buffers 90d, 90f, 91b, 91d, 91k, 92b, 92d, and 93d. The buffers 90b, 91f, 92k, 92f, 93k, and 93f receive control signals for outputting the input signals.

  Therefore, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the IQ signal generator 60 of the first circuit unit 40, but is cut off by the buffer 90d. On the other hand, the second oscillation signal generated by the second oscillation signal generation circuit 31 passes through the buffers 93f, 93k, 92f, 92k, and 91f in this order, and the IQ of the second to fourth circuit units 41 to 43 is changed. The signals are supplied to the signal generators 61 to 63, but are cut off by the buffer 91k.

  At this time, the buffers 90d, 90f, 91b, and 91k in the area A1 are all in an inactive state in which the input signal is not output. In other words, the first circuit unit 40 and the second circuit unit 41 are separated by two buffers 90d and 91b having different power supply systems, and two buffers 90f and 91k having different power supply systems. Will be separated by one buffer. Therefore, a high isolation between the first oscillation signal and the second oscillation signal can be secured, and the occurrence of crosstalk is suppressed.

  FIG. 5 shows a case where the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the first and second circuit units 40 to 41, and the first oscillation signal is generated by the second oscillation signal generation circuit 31. FIG. 9 is a diagram for explaining a circuit state when a second oscillation signal is supplied to third and fourth circuit units 42 to 43. In the present embodiment, this state is referred to as a third mode.

  As shown in FIG. 5, in the third mode, a control signal of an instruction not to output the input signal is input to the buffers 90f, 91d, 91f, 91k, 92b, 92d, 92k, and 93b. The buffers 90b, 90d, 91b, 92f, 93k, and 93f receive control signals for instructing to output the input signals.

  Therefore, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the IQ signal generators 60 to 61 of the first and second circuit units 40 to 41, but is supplied to the buffer 91d. Will be shut off. On the other hand, the second oscillation signal generated by the second oscillation signal generation circuit 31 passes through the buffers 93f, 93k, and 92f in order, and passes through the IQ signal generator 62 of the third and fourth circuit units 42 to 43. To 63, but is cut off by the buffer 92k.

  At this time, the buffers 91d, 91f, 92b, and 92k in the area A2 are all in an inactive state in which the input signal is not output. That is, the second circuit unit 41 and the third circuit unit 42 are separated by two buffers 91 d and 92 b having different power systems, and two buffers 91 f and 92 k having different power systems. Will be separated by one buffer. Therefore, a high isolation between the first oscillation signal and the second oscillation signal can be secured, and the occurrence of crosstalk is suppressed.

  FIG. 6 shows a case where the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the first to third circuit units 40 to 42 and generated by the second oscillation signal generation circuit 31. FIG. 9 is a diagram for explaining a circuit state when a second oscillation signal is supplied to a fourth circuit unit 43. In the present embodiment, this state is referred to as a fourth mode.

  As shown in FIG. 6, in the fourth mode, a control signal for instructing not to output the input signal is input to the buffers 90f, 91f, 91k, 92d, 92f, 92k, 93b, and 93k. The buffers 90b, 90d, 91b, 91d, 92b, and 93f receive control signals for outputting the input signals.

  For this reason, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the IQ signal generators 60 to 62 of the first to third circuit units 40 to 42, but is supplied to the buffer 92d. Will be shut off. On the other hand, the second oscillation signal generated by the second oscillation signal generation circuit 31 is supplied to the IQ signal generator 63 of the fourth circuit section 43 via the buffer 93f, but cut off by the buffer 93k. Is done.

  At this time, the buffers 92d, 92f, 93b, and 93k in the area A3 are all in an inactive state in which the input signal is not output. That is, the third circuit unit 42 and the fourth circuit unit 43 are separated by two buffers 92 d and 93 b having different power systems, and two buffers 92 f and 93 k having different power systems. Will be separated by one buffer. Therefore, a high isolation between the first oscillation signal and the second oscillation signal can be secured, and the occurrence of crosstalk is suppressed.

  FIG. 7 is a diagram for explaining a circuit state when the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the first to fourth circuit units 40 to 43. In the present embodiment, this state is referred to as a fifth mode.

  As shown in FIG. 7, in the fifth mode, a control signal indicating that the input signal is not output is input to the buffers 90f, 91f, 91k, 92f, 92k, 93f, and 93k. , 90d, 91b, 91d, 92b, 92d, and 93b receive control signals for instructing to output the input signals.

  Therefore, the first oscillation signal generated by the first oscillation signal generation circuit 30 is supplied to the IQ signal generators 60 to 63 of the first to fourth circuit units 40 to 43. On the other hand, the second oscillation signal generated by the second oscillation signal generation circuit 31 is cut off by the buffer 93f and is not supplied to any of the first to fourth circuit units 40 to 43.

  Next, a circuit configuration of a buffer that can individually control whether to output an input signal will be described with reference to FIG. FIG. 8 is a diagram illustrating an example of a specific circuit configuration of a buffer that can individually control whether to output an input signal based on a control signal.

  As shown in FIG. 8, the buffer includes P-channel MOS transistors P1, P2, P3, N-channel MOS transistors N1, N2, N3, a resistor R1, and an inverter circuit IN1.

  The control terminal of the P-channel MOS transistor P1, the control terminal of the N-channel MOS transistor N1, and one end of the resistor R1 are connected to input terminals, respectively, from which the input signal IN is input. The first terminal of the P-channel MOS transistor P1 is connected to the first power supply Vdd, and the first terminal of the N-channel MOS transistor N1 is connected to the second power supply Vcc.

  Further, P-channel MOS transistors P2 and P3 and N-channel MOS transistors N2 and N3 are connected in series between the first power supply Vdd and the second power supply Vcc. The control terminal of the P-channel MOS transistor P3 and the control terminal of the N-channel MOS transistor N2 are commonly connected to the second terminal of the P-channel MOS transistor P1, the second terminal of the N-channel MOS transistor N1, and the other end of the resistor R1. ing.

  The control signal Enable generated by the control circuit 50 is input to the control terminal of the N-channel MOS transistor N3. The control signal Enable is also input to the inverter circuit IN1, inverted, and then input to the control terminal of the P-channel MOS transistor P2.

  Therefore, when the high-level control signal Enable is input, the P-channel MOS transistor P2 and the N-channel MOS transistor N3 are turned on, and this buffer buffers the input signal IN. A circuit that outputs the output signal OUT. On the other hand, when the low-level control signal Enable is input, the P-channel MOS transistor P2 and the N-channel MOS transistor N3 are turned off, and this buffer is a circuit that does not output the input signal. That is, the high-level control signal is a control signal for instructing to output the input signal, and the low-level control signal is a control signal for not outputting the input signal.

  In the present embodiment, the input signal IN and the output signal OUT are either the first oscillation signal or the second oscillation signal. The first power supply Vdd and the second power supply Vcc are supplied from the power supply circuits 20 to 26 in FIG. More specifically, the first power supply Vdd and the second power supply Vcc are supplied from the power supply circuit 21 to the buffers 90b, 90d, and 90f in the first circuit unit 40, and the buffer 91b in the second circuit unit 41 , 91d, 91f, and 91k are supplied with the first power supply Vdd and the second power supply Vcc from the power supply circuit 22, and the buffers 92b, 92d, 92f, and 92k in the third circuit section 42 are supplied with the first power supply Vdd and the second power supply Vcc from the power supply circuit 23. The first power supply Vdd and the second power supply Vcc are supplied, and the buffers 93b, 93f, and 93k in the fourth circuit unit 43 are supplied with the first power supply Vdd and the second power supply Vcc from the power supply circuit 24.

  As described above, according to the semiconductor device 1 of the present embodiment, the buffer for buffering the first oscillation signal or the second oscillation signal is supplied to each of the first to fourth circuit units 40 to 43. The operation was performed with the electric power supplied. Further, each of the first to fourth circuit units 40 to 43 is separated by two inactive buffers. For this reason, high isolation between the first oscillation signal and the second oscillation signal can be ensured, and occurrence of crosstalk can be suppressed.

  Further, since the first oscillation signal and the second oscillation signal are exchanged between each of the first to fourth circuit units 40 to 43 using one transmission line, The layout area can be suppressed. In particular, when the frequency of the first oscillation signal and the frequency of the second oscillation signal are close to each other, it is necessary to lay out the transmission path of the two signals as far as possible, so that the layout area increases. However, it is possible to reduce the layout area by using a single transmission line as in this embodiment.

  FIG. 9 is a block circuit diagram for functionally explaining the semiconductor device 1 according to the present embodiment. As shown in FIG. 9, in the semiconductor device 1, the first oscillation signal or the second oscillation signal that has reached the first to fourth circuit units 40 to 43 via an alternative path does not intersect. , IQ signal generators 60 to 63. In order to realize such a function, it can be said that the first to fourth circuit units 40 to 43 include selection circuits SL1, SL2, SL3 and buffers BF1, BF2, respectively.

  The selection circuits SL1, SL2, and SL3 are circuits that output one of the input first oscillation signal and the second oscillation signal. Which of the oscillation signals is output is input from the control circuit 50. Switching is performed based on a control signal. The buffers BF1 and BF2 are circuits that buffer and output the input first oscillation signal or second oscillation signal, respectively.

  The first oscillation signal generated by the first oscillation signal generation circuit 30 and the second oscillation signal generated by the second oscillation signal generation circuit 31 are selected by switching control of the selection circuits SL1 and SL2. The signal reaches the first to fourth circuit units 40 to 43 via a path formed in a unified manner, and is supplied to the IQ signal generators 60 to 63 without switching by the switching control of the selection circuit SL3. That is, by controlling the selection circuits SL1, SL2, and SL3 by the control signal, the first oscillation signal and the second oscillation signal are supplied to the IQ signal generators 60 to 63 without intersecting.

  As shown in FIG. 10, the semiconductor device 1 according to the present embodiment can have two transmission paths between each of the first to fourth circuit units 40 to 43. That is, the transmission line for the first oscillation signal and the transmission line for the second oscillation signal may be provided separately. In this case, the layout area of the transmission line increases accordingly, but the first oscillation signal and the second oscillation signal are supplied to any combination of the first to fourth circuit units 40 to 43. Will be able to do it. For example, the first oscillation signal is supplied from the first oscillation signal generation circuit 30 to the first circuit section 40 and the third circuit section 42, and the second oscillation signal is supplied to the second circuit section 41 and the fourth circuit section 43. The second oscillation signal can be supplied from the oscillation signal generation circuit 31 of FIG.

  As shown in FIG. 11, in the semiconductor device 1 according to the present embodiment, the capacitor 90a and the buffer 90b are provided near the output of the first oscillation signal generation circuit 30, and the same power supply as that of the first oscillation signal generation circuit 30 is used. The buffer 90b operates based on the power obtained from the power supply system of the circuit 20, and the capacitor 93e and the buffer 93f are provided near the output of the second oscillation signal generation circuit 31, and are the same as those of the second oscillation signal generation circuit 31. The buffer 93f may operate based on the power obtained from the power supply system of the power supply circuit 25.

[Second embodiment]
The second embodiment is a modification of the first embodiment described above, in which the first oscillation signal generation circuit 30 generates the first oscillation signal and the second oscillation signal, and the first and second circuit units The second oscillation signal generation circuit 31 also generates the first oscillation signal and the second oscillation signal and supplies the first oscillation signal and the second oscillation signal to the first to fourth circuit units 40 to 43. With such a configuration, the layout area can be reduced. Hereinafter, portions different from the above-described first embodiment will be described.

  FIG. 12 is a circuit diagram and a block diagram illustrating a part of the circuit configuration of the semiconductor device 1 according to the present embodiment, and corresponds to FIG. 2 of the above-described first embodiment.

  As shown in FIG. 12, the first oscillation signal generation circuit 30 in the present embodiment generates both a first oscillation signal of a first frequency and a second oscillation signal of a second frequency, Output to the selection circuit MUX1. As in the first embodiment described above, for example, the first frequency is 2 GHz, and the second frequency is 5 GHz.

  A selection control signal from the control circuit 50 shown in FIG. 1 is input to the selection circuit MUX1, and based on the control signal, the selection circuit MUX1 outputs the first oscillation signal and the second oscillation signal. Or the selection circuit MUX1 does not output any of the input first oscillation signal and second input oscillation signal. The selection circuit MUX1 operates with power supplied from the power supply system of the power supply circuit 20, similarly to the first oscillation signal generation circuit 30.

  The second oscillation signal generation circuit 31 also generates both a first oscillation signal of the first frequency and a second oscillation signal of the second frequency, and outputs them to the selection circuit MUX2. Similarly to the first oscillation signal generation circuit 30, for example, the first frequency is 2 GHz, and the second frequency is 5 GHz. Note that, as in the first embodiment described above, 2 GHz and 5 GHz are merely examples relating to the first frequency and the second frequency. For example, the first frequency is 5.50 GHz and the second frequency is In the present embodiment, a case where the first frequency of the first oscillation signal is closer to the second frequency of the second oscillation signal, such as 5.52 GHz, is also assumed.

  The selection control signal from the control circuit 50 shown in FIG. 1 is also input to the selection circuit MUX2, and based on this control signal, the selection circuit MUX2 outputs the second oscillation signal and the second oscillation signal. Output either one. The selection circuit MUX2 operates with the power supplied from the power supply circuit 25, similarly to the second oscillation signal generation circuit 31.

  The first oscillation signal or the second oscillation signal output from the selection circuit MUX1 is supplied to the first circuit unit 40. Specifically, the signal is input to the buffer 90d via the capacitor 90c, and is input to the buffer 90i via the capacitor 90h.

  The first circuit unit 40 includes a first IQ signal generator 100a, a second IQ signal generator 100b, a first transceiver 110a, and a second transceiver 110b, and includes a buffer 90i. Receives the first oscillation signal or the second oscillation signal. That is, when the first oscillation signal is being input from the buffer 90i, the first IQ signal generator 100a operates, and transmission and reception are performed using the first transceiver 110a. On the other hand, when the second oscillation signal is being input from the buffer 90i, the second IQ signal generator 100b operates, and transmission and reception are performed using the second transceiver 110b.

  In FIG. 12, the “transmitter” and the “receiver” are combined and expressed as one block as a “transmitter / receiver”, but the “transmitter” and the “receiver” are separated as separate blocks. The functions are the same as those of the first embodiment.

  Similarly, the buffers 91i, 92i, and 93i of the second to fourth circuit units 41 to 43 output the first oscillation signal or the second oscillation signal, respectively, and output the first oscillation signal. The first IQ signal generators 101a, 102a, and 103a operate, transmit and receive using the first transceivers 111a, 112a, and 113a, and output the second oscillation signal. , The second IQ signal generators 101b, 102b, and 103b operate, and transmission and reception are performed using the second transceivers 111b, 112b, and 113b.

  However, the first circuit section 40 and the second circuit section 41 receive the first oscillation signal or the second oscillation signal from both the first oscillation signal generation circuit 30 and the second oscillation signal generation circuit 31. Can be supplied to the third circuit unit 42 and the fourth circuit unit 43, the first oscillation signal or the second oscillation signal can be supplied from the second oscillation signal generation circuit 31, The configuration is such that neither the first oscillation signal nor the second oscillation signal can be supplied from the first oscillation signal generation circuit 30.

  Further, unlike the above-described first embodiment, two transmission paths are provided between the first circuit unit 40 and the second circuit unit 41. That is, one dedicated transmission path is provided between the buffer 90d and the buffer 91b, and one dedicated transmission path is provided between the buffer 90f and the buffer 91k.

  Further, the buffer 93k provided in the fourth circuit section 43 non-selectively outputs the input first oscillation signal or the second oscillation signal, so that the buffer 93k is input based on a separate control signal. It is not a buffer that can control whether to output a signal. However, similarly to the first embodiment described above, the buffer 93k can be configured by a buffer capable of controlling whether to output an input signal based on a separate control signal. In this case, a control signal for instructing to output the input signal is constantly input to the buffer 93k during operation.

  The above is the circuit configuration of the semiconductor device 1 according to the present embodiment. Next, the operation of the semiconductor device 1 will be described.

<First oscillation signal × 4 or second oscillation signal × 4>
FIG. 13 illustrates the case where the first oscillation signal is supplied to the first to fourth circuit units 40 to 43 or the case where the second oscillation signal is supplied to the first to fourth circuit units 40 to 43. FIG. 4 is a diagram for explaining a circuit state. In this embodiment, this state is referred to as a first mode.

  As shown in FIG. 13, in the first mode, a control signal instructing not to output an input signal is input to buffers 90d and 91b, and input to buffer 90f, 91k, 91f and 92k. A control signal for outputting a signal is input. In addition, a control signal that outputs neither the first oscillation signal nor the second oscillation signal is input to the selection circuit MUX1.

  Therefore, when a control signal for selecting the first oscillation signal is input to the selection circuit MUX2, the first to fourth circuit units are sequentially passed through the buffers 93k, 92k, 91f, 91k, and 90f. The first oscillation signal is supplied to 40 to 43.

  On the other hand, when the control signal for selecting the second oscillation signal is input to the selection circuit MUX2, the first to fourth circuit units 40 through the buffers 93k, 92k, 91f, 91k, and 90f are sequentially transmitted. To 43 are supplied with a second oscillation signal.

<First oscillation signal × 1 + second oscillation signal × 3, or first oscillation signal × 3 + second oscillation signal × 1>
FIG. 14 illustrates a case where the first oscillation signal is supplied to the first circuit unit 40 and the second oscillation signal is supplied to the second to fourth circuit units 41 to 43, or FIG. 4 is a diagram for explaining a circuit state when a signal is supplied to a first circuit unit 40 and a first oscillation signal is supplied to second to fourth circuit units 41 to 43. In the present embodiment, this state is referred to as a second mode.

  As shown in FIG. 14, in the second mode, a control signal instructing not to output an input signal is input to buffers 90d, 90f, 91b, and 91k, and input to buffers 91f and 92k. A control signal for outputting a signal is input.

  Therefore, when the control signal for selecting the first oscillation signal is input to the selection circuit MUX1 and the control signal for selecting the second oscillation signal is input to the selection circuit MUX2, the selection circuit MUX1 outputs , The first oscillation signal is supplied to the first circuit unit 40, and the second to fourth circuit units 41 to 43 are supplied from the selection circuit MUX2 to the second to fourth circuit units 41 to 43 via the buffers 93k, 92k, and 91f in that order. An oscillation signal is provided.

  On the other hand, when the control signal for selecting the second oscillation signal is input to the selection circuit MUX1 and the control signal for selecting the first oscillation signal is input to the selection circuit MUX2, The second oscillation signal is supplied to the first circuit unit 40, and the first oscillation is supplied from the selection circuit MUX2 to the second to fourth circuit units 41 to 43 via the buffers 93k, 92k, and 91f in this order. A signal is provided.

  At this time, the buffers 90d, 90f, 91b, and 91k in the area A4 are all in an inactive state in which the input signal is not output. In other words, the first circuit unit 40 and the second circuit unit 41 are separated by two buffers 90d and 91b having different power supply systems, and two buffers 90f and 91k having different power supply systems. Will be separated by one buffer. Therefore, a high isolation between the first oscillation signal and the second oscillation signal can be secured, and the occurrence of crosstalk is suppressed.

<First oscillation signal × 2 + second oscillation signal × 2>
FIG. 15 illustrates a case where the first oscillation signal is supplied to the first to second circuit units 40 to 41 and the second oscillation signal is supplied to the third to fourth circuit units 42 to 43, or The circuit state when the second oscillation signal is supplied to the first and second circuit units 40 to 41 and the first oscillation signal is supplied to the third and fourth circuit units 42 to 43 will be described. FIG. In the present embodiment, this state is referred to as a third mode.

  As shown in FIG. 15, in the third mode, a control signal instructing not to output an input signal is input to buffers 90f, 91f, 91k, and 92k, and input to buffers 90d and 91b. A control signal for outputting a signal is input.

  Therefore, when the control signal for selecting the first oscillation signal is input to the selection circuit MUX1 and the control signal for selecting the second oscillation signal is input to the selection circuit MUX2, the selection circuit MUX1 outputs The first oscillation signal is supplied to the first and second circuit units 40 to 41, and the second oscillation signal is supplied from the selection circuit MUX2 to the third and fourth circuit units 42 to 43 via the buffer 93k. An oscillation signal is provided.

  In addition, although the numbers are the same, a control signal for selecting the second oscillation signal is input to the selection circuit MUX1, and a control signal for selecting the first oscillation signal is input to the selection circuit MUX2. In this case, the second oscillation signal is supplied from the selection circuit MUX1 to the first and second circuit units 40 to 41, and the third and fourth circuit units are supplied from the selection circuit MUX2 via the buffer 93k. The first oscillation signal is supplied to 42 to 43.

  At this time, the buffers 91f and 92k in the area A5 are in an inactive state in which the input signals are not output. That is, the second circuit unit 41 and the third circuit unit 42 are separated by two buffers 91f and 92k having different power supply systems. Therefore, a high isolation between the first oscillation signal and the second oscillation signal can be secured, and the occurrence of crosstalk is suppressed.

  As described above, according to the semiconductor device 1 of the present embodiment, the buffer for buffering the first oscillation signal or the second oscillation signal is supplied to each of the first to fourth circuit units 40 to 43. The operation was performed with the electric power supplied. Further, each of the first to third circuit units 40 to 42 is separated by two inactive buffers. For this reason, high isolation between the first oscillation signal and the second oscillation signal can be ensured, and occurrence of crosstalk can be suppressed.

  Further, the first oscillation signal generation circuit 30 and the second oscillation signal generation circuit 31 both generate both the first oscillation signal and the second oscillation signal, and the first oscillation signal generation circuit 30 A first oscillation signal or a second oscillation signal is selectively supplied to the first and second circuit units 40 to 41, and a first to fourth circuit unit is selectively supplied from the second oscillation signal generation circuit 31. Since the first oscillating signal or the second oscillating signal is supplied to 40 to 43, the active state / inactive state of the buffer is arbitrarily combined, so that the first oscillating signal can be supplied to a required number of circuit sections. And a second oscillation signal can be supplied. Further, the transmission path of the oscillation signal between the second circuit section 41 and the third circuit section 42 can be made one, and the oscillation signal between the third circuit section 43 and the fourth circuit section 43 can be formed. Since the number of transmission paths can be reduced to one, the layout area of the circuit can be reduced.

  As shown in FIG. 16, the semiconductor device 1 according to the present embodiment includes a single transmission line between the first circuit unit 40 and the second circuit unit 41 as in the first embodiment. To exchange the first oscillation signal or the second oscillation signal. Thereby, the circuit area can be further reduced.

  Also, as shown in FIG. 17, power is not supplied to the selection circuit MUX <b> 1 from the power supply system of the same power supply circuit 20 as the first oscillation signal generation circuit 30. Power may be supplied from the power supply system to the selection circuit MUX1. Similarly, instead of supplying power to the selection circuit MUX2 from the same power supply system of the power supply circuit 25 as the second oscillation signal generation circuit 31, the selection circuit MUX2 is not supplied from the power supply system of the same power supply circuit 24 as the fourth circuit unit 43. May be supplied with power.

  While some embodiments have been described above, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. The novel apparatus and method described herein can be implemented in various other forms. In addition, various omissions, substitutions, and changes can be made to the embodiments of the apparatus and method described in this specification without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications as fall within the scope and spirit of the invention.

10 power supply, 20 to 26: power supply circuit, 30: first oscillation signal generation circuit, 31: second oscillation signal generation circuit, 40 to 43: first to fourth circuit units, 50: control circuit, 60 63: IQ signal generator, 70 to 73: transmitter, 80 to 83: receiver, 90a, 90c, 90e, 90g, 90h: capacitor, 90b, 90d, 90f, 90i: buffer, 91a, 91c, 91e, 91g, 91h, 91j: Capacitor, 91b, 91d, 91f, 91i, 91k: Buffer, 92a, 92c, 92e, 92g, 92h, 92j: Capacitor, 92b, 92d, 92f, 92i, 92k: Buffer, 93a, 93e, 93g, 93h, 93j: Capacitor, 93b, 93f, 93i, 93k: Buffer

Claims (11)

A first circuit unit to which power is supplied from a first power supply system, the first circuit unit including a first buffer, a second buffer, and a first processing unit;
A second circuit unit supplied with power from a second power supply system different from the first power supply system, the second circuit unit having a third buffer;
A first oscillation signal generation circuit supplied with power from the first power supply system,
A second oscillation signal generation circuit supplied with power from the second power supply system,
With
A first oscillation signal generated by the first oscillation signal generation circuit is input to the first buffer;
A second oscillation signal generated by the second oscillation signal generation circuit is input to the second buffer via the third buffer;
Whether the first buffer outputs the input first oscillation signal to the first processing unit, or whether the second buffer outputs the input second oscillation signal to the first processing unit. A semiconductor device that can control whether or not to output to the processing unit. The second circuit unit further includes a fourth buffer and a second processing unit,
The fourth oscillation signal is input to the fourth buffer via the first buffer,
2. The semiconductor device according to claim 1, wherein whether the fourth buffer outputs the input first oscillation signal to the second processing unit can be controlled. A fifth buffer to which the first oscillation signal is input;
3. The device according to claim 1, wherein the fifth buffer is capable of controlling whether to output the input first oscillation signal to the first processing unit and the first buffer. 4. 13. The semiconductor device according to claim 1.   The semiconductor device according to claim 3, wherein the fifth buffer is provided in the first circuit unit, and is supplied with power from the first power supply system. The first oscillation signal generation circuit is capable of generating the first oscillation signal and the second oscillation signal,
The semiconductor device is
A first selection circuit that outputs one of the first oscillation signal and the second oscillation signal generated by the first oscillation signal generation circuit,
The semiconductor device according to claim 1, further comprising: The second oscillation signal generation circuit can also generate the first oscillation signal and the second oscillation signal,
The semiconductor device is
A second selection circuit that outputs one of the first oscillation signal and the second oscillation signal generated by the second oscillation signal generation circuit;
A third circuit unit to which power is supplied from a third power supply system different from the first and second power supply systems;
A fourth circuit unit to which power is supplied from a fourth power supply system different from the first to third power supply systems;
Is further provided,
The fourth circuit unit includes:
A sixth buffer to which power is supplied from the fourth power supply system and to which the first oscillation signal or the second oscillation signal output from the second selection circuit is input; Optionally, a sixth buffer that outputs the second oscillation signal to the third circuit unit,
The semiconductor device according to claim 5, further comprising: The third circuit unit includes:
A seventh buffer to which power is supplied from the third power supply system and to which the first oscillation signal or the second oscillation signal output from the sixth buffer is input; A seventh buffer capable of controlling whether to output the first oscillation signal or the second oscillation signal to the second circuit unit,
The semiconductor device according to claim 6 provided.   9. The third circuit unit and the fourth circuit unit, wherein neither the first oscillation signal nor the second oscillation signal generated by the first oscillation signal generation circuit is input. Semiconductor device. Power is supplied to the first selection circuit from the same power supply system as the first oscillation signal generation circuit,
9. The semiconductor device according to claim 6, wherein power is supplied to said second selection circuit from the same power supply system as said second oscillation signal generation circuit.   3. The transmission line according to claim 2, wherein a transmission line between the first buffer and the third buffer and a transmission line between the second buffer and the fourth buffer are shared. Semiconductor device.   A first transmission path is provided between the first buffer and the third buffer, and the first transmission path is provided between the second buffer and the fourth buffer. 3. The semiconductor device according to claim 2, wherein a second transmission path is provided separately.

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