JP2019528646A - Transition glitch suppression circuit - Google Patents

Abstract

By using a transition glitch suppression circuit, unwanted glitches that occur within the time delay of the rising or falling edge of the signal can be eliminated. The transition glitch suppression circuit has a delay element that can delay the input signal by a time delay in order to generate a delayed input signal. The transition glitch suppression circuit also has first and second logic circuits that process the input signal and the delayed input signal to produce a corresponding output. The multiplexer provides an output signal for the suppression circuit by selecting between the output of the first logic circuit and the output of the second logic circuit based on the value of the output signal. [Selection] Figure 4

Description

Cross-reference to related applications This application claims the priority of US Pat. No. 9,692,417, entitled “Transition Glitch Suppression Circuit”, patented on June 27, 2017. This application is incorporated herein by reference. This application is also entitled “Brown-Out Detector and Power-on-Reset Circuit” and claims priority from US patent application Ser. No. 15 / 253,731 filed Aug. 31, 2016. This application is incorporated herein by reference. This application is also entitled “AC Coupled Level Shifting Circuit” and claims priority to US patent application Ser. No. 15 / 253,769, filed Aug. 31, 2016, which is hereby incorporated by reference. Is incorporated into.

  Many elements of a chip (or integrated circuit) require periodic signals, such as clock signals, to ensure proper operation and timing of the elements of the chip. The clock signal may be a periodic signal having a duty cycle such as a 50% duty cycle (ie, the signal is in a logic 1 state for the same time that it is in a logic 0 state). In some examples, the clock signal is subject to unexpected glitches (ie, logic 1 and unintended as part of the clock signal period or duty cycle) during a high-to-low or low-to-high transition. Transition between logic 0). These glitches can be of short duration at the rising and falling edges of the clock signal. In some cases, unexpected glitches can interrupt the operation of the chip's elements, leading to timing problems that can lead to further interruption of the operation of the chip's elements.

  The payment terminal has a component that requires a clock signal that is used to process payment transactions and to interact with a payment device such as a payment card having a magnetic strip that is passed through the magnetic reader of the payment terminal. Payment device with one or more chips and a Europay / Mastercard / Visa (EMV) chip inserted into the corresponding EMV slot of the payment terminal, and tapped at the payment terminal to send payment information over a secure wireless connection And a near field communication (NFC) capable device such as a smartphone or an EMV card. In order to ensure the correct processing of payment transactions, stable operation of the chip at the payment terminal is required. Merchants and consumers trying to complete a payment transaction are frustrated if an error occurs during the payment transaction or if the payment transaction is not processed correctly due to unstable operation of the chip in the payment terminal Sometimes.

  The above and other features, their nature, and various advantages of the present disclosure will become more apparent upon consideration of the following detailed description considered in conjunction with the accompanying drawings.

FIG. 2 illustrates an exemplary block diagram of a payment system according to some embodiments of the present disclosure.

FIG. 3 illustrates an exemplary block diagram of a payment device and a payment terminal according to some embodiments of the present disclosure.

FIG. 4 illustrates an exemplary block diagram of a payment reader according to some embodiments of the present disclosure.

FIG. 4 shows an exemplary schematic of some components of a clock source, according to some embodiments of the present disclosure.

FIG. 5 illustrates an exemplary timing diagram for the transition filter of FIG. 4 in accordance with some embodiments of the present disclosure.

FIG. 4 shows an exemplary schematic diagram of some components of a bias generator, according to some embodiments of the present disclosure.

7 and 8 illustrate exemplary timing diagrams of the power supply voltage monitoring circuit of FIG. 6 according to some embodiments of the present disclosure. 7 and 8 illustrate exemplary timing diagrams of the power supply voltage monitoring circuit of FIG. 6 according to some embodiments of the present disclosure.

FIG. 3 shows an exemplary schematic diagram of some components of an AC level shift circuit, according to some embodiments of the present disclosure.

  The payment terminal chip may detect unwanted transitions (e.g., glitches) that occur near the rising edge (i.e., transition from logic 0 to logic 1) and falling edge (i.e., transition from logic 1 to logic 0) of the clock signal. And a clock having a transition filter that eliminates. The transition filter can receive an input clock signal from a clock source and provide an output clock signal that is used by other components of the reader chip. The output clock signal does not include unwanted glitches between logic 1 and logic 0 (or vice versa) even if such glitches are present on the input signal.

  The transition filter has a delay element that is used to delay the input signal by a time delay. The input signal and the delayed input signal are then provided as inputs to the first and second logic circuits. The first logic circuit includes a NAND gate coupled in series with a NOR gate, and the second logic circuit includes a NOR gate coupled in series with the NAND gate. The output of the first logic circuit (ie, the output of the corresponding NOR gate) and the output of the second logic circuit (ie, the output of the corresponding NAND gate) are provided as inputs to the multiplexer. The multiplexer then selects either the output of the first logic circuit or the output of the second logic circuit to be the output of the multiplexer and the corresponding output signal from the transition filter. The selection of the output of the first logic circuit or the output of the second logic circuit by the multiplexer is based on the value of the output signal. The multiplexer can select the output of the first logic circuit when the output signal is logic 0, and the multiplexer can select the output of the second logic circuit when the output signal is logic 1 .

  The first logic circuit can be used to remove unwanted transitions near the rising edge of the clock signal, and the second logic circuit can remove unwanted transitions near the falling edge of the clock signal. Can be used. The NAND gate of the first logic circuit keeps the output of the first logic circuit at logic 0 until the expiration of the time delay where glitches can occur, thereby causing undesirable transitions near the rising edge of the clock signal. Can be removed. The first logic circuit maintains its output at logic zero until the time delay expires by delaying the change in the output of the NAND gate. The change in the NAND gate is delayed as a result of the delayed input signal supplied to the NAND gate remaining at logic 0 until the time delay expires, which logic 0 input produces the output of the NAND gate at logic 1 (preferably resulting in the input signal). And the output of the first logic circuit is kept at logic zero.

  Similarly, the NOR gate of the second logic circuit may eliminate undesirable transitions near the falling edge of the clock signal by maintaining the output of the second logic circuit at logic 1 until the time delay expires. it can. The second logic circuit maintains its output at logic 1 until the time delay expires by delaying the change in the output of the NOR gate. The change in the NOR gate is delayed as a result of the delayed input signal supplied to the NOR gate remaining at a logic 1 until the time delay expires, and this logic 1 input causes the output of the NOR gate to be a logic 0 (preferably resulting in the input signal). And the output of the second logic circuit is kept at logic 1.

  FIG. 1 illustrates an exemplary block diagram of a payment system 1 according to some embodiments of the present disclosure. In an embodiment, the payment system 1 includes a payment device 10, a payment terminal 20, a network 30, and a payment server 40. In the exemplary embodiment, payment server 40 may include multiple servers operated by different entities, such as payment service system 50 and bank server 60. These components of the payment system 1 facilitate electronic payment transactions between the merchant and the customer.

  An electronic interaction between the merchant and the customer takes place between the customer payment device 10 and the merchant payment terminal 20. A customer has a payment device 10 such as a credit card with a magnetic stripe, a credit card with an EMV chip, or an NFC-enabled electronic device such as a smartphone that executes a payment application. The merchant can process payment information (eg, encrypted payment card data and user authentication data) and transaction information (eg, purchase price and point-of-purchase information) or a payment terminal or other electronic device (eg, payment application) A payment terminal 20 such as a smartphone or tablet).

  In some embodiments (eg, for low value transactions or for payment transactions below the payment limit indicated by the NFC or EMV payment device 10), the initial processing and approval of the payment transaction is processed at the payment terminal 20. May be. In other embodiments, the payment terminal 20 can communicate with the payment server 40 via the network 30. Although the payment server 40 may be operated by a single entity, in some embodiments the payment server 40 is optional, such as the payment service system 50 and one or more banks of merchants and customers (eg, bank server 60). Any suitable number of servers operated by any suitable entity may be included. Payment terminal 20 and payment server 40 communicate payment and transaction information to determine whether a transaction is permitted. For example, the payment terminal 20 can provide encrypted payment data, user authentication data, purchase amount information, and purchase point-in-time information to the payment server 40 via the network 30. The payment server 40 determines whether the transaction is permitted based on the received information and information related to the customer account or the merchant account, and the payment transaction is permitted in response to the payment terminal 20 via the network 30. Can indicate whether or not The payment server 40 may also send additional information, such as a transaction identifier, to the payment terminal 20.

  Based on the information received from the payment server 40 at the payment terminal 20, the merchant can indicate to the customer whether the transaction has been approved. In some embodiments, such as a chip card payment device, the authorization may be shown at the payment terminal, eg, at the payment terminal screen. In other embodiments, such as smartphones or watches that act as NFC payment devices, information about approved transactions and additional information (eg, receipts, special offers, coupons, or loyalty program information) are displayed on the screen of the smartphone or watch. Can be provided to an NFC payment device for storage or storage in memory.

  FIG. 2 illustrates an exemplary block diagram of payment device 10 and payment terminal 20 in accordance with some embodiments of the present disclosure. It will be appreciated that the payment device 10 and payment terminal 20 of the payment system 1 may be implemented in any suitable manner, but in one embodiment, the payment terminal 20 comprises a payment reader 22 and a merchant device 29. May be. However, it should be understood that the term payment terminal, as used herein, can refer to any suitable component of a payment terminal, such as payment reader 22. In one embodiment, payment reader 22 of payment terminal 20 may be a wireless communication device that facilitates transactions between payment device 10 and merchant device 29 executing a POS application.

  In one embodiment, payment device 10 may be a device that can communicate with payment terminal 20 (eg, via payment reader 22), such as NFC device 12 or EMV chip card 14. Chip card 14 communicates with a payment terminal, such as payment terminal 20, and generates encrypted payment information according to one or more electronic payment standards, such as those promulgated by EMVCo, encrypted payment information, and It may include a secure integrated circuit that can provide other payment or transaction information (eg, transaction limits for locally processed payments). The chip card 14 may include contact pins for communicating with the payment reader 22 (eg, according to ISO 7816), and in some embodiments, inductively coupled to the payment reader 22 via the near field 15. Also good. The chip card 14 inductively coupled to the payment reader 22 can communicate with the payment reader 22 using load modulation of the wireless carrier signal provided by the payment reader 22 in accordance with a wireless communication standard such as ISO 14443.

  The NFC device 12 may be an electronic device such as a smartphone, tablet, or smart watch that can perform secure transactions with the payment terminal 20 (eg, via communication with the payment reader 22). NFC device 12 includes hardware (eg, secure elements including hardware and executable code) and / or software (eg, executable code that operates on a processor according to a host card emulation routine) to perform secure transaction functions. ). During a payment transaction, the NFC device 12 may be inductively coupled to the payment reader 22 via the near field 15 and in accordance with one or more wireless communication standards such as ISO 14443 and ISO 18092, the payment reader 22 May communicate with the payment terminal 20 by active or passive load modulation of the radio carrier signal provided by.

  Payment terminal 20 may be implemented in any suitable manner, but in one embodiment, payment terminal 20 may include payment reader 22 and merchant device 29. Merchant device 29 provides a user interface for the merchant and executes point-of-sale applications that facilitate communication with payment reader 22 and payment server 40. The payment reader 22 can facilitate communication between the payment device 10 and the merchant device 29. As described herein, payment device 10, such as NFC device 12 or chip card 14, can communicate with payment reader 22 via inductive coupling. This is shown in FIG. 2 as a near field 15 containing a radio carrier signal having an appropriate frequency (eg, 13.56 MHz) emanating from the payment reader 22.

  In one embodiment, payment device 10 may be a contactless payment device, such as NFC device 12 or chip card 14, and payment reader 22 and contactless payment device 10 modulate the radio carrier signal within near field 15. You may communicate by. In order to communicate information to the payment device 10, the payment reader 22 changes the amplitude and / or phase of the wireless carrier signal based on the data transmitted from the payment reader 22, and as a result, the wireless data transmitted to the payment device. A signal is obtained. This signal is transmitted by the antenna of the payment reader 22 tuned to transmit at 13.56 MHz, and the payment device 10 also has an appropriately tuned antenna within the range of the near field 15 (eg 0-10 cm). If so, the payment device receives a wireless carrier signal or a wireless data signal transmitted by the payment reader 22. In the case of a wireless data signal, the processing circuit of the payment device 10 can demodulate the received signal and process the data received from the payment reader 22.

  When a contactless payment device, such as payment device 10, is within range field 15, it is inductively coupled to payment reader 22. Accordingly, the payment device 10 can also modulate the radio carrier signal via active or passive load modulation. By changing the tuning characteristics of the antenna of the payment device 10 (eg, by selectively switching the parallel load on the antenna circuit based on the modulation data to be transmitted), the wireless carrier signal is transmitted to the payment device 10 and the payment reader. 22 both resulting in a modulated and modulated radio carrier signal. In this way, the payment device can send the modulated data to the payment reader 22.

  In some embodiments, the payment reader 22 also includes an EMV slot 21 that can accept the chip card 14. The chip card 14 can have contacts that engage the corresponding contacts of the payment reader 22 when the chip card 14 is inserted into the EMV slot 21. The payment reader 22 supplies power to the EMV chip of the chip card 14 via these contacts, and the payment reader 22 and the chip card 14 communicate via a communication path established by the contacts.

  The payment reader 22 can also include hardware for interacting with a magnetic strip card (not shown in FIG. 2). In some embodiments, the hardware may include a slot that guides the customer to swipe or dip the magnetic strip of the magnetic strip card so that the magnetic strip reader can receive payment information from the magnetic strip card. it can. The received payment information is processed by the payment reader 22.

  Merchant device 29 may be any suitable device such as tablet payment device 24, mobile payment device 26, or payment terminal 28. For computing devices such as tablet payment device 24 or mobile payment device 26, point-of-sale applications can provide purchase and payment information input, customer interaction, and communication with payment server 40. For example, a payment application may provide a menu of services that a merchant can select and a series of menus or screens for automating transactions. The payment application can also facilitate entry of customer authentication information such as a signature, PIN number, or biometric information. Similar functionality may be provided on a dedicated payment terminal 28.

  The merchant device 29 can communicate with the payment reader 22 via a communication path 23/25/27. The communication path 23/25/27 may be implemented via a wired connection (eg Ethernet, USB, FireWire, Lightning) or a wireless connection (eg Wi-Fi, Bluetooth, NFC, or ZigBee), but one implementation In the form, the payment reader 22 communicates with the merchant device 29 via the Bluetooth Low Energy interface, so that the payment reader 22 and the merchant device 29 become connected devices. In some embodiments, payment transaction processing may be performed locally on the payment reader 22 and the merchant device 29, for example, when the transaction amount is low or when there is no connection to the payment server 40. In other embodiments, the merchant device 29 or payment reader 22 can communicate with the payment server 40 via a public or private communications network 30. The communication network 30 may be any suitable communication network, but in one embodiment the communication network 30 may be the Internet, and payment and transaction information may be transport layer security (TLS) protocol or secure socket layer. Communication may be performed between the payment terminal 20 and the payment server 40 in a format encrypted by (SSL) protocol or the like.

  FIG. 3 shows a block diagram of an exemplary payment reader 22 according to some embodiments of the present disclosure. In one embodiment, payment reader 22 may be a wireless communication device that communicates wirelessly with an interactive electronic device such as merchant device 29 using, for example, Bluetooth Classic or Bluetooth Low Energy. Although specific components are shown in a specific configuration in FIG. 3, the payment reader 22 can include additional components, one or more of the components shown in FIG. 3 being a payment reader. It should be understood that the components of payment reader 22 may not be included in 22 and may be reconfigured in any suitable manner. In one embodiment, payment reader 22 includes a terminal chip that utilizes the payment reader (eg, within payment terminal 20), reader chip 100, a plurality of payment interfaces (eg, contactless interface 102 and contact interface 104), A power source 106, a wireless communication interface 108, a wired communication interface 110, and a signal conditioning device 112 are included. The payment reader 22 may also include a general purpose processing unit 120 (eg, a terminal / reader processing unit), a general purpose memory 122, a cryptographic processing unit 125, and a cryptographic memory 128. In one embodiment, the processing unit and memory are described as being packaged and configured in a particular manner on the reader chip 100, but the general processing unit 120, the general purpose memory 122, the cryptographic processing unit 125, and the cryptographic memory 128 are described. It will be appreciated that may be configured in any suitable manner to perform the functions of the payment reader 22 described herein. In addition, the functions of the reader chip 100 can be implemented on a single chip or multiple chips, each of which has a processing unit and memory to collectively perform the functions of the reader chip 100 described herein. It will also be understood to include any suitable combination of

  In some embodiments, the reader chip 100 may be a suitable chip having a processing unit. The processing unit 120 of the reader chip 100 of the payment reader 22 may be a suitable processor and may include hardware, software, memory, and circuitry necessary to perform and control the payment reader 22 functions. The processing unit 120 can include one or more processors and can perform the operations of the reader chip 100 based on instructions in any suitable number of memories and memory types. In some embodiments, the processing unit 120 may have multiple independent processing units, such as a multi-core processor or other similar component. The processing unit 120 can execute instructions stored in the memory 122 of the reader chip 100 to control the operation and processing of the payment reader 22. As used herein, a processor or processing unit is hardware logic (eg, hardware designed by software that describes the configuration of the hardware, such as hardware description language (HDL) software), on the processor. One or more having the processing power necessary to perform the processing functions described herein, including but not limited to computer readable instructions executed on the computer, or any suitable combination thereof. A processor may be included. The processor may execute software for performing the operations described herein, including software accessed in a machine readable form on a tangible non-transitory computer readable storage medium.

  In the exemplary embodiment, processing unit 120 of reader chip 100 is configured to operate as a hub for controlling the operation of various components of payment reader 22 based on instructions stored in memory 122. Two RISC processors can be included. As used herein, memory can refer to any suitable tangible or non-transitory storage medium. Examples of tangible (or non-transitory) storage media include disks, USB memories, memories, etc., but do not include propagated signals. Tangible computer readable media include volatile and non-volatile removable and non-removable media such as computer readable instructions, data structures, program modules, or other data. Examples of such media include RAM, ROM, EPROM, EEPROM, SRAM, flash memory, disk or optical storage device, magnetic storage device, or any other non-information that stores information accessed by a processor or computing device. Includes temporary media.

The reader chip 100 can also include additional circuitry such as interface circuitry, analog front end circuitry, security circuitry, and monitoring component circuitry. In one embodiment, the interface circuit includes a circuit for interfacing with a wireless communication interface 108 (e.g., WiFi, Bluetooth Classic, and Bluetooth Low Energy) and a wired communication interface 110 (e.g., USB, Ethernet). , FireWire, and Lightning), a circuit for interfacing with other communication interfaces or buses (eg, I ² C, SPI, UART, and GPIO), and power supply 106 And a circuit to be an interface (for example, a power management circuit, a power conversion circuit, a rectifier, and a battery charging circuit).

  In the exemplary embodiment, reader chip 100 may perform functions related to processing payment transactions, interfacing with payment devices, encryption, and other payment-specific functions. In some embodiments, the reader chip 100 can include a cryptographic processing unit 125 for processing cryptographic processing operations. Note that each of the general purpose processing unit 120 and the cryptographic processing unit 125 can have dedicated memory associated therewith (ie, the general purpose memory 122 and the cryptographic memory 128). In this way, certain cryptographic processing and critical security information (eg, cryptographic keys, passwords, user information, etc.) can be securely stored by the cryptographic memory 128 and processed by the cryptographic processing unit 125.

  One or both of the general-purpose processing unit 120 and the cryptographic processing unit 125 of the reader chip 100 can communicate with the other using, for example, any suitable internal bus and communication technique (eg, the processing unit 120 can perform cryptographic processing). Can communicate with the unit 125 and vice versa). In this way, the leader chip 100 can process the transaction and communicate information about the processed transaction (eg, with the merchant device 29).

  The reader chip 100 can also include circuitry for implementing the contact interface 104 (eg, power and communication circuitry for directly interfacing with the EMV chip of the chip card 14 inserted into the slot 21). In some embodiments, the reader chip 100 also includes analog front-end circuitry (eg, electromagnetic compatibility (EMC) circuitry, matching circuitry, modulation circuitry, and measurement circuitry) for interfacing with analog components of the contactless interface 102. ).

  The contactless interface 102 can provide NFC communication with contactless devices such as the NFC device 12 and the chip card 14. Based on the signal provided by the reader chip 100, the antenna of the contactless interface 102 can output either a carrier signal or a modulated signal. The carrier signal may be a signal having a fixed frequency such as 13.56 MHz. The modulated signal may be a modulated version of the carrier signal according to modulation procedures such as ISO 14443 and ISO 18092. When the payment reader 22 is inductively coupled to a contactless device, the contactless device can also modulate the carrier signal, which is sensed by the contactless interface 102 for processing. It can be provided to the reader chip 100. Based on these modulations of the carrier signal, payment reader 22 and contactless device can communicate information such as payment information.

  Contact interface 104 may be a suitable interface for supplying power to and communicating with a payment chip, such as an EMV chip, on chip card 14. The contact interface 104 may include a plurality of contact pins (not shown in FIG. 3) for physically interfacing with the chip card 14 according to the EMV specification. In some embodiments, the contact interface 104 includes a power (VCC) pin, a ground (GND) pin, a reset (RST) pin for resetting the EMV card, a clock (CLK) pin for providing a clock signal, A programming voltage (VPP) pin for providing a programming voltage to the EMV card, an input output (I / O) pin for providing EMV communication, and two auxiliary pins may be included. In this way, the payment reader and the chip card 14 can exchange information such as payment information. In some embodiments, the contact interface 104 may be housed on the reader chip 100 and may communicate with various components of the reader chip 100 via any suitable means (eg, a common internal bus). Please note that it is good.

  The power source 106 can include one or more power sources, such as AC power, DC power, or a physical connection to a battery. The power source 106 may include a power conversion circuit for converting an AC or DC power source into a plurality of DC voltages used by components of the payment reader 22. If the power source 106 includes a battery, the battery may be charged via a physical power connection, via inductive charging, or via any other suitable method. Although not shown in FIG. 3 as being physically connected to other components of payment reader 22, power source 106 supplies various voltages to components of payment reader 22 according to the requirements of these components. can do.

  The wireless communication interface 108 is required to participate in wireless communication with appropriate wireless communication hardware (eg, antennas, matching circuits, etc.) and (eg, merchant device 29 via a protocol such as Bluetooth Low Energy). It may include one or more processors having processing capabilities and control related circuitry including, but not limited to, hardware logic, computer readable instructions executing on the processor, and any suitable combination thereof. The wireless communication interface 108 may be implemented in any suitable manner, but in the exemplary embodiment, the Texas Instruments may include a processing unit (not shown) and a memory (not shown). It may be implemented as a CC2640 device.

  The wired communication interface 110 is for wired communication with other devices or communication networks, such as USB, Lightning, Firewire, Ethernet, any other suitable wired communication interface, or any combination thereof. Any suitable interface can be included. In some embodiments, the wired communication interface 110 may allow a payment reader to communicate with one or both of the merchant device 29 and the payment server 40.

  In some embodiments, the reader chip 100 can include a signal conditioning device 112. Although the signal conditioning device 112 can include any suitable hardware, software, or any combination thereof, in an exemplary embodiment the signal conditioning device can include an FPGA. The signal conditioning device 112 can receive and adjust signals transmitted from the contactless interface 102, such as when the payment device 10 using NFC communication communicates with the payment reader 22. In one embodiment, the signal conditioning device 112 can operate based on instructions (eg, signal conditioning instructions 136) stored in the reader chip 100 for use in interacting with the contactless interface 102.

  In some embodiments, general purpose memory 122 may be any suitable memory described herein, such as operating instructions 130, transaction processing instructions 132, data authentication instructions 134, and signal conditioning instructions 136, such as A plurality of instruction sets for controlling the operation of the payment reader 22 and performing the general transaction processing operations of the payment reader 22 may be included.

  Operating instructions 130 include internal communication, power management, message processing, system monitoring, sleep mode, user interface response and control, contact interface 104, wireless interface 108, wired interface 110, operation of signal conditioning device 112, other instruction sets. Instructions for controlling the general operation of the payment reader 22, such as managing In one embodiment, the operating instructions 130 may provide the operating system and applications necessary to perform most of the processing operations performed by the processing unit 120 of the leader chip 100 of the payment reader 22.

  Operating instructions 130 may also include instructions for interacting with merchant device 29. In one embodiment, merchant device 29 may execute a point-of-sale application. Operating instructions 130 may include instructions for complementary applications that are executed on processing unit 120 of reader chip 100 to exchange information with point-of-sale information management applications. For example, point-of-sale applications can provide a user interface that facilitates a user, such as a merchant, to conduct purchase transactions with a customer. The menu may provide item selection, tax calculation, adding hints, and other related functions. Upon receipt of the payment, the point-of-sale application can send a message (eg, via the wireless interface 108) to the payment reader 22. The operating instruction 130 may, for example, obtain payment information via the contactless interface 102 or the contact interface 104 and invoke various resources of the reader chip 100 to process the payment information (eg, the cryptographic processing unit 125). Payment by generating a response message that is sent to the POS application of the merchant device 29 via the wireless communication interface 108 and the wired communication interface 110) and by executing the memory stored in the cryptographic memory 128 using To make the process easier.

  Operating instructions 130 may also include instructions for interacting with payment service system 50 at payment server 40. In one embodiment, payment service system 50 may be associated with point-of-sale management applications for payment reader 22 and merchant device 29. For example, payment service system 50 may have information regarding payment reader 22 and merchant device 29 registered with payment service system 50 (eg, based on a unique identifier). This information can be used to process transactions with merchant and customer financial institution servers, provide analysis and reports to the merchant, and aggregate transaction data. The payment reader 22 processes the payment information (eg, based on the operation of the reader chip 100) and communicates the processed payment information to the point-of-sale application, which communicates with the payment service system 50. In this way, the message from the payment reader 22 is forwarded to the payment service system 50 of the payment server 40, and the payment reader 22 and the payment service system 50 can process the payment transaction in cooperation.

  The transaction processing instruction 132 controls the interaction between the payment reader 22 and the payment device 10 (e.g., interfaces with the payment device via the contactless interface 102 and the contact interface 104), and the payment processing procedure. General transaction of payment reader 22 such as selecting (eg, based on payment processing entity associated with payment method), interfacing with cryptographic processor 125, and any other suitable aspect of transaction processing Instructions for controlling processing operations may be included.

  Transaction processing instructions 132 may also include instructions for processing payment transactions at payment reader 22. In one embodiment, transaction processing instructions can comply with payment standards, such as payment standards promulgated by EMV. Depending on the payment method used (eg, Europay, MasterCard, Visa, American Express, etc.), a specific processing procedure associated with the payment method may be selected and the transaction may be processed according to that procedure. Good. When executed by the processing unit 120, these instructions include whether to process the transaction locally, how the payment device accesses the payment information, how the payment information is processed, and what encryption The type of communication that performs the function or exchanges with the payment server and any other suitable information related to the processing of the payment transaction may be determined. In some embodiments, transaction processing instructions 132 may perform high-level processing and provide instructions for processing unit 120 to communicate with cryptographic processing unit 125 to perform most transaction processing operations. . In addition, the transaction processing instruction 132 provides instructions for obtaining any appropriate information from the chip card (eg, via the contact interface 104 and the cryptographic processing unit 125) such as an authentication response, card username, card expiration, etc. can do.

  The data authentication instruction 134 may include an instruction for providing setting information to the payment terminal 20. The configuration information can include any suitable information such as local transactions (ie, transactions that occur without contacting payment server 40) and payment limits and transaction types for supported applications. As an example, in some embodiments, the data authentication instruction 134 can include a configuration instruction, such as a TMS-CAPK instruction. In some embodiments, TMS-CAPK may be tailored (eg, country specific) for a particular jurisdiction.

  The signal conditioning instructions 136 may include instructions for adjusting signals received from the payment device 10 via the contactless interface 102 (eg, from the NFC payment device 10). In some embodiments, the signal conditioning instructions 136 may include instructions for manipulating signals received via the contactless interface 102, but the signal conditioning instructions 136 may be generated by signal conditioning hardware such as the signal conditioning device 112. Instructions for conditioning the signal can be included, including the first processed signal.

  Cryptographic processing unit 125 may be any suitable processor as described herein, and in some embodiments may perform cryptographic functions for processing payment transactions. For example, in some embodiments, the cryptographic processing unit 125 separates the encryption function from other components of the payment reader 22 and protects the encryption key from exposure to other components of the payment reader 22. In addition, data can be encrypted and decrypted based on one or more encryption keys.

  In some embodiments, the cryptographic memory 128 may be any suitable memory or combination thereof, as described herein, and performs cryptographic operations such as payment processing instructions 176 and cryptographic instructions 178. A plurality of instruction sets may be included. Payment processing instruction 176 provides encryption techniques used in connection with a particular payment procedure, accessing an account, processing information, any other suitable payment processing functionality, or Instructions for performing payment processing aspects, such as any suitable combination thereof, may be included. Cryptographic instructions 178 can include instructions for performing cryptographic operations. The cryptographic processing unit 125 may execute cryptographic instructions 178 to perform various cryptographic functions such as encryption, decryption, signature, signature verification, etc. on payment and transaction information as part of the payment transaction. it can.

  The reader chip 100 can also include a clock 124 and a bias generator 126. Bias generator 126 can be connected to power source 106 and can generate one or more bias voltages that are provided to components of reader chip 100 such as contact interface 104, processing unit 120, and memory 122. . In one embodiment, a suitable bias voltage generated by the bias generator 126 may be 3.3 volts. The clock 124 may include a clock source (not shown) and a clock management unit (not shown). The clock source can be any suitable clock source, such as a crystal oscillator, and a clock signal with a clock frequency can be provided to the clock management unit. Based on the input from the clock source, the clock management unit is configured with a plurality of clock signals (output by the clock 124), for example, a clock signal for the processing unit 120 and a frequency suitable for transmission for near field communication ( For example, a clock signal having 13.56 MHz) can be generated.

  FIG. 4 illustrates an exemplary schematic diagram of some components of the clock 124 according to some embodiments of the present disclosure. In one embodiment, the components and circuits shown in FIG. 4 may correspond to a transition filter 400 that removes unwanted transitions (eg, glitches) from the rising and falling edges of the clock signal. In other embodiments, transition filter 400 may be used to remove unwanted transitions from the rising and falling edges of other data signals. Although particular components are shown in the particular configuration of FIG. 4, transition filter 400 can include additional components, one or more of the components shown in FIG. 4 being transition filters. It should be understood that the components of transition filter 400 may not be included in 400 and may be reconfigured in any suitable manner. In one embodiment, transition filter 400 includes at least input connection 402, delay element 404, first and second NAND gates 406 and 408, first and second NOR gates 410 and 412, multiplexer 414, Output connection 416.

  Transition filter 400 may receive a clock signal at input connection 402. In one embodiment, the clock signal at the input connection can be provided by either a clock source or a clock management unit. The input clock signal can be supplied to the first path 401 and the second path 403 in parallel with the first path 401. The first path 401 can include a first NAND gate 406 and a second NOR gate 412. The second path 403 can include a delay element 404, a first NOR gate 410, and a second NAND gate 408. The first path 401 and the second path 403 can be provided as individual inputs to the multiplexer 414. The output of multiplexer 414 can be coupled to output connection 416. The output connection 416 can be used to provide an output clock signal to another component of the clock 124 (eg, a clock management unit) or the reader chip 100 (eg, the contact interface 104).

  A clock signal from input connection 402 may be provided to the first inputs of both first NAND gate 406 and first NOR gate 410 and to delay element 404. The delay element 404 can delay the input clock signal by a predetermined time delay ΔT (see FIG. 5). In one embodiment, the predetermined time delay can be shorter than the period of the clock signal and longer than any expected “glitch” period. In another embodiment, the predetermined time delay can be greater than the period of the clock signal. Less than half (1/2). In one embodiment, the delay element 404 can include one or more buffer elements or inverters for delaying the input clock signal. However, in other embodiments, other elements (eg, RC filters) can be used to delay the input clock signal. The delayed clock signal from delay element 404 can then be provided to the second inputs of both first NAND gate 406 and first NOR gate 410.

  The output of the first NAND gate 406 when the voltage of the signal at the first and second inputs of the first NAND gate 406 exceeds a value that is less than both (eg, logic 0) (eg, logic 1). Can be a signal having a voltage below the voltage threshold (eg, logic 0). In other words, if both the input clock signal and the delayed clock signal supplied to the first NAND gate 406 are “high” voltage (eg, logic 1), the output signal of the first NAND gate 406 is “low”. Voltage (eg, logic 0). For any other combination of “high” or “low” inputs in the first NAND gate 406 provided by the input clock signal and the delayed clock signal, the output signal of the first NAND gate 406 is “high” or Can be logic one.

  When the voltage of the signal at the first and second inputs of the first NOR gate 410 is both below the voltage threshold of the NOR gate 410 (eg, logic 0), the output of the first NOR gate 410 is It can be a signal (eg, logic 1) having a voltage that exceeds a voltage threshold. In other words, if both the input clock signal and the delayed clock signal supplied to the first NOR gate 410 are “low” (eg, logic 0), the output signal of the first NOR gate 410 is “high” ( For example, logic 1). For any other combination of “high” or “low” inputs in the first NOR gate 410 provided by the input clock signal and the delayed clock signal, the output signal of the first NOR gate 410 is “low” or Can be logic zero.

  The output signal of the first NAND gate 406 can be supplied to both inputs of the second NOR gate 412. The output signal of the second NOR gate 412 may be “high” or logic 1 when the output signal of the first NAND gate 406 is “low” or logic 0, and the output signal of the second NOR gate 412 Can be “low” or logic zero when the output signal of the first NAND gate 406 is “high” or logic one. In one embodiment, the inputs of the second NOR gate 412 are coupled together and receive the same signal (eg, the output of the first NAND gate 406), so that the second NOR gate 412 behaves like an inverter. Can do.

  The output signal of the first NOR gate 410 can be supplied to both inputs of the second NAND gate 408. The output signal of the second NAND gate 408 can be “high” or logic 1 when the output signal of the first NOR gate 410 is “low” or logic 0, and the output signal of the second NAND gate 408 is If the output signal of the first NOR gate 410 is “high” or logic one, it can be “low” or logic zero. In one embodiment, the inputs of the second NAND gate 408 are coupled together and receive the same signal (eg, the output of the first NOR gate 410), so that the second NAND gate 408 operates similarly to an inverter. Can do.

  In one embodiment, the second NOR gate 412 and the second NAND gate 408 are replaced by “replicas” (ie, substantially the same or identical components) of the first NOR gate 410 and the first NAND gate 406. It can be. By using a “replica” of the first NOR gate 410 and the first NAND gate 406 to the second NOR gate 412 and the second NAND gate 408, the input of the first NAND gate 406 and the second NOR gate are used. The propagation delay between the output of gate 412 can be the same as the propagation delay between the input of first NOR gate 410 and the output of second NAND gate 408. In other words, the first NAND gate 406 and the second NOR gate 412 can operate at the same speed as the first NOR gate 410 and the second NAND gate 408. By maintaining the same speed or propagation delay for the signals passing through the first NAND gate 406 and the second NOR gate 412 and the first NOR gate 410 and the second NAND gate 408, the duty cycle of the output signal is It can be kept substantially the same as the duty cycle of the input signal at the input connection 402. In one embodiment, if the input signal at input connection 402 is a clock signal having a 50% duty cycle, the output signal maintains a 50% duty cycle. In another embodiment, the first NAND gate 406 and the second NOR gate 412 of the first path 401 can provide the same logic output as the AND gate (based on the same input) The first NOR gate 410 and the second NAND gate 408 can provide the same logic output as the OR gate (based on the same input).

  The output signal of the second NOR gate 412 can be supplied to the first input of the multiplexer 414 (identified as 0 in FIG. 4), and the output signal of the second NAND gate 408 is supplied to the second input of the multiplexer 414. Input (identified by 1 in FIG. 4). The select signal supplied to multiplexer 414 determines whether the signal at the first input of multiplexer 414 or the signal at the second input of multiplexer 414 is supplied to the output of multiplexer 414. If the select signal is “low” or logic zero (eg, as a result of the output being a logic zero or “low” signal previously), multiplexer 414 provides a signal at the first input to output connection 416. . If the select signal is “high” or logic 1 (eg, as a result of the output being a logic 1 or “high” signal previously), multiplexer 414 provides a signal at the second input to output connection 416. . In one embodiment, the output of multiplexer 414 can be used as a selection signal, thereby enabling multiplexer 414 to be self-selectable.

  An exemplary operation of the transition filter 400 will be described with respect to the input / output signals shown in FIG. As shown in FIG. 5, undesirable transitions that occur in the input signal in relation to the rising or falling edge of the signal are not propagated to the output signal. Thus, the transition filter 400 can provide “time domain hysteresis” to the input signal and eliminate short-term changes in the input signal. In FIG. 5, the input signal transitions from “low” to “high” at time T1, an undesirable transition (or glitch) of the input signal occurs for a short duration at time T2, and the input signal is “high” at time T3. To “low” and another undesired transition (or glitch) of the input signal occurs for a short duration at time T4. After the input signal of FIG. 5 passes through the transition filter 400, the output signal of FIG. 5 is generated. The output signal transitions from “low” to “high” at time T5, and transitions from “high” to “low” at time T6. The transition of the output signal at T5 and T6 occurs after a predetermined time delay ΔT from the corresponding transition of the input signal occurring at T1 and T3. As can be seen from the output signal of FIG. 5, the undesired transitions of the input signal occurring at T2 and T4 are removed from the output signal by transition filter 400, and the duty cycle is maintained by a balanced delay ΔT occurring at both transitions. . In this way, the transition filter 400 can remove unnecessary transitions of the input signal having a duration shorter than a predetermined time delay ΔT, as will be described later.

  As described above, the output of multiplexer 414 is based on the current output signal at output connection 416, ie, the signal at the first input (ie, the output of second NOR gate 412) or the signal at the second input (ie, , The output of the second NAND gate 408). In the exemplary embodiment of FIG. 5, both the input signal and the output signal start “low” so that multiplexer 414 selects first path 401 to provide the output signal. As long as the input signal remains “low”, the first input to the multiplexer is “low” because of the “low” input to the first NAND gate 406 (ie, the input signal and the delayed input signal). As such, the output signal remains “low”. The “low” output signal from multiplexer 414 indicates that the first input of multiplexer 414 is selected as the output, and therefore the second input to multiplexer 414 need not be discussed at this point. .

  When the input signal transitions to “high” at time T1, the second input to the NAND gate 406 remains low based on the delay ΔT of the delay element 404, so a predetermined time delay ΔT elapses at time T5. Until then, the output signal remains “low”. Once the predetermined time delay ΔT has elapsed, the first input to the multiplexer 414 is “high” due to the “high” input (ie, the input signal and the delayed input signal) to the first NAND gate 406, so The output signal goes “high”. The output of the first NAND gate 406 remains “high” because the delayed input signal is “low” for a predetermined time delay ΔT, which includes a period of undesirable transitions at T2, so at time T2. Undesirable transitions are not propagated to the output signal. In other words, the first NAND gate 406 does not “see” an undesired transition at T2 because the “low” or logic zero input from the delayed input signal controls the output of the first NAND gate 406.

  After the output signal at output connection 416 transitions high at time T5 based on delay ΔT, multiplexer 414 begins using the signal at the second input of multiplexer 414 as the output signal. A “high” output signal from multiplexer 414 indicates that the second input from second path 403 of multiplexer 414 is selected as an output. Therefore, the delayed version of the glitch at time T2 is not seen in the first path 401 because the first path 401 is no longer selected. When both the input signal and the delayed input signal are “high” and the second path 403 is selected, the second input to the multiplexer 414 is the “high” input to the first NOR gate 410 (ie, Initially "high" for the input signal and the delayed input signal). When a delayed version of the glitch occurs in the delayed input signal, the input signal from the input connection 402 remains “high”, so the output of the first NOR gate 410 remains “low”, which is an undesirable transition. Does not propagate to the output signal. In other words, the “high” of the input signal from the input connection 402 or a logic 1 input prevents the output transition of the first NOR gate 410 (ie, the “high” input signal is the output of the first NOR gate 410. The first NOR gate 410 does not “see” unwanted transitions in the delayed input signal.

  When the input signal transitions to “low” at time T3, the output signal remains “high” until a predetermined time delay ΔT elapses at time T6. Once the predetermined time delay ΔT has elapsed, the second input to the multiplexer 414 is “low” due to the “low” input to the first NOR gate 410 (ie, the input signal and the delayed input signal), so The output signal goes “low”. Since the delayed input signal is “high” for a predetermined time delay including the period of unnecessary transition at T4, the output of the first NOR gate 410 remains “high”, and therefore unnecessary at time T4. Transitions do not propagate to the output signal. In other words, since the “high” or logic 1 input from the delayed input signal controls the output of the first NOR gate 410, the first NOR gate 410 does not “see” an undesirable transition at T4.

  After the output signal at output connection 416 transitions “low” at time T6, multiplexer 414 begins to use the signal at the first input from first path 401 of multiplexer 414 as described above, as described above. . Therefore, a delayed version of the glitch at time T4 is not seen in the second path 403 because the second path 403 is no longer selected. When both the input signal and the delayed input signal are “low” and the first path 401 is selected, the first input to the multiplexer 414 is the “low” input to the first NAND gate 406 ( That is, it is initially “low” for the input signal and the delayed input signal. If a delayed version of the glitch occurs in the delayed input signal, the input signal from the input connection 402 remains “low”, which is undesirable because the output of the first NAND gate 406 remains “high”. Transitions do not propagate to the output signal. In other words, the “low” or logic zero input of the input signal from the input connection 402 prevents the output transition of the first NAND gate 406 (ie, the “low” input signal causes the output of the first NOR gate 410 to The first NAND gate 406 does not “see” unwanted transitions in the delayed input signal.

  FIG. 6 illustrates an exemplary schematic diagram of some components of the bias generator 126 according to some embodiments of the present disclosure. In one embodiment, the components and circuits shown in FIG. 6 correspond to the supply voltage monitoring circuit 600, which monitors the supply voltage (AVDD) provided by the bias generator 126 and the supply voltage is low (ie, A reset signal (RESETN_OUT) can be provided when less than a predetermined threshold voltage. Although particular components are shown in the particular configuration of FIG. 6, supply voltage monitoring circuit 600 can include additional components, one or more of the components shown in FIG. It should be understood that the supply voltage monitoring circuit 600 may not be included and the components of the supply voltage monitoring circuit 600 may be reconfigured in any suitable manner.

  In one embodiment, the supply voltage monitoring circuit 600 includes at least a first voltage monitoring circuit 602, a second voltage monitoring circuit 604, a first current source 606, a capacitor 608, and a first comparator 610. And an output connection 612. The first voltage monitoring circuit 602 includes at least a band gap circuit having a second current source 614 and a first resistor 616, a voltage divider having a second resistor 618 and a third resistor 620, A second comparator 622 and a first switching element 624 can be included. The second voltage monitoring circuit 604 can include a diode 626, a fourth resistor 628, a third current source 630, a second switching element 632, and a third switching element 634. .

  The power supply voltage monitoring circuit 600 can be used to provide a RESETN_OUT signal. The RESETN_OUT signal provided at output connection 612 may be used to control the operation of one or more elements of reader chip 100 based on the level of supply voltage AVDD provided by bias generator 126. In one embodiment, AVDD can be 3.3V, while in other embodiments AVDD can have different voltage values. When AVDD falls below a predetermined supply voltage threshold, the RESETN_OUT signal can be used to initiate a reset state of one or more elements of the reader chip 100. In one embodiment, the predetermined supply voltage threshold can be set by a voltage divider as described in detail below, and can be a voltage in the range of about 2.3V to about 3.2V. In one embodiment, the RESETN_OUT signal can be “high” or logic 1 if AVDD is greater than the predetermined supply voltage threshold, and if AVDD is less than the predetermined supply voltage threshold. The RESETN_OUT signal can be “low” or logic zero. When the RESETN_OUT signal is “low”, one or more elements of the reader chip 100 are reset until AVDD stabilizes at a voltage higher than a predetermined supply voltage threshold and the RESETN_OUT signal becomes “high”. However, in other embodiments, one or more elements of the reader chip 100 can be reset in response to the RESETN_OUT signal becoming “high” or a logic one.

  The RESETN_OUT signal is supplied to the output connection 612 by the first comparator 610. The output of the first comparator 610 can be controlled by the voltage at VA provided as an input to the first comparator. The first comparator 610 compares the voltage at VA with a predetermined reset voltage threshold (or a predetermined comparator voltage threshold). If the voltage at VA is less than a predetermined reset voltage threshold, the first comparator 610 outputs a reset voltage value that is “low” or logic 0 as a RESETN_OUT signal (AVDD is a predetermined supply voltage threshold). If the voltage at VA is greater than or equal to a predetermined reset voltage threshold, the first comparator 610 sets the operating voltage value that is “high” or logic 1 to the RESETN_OUT signal. (Corresponding to AVDD being larger than a predetermined supply voltage threshold). In one embodiment, the first comparator 610 can be a Schmitt trigger, but in other embodiments other configurations of the first comparator 610 are possible.

  The voltage at VA can be controlled by the operation of first current source 606, capacitor (or charge storage device) 608, first switching element 624, and third switching element 634. A first current source 606 is coupled between AVDD and VA and can be used to charge a capacitor 608 coupled between VA and ground. Both the first switching element 624 of the first voltage monitoring circuit 602 and the third switching element 634 of the second monitoring circuit are in an “off” state in response to receiving the enable voltage (ie, open circuit). The charging capacitor 608 may be charged by the first current source 606. When capacitor 608 is charging, the voltage at VA increases from the charge stored in capacitor 608 and provides an enable input to first comparator 610. As described above, when the voltage at VA is greater than or equal to a predetermined reset voltage threshold, the RESETN_OUT signal output from the first comparator 610 changes from “low” or logic 0 to “high” or logic 1. be able to.

  Each of first switching element 624 and third switching element 634 may also be coupled between VA and ground when in an “on” state in response to receiving a disable voltage. When either or both of the first switching element 624 and the third switching element 634 are in the “on” state (ie, operate as a short circuit), the “on” switching element is grounded from the first current source 606. The first current source 606 does not charge the capacitor 608 since the capacitor 608 is discharged. As capacitor 608 is discharged, the voltage at VA drops and eventually drops to about 0 V (volt), providing a disable input to first comparator 610. When the voltage at VA falls below a predetermined reset voltage threshold (eg, including an additional hysteresis drop in some embodiments), the RESETN_OUT signal output from the first comparator 610 is “low” or a logic zero. Can be. In one embodiment, the first current source 606 can include one or more transistors and one or more resistors. However, other configurations of the first current source 606 are possible in other embodiments. In another embodiment, the first switching element 624 and the third switching element 634 can each be a p-channel MOSFET (metal oxide semiconductor field effect transistor). However, in other embodiments, the first switching element 624 and the third switching element 634 may be other types of transistors (eg, bipolar junction transistor (BJT) or junction field effect transistor (JFET)), or other Other switching configurations that use components (eg, physical switches or other semiconductor devices) can be used.

  The first voltage monitoring circuit 602 can be used to switch the first switching element 624 to the “on” state when AVDD is below a predetermined supply voltage threshold. If AVDD is greater than a predetermined supply voltage threshold, the first voltage monitoring circuit 602 can switch the first switching element 624 to the “off” state. The first switching element 624 can be controlled by the voltage of VCNTRL corresponding to the output of the second comparator 622. When the voltage on VCNTRL is “high” or logic 1, the first switching element 624 is switched to the “on” state, and when the voltage on VCNTRL is “low” or logic 0, the first switching element 624 is Switched to the “off” state. As described above, in one embodiment, the first switching element 624 may be a p-channel MOSFET. The gate of switching element 624 can be coupled to VCNTRL, the source can be coupled to ground, and the drain can be coupled to VA.

  The output of the second comparator 622 includes a first input that receives a voltage at VBG that is an output voltage from the bandgap circuit, and a second input that receives a voltage at VSUPPLY_MON that is an output voltage from the voltage divider. Can be based on a comparison between. If the voltage on VBG is greater than the voltage on VSUPPLY_MON, the second comparator 622 can output a “high” or logic 1 signal, and if the voltage on VBG is less than or equal to the voltage on VSUPPLY_MON, the second comparator. Can output a “low” or logic zero signal. In one embodiment, the second comparator 622 can be an operational amplifier, but in other embodiments, other configurations of the second comparator 622 are possible.

  As mentioned above, the voltage divider can include a second resistor 618 and a third resistor 620 and can be used to establish a proportional supply voltage or monitor voltage at VSUPPLY_MON. A second resistor 618 can be coupled between AVDD and VSUPPLY_MON, and a third resistor 620 can be coupled between VSUPPLY_MON and ground. The voltage at VSUPPLY_MON can be used by the second comparator 622 to monitor AVDD and corresponds to a predetermined portion of AVDD based on the resistance values of the second resistor 618 and the third resistor 620. To do. In one embodiment, the ratio of resistance values between the second resistor 618 and the third resistor 620 may be selectable to obtain different predetermined supply voltage thresholds. In other words, the resistance values of the second resistor 618 and the third resistor 620 can be selected such that the voltage at VSUPPLY_MON can drop below the voltage at VBG due to different values of AVDD. For example, the second resistor 618 and the third resistor 620 may have resistance values such that the voltage at VSUPPLY_MON drops below the voltage at VBG when AVDD is 3V. Thus, as a result of the configuration of the second resistor 618 and the third resistor 620, a predetermined supply voltage threshold is established at 3V. However, the second resistor 618 and the third resistor 620 may have resistance values such that when AVDD is 2.4 V, the voltage at VSUPPLY_MON drops below the voltage at VBG. Results in a predetermined supply voltage threshold which is 2.4V.

  A bandgap circuit can be used to establish a substantially constant and temperature independent voltage in the VBG. The bandgap circuit can be coupled to AVDD and can begin to operate when AVDD exceeds a predetermined bandgap voltage threshold (or bandgap turn-on voltage). In one embodiment, the predetermined bandgap voltage threshold can be about 0.74 V, but in other embodiments, other voltages can be used as the predetermined bandgap voltage. The bandgap circuit includes a second current source 614 coupled between AVDD and VBG, and a first resistor 616 coupled between VBG and ground. The first resistor 616 may be a polysilicon resistor in one embodiment, but may be other types of resistors in other embodiments. The second current source 614 can provide a current that is inversely proportional to the sheet resistance of the first resistor 616. When the current from the second current source 614 is passed to the first resistor 616, it can generate a fixed or constant voltage over process and temperature. In one embodiment, the current from the second current source 614 can be provided from an analog front end (AFE) circuit on the reader chip 100. In another embodiment, the second current source 614 and the first resistor 616 can be fabricated on the same material so that they have the same temperature coefficient. In one embodiment, the second current source 614 can include one or more transistors and one or more resistors. However, other configurations of the second current source 614 are possible in other embodiments.

  The second voltage monitoring circuit 604 can be used to monitor AVDD when AVDD is less than a predetermined bandgap voltage threshold, below which the first voltage monitoring is performed. The circuit 602 is inoperable or unpredictable due to variations in operation of the bandgap circuit due to low AVDD. The second voltage monitoring circuit 604 switches the third switching element 634 to the “on” state when AVDD is less than a predetermined diode voltage threshold of the diode 626 (eg, the capacitor 608 is discharged). Can be used, so as not to be charged). If AVDD is greater than a predetermined diode voltage threshold, the second voltage monitoring circuit 604 can charge the capacitor 608 by switching the third switching element 634 to the “off” state. The third switching element 634 can be controlled by the voltage of VCNTRL2. When the voltage on VCNTRL2 is “high” or logic 1, the third switching element 634 is switched to the “on” state, and when the voltage on VCNTRL2 is “low” or logic 0, the third switching element 634 is Switched to the “off” state. As described above, in one embodiment, the third switching element 624 can be a p-channel MOSFET. The gate of switching element 624 can be coupled to VCNTRL2, the source can be coupled to ground, and the drain can be coupled to VA.

  The second voltage monitoring circuit 604 can include a third current source 630 coupled to AVDD and VCNTRL2. The third current source 630 can be used to set the voltage of VCNTRL2 to “high” or logic 1 when the second switching element 632 is in the “off” state. In one embodiment, the second switching element 632 can operate like an open drain transistor. When the second switching element 632 is in the “on” state, the second switching element 632 sinks current from the third current source 630 to ground, and the voltage of VCNTRL2 is about 0V, which is Corresponds to a “low” or logic zero signal. In one embodiment, the third current source 630 can include one or more transistors and one or more resistors. However, other configurations of the third current source 630 are possible in other embodiments.

  The second switching element 632 is switched to an “on” state when the voltage on VDIODE is “high” or a logic one, and the second switching element 632 is when the voltage on VDIODE is “low” or a logic zero To the “off” state. In one embodiment, the second switching element 632 can be a p-channel MOSFET. However, the second switching element 632 may be, in other embodiments, other types of transistors (eg, bipolar junction transistor (BJT) or junction field effect transistor (JFET)), or other components (eg, physical switches). Alternatively, other switching configurations using other semiconductor devices) can be used. The gate of the second switching element 632 can be coupled to VDIODE, the source can be coupled to ground, and the drain can be coupled to VCNTRL2. The voltage at VDIODE is based on whether AVDD is greater or less than a predetermined diode voltage threshold associated with diode 626. If AVDD is greater than a predetermined diode voltage threshold, current flows through diode 626 and fourth resistor 628 provides a voltage of VDIODE. If VDIODE is greater than the threshold voltage of second switching element 632 (ie, VDIODE goes to logic 1), second switching element 632 is switched to the “on” state. In contrast, when AVDD is below a predetermined diode voltage threshold, diode 626 blocks the current, fourth resistor 628 raises the voltage on VDIODE to about 0V, and second switching element 632 “ Switched to the “off” state.

  An exemplary operation of the voltage monitoring circuit 600 will be described with respect to the input and output signals shown in FIGS. FIG. 7 shows the value of the selected signal during a power up event (ie, AVDD goes from 0V to the desired voltage level). FIG. 8 shows the value of the selected signal during a power saving event (ie, AVDD is below a predetermined supply voltage threshold for a short period of time).

As shown in FIG. 7, AVDD starts at about 0V at time t0 and gradually increases until AVDD reaches its maximum value at time t6. Since VSUPPLY_MON is based on AVDD, the VSUPPLY_MON signal tracks AVDD except that it is a fraction of the value of AVDD. At time t0, the voltage at VDIODE is 0V because AVDD is not greater than a predetermined diode voltage threshold (this switches the second switching element 632 “off”), and the voltage at VCNTRL2 is the second Since the switching element 632 of the second switch is “off”, it is “high” or logic one (this turns on the third switching element 634). Since the third switching element 634 is “on” at time t0, and the third switching element 634 short-circuits VA to the ground, and as a result, the RESETN_OUT signal becomes “low”, the voltage of VA is about 0V. The voltage at VBG is about 0 V at time t0 because AVDD is equal to or lower than a predetermined band gap voltage threshold value for operating the band gap circuit. When VBG is at a low voltage, VSUPPLY_MON is equal to or higher than VBG, and the first switching element 624 can be switched “off”, so that VCNTRL can be set to “low”.

  At time t1, since AVDD is greater than a predetermined bandgap voltage threshold, the bandgap circuit is switched “on”. Next, the band gap circuit starts to supply the band gap reference voltage in VBG at time t2. Since the bandgap reference voltage at t2 is greater than the voltage at VSUPPLY_MON, the signal at VCNTRL goes “high” and switches the first switching element 624 “on”. Since the first switching element 624 is on at time t2, and the first switching element 624 short-circuits VA to the ground, and as a result, the RESETN_OUT signal becomes “low”, the voltage of VA is about 0V. VCNTRL can remain “high” until time t5 when VCNTRL switches to “low” in response to the voltage at VSUPPLY_MON being greater than the VBG bandgap reference voltage. At time t3, since AVDD is greater than a predetermined diode voltage threshold, diode 626 is turned “on”. The diode 626 then begins to allow some current flow and the voltage at VDIODE begins to increase. At time t4, the voltage at VDIODE becomes greater than the threshold voltage of the second switching element 632, and the second switching element 632 is switched “on”. Switching the second switching element “ON” sinks current from the third current source 630 to ground, driving the voltage of VCNTRL2 to about 0 V, which turns the third switching element 634 “OFF”. .

  When VCNTRL switches to “low” at time t5, the first switching element 624 switches to “off” and the first current source 606 (since the third switching element switches to “off” at time t4). Capacitor 608 can begin to charge. The voltage at VA can be increased by charging capacitor 608, at time t6, voltage VA becomes greater than a predetermined reset voltage threshold, and the RESETN_OUT signal from first comparator 610 is “high” or logic Switch to 1.

  As shown in FIG. 8, AVDD starts at its maximum voltage at time t0, starts a power saving event at time t1, reaches a reduced voltage value at time t2, ends the power saving event at time t3, and time t4 and t5. To return to its maximum voltage. Since VSUPPLY_MON is based on AVDD, the VSUPPLY_MON signal tracks AVDD except that it is a fraction of the value of AVDD. Since AVDD is greater than a predetermined diode voltage threshold of diode 626, diode 626 is “on” and the voltage on VDIODE is “high”. Since the voltage of VDIODE is “high”, the second switching element 632 is switched “on”. Switching the second switching element “ON” sinks current from the third current source 630 to ground, driving the voltage of VCNTRL2 to about 0 V, which turns the third switching element 634 “OFF”. .

  At time t0, the voltage at VSUPPLY_MON is greater than the bandgap reference voltage at VBG, and as a result, VCNTRL goes “low” and the first switching element 624 turns “off”. When both the first switching element 624 and the third switching element 634 are switched “off”, the first current source 606 charges the capacitor 608 to bring the voltage at VA above a predetermined reset voltage threshold. Can be driven high so that the RESETN_OUT signal from the first comparator 610 goes high or logic one.

  When a power saving event occurs at time t1, the bandgap reference voltage becomes greater than the voltage at VSUPPLY_MON, the signal at VCNTRL goes “high” and switches the first switching element 624 “on”. Since the first switching element 624 is on at time t1, and the first switching element 624 shorts VA to ground, resulting in the RESETN_OUT signal going “low”, the voltage on VA is about 0V. When the power saving event ends at time t4, the voltage at VSUPPLY_MON becomes greater than the bandgap reference voltage at VBG, and the signal at VCNTRL switches to “low”. When VCNTRL switches to “low” at time t4, the first switching element 624 switches to “off”, and the first current source 606 switches (because the third switching element switches to “off” at time t0). ) Capacitor 608 can begin to charge. The voltage at VA can be increased by charging capacitor 608, at time t5, voltage VA becomes greater than a predetermined reset voltage threshold, and the RESETN_OUT signal from first comparator 610 is “high” or logic Switch to 1.

  FIG. 9 shows an exemplary schematic diagram of some components of an AC level shift circuit according to some embodiments of the present disclosure. In one embodiment, the components and circuits shown in FIG. 9 correspond to a level shift circuit 900 for shifting the voltage level of the input clock signal from a first level to a second level that is greater than the first level. May be. Although specific components are shown in the specific configuration of FIG. 9, level shift circuit 900 can include additional components, and one or more of the components shown in FIG. It should be understood that the shift circuit 900 may not be included and the components of the level shift circuit 900 may be reconfigured in any suitable manner. In one embodiment, the level shift circuit 900 includes at least an input connection 902, a buffer 904, a capacitor 906, a first switch 908 and a second switch 910, a self-bias inverter 925, an inverter 920, and an output. Connection 922. The self-biased inverter 925 can include a first resistor 912 and a second resistor 914, a first switching element 916, and a second switching element 918.

  Level shift circuit 900 can be used to raise (or boost) the voltage level of the signal supplied to input connection 902 to the desired voltage level for the signal at output connection 922. In one embodiment, the level shift circuit 900 can adjust a periodic input signal of about 1.2V to a periodic output signal of about 5V having the same frequency as the input signal. However, in other embodiments, the level shift circuit 900 can be used with different input voltages and can provide different output voltages. Further, the level shift circuit 900 can provide an output signal with substantially the same duty cycle as the input signal.

  Level shift circuit 900 can receive an input signal at input connection 902. In one embodiment, the input signal may be a 1.2V clock signal. The input signal passes through buffer element 904 and capacitor 906, and capacitor 906 AC couples the input signal to self-biased inverter 925 at P1. In one embodiment, the buffer element 904 can include one or more inverters, although other components can be used for the buffer element 904 in other embodiments. In one embodiment, the capacitor 906 can have a capacitance of about 1.25 pF (picofarad), although other embodiments can have other capacitances. In another embodiment, the capacitor 906 can operate similar to a high pass filter to remove frequencies below a predetermined threshold frequency. Capacitor 906 passes the frequency of the input signal, but can be configured to remove any DC component of the input signal.

  The self-biased inverter 925 can have an input P1 that is biased with a bias voltage. In one embodiment, the bias voltage can correspond to the threshold voltage of the self-biased inverter 925. The input signal from capacitor 906 is then AC coupled (ie, hopped) to the bias voltage at P1, and if the input signal is “high” or logic one, the self-biased inverter 925 is switched to the “on” state, Alternatively, the self-biased inverter 925 can be switched to the “off” state when the input signal is “low” or logic zero. In other words, if the input signal from the capacitor 906 is positive or “high”, the input voltage of the self-bias inverter 925 exceeds the threshold voltage (and the self-bias inverter 925 is switched to the “on” state). The input voltage at P1 can be increased so that the input signal from capacitor 906 is negative or “low” so that the input voltage of self-biased inverter 925 does not exceed the threshold voltage. (And so that the self-biased inverter 925 can switch to the “off” state), the input voltage at P1 can be reduced. The self-biased inverter 925 can output “low” or logic 0 when in the “on” state and can output “high” or logic 1 when in the “off” state. By providing the output of the self-biased inverter 925 at P2 to the inverter 920, the output of the self-biased inverter 925 matches the polarity of the input clock signal (eg, if the input clock signal is “high”, the output signal is Can be converted to a signal on the output connection 922, which can be “high”. The output of the self-biased inverter 925 may be a voltage corresponding to the voltage of VCC when “high”, and this voltage level is conveyed to the output signal of the inverter 920 (ie, the output of the inverter 920 is “high”. ”May be a voltage corresponding to the voltage of VCC).

  The self-biased inverter 925 can include a first switching element 916 connected in series with a second switching element 918. Both the first switching element 916 and the second switching element 918 receive the same input from P1. Similarly, the outputs of the first switching element 916 and the second switching element 918 are coupled together at P2. Furthermore, the output at P2 is connected to the input at P1 in a feedback loop. In one embodiment, the feedback loop can include a first resistor 912 and a second resistor 914. However, in other embodiments, the feedback loop may use different configurations such as more or fewer resistors and additional components (eg, capacitors) than shown in FIG. In one embodiment, the first resistor 912 and the second resistor 914 can each have a resistance of about 500 kΩ (kiloohms), while other embodiments can have other resistances or different resistances. . In addition, the first switching element 916 can be connected to the voltage source VCC, and the second switching element can be grounded. In one embodiment, VCC can be 5V, but in other embodiments, VCC can have other voltages. In one embodiment, the first switching element 916 can be an n-channel MOSFET and the second switching element 918 can be a p-channel MOSFET. However, in other embodiments, the first switching element 916 and the second switching element 918 are other types of transistors (eg, bipolar junction transistor (BJT) or junction field effect transistor (JFET)), or other Other switching configurations that use components (eg, physical switches or other semiconductor devices) can be used.

  In one embodiment, when a “high” input is applied to P1, the first switching element 916 switches to “off”, operates like an open circuit, the second switching element 918 switches to “on”, It behaves like a short circuit that pulls P2 to ground (ie, 0V). When a “low” input is applied to P1, the second switching element 918 switches “off” and operates like an open circuit, and the first switching element 916 switches “on” and operates like a short circuit. As a result, P2 receives a voltage of VCC (for example, 5V). The operation of the first switching element 916 to supply a voltage of VCC to P2 with a “low” input has a first resistor 912 and a second resistor 914 to establish a bias voltage of P1. Can be used in conjunction with a feedback loop. In one embodiment, the bias voltage may be half (1/2) of the voltage at VCC.

  The level shift circuit 900 can also include a first switch 908 and a second switch 910. The first switch 908 and the second switch 910 may be in a closed position during operation of the level shift circuit. When the level shift circuit 900 is deactivated (or powered down), one or both of the first switch 908 and the second switch 910 are opened so that the capacitor 906 and the input P1 and the self-bias inverter 925 The coupling can be broken or the feedback path can be removed from the self-biased inverter 925.

  Since the self-bias inverter 925 has a bias voltage close to the threshold voltage at the input P1, the self-bias inverter 925 can maintain the duty cycle of the input signal at the output P2 from the self-bias inverter 925. As noted above, the change in input signal between “high” and “low”, when combined with the bias voltage at P1, causes a similar timing change at the input to the self-biased inverter 925, thereby The duty cycle of the input signal at the output of the self-biased inverter 925 and the output connection 922 can be maintained.

  In one embodiment of the present disclosure, a system for monitoring a supply voltage includes an input connection for receiving a supply voltage, a first current source, and a capacitor connected to the first current source at a first node. , And the capacitor is configured to be charged by a current from the first current source. The system further comprises a first comparator connected to the capacitor and the first current source at the first node, the first comparator having a voltage at the first node lower than a comparator voltage threshold. And a reset signal having a reset voltage value is output, and an operating voltage value is output based on the voltage at the first node being higher than the comparator voltage threshold. The system further comprises a first monitoring circuit connected to the input connection and the first node, the first monitoring circuit comprising a supply voltage divider connected to the input connection, wherein the supply voltage divider is A first monitoring circuit configured to provide a proportional supply voltage based on the supply voltage and the supply voltage divider; and a bandgap circuit connected to the input connection, wherein the bandgap circuit is a temperature A bandgap circuit configured to provide a reference voltage independent of variation, and a second comparator connected to the supply voltage divider and the bandgap circuit, the second comparator being the reference voltage A first disable voltage in response to being higher than the proportional supply voltage, and a first enable voltage in response to the proportional supply voltage being higher than the reference voltage. A second comparator configured to output; and a first switching element connected to the second comparator and connected to the first node in parallel with the capacitor, the first switching element Provides a circuit path between the first node and ground when the first disable voltage is received from the second comparator, and the first enable voltage is received from the second comparator. Then, an open circuit is provided between the first node and ground. The system further includes a second monitoring circuit connected to the input connection and the first node, the second monitoring circuit comprising a diode connected in series between the input connection and ground. A monitoring circuit; a first resistor connected directly between the diode and ground; and a diode switching element having a diode switching input connected to the first resistor, the diode switching element comprising: Outputting a second disable voltage in response to the voltage at the diode switching input being lower than a diode bias threshold voltage, and the voltage at the diode switching input being higher than the diode bias threshold voltage. In response to the second enable voltage. The system further includes a second switching element connected to the diode switching element and connected to the first node in parallel with the capacitor, wherein the second switching element has the second disable voltage applied to the diode switching element. When received from an element, it provides a circuit path between the first node and ground, and when the second enable voltage is received from the diode switching element, it opens between the first node and ground. Configured to provide a circuit.

  In one embodiment, the reference voltage is substantially constant in response to the supply voltage being higher than the band gap voltage minimum threshold.

  In one embodiment, the supply voltage divider comprises a plurality of voltage divider resistors, and the proportional supply voltage is based on the supply voltage and a ratio of resistance values of the plurality of voltage divider resistors.

  In one embodiment, the ratio of one or more of the resistance values of the plurality of voltage divider resistors is a threshold supply voltage required to provide the first enable voltage from the second comparator. Adjustable to adjust.

In one embodiment of the present disclosure, a system for monitoring a supply voltage includes an input connection for receiving the supply voltage, a first current source, and a charge holding connected to the first current source at a first node. A charge retention device configured to be charged by a current from the first current source. The system further comprises a first comparator connected to the charge retention device and the first current source at the first node, the first comparator having a voltage at the first node that is a comparator voltage threshold. A reset signal having a reset voltage value is output based on the lower value, and an operating voltage value is output based on the voltage at the first node being higher than the comparator voltage threshold. The system further comprises a first monitoring circuit connected to the input connection and the first node, wherein the first monitoring circuit is a second comparator having a supply voltage input and a reference voltage input, The comparator has a first disable voltage in response to a voltage at the reference voltage input being higher than a voltage at the supply voltage input, and a first in response to a voltage at the reference voltage input being lower than a voltage at the supply voltage input. A second comparator configured to output an enable voltage; and a first switching element connected to the second comparator and connected in parallel to the charge retention device to the first node. The first switching element provides a circuit path between the first node and ground when the first disable voltage is received from the second comparator. , When the first enable voltage is received from the second comparator configured to provide an open circuit between the ground and the first node.
The system further comprises a second monitoring circuit connected to the input connection and the first node, wherein the second monitoring circuit is connected in series between the input connection and ground, and connected to the diode A diode switching element having a diode switching input, wherein the diode switching element outputs a second disable voltage in response to the supply voltage being lower than a diode bias threshold voltage, and the supply voltage Is configured to output a second enable voltage in response to being higher than the diode bias threshold voltage, and the second monitoring circuit is connected to the diode switching element and in parallel with the charge holding device. A second switching element connected to one node, wherein the second switching element A child provides a circuit path between the first node and ground when the second disable voltage is received from the diode switching element, and the second enable voltage is received from the diode switching element. And an open circuit is provided between the first node and ground.

  In one embodiment, the first monitoring circuit comprises a first circuit configured to provide a voltage proportional to the supply voltage to the supply voltage input of the second comparator.

  In one embodiment, the first circuit includes a plurality of resistors, and the voltage proportional to the supply voltage is based on a ratio of resistance values of the plurality of resistors and the supply voltage.

  In one embodiment, the ratio of one or more of the resistance values of the plurality of resistors adjusts a threshold supply voltage required to provide the first enable voltage from the second comparator. Can be adjusted.

  In one embodiment, the first monitoring circuit comprises a second circuit configured to provide a reference voltage independent of temperature fluctuations to the reference voltage input of the second comparator.

  In one embodiment, the reference voltage is substantially constant in response to the supply voltage being higher than the band gap voltage minimum threshold.

  In one embodiment, the second circuit includes a second current source connected in series with a second resistor, and the reference voltage input to the comparator is connected to the second resistor.

  In one embodiment, the diode switching element includes a first transistor, the second switching element includes a second transistor, the first transistor includes the diode switching input and an output node, and the second transistor includes Connected to the output node and the input node of the first transistor, the first transistor providing a first enable voltage to the second transistor in response to the supply voltage being higher than a diode bias threshold voltage. And a second disable voltage is provided to the second transistor in response to the supply voltage being lower than the diode bias threshold.

  In one embodiment, the first comparator includes a Schmitt trigger.

  In one embodiment of the present disclosure, a system for monitoring a supply voltage comprises an input connection for receiving a supply voltage, and a first comparator, wherein the first comparator is the first comparator. Outputting a reset signal having a reset voltage value based on a voltage at an input to the comparator being lower than a comparator voltage threshold, wherein the voltage at the input to the first comparator is less than the comparator voltage threshold. It is configured to output an operating voltage value based on the high. The system further comprises a first monitoring circuit connected to the input connection and the input to the first comparator, wherein the first monitoring circuit is connected to the input connection; One circuit is configured to provide a proportional supply voltage based on the supply voltage, the first monitoring circuit comprises a second circuit connected to the input connection, the second circuit being independent of temperature variations Configured to provide a voltage, wherein the first monitoring circuit comprises a second comparator connected to the first circuit and the second circuit, wherein the second comparator has the reference voltage as the proportional supply voltage. The first monitoring circuit is configured to output a first disable voltage in response to a higher voltage, and a first enable voltage in response to the proportional supply voltage being higher than the reference voltage. Connected with comparator Both comprising a first switching element connected to the input to the first comparator, the first switching element receiving the first disable voltage when the first disable voltage is received from the second comparator. Providing a first circuit path between the input to the comparator and ground, and when the first enable voltage is received from the second comparator, between the input to the first comparator and ground. Configured to provide an open circuit. The system further comprises a second monitoring circuit connected to the input connection and the input to the first comparator, the second monitoring circuit being connected in series between the input connection and ground. And a first resistor connected directly between the diode and ground, and a second switching element having a switching input connected to the first resistor, the second switching element comprising: Providing a second circuit path between the input to the first comparator and ground in response to the voltage at the switching input being lower than a diode bias threshold voltage, the voltage at the switching input being A circuit is configured to provide an open circuit between the input to the first comparator and ground in response to being higher than the diode bias threshold.

  In one embodiment, the system further comprises a current source and a capacitor connected to the current source at the input to the first comparator, the capacitor being charged by a current from the current source. And is arranged in parallel with the first switching element and the second switching element.

  In one embodiment, the second switching element includes a first transistor having the switching input connected to the first resistor, wherein the first transistor has a voltage at a diode bias threshold. A first enable voltage is provided to the second transistor in response to being higher than a voltage, and a second disable voltage is provided to the second transistor in response to the supply voltage being lower than the diode bias threshold. The second switching element includes a second transistor connected to the output of the first comparator and connected to the input of the first comparator in parallel with the capacitor. Two transistors, when the second disable voltage is received from the first transistor; Providing a second circuit path between the input of the first comparator and ground, and receiving the second enable voltage from the first transistor, the input and ground of the first comparator; Configured to provide an open circuit between.

  In one embodiment, the current source includes a first current source, the second switching element further includes a second current source, the second current source is connected to an output of the first transistor, and The second transistor is configured to provide the second enable voltage.

  In one embodiment, the first circuit includes a plurality of resistors, and the proportional supply voltage is based on a ratio of resistance values of the plurality of resistors and the supply voltage.

  In one embodiment, the ratio of one or more of the resistance values of the plurality of resistors adjusts a threshold supply voltage required to provide the first enable voltage from the second comparator. Can be adjusted.

  In one embodiment, the first comparator includes a Schmitt trigger.

  In certain embodiments of the present disclosure, a method for monitoring a supply voltage includes receiving a supply voltage, providing a proportional supply voltage proportional to the supply voltage, and a first monitoring circuit, wherein the proportional Comparing the supply voltage with a reference voltage; comparing the supply voltage with a diode bias threshold voltage in a second monitoring circuit; and comparing the proportional supply voltage with the reference voltage; Setting an input to a comparator based on the comparison of the supply voltage and the diode bias threshold voltage and providing a reset signal from the comparator based on the input to the comparator. The reset signal has an operating voltage value in response to the input to the comparator being an enable input of a first voltage, and the input to the comparator is the first Voltage A reset voltage value in response to being a disable input of a lower second voltage, wherein the reset voltage value of the reset signal holds at least one component that receives the reset signal in a reset state. Composed. In one embodiment, the setting of the input to the comparator is responsive to at least one of the proportional supply voltage being lower than the reference voltage or the supply voltage being lower than the diode bias threshold voltage. Receiving the disable input at the comparator.

  In one embodiment, the setting of the input to the comparator is dependent on both the proportional supply voltage being higher than the reference voltage and the supply voltage being higher than the diode bias threshold voltage. , Receiving the enable input at the comparator.

  In one embodiment, receiving the enable input includes establishing a first voltage as the input to the comparator by charging a capacitor with a current source, and receiving the disable input comprises: Establishing the second voltage as the input to the comparator by creating a circuit path between the capacitor node and ground.

  In one embodiment, the first monitoring circuit includes a voltage divider, a bandgap circuit, and a switching element, wherein the bandgap circuit is configured to output the reference signal, and the voltage divider is the proportional supply. Configured to provide a voltage, wherein the switching element is responsive to a first state in response to the proportional supply voltage being higher than the reference voltage, and in response to the proportional supply voltage being lower than the reference voltage. Receiving the enable input includes switching the switching element to the first state, and receiving the disable input switches the switching element to the second state. including.

  In one embodiment, the second monitoring circuit includes a diode connected in series with a resistor, and a switching configuration, wherein the diode has the diode bias threshold voltage, and the switching configuration includes: A first state in response to a supply voltage being higher than the diode bias threshold voltage; and a second state in response to the supply voltage being lower than the diode bias threshold voltage; Receiving an enable input includes switching the switching element to the first state, and receiving the disable input includes switching the switching element to the second state.

  In one embodiment, providing the reset signal at the comparator comprises comparing the input to the comparator with a predetermined comparator voltage threshold, the predetermined comparator. The voltage threshold is higher than the second voltage and lower than the first voltage.

  In one embodiment of the present disclosure, a system for adjusting a voltage level of a clock signal includes an input connection for receiving an input clock signal having a first voltage level, and a second voltage higher than the first level. An output connection for providing an output signal having a level, and a capacitor connected to the input connection. The system further includes a first inverter connected to the capacitor at an input node, wherein the first inverter is configured to provide the output signal to the output connection, the output connection being connected to the input node in a feedback loop. The feedback loop is configured to bias the first inverter with a threshold voltage for the first inverter. The first inverter is a first transistor connected to the input node, the output connection, and a voltage source, the voltage source providing a voltage at the second voltage level, and the threshold voltage is Based on a second voltage level, a first transistor, a second transistor connected to the input node, the output connection and ground, and a connection between the input node and the output connection to form the feedback loop The capacitor is connected to the input node for AC coupling the input clock signal to the threshold voltage, so that a change in the input clock signal is A change in the output signal from one inverter is caused.

  In one embodiment, the first transistor includes an n-channel metal oxide semiconductor field effect transistor (MOSFET), and the second transistor includes a p-channel MOSFET.

  In one embodiment, the capacitor is a high pass filter configured to remove frequencies below a threshold frequency.

  In one embodiment, the output signal has a duty cycle that is substantially equal to the duty cycle of the input clock signal.

  In one embodiment, the resistor includes a first resistor connected in series with a second resistor.

  In an embodiment, the system further includes a second inverter connected to the output connection of the first inverter to invert the output signal.

  In one embodiment of the present disclosure, the signal level shift circuit has an input connection for receiving an input signal having a first voltage level and a low voltage level, and a second voltage level higher than the first voltage level. An output connection for providing an output signal; a capacitor connected to the input connection for receiving the input signal; and a capacitor connected to the capacitor for receiving the input signal and for providing the output signal An output module connected to the output connection. In one embodiment, the output module may include a switching circuit. The switching circuit has an input node and an output node connected in a feedback loop. The feedback loop of the switching circuit biases the switching circuit with a threshold voltage. The switching circuit switches to a first state in response to an input voltage at the input node being higher than the threshold voltage, and in response to the input voltage at the input node being lower than the threshold voltage. To switch to the second state. The output signal is based on the switching circuit switching between the first state and the second state. The capacitor is configured to AC couple the input signal to the threshold voltage such that a portion of the input signal at the first voltage level is equal to the input voltage at the input node. A part of the input signal at the low voltage level causes the input voltage at the input node to be lower than the threshold voltage.

  In one embodiment, the switching circuit outputs a signal of the second voltage level in response to the switching circuit switching to the second state, and the switching circuit switches to the first state. Accordingly, a signal having a third voltage level lower than the first voltage level is output.

  In one embodiment, the third voltage level includes a ground voltage level.

  In one embodiment, the switching circuit includes a first inverter, the system includes a second inverter connected to the output connection, the second inverter receives the output signal, and provides an inverted version of the output signal. Configured to provide.

  In one embodiment, the output signal of the second inverter has substantially the same polarity as the input signal.

  In one embodiment, the feedback loop includes a resistor connected between the input node and the output node.

  In one embodiment, the resistor includes a first resistor connected in series with a second resistor.

  In one embodiment, the feedback loop further includes a switch connected between the first resistor and the second resistor, and the switch connects the input node and the output node when in the first state. In the second state, the input node and the output node are separated.

  In one embodiment, the capacitor is configured to remove frequencies below a threshold frequency.

  In one embodiment, the output signal has a duty cycle that is substantially equal to the duty cycle of the input signal.

  In one embodiment, the switching circuit is a first transistor connected to the input node, the output node, and a voltage source, and the voltage source provides a voltage at the second voltage level. A transistor, and a second transistor connected to the input node, the output node, and ground.

  In one embodiment, the first transistor includes an n-channel metal oxide semiconductor field effect transistor (MOSFET), and the second transistor includes a p-channel MOSFET.

  In one embodiment, the level shift circuit further comprises a switch connected between the capacitor and the output module, the switch connecting the capacitor and the output module when in the first state, In the second state, the capacitor and the output module are disconnected.

  In one embodiment, the level shift circuit comprises a buffer element connected between the input connection and the capacitor, the buffer element being configured to buffer the input signal.

  In an embodiment of the present disclosure, a method for shifting the voltage level of a signal includes biasing a switching circuit to a threshold voltage for the switching circuit and a capacitor with an input signal at a first voltage level. Generating an input voltage for the inverter by AC coupling to the threshold voltage, and switching the switching circuit to the first state in response to the input voltage being higher than the threshold voltage. The input voltage is higher than the threshold voltage while the first portion of the input signal has the first voltage, and the input voltage is lower than the threshold voltage. And switching the switching circuit to a second state in response to the input signal while the second portion of the input signal has a second voltage lower than the first voltage. There comprising less than the threshold voltage, and to switch, the. The method further generates a switching circuit output signal at a second voltage level higher than the first voltage based on switching the switching circuit to a first state and switching the switching circuit to a second state. And providing an output signal at the second voltage level based on the switching circuit output signal.

  In one embodiment, biasing the switching circuit includes coupling an output node of the switching circuit to an input node of the switching circuit in a feedback loop, the feedback loop having at least one resistor.

  In one embodiment, providing the output signal includes inverting the switching circuit output signal with an inverter.

  In one embodiment, generating the switching circuit output signal comprises setting the switching circuit output signal to a first value in response to switching the switching circuit to the first state; and And setting the switching circuit output signal to a second value in response to switching to the second state.

  In one embodiment, the switching circuit includes a first transistor connected to a second transistor. The first transistor is connected to a voltage source that provides a voltage of the second voltage level. The second transistor is connected to ground. Setting the switching circuit output signal to a first value includes coupling the output node of the switching circuit to ground with the second transistor. Setting the switching circuit output signal to a second value includes coupling the output node of the switching circuit to the voltage source with the first transistor.

  In one embodiment, the method may include removing a frequency below a threshold frequency with a capacitor.

  The foregoing is merely illustrative of the principles of the present disclosure and various modifications can be made by those skilled in the art without departing from the scope of the present disclosure. The above-described embodiments are presented for illustrative purposes and not for the purpose of limitation. The present disclosure can also take many forms other than those explicitly described herein. Accordingly, it is emphasized that this disclosure is not limited to explicitly disclosed methods, systems, and devices, but is intended to include variations and modifications thereof that are within the spirit of the following paragraphs. To do.

  By way of further example, the provided structure, device, as shown and described herein, by making a modification of a device or process parameters (e.g., dimensions, configurations, components, process step order, etc.) And the method can be further optimized. In any case, the structures and devices described herein, and associated methods, have many applications. Accordingly, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims.

Claims (15)

A transition filter for a signal,
An input connection for receiving the input signal;
An output connection to provide an output signal;
A delay element connected to the input connection for receiving the input signal, the delay element configured to generate a delayed input signal by delaying the input signal by a time delay When,
A first logic circuit for receiving the input signal as a first input by being connected to the input connection, and receiving the delayed input signal as a second input by being connected to the delay element; A first logic circuit, wherein the first logic circuit is configured to provide a first output;
A second logic circuit for receiving the input signal as a first input by being connected to the input connection and receiving the delayed input signal as a second input by being connected to the delay element; A second logic circuit, wherein the second logic circuit is configured to provide a second output;
A multiplexer that is connected to the first logic circuit and the second logic circuit to receive the first output from the first logic circuit and the second output from the second logic circuit as inputs; A multiplexer configured to select one of the first output or the second output as to be provided as the output signal to the output connection based on a selection signal;
The transition filter, wherein the first logic circuit, the second logic circuit, and the multiplexer are configured to remove, from the output signal, transitions having a duration shorter than the time delay among transitions in the input signal.   The transition filter according to claim 1, wherein the time delay is shorter than a period of the input signal.   The transition filter of claim 1, wherein the first logic circuit has a propagation delay substantially equal to a propagation delay of the second logic circuit.   The transition filter of claim 1, wherein the output signal has a duty cycle that is substantially equal to a duty cycle of the input signal.   The transition filter according to claim 1, wherein the delay element includes at least one inverter.   The transition filter according to claim 1, wherein the first output from the first logic circuit corresponds to an output from an AND gate, and the second output from the second logic circuit corresponds to an output from an OR gate.   The transition filter according to claim 1, wherein the selection signal for the multiplexer is the output signal.   The first logic circuit is configured to remove a transition shorter than the time delay among transitions in the input signal in response to the input signal transitioning from a first state to a second state; The circuit of claim 1, wherein the circuit is configured to remove transitions in the input signal that are shorter than the time delay in response to the input signal transitioning from the second state to the first state. Transition filter. The first logic circuit comprises:
A first NAND gate connected in series with a first NOR gate;
The first NOR gate configured to provide the first output; and
The transition filter of claim 1, wherein the first NAND is configured to receive the input signal and the delayed input signal as inputs.   The transition filter of claim 9, wherein the first NOR gate has a first input and a second input, each of which receives the output of the first NAND gate. The second logic circuit comprises:
A second NOR gate connected in series with the second NAND gate;
The second NAND gate configured to provide the second output; and
The transition filter of claim 9, wherein the second NOR gate is configured to receive the input signal and the delayed input signal as inputs.   The transition filter of claim 11, wherein the second NAND gate has a first input and a second input, each of which receives the output of the second NOR gate.   The transition filter of claim 11, wherein the second NAND gate is substantially the same as the first NAND gate, and the first NOR gate is substantially the same as the second NOR gate. A method for removing unwanted transitions from a signal comprising:
Generating a delayed input signal by delaying the input signal by a time delay with a delay element;
Processing the input signal and the delayed input signal in a first logic circuit, wherein the first logic circuit is configured to generate a first logic circuit output;
Processing the input signal and the delayed input signal in a second logic circuit, wherein the second logic circuit is configured to generate a second logic circuit output;
A multiplexer selecting one of the first logic circuit output or the second logic circuit output as an output signal;
Removing at the first logic circuit, the second logic circuit and the multiplexer from the output signal a transition having a duration shorter than the time delay among the transitions in the input signal.   Selecting one of the first logic circuit output or the second logic circuit output selects the first logic circuit output in response to the output signal having a first value, and the output signal is the first logic circuit output. 15. The method of claim 14, comprising selecting the second logic circuit output in response to having a second value that is different from a value of one.

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