JP2019525507A - Channel training using replica lanes - Google Patents

Abstract

Systems, apparatus, and methods that utilize training sequences in replica lanes are described. The transmitter is connected to the receiver via a communication channel having a plurality of lanes. One lane is a replica lane that is used to track optimal sampling point drift due to temperature variations, power supply variations, or other factors. While data is transmitted on the data lane, a test pattern is transmitted on the replica lane to determine if the optimal sampling point of the replica lane has drifted since the previous test. If the optimal sampling point drifts with respect to the replica lane, adjustments are made to the sampling point of the replica lane and the sampling point of the data lane. [Selection] Figure 6

Description

  Embodiments described herein relate to data communications, and more particularly, to performing bit serial data link training.

  Integrated circuit data throughput continues to increase as application demand and data consumption increase. For example, the microprocessor speed improvement rate continues to exceed the memory speed improvement rate. Increasing the data transmission rate increases the timing requirements of the circuits used to transmit and receive data. In many circuits utilized in computing devices and systems, data is transferred within these circuits using a global clock. For example, a rising edge of the clock can load data that enters the flip-flop, and then the data can be passed through or processed from the flip-flop. In some scenarios, a single clock is used on the data bus for multiple data lanes, and each data lane carries a separate serial bit stream. However, this limits the speed of the data bus because clock transitions must be used for the entire data bus, but some data bits take time to pass through the bus compared to other data bits. May take. If the variation between data lanes is too great, there may not be a place to place a clock edge to clock accurately across the data bus. In addition, lane phase alignment may vary over time due to temperature or voltage variations. When such variations are corrected, the data flow is interrupted, important operations are interrupted, and data transfer may be delayed.

  Consider a system, apparatus, and method for performing bit serial data link training.

  In one embodiment, a training sequence is performed to test the delay setting between the transmitter and receiver. The transmitter is connected to the receiver via communication channels of a plurality of data lanes. In one embodiment, the communication channel includes additional replica lanes. This additional replica lane is sometimes referred to as a periodic tracking (PT) lane. In various embodiments, replica lanes do not send system data. Rather, the replica lane is configured only for test data transmission. The transmitter periodically performs a series of training sequences on the replica lane while the data lane is sending normal system data. The training sequence is performed to detect slight timing changes in the replica lane due to temperature variations, power supply variations, and / or other factors. When a change in the phase timing of the replica lane is detected, the control logic updates the phase timing of the replica lane and the normal data lane.

  In one embodiment, the transmitter transmits the first pattern in at least the second lane of the channel simultaneously with transmitting the test pattern in the replica lane. If the receiver detects one or more errors in the test pattern received in the replica lane, the transmitter and / or receiver determines that the sampling point is misaligned in the replica lane. If the transmitter and / or the receiver determine that the sampling point is misaligned in the replica lane, the transmitter and / or the receiver perform the first adjustment on the sampling point of the first lane and perform the first adjustment on the sampling point of the second lane. Perform adjustments. The first adjustment for the sampling point of the second lane corresponds to the first adjustment for the sampling point of the replica lane. The transmitter is configured to transmit the second data in the second lane after performing the first adjustment on the sampling point of the second lane.

  These and other features and advantages will be apparent to those skilled in the art in view of the following detailed description presented herein.

  The above and further advantages of the method and mechanism can be better understood by referring to the following description in conjunction with the accompanying drawings.

1 is a block diagram of one embodiment of a transmitter and receiver of a computing system. FIG. 6 is a timing diagram of an embodiment for executing a replica lane training sequence. 1 is a block diagram of one embodiment of a system having a transmitter and a communication channel. 1 is a block diagram of an embodiment of a system having a receiver and a communication channel. It is a figure which shows one Embodiment of a data eye. FIG. 4 is a generalized flow diagram illustrating one embodiment of a method for adjusting the phase timing of multiple lane channels. FIG. 6 is a generalized flow diagram illustrating another embodiment of a method for adjusting sampling points of other lanes of a channel using replica lanes.

  In the following description, numerous specific details are set forth in order to provide a thorough understanding of the methods and mechanisms presented herein. However, one of ordinary skill in the art should appreciate that various embodiments can be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions and techniques have not been shown in detail in order to avoid obscuring the approaches described herein. It should be understood that the elements shown in the drawings are not necessarily drawn to scale for simplicity and clarity of explanation. For example, the dimensions of some elements are exaggerated relative to other elements.

  Referring to FIG. 1, a block diagram illustrating one embodiment of a transmitter 105 and a receiver 110 of a computing system 100 is shown. The transmitter 105 is connected to the receiver 110 via a channel 155. Channel 155 includes any number of data lanes, depending on the embodiment. Channel 155 also includes replica lanes, clock lanes, and / or one or more other lanes. The computing system 100 includes a clock 145, a clock 150, and one or more other components not shown to avoid obscuring the drawing. For example, the computing system 100 includes one or more processing units (eg, a processor, processor core, programmable logic device, application specific integrated circuit, etc.), one or more memory devices, and / or other components. . One or more processing units are configured to execute instructions and / or perform one or more types of calculations (eg, floating point, integer, memory, I / O), depending on the embodiment. Has been. In various embodiments, the components of computing system 100 are interconnected by one or more communication buses. In one embodiment, transmitter 105 and receiver 110 are in the memory path of the processor. In various embodiments, the memory connected to the processor is a double data rate synchronous dynamic random access memory (DDR SDRAM). In other embodiments, the memory is implemented using other types of memory devices.

  Transmitter 105 includes a buffer 115 connected to channel 155. In one embodiment, the buffer 115 drives the output of the channel 155 or puts it in a high impedance state when the transmitter 105 is waiting to receive feedback from the receiver 110 regarding the state of the training sequence. This is a tri-state buffer for generation. The transmitter 105 also includes control logic 135 that generates a training sequence, controls lane delay settings for the channel 155, and / or performs other functions. In addition, transmitter 105 includes a counter 125 for counting supercycles. In various embodiments, a supercycle is “N” clock cycles in length, where “N” is a positive integer. For example, in one embodiment, the super cycle is 8 clock cycles long, and in another embodiment, the super cycle is a few clock cycles. In one embodiment, clock 145 provides a clock signal for clocking counter 125.

  Receiver 110 includes a buffer 120 for connection to channel 155. In one embodiment, buffer 120 is a tri-state buffer for carrying the feedback result to channel 155 or generating a high impedance state when receiver 110 is receiving data from transmitter 105. The receiver 110 also detects a training sequence indication on the channel 155, compares the received test pattern with an expected value, controls the lane delay setting of the channel 155, and / or performs other functions. Control logic 140 is included. In addition, receiver 110 includes a counter 130 for counting supercycles. In one embodiment, clock 150 provides a clock signal for clocking counter 130. In other embodiments, receiver 110 uses the clock signal received on channel 155 as the clock signal for clocking counter 130.

  The transmitter 105 is configured to transmit the test pattern via the replica lane of the channel 155 and one or more data lanes. The test pattern is used to determine the optimal sampling points for the replica lane and data lane of channel 155. The delay of the replica lane and the data lane is adjusted based on the result of the test pattern, and normal data operation is started. Periodically, the transmitter 105 is configured to send additional test patterns via the replica lane while the data lane sends system data. If the system 100 determines that the optimal sampling point of the replica lane has drifted since the previous test, the system 100 adjusts the sampling point of the replica lane to align with the optimal sampling point. The system 100 also makes equivalent adjustments to the sampling points of the data lane. In this way, drifts in the sampling points of the data lane due to temperature variations, power supply variations, and / or other factors are corrected without interrupting the flow of system data.

  The receiver 110 is configured to capture the test pattern transmitted by the transmitter 105 in the replica lane and the data lane. The receiver 110 then checks for errors in the captured test pattern. In one embodiment, the transmitter 105 invalidates the buffer 115 after sending the training pattern and waits for the receiver 110 to send feedback regarding the captured test pattern. The receiver 110 enables the buffer 120 and determines whether an error has been detected in the captured test pattern, and then transmits feedback to the transmitter 105. The transmitter 105 captures feedback and uses that feedback (along with feedback from other tests with other delay settings) to determine the data validity period (or “data eye”) for a given data lane. decide. The transmitter 105 decides whether to perform another test or return to normal data operation after capturing the feedback. In another embodiment, the receiver 110 adjusts the replica lane and data lane delay settings based on the number of errors detected in the captured test pattern.

  System 100 represents any type of computing system or device including transmitter 105 and receiver 110. For example, in various embodiments, the system 100 includes a computer, server, computing node, processor, processing device, programmable logic device, memory device, processing in memory (PIM) node, mobile device, television, entertainment system or device, and / Or other types of systems or devices may be included. The system 100 also includes any number of other transmitters and receivers in addition to the transmitter 105 and the receiver 110.

  Referring now to FIG. 2, a timing diagram 200 of one embodiment for performing a training sequence on a replica lane is shown. The training sequence is performed between a transmitter (eg, transmitter 105 of FIG. 1) and a receiver (eg, receiver 110 of FIG. 1) via a multi-lane channel (eg, channel 155). The multi-lane channel includes a replica lane and a plurality of data lanes for sending system data.

  The cycle of system clock 202 is shown in the top row of timing diagram 200. In one embodiment, the cycle shown in clock 202 row of timing diagram 200 represents a supercycle. A supercycle is an “N” system clock, where “N” is a positive integer greater than 1, and “N” is stored in a programmable register. In one embodiment, both the transmitter and the receiver include a counter that counts supercycles. In one embodiment, the supercycle is 8 clock cycles in length and the counter is a modulo 8 counter. In other embodiments, the super cycle is another number of clock cycles. Replica lane state 204 indicates the replica lane state of the channel during the clock cycle shown in timing diagram 200. A replica lane 206 indicates data transmitted in the replica lane. Similarly, the data lane state 208 indicates the state of the data lane, and the data lane 210 indicates data transmitted in the data lane during the clock cycle shown in the timing diagram 200.

  During the initial test phase, the transmitter transmits a test pattern on the replica lane and data lane to the receiver. This is shown as test data 215 for replica lane 206 and test data 220 for data lane 210. In one embodiment, the test pattern is a pseudo-random binary sequence. Before transmitting the test pattern in the replica lane and the data lane, the transmitter transmits a training sequence instruction to inform the receiver that the test pattern is transmitted. When the receiver receives a training sequence instruction in a predetermined lane, the receiver is ready to receive a test pattern in the predetermined lane. Test data 215 and test data 220 correspond to any number of tests performed with different delay settings.

  The receiver receives the test pattern in the replica lane and the data lane, and checks whether there is an error in the received test pattern. In one embodiment, the receiver sends feedback regarding the presence or absence of errors in the received test pattern to the transmitter. This occurs during the “waiting” state of the replica lane and data lane. The system uses the test pattern results to identify the data eye for each of the replica lane and the data lane. Next, the system updates the phase timing of the replica lane and each data lane based on the result of the test data. Each lane is updated independently of other lanes based on the result of the test pattern received in the lane. Note that if the result indicates that a given lane is already configured for the optimal sampling point, the delay setting for the given lane is not adjusted during the phase timing update period.

  After the initial update to the phase timing of the replica lane and data lane, the replica lane is idle while the data lane sends system data 230. After a certain period of time, the system tests the replica lane to see if the phase timing of the replica lane is drifting. While the system continues to send system data 230 on the data lane, test data 225 is sent simultaneously on the replica lane. Next, the system determines whether to adjust the phase timing of the replica lane after the test data 225 is transmitted. Based on the test pattern results received at the replica lane, the system updates the phase timing of the replica lane when the optimal sampling point has drifted since the previous test. This update is shown as row update 235 in the replica lane state 204. The system also performs a similar update 240 for the data lane update timing based on the assumption that any drift in the replica lane occurs in the data lane. In various embodiments, data lane timing updates are performed while data transmission is active on the data lane (eg, while transmitting system data 230). In other embodiments, the data lane temporarily suspends transmission of data while the timing parameters are adjusted during the update phase (eg, 240). Both approaches are conceivable. The system returns to transmitting system data on the data lane after each replica lane and data lane phase timing update 235, 240 while the replica lane returns to the idle state. Next, if the phase timing of the replica lane is drifting, the system will periodically test the replica lane and continue to make changes to the replica lane and data lane.

  Referring now to FIG. 3, a block diagram of an embodiment system 300 having a transmitter 305 and a communication channel 320 is shown. Communication channel 320 represents any type of communication channel that connects transmitter 305 and receiver (not shown). The communication channel 320 includes a replica lane 325A and any number of data lanes 325B-N, depending on the embodiment. Replica lane 325A is configured to send test data to determine if the optimal sampling point has drifted since the previous test. In normal data operation, replica lane 325A is not utilized to send system data, but rather is idle. Each data lane 325B-N is configured to send a serial bit stream of system data. The communication channel 320 also includes a clock lane (not shown) and / or one or more other lanes.

  In one embodiment, transmitter 305 includes control logic 310 and delay elements 315A-N. Each set of delay elements 315A-N includes one or more delay elements for selecting a delay setting for the corresponding lane among lanes 325A-N. In one embodiment, the one or more delay elements include a coarse delay adjustment and a fine delay adjustment applied to a single lane of lanes 325A-N.

  Transmitter 305 is configured to transmit a test pattern on all of lanes 325A-N to test the delay settings of lanes 325A-N during the initial test period. For example, this first test period occurs at startup or after reset. The transmitter invalidates the output buffer (eg, buffer 115 of FIG. 1) after transmitting the test pattern. The output buffer is a tri-state buffer that is switched to a high impedance state by the transmitter 305 after the transmitter 305 transmits a test pattern to the receiver. The receiver activates the output buffer and sends the feedback to the transmitter after a period of preparing feedback. In one embodiment, the feedback indicates whether there is an error in the received test pattern. In one embodiment, the feedback is a single bit. In other embodiments, the feedback utilizes multiple bits to indicate the number of errors. The transmitter receives the feedback and uses the feedback to determine whether the current delay setting is inside or outside the data eye. Another test may be performed after the transmitter receives feedback, or the transmitter may perform normal data operations.

  In one embodiment, transmitter 305 sends a test pattern on each lane, and a receiver (not shown) sends feedback to transmitter 305 along with the number of errors detected in each test pattern. Next, the control logic 310 of the transmitter 305 uses this feedback to determine the data eye for each lane 325A-N. For example, the transmitter transmits a plurality of test patterns having different delay settings for each of the lanes 325A to 325N of the channel 320. Feedback from the receiver for these test patterns is used by the control logic 310 to determine the position of the data eye for each lane. The control logic 310 adjusts each of the delay elements 315A-N to correspond the sampling point of the corresponding lane receiver to the optimal sampling point based on the position of the data eye. The adjustment for each of the delay elements 315A to 315N is performed independently of the adjustment for the other delay elements 315A to 315N.

  The system 300 then begins normal data operation after performing the phase test sequence for all lanes 325A-N. Data lanes 325B-N are utilized to send system data during normal data operations, while replica lane 325A is idle. In other words, replica lane 325A is not used to send system data. The system 300 then performs a phase test during normal data operations to periodically utilize the replica lane 325A to see if the phase timing has drifted from the previous test. Depending on the embodiment, the phase timing of the replica lane 325A drifts based on temperature fluctuations, power supply fluctuations, and / or factors. System 300 performs a phase test on replica lane 325A while data lanes 325B-N are sending system data. Thus, the system 300 can test the phase timing of the replica lane 325A without interrupting the flow of system data in the data lanes 325B-N.

  When the system 300 detects a phase timing drift of the replica lane 325A, the system 300 corrects the timing of the replica lane 325A by adjusting the delay element 315A. The system 300 also makes the same adjustments to the other delay elements 315B-N that affect the data lanes 325B-N. In many cases, the drift generated at the phase timing of the replica lane 325A also occurs in the data lanes 325B to 325N. Thus, the system 300 can correct for phase timing drift of all lanes 325A-N by simply performing a test on a single replica lane 325A. In one embodiment, system 300 is configured to perform these tests on a single replica lane 325A at regular intervals. In another embodiment, the system 300 is configured to perform a test on the replica lane 325A in response to detecting one or more conditions (eg, increased error rate, temperature fluctuation, power supply fluctuation, etc.). .

  Turning now to FIG. 4, a block diagram of an embodiment system 400 comprising a communication channel 405 and a receiver 415 is shown. Similar to system 300 of FIG. 3, system 400 is configured to correct the phase timing of data lanes 410B-N based on detection of phase timing drift in replica lane 410A. However, in contrast to system 300, system 400 uses delay elements 420A-N to correct the phase timing at receiver 415. In the present embodiment, the control logic 425 of the receiver 415 adjusts the delay elements 420A to 420N using feedback on the received test pattern, instead of transmitting feedback to a transmitter (not shown).

  Turning now to FIG. 5, a diagram of one embodiment of a data eye 500 is shown. Data eye 500 is an example of a data validity period that is monitored by capturing bit transitions in the lane of a channel (eg, communication channel 320 of FIG. 3). In one embodiment, the system (eg, system 300) is configured to perform multiple training sequences with different delay settings to detect the boundaries of the data eye 500. The system is configured to utilize feedback generated by a receiver (eg, receiver 110 of FIG. 1) for each test result.

  The system performs multiple tests with multiple delay settings, and if the feedback goes from bad (ie, one or more errors) to good (ie, no errors), that particular delay setting is It is recognized that it coincides with the start 510 of. The system adds a delay in small increments, performs additional tests, and identifies this as an end 520 of the data eye 500 when the feedback goes from good to bad. The system then determines the average of start 510 and end 520 to calculate the center 530 of the data eye 500. The delay setting corresponding to the center 530 of the data eye 500 is considered the optimal delay setting for a given lane of the channel. In one embodiment, the system performs these tests on the channel's replica lanes, and then uses the results of these tests to update the delay settings of the channel's data lanes.

  Referring now to FIG. 6, one embodiment of a method 600 for adjusting the phase timing of a multilane channel is shown. For illustrative purposes, the steps in this embodiment are shown in order. In various embodiments of the methods described below, one or more of the described elements may be performed simultaneously, may be performed in an order different from the illustrated order, or may be omitted entirely. Please note that. Other additional elements may be performed as needed. Any of the various systems or devices described herein are configured to perform method 600.

  A system having a transmitter connected to a receiver via a multi-lane communication channel simultaneously performs a training sequence on multiple lanes of the channel (block 605). In one embodiment, the communication channel includes a replica lane and one or more data lanes. As part of performing the training sequence on multiple lanes of the channel, the system updates the lane delay settings so that each lane samples incoming data at the optimal sampling point.

  The system may then utilize the data lane for normal data operation (block 610). During normal data operation, the replica lane of the channel is idle. Next, the system determines whether a predetermined time has elapsed since the last training sequence was executed (condition block 615). For example, the system has a timer that tracks a predetermined time, which is programmable and varies from embodiment to embodiment.

  If the predetermined time has elapsed (condition block 615: “Yes”), the system performs one or more training sequences in the replica lane and simultaneously transmits system data in the data lane (block 620). If the predetermined time has not elapsed (condition block 615: “No”), the method 600 remains in the condition block 615. After block 620, the system determines whether the training sequence performed on the replica lane indicates that the optimal sampling point of the replica lane has drifted from a previous test (condition block 625).

  If the optimal sampling point of the replica lane has drifted from a previous test (condition block 625: “Yes”), the system applies the first adjustment to the replica lane delay setting to determine the replica lane sampling point. Readjustment (block 630). The system also applies the first adjustment to the channel data lane delay setting to readjust the data lane sampling points (block 635). This system operates on the assumption that optimal sampling point drift in the replica lane occurs in the data lane. Thus, the system applies the same adjustments applied to the data lane delay settings as applied to the replica lane delay settings. For example, if a first amount of delay is added to the replica lane delay setting, the first amount of delay is added to the data lane delay setting. If the optimal sampling point for the replica lane has not drifted from the previous test (condition block 625: “No”), the system maintains the current delay settings for the replica lane and the data lane (block 640). After blocks 635 and 640, the method 600 returns to block 610 and the system continues to use the data lane for normal data operation.

  Referring now to FIG. 7, one embodiment of a method 700 that utilizes replica lanes to adjust sampling points in other lanes of a channel is illustrated. For illustrative purposes, the steps in this embodiment are shown in order. In various embodiments of the methods described below, one or more of the described elements may be performed simultaneously, may be performed in an order different from the illustrated order, or may be omitted entirely. Please note that. Other additional elements may be performed as needed. Any of the various systems or devices described herein are configured to perform method 700.

  The transmitter transmits the first data in the second lane of the channel simultaneously with transmitting one or more test patterns to the receiver in the first lane of the multi-lane channel (block 705). The transmitter and receiver are components in the host system. The first lane may be referred to as a “replica lane”. One or more test patterns are transmitted to the receiver in the first lane as part of the training sequence to test the delay setting of the first lane between the transmitter and receiver. These training sequences are used to determine the position of the data eye in the first lane and determine whether the data eye (and the corresponding optimal sampling point) has shifted from the previous test.

  Next, the system determines whether the current sampling point of the first lane is misaligned based on the result of the test pattern received by the receiver (condition block 710). For example, if the system performs multiple tests for the first lane with multiple delay settings and the received test pattern goes from having one or more errors to being error free, that particular delay setting may be Recognize that it coincides with the start of. The system adds a delay in small increments, performs additional tests, and recognizes the end of the data eye when the received test pattern goes from an error-free state to one or more errors. The system calculates the center of the data eye (or the optimal sampling point) by taking the average of the start and end of the data eye. The system then determines whether this new optimal sampling point matches the actual sampling point of the first lane. In other embodiments, the system utilizes other suitable techniques for determining whether the optimal sampling point has drifted with respect to the first lane.

  If the system determines that the current sampling point of the first lane is misaligned based on the result of the test pattern received by the receiver (condition block 710: “Yes”), the sampling of the first lane A first adjustment is made to the point to realign the sampling point to the optimal sampling point (block 715). The system also makes a first adjustment to the sampling point of the second lane of the channel (block 720). In addition, the system makes a first adjustment to sampling points in one or more other lanes of the channel. For example, in one embodiment, the system makes a first adjustment to the sampling points of all data lanes of the channel. If the system determines that the sampling points of the first lane are properly aligned based on the result of the test pattern received by the receiver (condition block 710: “No” branch), the transmitter Second data is transmitted in the second lane (block 725).

  Variations in signal delay for the first lane and other lanes in a similar manner due to temperature variations, power supply variations, and / or other factors. Thus, detecting the optimal sampling point change for the first lane typically means that other lanes experienced similar drifts in the data eye and that changes to correct the first lane are The same change required to correct the other lanes. Accordingly, the first adjustment performed on the second lane (and other lanes) of the channel is the same as the first adjustment performed on the first lane. For example, if the first adjustment increases the delay applied to the first lane by ¼ of the clock cycle, the delay applied to the other lanes is increased by ¼ of the clock cycle. Alternatively, if the first adjustment reduces the delay applied to the first lane by 1/8 of the clock cycle, the delay applied to the other lanes is reduced by 1/8 of the clock cycle. In other embodiments, other delay increments are added to or removed from the lane in a manner equivalent to adjustments made to the first lane. In one embodiment, adjustments to the sampling points are made by the transmitter. In another embodiment, adjustments to the sampling points are made by the receiver.

  After block 720, the transmitter transmits the second data on the second lane (block 725). Also, the transmitter transmits additional data on one or more other lanes of the channel after adjusting the sampling points used for the other lanes. After block 725, method 700 ends.

  In various embodiments, software application program instructions are used to implement the methods and / or mechanisms described above. In the program instructions, hardware operations are described in a high-level programming language such as C. Alternatively, a hardware design language (HDL) such as Verilog is used. The program instructions are stored on a non-transitory computer readable storage medium. Many types of storage media are available. The storage medium is accessible by the computing system during use to provide program instructions and accompanying data to the computing system for program execution. The computing system includes at least one or more memories and one or more processors configured to execute program instructions.

  It should be emphasized that the above-described embodiments are merely non-limiting examples of implementations. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be construed to include all such variations and modifications.

Claims (20)

A receiver,
A transmitter connected to the receiver via a communication channel having a plurality of lanes;
A system comprising:
Sending a test pattern on the first lane of the channel;
At the same time as transmitting the first data in the second lane of the channel, transmitting the test pattern in the first lane,
In response to determining that the sampling point of the first lane is misaligned, the first adjustment is performed on the sampling point of the first lane, and the sampling point of the second lane of the channel is performed. Performing the first adjustment;
Configured as
system. In response to training both the first lane and the second lane simultaneously, the sampling point of the first lane and the sampling point of the second lane are set.
The system of claim 1. The first lane is not used for transmitting system data.
The system of claim 1. The receiver
Receiving the first data in the second lane simultaneously with receiving the test pattern in the first lane;
An error indication indicating whether an error has been detected in the test pattern is communicated to the transmitter via the first lane.
Configured as
The system of claim 1. The transmitter, when the error indication indicates that an error has been detected in response to receiving the error indication in the first lane, the first adjustment to the sampling point of the first lane. Is configured to change the delay setting of the first lane to
The system of claim 4. The transmitter, when the error indication indicates that an error has been detected in response to receiving the error indication on the first lane, the first adjustment to the sampling point of the second lane. In order to change the delay setting of the second lane,
The first adjustment for the sampling point of the second lane corresponds to the first adjustment for the sampling point of the first lane;
The system of claim 4. The first adjustment to the sampling point of the second lane is performed without transmitting a test pattern in the second lane;
The system of claim 6. A receiver,
A transmitter,
A communication channel including a replica lane and at least one data lane;
A device comprising:
The transmitter is
Send a test pattern in the replica lane,
At the same time as transmitting the first data in the data lane of the channel, the test pattern is transmitted in the replica lane,
In response to determining that the sampling point of the replica lane is misaligned, the first adjustment is performed on the sampling point of the replica lane, and the first adjustment is performed on the sampling point of the data lane of the channel. Run the
Configured as
apparatus. In response to training both the replica lane and the data lane at the same time, the sampling point of the replica lane and the sampling point of the data lane are set.
The apparatus of claim 8. The replica lane is not used for transmission of system data.
The apparatus of claim 8. The receiver
At the same time as receiving the test pattern in the replica lane, receiving the first data in the data lane,
An error indication indicating whether an error has been detected in the test pattern is communicated to the transmitter via the replica lane.
Configured as
The apparatus of claim 8. The transmitter makes the first adjustment to the sampling point of the replica lane when the error indication indicates that an error has been detected in response to receiving the error indication in the replica lane In order to change the delay setting of the replica lane,
The apparatus of claim 11. The transmitter performs the first adjustment to the sampling point of the data lane when the error indication indicates that an error has been detected in response to receiving the error indication in the replica lane In order to change the delay setting of the data lane,
The first adjustment to the sampling point of the data lane corresponds to the first adjustment to the sampling point of the replica lane;
The apparatus of claim 11. The first adjustment to the sampling point of the data lane is performed without transmitting a test pattern in the data lane;
The apparatus of claim 13. Transmitting a test pattern on the first lane of the communication channel;
Simultaneously transmitting the first data in the second lane of the channel, and transmitting the test pattern in the first lane;
In response to determining that the sampling point of the first lane is misaligned based on the number of errors detected in the test pattern received by the receiver, with respect to the sampling point of the first lane Performing a first adjustment and performing the first adjustment on a sampling point utilized by a second lane of the channel;
Method. Setting a sampling point for the first lane and a sampling point for the second lane in response to training both the first lane and the second lane simultaneously,
The method of claim 15. The first lane is not used for transmitting system data.
The method of claim 15. Receiving the first data in the second lane simultaneously with receiving the test pattern in the first lane;
Communicating an error indication to the transmitter via the first lane indicating whether an error has been detected in the test pattern.
The method of claim 15. The first adjustment to the sampling point of the first lane when the error indication indicates that an error has been detected in response to the transmitter receiving the error indication in the first lane. Changing the delay setting of the first lane to perform
The method of claim 18. The first adjustment to the sampling point of the second lane when the error indication indicates that an error has been detected in response to the transmitter receiving the error indication in the first lane. Changing the delay setting of the second lane to perform
The first adjustment for the sampling point of the second lane corresponds to the first adjustment for the sampling point of the first lane;
The method of claim 18.

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