JP2019517035A - Liquid crystal panel and thin film transistor array substrate thereof - Google Patents

Liquid crystal panel and thin film transistor array substrate thereof Download PDF

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JP2019517035A
JP2019517035A JP2018562030A JP2018562030A JP2019517035A JP 2019517035 A JP2019517035 A JP 2019517035A JP 2018562030 A JP2018562030 A JP 2018562030A JP 2018562030 A JP2018562030 A JP 2018562030A JP 2019517035 A JP2019517035 A JP 2019517035A
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reinforcing member
thin film
control chip
film transistor
transistor array
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JP6720349B2 (en
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▲キン▼ 邱
▲キン▼ 邱
耀立 黄
耀立 黄
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/13456—Cell terminals located on one side of the display only
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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Abstract

本発明は、薄膜トランジスタアレイ基板を提供し、基板と、基板に形成された表示領域と、基板に設置され且つ表示領域の一側に位置するフレキシブル回路基板と、表示領域とフレキシブル回路基板との間に設置された制御チップであって、フレキシブル回路基板の両側がそれぞれ制御チップの対応する両側を超える制御チップと、制御チップの第１側に設置された第１補強部材であって、第１側は、制御チップが表示領域に向いている一側に隣接する、第１補強部材と、制御チップの第１側に対向する第２側に設置された第２補強部材と、制御チップ、第１補強部材及び第２補強部材を被覆する第３補強部材と、を含む。本発明はさらに、当該薄膜トランジスタアレイ基板を有する液晶パネルを提供する。本発明は、制御チップの周囲に補強部材を設置することで、制御チップが占める領域の強度を高める。The present invention provides a thin film transistor array substrate, and the substrate, a display area formed on the substrate, a flexible circuit board disposed on the substrate and positioned on one side of the display area, and between the display area and the flexible circuit board A control chip installed on the control circuit, the control chip extending on both sides of the flexible circuit board over the corresponding control chip, and a first reinforcing member installed on the first side of the control chip A first reinforcing member adjacent to one side where the control chip faces the display area, a second reinforcing member installed on the second side opposite to the first side of the control chip, the control chip, the first And a third reinforcing member covering the reinforcing member and the second reinforcing member. The present invention further provides a liquid crystal panel having the thin film transistor array substrate. The present invention increases the strength of the area occupied by the control chip by installing reinforcing members around the control chip.

Description

本発明は液晶表示技術分野に属し、具体的には、液晶パネル及びその薄膜トランジスタアレイ基板に関する。   The present invention relates to the field of liquid crystal display technology, and more particularly, to a liquid crystal panel and a thin film transistor array substrate thereof.

光電技術と半導体技術の発展に伴い、フラットパネルディスプレイ（Ｆｌａｔ Ｐａｎｅｌ Ｄｉｓｐｌａｙ）の発展は盛んになっており、多数のフラットパネルディスプレイのうち、液晶ディスプレイ（Ｌｉｑｕｉｄ Ｃｒｙｓｔａｌ Ｄｉｓｐｌａｙ、ＬＣＤ）は、高空間利用効率、低消費電力、不要輻射がない、低電磁干渉などの複数の優れた特性を有するため、生産生活の様々な場面で使用されている。   With the development of photoelectric technology and semiconductor technology, flat panel display (Flat Panel Display) has been actively developed, and among many flat panel displays, liquid crystal display (Liquid Crystal Display, LCD) has high space utilization efficiency. Because it has several excellent characteristics such as low power consumption, no unwanted radiation, low electromagnetic interference, it is used in various scenes of production life.

従来の液晶ディスプレイは、ほとんどバックライト型液晶ディスプレイであり、液晶パネル及びバックライトモジュール（Ｂａｃｋｌｉｇｈｔ Ｍｏｄｕｌｅ）を含む。液晶パネルの作動原理としては、二枚の平行なガラス基板に液晶分子が配置され、二枚のガラス基板の中間には多数の微細な垂直ワイヤと水平ワイヤを有し、通電の有無により液晶分子を制御してその方向を変えることで、バックライトモジュールの光線を屈折して画面を発生させる。   The conventional liquid crystal display is mostly a backlight liquid crystal display, and includes a liquid crystal panel and a backlight module. As the operation principle of the liquid crystal panel, liquid crystal molecules are disposed on two parallel glass substrates, a large number of fine vertical wires and horizontal wires are provided between the two glass substrates, and the liquid crystal molecules are switched depending on the presence or absence of electricity. Control the light source to refract the light of the backlight module to generate a screen.

通常、液晶パネルはカラーフィルム基板（ＣＦ、Ｃｏｌｏｒ Ｆｉｌｔｅｒ）、薄膜トランジスタアレイ基板（ＴＦＴ、Ｔｈｉｎ Ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ）、カラーフィルム基板と薄膜トランジスタアレイ基板との間に介装される液晶（ＬＣ、Ｌｉｑｕｉｄ Ｃｒｙｓｔａｌ）、及びシーラント（Ｓｅａｌａｎｔ）からなる。   In general, the liquid crystal panel is a color film substrate (CF, color filter), a thin film transistor array substrate (TFT, thin film transistor), a liquid crystal (LC, liquid crystal) interposed between the color film substrate and the thin film transistor array substrate, It consists of a sealant (Sealant).

現在、薄膜トランジスタアレイ基板上における表示駆動チップ（又は制御チップと呼ばれる）はチップオングラス（ＣＯＧ）方式で実装する場合が多い。このような方式の利点は、はんだ付けプロセスを削減し、且つ体積がチップオンボード（ＣＯＢ）方式の体積より遥かに小さくなり、小型化、簡易化及び高度集積化を容易にし、且つチップ変形などの問題がないことにある。   Currently, a display driving chip (or called a control chip) on a thin film transistor array substrate is often mounted by a chip on glass (COG) method. The advantage of such a scheme is that it reduces the soldering process and the volume is much smaller than that of a chip on board (COB) scheme, facilitating miniaturization, simplification and high integration, and chip deformation etc. There is no problem with

しかしながら、表示駆動チップの長さが薄膜トランジスタが占める領域（すなわち表示領域）の幅に満たないため、表示駆動チップが占める領域は薄膜トランジスタアレイ基板全体にわたって強度が最も低い領域となる。同時に、表示駆動チップが薄膜トランジスタアレイ基板に直接実装されるため、表示駆動チップと表示領域との間に静電気対策を施す空間がなくなる。この２つの問題は液晶パネルの歩留まりを低減させる。   However, since the length of the display driving chip is less than the width of the area occupied by the thin film transistor (that is, the display area), the area occupied by the display driving chip is the area with the lowest intensity over the entire thin film transistor array substrate. At the same time, since the display driving chip is directly mounted on the thin film transistor array substrate, there is no space for taking measures against static electricity between the display driving chip and the display area. These two problems reduce the yield of the liquid crystal panel.

上記従来技術に存在している問題を解決するために、本発明の目的は、薄膜トランジスタアレイ基板を提供することにあり、当該薄膜トランジスタアレイ基板は、基板と、前記基板にアレイ状に配列される複数の薄膜トランジスタであって、前記複数の薄膜トランジスタが占める領域は表示領域である複数の薄膜トランジスタと、前記基板に設置され且つ前記表示領域の一側に位置するフレキシブル回路基板と、前記表示領域と前記フレキシブル回路基板との間に設置された制御チップであって、前記フレキシブル回路基板の両側がそれぞれ前記制御チップの対応する両側を超える制御チップと、前記制御チップの第１側に設置された第１補強部材であって、前記第１側は、前記制御チップが前記表示領域に向いている一側に隣接する、第１補強部材と、前記制御チップの前記第１側に対向する第２側に設置された第２補強部材と、前記制御チップ、前記第１補強部材及び前記第２補強部材を被覆する第３補強部材と、を含む。   SUMMARY OF THE INVENTION In order to solve the problems existing in the prior art, an object of the present invention is to provide a thin film transistor array substrate, and the thin film transistor array substrate comprises a substrate and a plurality of substrates arranged in an array on the substrate. A plurality of thin film transistors which are display areas, an area occupied by the plurality of thin film transistors, a flexible circuit board disposed on the substrate and positioned on one side of the display area, the display area and the flexible circuit A control chip disposed between the substrate and the control chip, wherein both sides of the flexible circuit board respectively exceed the corresponding sides of the control chip, and a first reinforcing member disposed on the first side of the control chip The first side is adjacent to one side where the control chip is facing the display area; A third reinforcement member covering a strong member, a second reinforcement member installed on the second side opposite to the first side of the control chip, the control chip, the first reinforcement member, and the second reinforcement member And.

さらに、前記第１補強部材及び前記第２補強部材の上面が前記制御チップの上面と面一である。   Furthermore, the upper surfaces of the first reinforcing member and the second reinforcing member are flush with the upper surface of the control chip.

さらに、前記第１補強部材及び前記第２補強部材はいずれも、補強本体と、前記表示領域に向いている前記補強本体の一側から窪んでなる第１接着剤収容溝と、前記制御チップに向いている前記補強本体の一側と前記表示領域に対して反対側の前記補強本体の一側との接続箇所から窪んでなる第２接着剤収容溝と、を含む。   Further, each of the first reinforcing member and the second reinforcing member may include a reinforcing body, a first adhesive receiving groove recessed from one side of the reinforcing body facing the display area, and the control chip. And a second adhesive receiving groove recessed from a connection point between one side of the reinforcing body facing the one side and the one side of the reinforcing body opposite to the display area.

さらに、前記フレキシブル回路基板の前記制御チップの側端を超える端部が前記第２接着剤収容溝と係合する。   Furthermore, the end of the flexible circuit board beyond the side end of the control chip engages with the second adhesive receiving groove.

さらに、前記第３補強部材は、補強本体と、前記補強本体の前記表示領域に向いている一側の両端からそれぞれ窪んでなる２つの第３接着剤収容溝と、を含む。   Furthermore, the third reinforcing member includes a reinforcing body and two third adhesive receiving grooves respectively recessed from both ends of one side of the reinforcing body facing the display area.

さらに、前記第３接着剤収容溝は、前記第１接着剤収容溝と上下に１対１で対応する。   Furthermore, the third adhesive receiving groove corresponds to the first adhesive receiving groove in a one-to-one correspondence with the first adhesive receiving groove.

さらに、接着剤を前記第１接着剤収容溝、前記第２接着剤収容溝及び前記第３接着剤収容溝に収容することで、前記第１補強部材、前記第２補強部材及び前記第３補強部材を固定する。   Furthermore, the first reinforcing member, the second reinforcing member, and the third reinforcing member are accommodated by storing the adhesive in the first adhesive receiving groove, the second adhesive receiving groove, and the third adhesive receiving groove. Fix the members.

さらに、前記薄膜トランジスタアレイ基板はさらに、前記第３補強部材上に設置された導電性テープを含み、前記導電性テープの一端は、前記表示領域と前記制御チップとの間まで延伸して前記制御チップに電気的に接続され、前記導電性テープの他端は、前記フレキシブル回路基板まで延伸して前記フレキシブル回路基板上の接地端子に電気的に接続される。   Furthermore, the thin film transistor array substrate further includes a conductive tape disposed on the third reinforcing member, and one end of the conductive tape extends between the display area and the control chip to control the control chip. The other end of the conductive tape is extended to the flexible circuit board and electrically connected to the ground terminal on the flexible circuit board.

さらに、前記第１補強部材、前記第２補強部材及び前記第３補強部材はいずれもポリエチレンテレフタレートから製造される。   Furthermore, the first reinforcing member, the second reinforcing member, and the third reinforcing member are all made of polyethylene terephthalate.

本発明の別の目的は液晶パネルを提供することであり、当該液晶パネルは上記薄膜トランジスタアレイ基板を含む。   Another object of the present invention is to provide a liquid crystal panel, which includes the thin film transistor array substrate.

本発明の有益な効果は以下のとおりである。本発明は、制御チップの周囲に補強部材を設置することで、制御チップが占める領域の強度を高め、且つ第３補強部材上に設置された導電性テープにより制御チップとフレキシブル回路基板の接地点とを接続し、このように、外部環境による制御チップへの干渉を効果的に遮断するとともに、静電気が直接導電性テープを介してフレキシブル回路基板の接地点に流れて、静電気による制御チップへの静電気破壊を防止することができる。   The beneficial effects of the present invention are as follows. The present invention increases the strength of the area occupied by the control chip by installing a reinforcing member around the control chip, and the contact point between the control chip and the flexible circuit board by the conductive tape installed on the third reinforcing member. To effectively block the interference to the control chip due to the external environment, and the static electricity flows directly to the ground point of the flexible circuit board through the conductive tape, to the control chip due to the static electricity. It is possible to prevent electrostatic breakdown.

以下、図面とあわせて説明をすることによって、本発明の実施例の上記及びほかの態様、特徴や利点が明らかになるであろう。   These and other aspects, features and advantages of embodiments of the present invention will be apparent from the following description taken in conjunction with the drawings.

図１は本発明の実施例による薄膜トランジスタアレイ基板の立体分解図である。FIG. 1 is an exploded view of a thin film transistor array substrate according to an embodiment of the present invention. 図２は本発明の実施例による第１補強部材、第２補強部材及び第３補強部材の構造模式図である。FIG. 2 is a structural schematic view of a first reinforcing member, a second reinforcing member and a third reinforcing member according to an embodiment of the present invention. 図３は本発明の実施例による液晶パネルの側面図である。FIG. 3 is a side view of a liquid crystal panel according to an embodiment of the present invention. 図４は図３中のＡ−Ａ矢視図である。FIG. 4 is a view on arrow AA in FIG.

以下、図面を参照して本発明の実施例を詳細に説明する。ただし、複数の異なる形態で本発明を実施することができ、且つ本発明はここで説明する具体的な実施例に制限されると理解すべきではない。逆に、これら実施例を提供するのは、本発明の原理及びその実際の応用を解釈し、それにより当業者が本発明の各種の実施例と特定の期待される用途に適する各種の修正を理解できるようにするためである。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, it should not be understood that the present invention can be practiced in a number of different forms and that the present invention is limited to the specific embodiments described herein. Rather, these examples are provided to interpret the principles of the invention and their practical applications, thereby enabling one of ordinary skill in the art to make various modifications that are appropriate to the various embodiments of the invention and the particular expected application. This is to make it understandable.

図面では、明瞭にするために、層と領域の厚さを拡大する可能性がある。同一符号は、図面では常に同じ部材を示す。   In the drawings, the thickness of layers and regions may be increased for clarity. The same reference numerals always denote the same members in the drawings.

なお、ここで、用語「第１」、「第２」などで各種の部材を説明できるが、これら部材はこれら用語により制限されない。これら用語は、１つの部材を別の部材と区別することにのみ用いられる。   Here, various members can be described by the terms “first”, “second” and the like, but these members are not limited by these terms. These terms are only used to distinguish one member from another.

図１は本発明の実施例による薄膜トランジスタアレイ基板の立体分解図である。   FIG. 1 is an exploded view of a thin film transistor array substrate according to an embodiment of the present invention.

図１に示されるように、本発明の実施例による薄膜トランジスタアレイ基板１０は、基板１１と、基板１１に形成された表示領域１２であって、表示領域１２は基板１１にアレイ状に配列される複数の薄膜トランジスタ（未図示）が占める領域で形成される表示領域１２と、基板１１に設置され且つ表示領域１２の一側に位置するフレキシブル回路基板（ＦＰＣ）１３と、基板１１に設置され且つ表示領域１２とフレキシブル回路基板１３との間に位置する制御チップ１４（又は表示駆動チップと呼ばれる）であって、フレキシブル回路基板１３の両側がそれぞれ制御チップ１４の対応する両側を超える制御チップ１４と、制御チップ１４の第１側に設置された第１補強部材１５であって、制御チップ１４の第１側は、制御チップ１４が表示領域１２に向いている一側に隣接する、第１補強部材１５と、制御チップ１４の第２側に設置された第２補強部材１６であって、制御チップ１４の第２側は、制御チップ１４の第１側に対向する第２補強部材１６と、制御チップ１４、第１補強部材１５及び第２補強部材１６を被覆する第３補強部材１７と、を含む。このように、制御チップ１４の周囲に補強部材を設置することで、制御チップ１４が占める領域の強度を高める。   As shown in FIG. 1, the thin film transistor array substrate 10 according to an embodiment of the present invention is a substrate 11 and a display area 12 formed on the substrate 11, and the display areas 12 are arrayed on the substrate 11. A display area 12 formed by an area occupied by a plurality of thin film transistors (not shown), a flexible circuit board (FPC) 13 provided on the substrate 11 and positioned on one side of the display area 12, provided on the substrate 11 A control chip 14 (also referred to as a display driving chip) located between the area 12 and the flexible circuit board 13, wherein both sides of the flexible circuit board 13 respectively extend beyond the corresponding sides of the control chip 14; The first reinforcing member 15 disposed on the first side of the control chip 14, the first side of the control chip 14 being indicated by the control chip 14 The first reinforcing member 15 adjacent to one side facing the area 12 and the second reinforcing member 16 installed on the second side of the control chip 14, the second side of the control chip 14 being the control chip And a third reinforcing member 17 covering the control chip 14, the first reinforcing member 15, and the second reinforcing member 16. Thus, by installing the reinforcing member around the control chip 14, the strength of the area occupied by the control chip 14 is increased.

さらに、本発明の実施例による薄膜トランジスタアレイ基板１０はさらに、第３補強部材１７上に設置された導電性テープ１８を含む。導電性テープ１８は、制御チップ１４とフレキシブル回路基板１３上の接地点とを接続することに用いられ、このようにして、外部環境による制御チップ１４への干渉を効果的に遮断するとともに、静電気が直接導電性テープ１８を介してフレキシブル回路基板１３の接地点に流れて、静電気による制御チップ１４への静電気破壊を防止することができる。   Furthermore, the thin film transistor array substrate 10 according to the embodiment of the present invention further includes the conductive tape 18 disposed on the third reinforcing member 17. The conductive tape 18 is used to connect the control chip 14 and the ground point on the flexible circuit board 13, and in this way, effectively prevents interference with the control chip 14 due to the external environment, and also electrostatics. Can flow directly to the ground point of the flexible circuit board 13 via the conductive tape 18 to prevent electrostatic breakdown of the control chip 14 due to static electricity.

図２は本発明の実施例による第１補強部材、第２補強部材及び第３補強部材の構造模式図である。   FIG. 2 is a structural schematic view of a first reinforcing member, a second reinforcing member and a third reinforcing member according to an embodiment of the present invention.

図１及び図２に示されるように、本発明の実施例による第１補強部材１５は、第１補強本体１５１と、表示領域１２に向いている第１補強本体１５１の一側から窪んでなる第１接着剤収容溝１５２と、制御チップ１４に向いている第１補強本体１５１の一側と表示領域１２に対して反対側の第１補強本体１５１の一側との接続箇所から窪んでなる第２接着剤収容溝１５３と、を含む。   As shown in FIG. 1 and FIG. 2, the first reinforcing member 15 according to the embodiment of the present invention is recessed from one side of the first reinforcing body 151 and the first reinforcing body 151 facing the display area 12. Concave from the connection point between the first adhesive receiving groove 152, one side of the first reinforcing main body 151 facing the control chip 14 and one side of the first reinforcing main body 151 opposite to the display area 12 And a second adhesive receiving groove 153.

同様に、本発明の実施例による第２補強部材１６は、第２補強本体１６１と、表示領域１２に向いている第２補強本体１６１の一側から窪んでなる第３接着剤収容溝１６２と、制御チップ１４に向いている第２補強本体１６１の一側と表示領域１２に対して反対側の第２補強本体１６１の一側との接続箇所から窪んでなる第４接着剤収容溝１６３と、を含む。   Similarly, the second reinforcing member 16 according to the embodiment of the present invention includes a second reinforcing body 161 and a third adhesive receiving groove 162 recessed from one side of the second reinforcing body 161 facing the display area 12. A fourth adhesive receiving groove 163 recessed from a connection point between one side of the second reinforcing body 161 facing the control chip 14 and one side of the second reinforcing body 161 opposite to the display area 12; ,including.

本発明の実施例による第３補強部材１７は、第３補強本体１７１と、第３補強本体１７１の表示領域１２に向いている一側の両端からそれぞれ窪んでなる２つの第５接着剤収容溝１７２と、を含む。   The third reinforcing member 17 according to the embodiment of the present invention includes two third adhesive receiving grooves respectively recessed from the third reinforcing main body 171 and one end of the third reinforcing main body 171 facing the display area 12. And 172.

第３補強部材１７が制御チップ１４、第１補強部材１５及び第２補強部材１６を被覆する場合、２つの第５接着剤収容溝１７２の一方は第１接着剤収容溝１５２と上下に重なって揃い、２つの第５接着剤収容溝１７２の他方は第３接着剤収容溝１６２と上下に重なって揃う。   When the third reinforcing member 17 covers the control chip 14, the first reinforcing member 15, and the second reinforcing member 16, one of the two fifth adhesive receiving grooves 172 vertically overlaps the first adhesive receiving groove 152. The other one of the two fifth adhesive receiving grooves 172 is aligned with the third adhesive receiving groove 162 vertically in alignment.

第１補強部材１５、第２補強部材１６及び第３補強部材１７を固定する場合、制御チップ１４の両側に所定の長さと厚さの接着剤をコーティングし、次に第１補強部材１５、第２補強部材１６をそれぞれ制御チップ１４の両側に接着し、且つ第３補強部材１７に制御チップ１４、第１補強部材１５及び第２補強部材１６を被覆させ、押圧過程において、接着剤が溢れて各接着剤収容溝に収容され、それにより第１補強部材１５、第２補強部材１６及び第３補強部材１７の固定は完了する。具体的には図３及び図４を参照する。   When the first reinforcing member 15, the second reinforcing member 16 and the third reinforcing member 17 are fixed, an adhesive of a predetermined length and thickness is coated on both sides of the control chip 14, and then the first reinforcing member 15, the (2) Glue the reinforcing members 16 on both sides of the control chip 14 and coat the third reinforcing member 17 with the control chip 14, the first reinforcing member 15 and the second reinforcing member 16, and the adhesive overflows in the pressing process. It is accommodated in each adhesive accommodation groove, and fixation of the 1st reinforcement member 15, the 2nd reinforcement member 16, and the 3rd reinforcement member 17 is completed by it. Specifically, refer to FIG. 3 and FIG.

図３は本発明の実施例による液晶パネルの側面図である。図４は図３中のＡ−Ａ矢視図である。   FIG. 3 is a side view of a liquid crystal panel according to an embodiment of the present invention. FIG. 4 is a view on arrow AA in FIG.

図３及び図４に示されるように、本発明の実施例による液晶パネルは、モジュール化して設けられた薄膜トランジスタアレイ基板１０と、薄膜トランジスタアレイ基板１０とカラーフィルム基板２０との間に介装される液晶層（未図示）と、を含む。   As shown in FIGS. 3 and 4, the liquid crystal panel according to the embodiment of the present invention is interposed between the thin film transistor array substrate 10 provided by modularization, the thin film transistor array substrate 10 and the color film substrate 20. And a liquid crystal layer (not shown).

カラーフィルム基板２０の面積は薄膜トランジスタアレイ基板１０の表示領域１２の面積とほぼ対応する。通常、カラーフィルム基板２０は、カラーレジスト、ブラックマトリックス、配向膜層などの必要な部材を含む。   The area of the color film substrate 20 substantially corresponds to the area of the display region 12 of the thin film transistor array substrate 10. In general, the color film substrate 20 includes necessary members such as a color resist, a black matrix, and an alignment film layer.

第１補強部材１５、第２補強部材１６はそれぞれ接着剤１９で制御チップ１４の両側に接着される。さらに、第１補強部材１５と基板１１との間及び第２補強部材１６と基板１１との間の接着剤１９により、第１補強部材１５と第２補強部材１６は高くなり、それにより第１補強部材１５及び第２補強部材１６の上面はいずれも制御チップ１４の上面と面一となり、このようにして、第３補強部材１７が設置されやすくなる。   The first reinforcing member 15 and the second reinforcing member 16 are bonded to both sides of the control chip 14 with an adhesive 19 respectively. Furthermore, the adhesive 19 between the first reinforcing member 15 and the substrate 11 and between the second reinforcing member 16 and the substrate 11 makes the first reinforcing member 15 and the second reinforcing member 16 higher, whereby the first reinforcing member 15 and the second reinforcing member 16 are raised. The upper surfaces of the reinforcing member 15 and the second reinforcing member 16 are both flush with the upper surface of the control chip 14, and in this manner, the third reinforcing member 17 can be easily installed.

第１補強部材１５、第２補強部材１６がそれぞれ接着剤１９で制御チップ１４の両側に接着された場合、第２接着剤収容溝１５３及び第４接着剤収容溝１６３はそれぞれフレキシブル回路基板１３の制御チップ１４の側端を超える端部と係合する。   When the first reinforcing member 15 and the second reinforcing member 16 are respectively adhered to both sides of the control chip 14 with the adhesive 19, the second adhesive receiving groove 153 and the fourth adhesive receiving groove 163 are each of the flexible circuit board 13. It engages with the end beyond the side end of the control tip 14.

導電性テープ１８は第３補強部材１７上に設置される。導電性テープ１８の一端は表示領域１２と制御チップ１４との間の領域まで延伸するとともに、カラーフィルム基板２０上まで延伸して制御チップ１４に電気的に接続され、導電性テープ１８の他端はフレキシブル回路基板１３まで延伸してフレキシブル回路基板１３上の接地点に電気的に接続される。   The conductive tape 18 is placed on the third reinforcing member 17. One end of the conductive tape 18 extends to the area between the display area 12 and the control chip 14 and also extends onto the color film substrate 20 to be electrically connected to the control chip 14, and the other end of the conductive tape 18 Are extended to the flexible circuit board 13 and electrically connected to the ground point on the flexible circuit board 13.

また、本実施例では、第１補強部材１５、第２補強部材１６及び第３補強部材１７はいずれもポリエチレンテレフタレート（ＰＥＴ）フィルムから製造されるが、本発明では、それに制限されない。   Further, in the present embodiment, although the first reinforcing member 15, the second reinforcing member 16 and the third reinforcing member 17 are all manufactured from a polyethylene terephthalate (PET) film, the present invention is not limited thereto.

特定の実施例を参照して本発明を例示的に説明したが、当業者であれば、特許請求の範囲及びその同等物により限定された本発明の精神と範囲を逸脱しない限り、ここで、形態や詳細について様々な変化をすることができることを理解できる。   While the invention has been described by way of example with reference to specific embodiments, those skilled in the art will now appreciate, without departing from the spirit and scope of the invention as limited by the claims and their equivalents. It can be understood that various changes in form and detail can be made.

１０ 薄膜トランジスタアレイ基板
１１ 基板
１２ 表示領域
１３ フレキシブル回路基板
１４ 制御チップ
１５ 第１補強部材
１６ 第２補強部材
１７ 第３補強部材
１８ 導電性テープ
１９ 接着剤
２０ カラーフィルム基板
１５１ 第１補強本体
１５２ 第１接着剤収容溝
１５３ 第２接着剤収容溝
１６１ 第２補強本体
１６２ 第３接着剤収容溝
１６３ 第４接着剤収容溝
１７１ 第３補強本体
１７２ 第５接着剤収容溝 DESCRIPTION OF SYMBOLS 10 thin film transistor array substrate 11 substrate 12 display area 13 flexible circuit board 14 control chip 15 1st reinforcement member 16 2nd reinforcement member 17 3rd reinforcement member 18 electroconductive tape 19 adhesive agent 20 color film substrate 151 1st reinforcement main body 152 1st Adhesive storage groove 153 second adhesive storage groove 161 second reinforcement main body 162 third adhesive storage groove 163 fourth adhesive storage groove 171 third reinforcement main body 172 fifth adhesive storage groove

Claims (13)

薄膜トランジスタアレイ基板であって、
基板と、
前記基板にアレイ状に配列される複数の薄膜トランジスタであって、前記複数の薄膜トランジスタが占める領域は表示領域である複数の薄膜トランジスタと、
前記基板に設置され且つ前記表示領域の一側に位置するフレキシブル回路基板と、
前記表示領域と前記フレキシブル回路基板との間に設置された制御チップであって、前記フレキシブル回路基板の両側がそれぞれ前記制御チップの対応する両側を超える制御チップと、
前記制御チップの第１側に設置された第１補強部材であって、前記第１側は、前記制御チップが前記表示領域に向いている一側に隣接する、第１補強部材と、
前記制御チップの前記第１側に対向する第２側に設置された第２補強部材と、
前記制御チップ、前記第１補強部材及び前記第２補強部材を被覆する第３補強部材と、を含む薄膜トランジスタアレイ基板。 A thin film transistor array substrate,
A substrate,
A plurality of thin film transistors arranged in an array on the substrate, wherein a region occupied by the plurality of thin film transistors is a display region;
A flexible circuit board disposed on the substrate and positioned on one side of the display area;
A control chip disposed between the display area and the flexible circuit board, wherein both sides of the flexible circuit board respectively exceed the corresponding sides of the control chip;
A first reinforcing member disposed on a first side of the control chip, wherein the first side is adjacent to one side where the control chip is directed to the display area;
A second reinforcing member disposed on a second side opposite to the first side of the control chip;
A thin film transistor array substrate including the control chip, and a third reinforcing member covering the first reinforcing member and the second reinforcing member. 請求項１に記載の薄膜トランジスタアレイ基板であって、
前記第１補強部材及び前記第２補強部材の上面が前記制御チップの上面と面一であることを特徴とする薄膜トランジスタアレイ基板。 The thin film transistor array substrate according to claim 1, wherein
The upper surfaces of the first reinforcing member and the second reinforcing member are flush with the upper surface of the control chip. 請求項１に記載の薄膜トランジスタアレイ基板であって、
前記第１補強部材及び前記第２補強部材はいずれも、補強本体と、前記表示領域に向いている前記補強本体の一側から窪んでなる第１接着剤収容溝と、前記制御チップに向いている前記補強本体の一側と前記表示領域に対して反対側の前記補強本体の一側との接続箇所から窪んでなる第２接着剤収容溝と、を含むことを特徴とする薄膜トランジスタアレイ基板。 The thin film transistor array substrate according to claim 1, wherein
Both the first reinforcing member and the second reinforcing member face the reinforcing main body, a first adhesive receiving groove recessed from one side of the reinforcing main body facing the display area, and the control chip. A thin film transistor array substrate comprising: a second adhesive receiving groove recessed from a connection point between one side of the reinforcing body and one side of the reinforcing body opposite to the display area. 請求項３に記載の薄膜トランジスタアレイ基板であって、
前記フレキシブル回路基板の前記制御チップの側端を超える端部が前記第２接着剤収容溝と係合することを特徴とする薄膜トランジスタアレイ基板。 The thin film transistor array substrate according to claim 3, wherein
The thin film transistor array substrate, wherein an end of the flexible circuit board beyond the side end of the control chip is engaged with the second adhesive receiving groove. 請求項３に記載の薄膜トランジスタアレイ基板であって、
前記第３補強部材は、補強本体と、前記表示領域に向いている前記補強本体の一側の両端からそれぞれ窪んでなる２つの第３接着剤収容溝と、を含むことを特徴とする薄膜トランジスタアレイ基板。 The thin film transistor array substrate according to claim 3, wherein
The third reinforcing member includes a reinforcing body, and two third adhesive receiving grooves respectively recessed from both ends of one side of the reinforcing body facing the display area. substrate. 請求項４に記載の薄膜トランジスタアレイ基板であって、
前記第３補強部材は、補強本体と、前記表示領域に向いている前記補強本体の一側の両端からそれぞれ窪んでなる２つの第３接着剤収容溝と、を含むことを特徴とする薄膜トランジスタアレイ基板。 The thin film transistor array substrate according to claim 4, wherein
The third reinforcing member includes a reinforcing body, and two third adhesive receiving grooves respectively recessed from both ends of one side of the reinforcing body facing the display area. substrate. 請求項５に記載の薄膜トランジスタアレイ基板であって、
前記第３接着剤収容溝は、前記第１接着剤収容溝と上下に１対１で対応することを特徴とする薄膜トランジスタアレイ基板。 The thin film transistor array substrate according to claim 5, wherein
3. The thin film transistor array substrate according to claim 1, wherein the third adhesive receiving groove corresponds to the first adhesive receiving groove on the upper and lower sides. 請求項６に記載の薄膜トランジスタアレイ基板であって、
前記第３接着剤収容溝は、前記第１接着剤収容溝と上下に１対１で対応することを特徴とする薄膜トランジスタアレイ基板。 7. The thin film transistor array substrate according to claim 6, wherein
3. The thin film transistor array substrate according to claim 1, wherein the third adhesive receiving groove corresponds to the first adhesive receiving groove on the upper and lower sides. 請求項７に記載の薄膜トランジスタアレイ基板であって、
接着剤を前記第１接着剤収容溝、前記第２接着剤収容溝及び前記第３接着剤収容溝に収容することで、前記第１補強部材、前記第２補強部材及び前記第３補強部材を固定することを特徴とする薄膜トランジスタアレイ基板。 8. The thin film transistor array substrate according to claim 7, wherein
The adhesive is contained in the first adhesive receiving groove, the second adhesive receiving groove, and the third adhesive receiving groove, whereby the first reinforcing member, the second reinforcing member, and the third reinforcing member are used. A thin film transistor array substrate characterized by fixing. 請求項８に記載の薄膜トランジスタアレイ基板であって、
接着剤を前記第１接着剤収容溝、前記第２接着剤収容溝及び前記第３接着剤収容溝に収容することで、前記第１補強部材、前記第２補強部材及び前記第３補強部材を固定することを特徴とする薄膜トランジスタアレイ基板。 A thin film transistor array substrate according to claim 8, wherein
The adhesive is contained in the first adhesive receiving groove, the second adhesive receiving groove, and the third adhesive receiving groove, whereby the first reinforcing member, the second reinforcing member, and the third reinforcing member are used. A thin film transistor array substrate characterized by fixing. 請求項１に記載の薄膜トランジスタアレイ基板であって、
前記第３補強部材上に設置された導電性テープをさらに含み、前記導電性テープの一端は、前記表示領域と前記制御チップとの間まで延伸して前記制御チップに電気的に接続され、前記導電性テープの他端は、前記フレキシブル回路基板まで延伸して前記フレキシブル回路基板上の接地端子に電気的に接続されることを特徴とする薄膜トランジスタアレイ基板。 The thin film transistor array substrate according to claim 1, wherein
The conductive tape may further include a conductive tape disposed on the third reinforcing member, one end of the conductive tape being extended between the display area and the control chip and electrically connected to the control chip, The other end of the conductive tape is extended to the flexible circuit board and electrically connected to the ground terminal on the flexible circuit board. 請求項１に記載の薄膜トランジスタアレイ基板であって、
前記第１補強部材、前記第２補強部材及び前記第３補強部材はいずれもポリエチレンテレフタレートから製造されることを特徴とする薄膜トランジスタアレイ基板。 The thin film transistor array substrate according to claim 1, wherein
The thin film transistor array substrate, wherein the first reinforcing member, the second reinforcing member, and the third reinforcing member are all made of polyethylene terephthalate. 液晶パネルであって、
モジュール化して設けられた薄膜トランジスタアレイ基板と、カラーフィルム基板と、前記薄膜トランジスタアレイ基板と前記カラーフィルム基板との間に介装される液晶層と、を含み、
前記薄膜トランジスタアレイ基板は、
基板と、
前記基板にアレイ状に配列される複数の薄膜トランジスタであって、前記複数の薄膜トランジスタが占める領域は表示領域である複数の薄膜トランジスタと、
前記基板に設置され且つ前記表示領域の一側に位置するフレキシブル回路基板と、
前記表示領域と前記フレキシブル回路基板との間に設置された制御チップであって、前記フレキシブル回路基板の両側がそれぞれ前記制御チップの対応する両側を超える制御チップと、
前記制御チップの第１側に設置された第１補強部材であって、前記第１側は、前記制御チップが前記表示領域に向いている一側に隣接する、第１補強部材と、
前記制御チップの前記第１側に対向する第２側に設置された第２補強部材と、
前記制御チップ、前記第１補強部材及び前記第２補強部材を被覆する第３補強部材と、を含む液晶パネル。 A liquid crystal panel,
A thin film transistor array substrate provided in a modular form, a color film substrate, and a liquid crystal layer interposed between the thin film transistor array substrate and the color film substrate,
The thin film transistor array substrate is
A substrate,
A plurality of thin film transistors arranged in an array on the substrate, wherein a region occupied by the plurality of thin film transistors is a display region;
A flexible circuit board disposed on the substrate and positioned on one side of the display area;
A control chip disposed between the display area and the flexible circuit board, wherein both sides of the flexible circuit board respectively exceed the corresponding sides of the control chip;
A first reinforcing member disposed on a first side of the control chip, wherein the first side is adjacent to one side where the control chip is directed to the display area;
A second reinforcing member disposed on a second side opposite to the first side of the control chip;
A liquid crystal panel comprising: the control chip; and a third reinforcing member covering the first reinforcing member and the second reinforcing member.
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