JP2019502216A - In-situ quantum error correction - Google Patents

Abstract

  A method, system, and apparatus for parallel optimization of sequential execution of quantum error correction with closed loop feedback. In one aspect, the method includes continuously and effectively optimizing qubit performance in situ while performing error correction operations on the quantum system. The method directly monitors the output from error detection and provides this information as feedback to calibrate the quantum gate associated with the quantum system. In some implementations, the physical qubits are spatially divided into one or more independent hardware patterns, and the errors that can be attributed to each hardware pattern are non-overlapping. The one or more different sets of hardware patterns are then temporarily interleaved so that all physical qubits and operations are optimized. With the method, optimization of each section of the hardware pattern can be performed individually and in parallel, resulting in O (1) scaling.

Description

  Optimization of physical gate parameters is required to build fault tolerant quantum computers. Characterization methods such as randomized benchmarking or tomography require interruption of the necessary error detection operations and do not guarantee optimal performance in the error correction circuit. Optimizing physical gate parameters using error model optimization methods requires that the error model be trained so that the measured physical error can be linked to the physical gate, and the determined error is controlled. Require that it be linked back to parameter changes, increasing the complexity of the optimization process.

  This specification relates to qubit performance in quantum computation.

  This document describes techniques for optimizing on-the-fly continuous and parallel qubit performance while performing error correction operations on quantum systems.

  In general, one inventive aspect of the subject matter described herein is a plurality of measurements that interleave with a plurality of data qubits and each data qubit has a nearby measurement qubit such that it has a nearby measurement qubit. Multiple read qugates and each single qubit qugate configured to operate with data qubits or measurement qubits, each qubit configured to operate with measurement qubits A plurality of single qubit quantum gates and each CNOT quantum gate configured to operate with data qubits and nearby measurement qubits, each CNOT gate defining one of a plurality of directions, Accessing a quantum information storage system comprising a CNOT quantum gate, and data qubits and measurements Dividing the child bits into a plurality of patterns, wherein at least one pattern receives a non-overlapping error for the pattern, the non-overlapping error for the pattern is an error that can be attributed to the pattern, and a measurement qubit For each pattern including the steps of optimizing in parallel the parameters of a read qugate that operates with the measurement qubit, and optimizing the parameters of a single qubit quantum gate that operates with the measurement qubit in parallel, For each pattern including a data qubit and a measurement qubit operated by a CNOT gate, a step of optimizing the parameters of a single qubit quantum gate operating with the data qubit in parallel and a CNOT gate defining the same direction Select a set of The parameters for the CNOT gates may include an action comprising the step of optimizing in parallel.

  Other implementations of the aspect include corresponding computer systems, apparatuses, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method. Configuring a system of one or more computers to perform a specific operation or action by software, firmware, hardware, or a combination thereof installed in the system that causes the system to perform an action Can do. One or more computer programs, when executed by a data processing device, can be configured to perform a particular operation or action by including instructions that cause the device to perform an action.

  Each of these and other implementations may optionally include one or more of the following features, alone or in combination.

  In some implementations, the plurality of data qubits and measurement qubits define a one-dimensional chain of qubits where the plurality of data qubits and measurement qubits are the first direction and the plurality of directions. Interleaved to include a second direction opposite to the first direction.

  In other implementations, the plurality of single qubit gates are phase shift gates or rotation gates.

  In some cases, the data qubit is a control qubit, and the neighboring measurement qubit is a target qubit for each CNOT gate.

  In other cases, the data qubit is a target qubit, and the neighboring measurement qubit is a control qubit for each CNOT gate.

  In some implementations, the step of optimizing the parameters of the readout quantum gate operating on the measurement qubit in parallel is an iterative process using closed-loop feedback, and each iteration is minimally measured in parallel for each measurement qubit. Defining a corresponding metric for initialization as a determined error rate, measuring the measured qubit to determine a current error rate, and storing the determined current error rate Calculating a change in error rate between the current error rate and the stored error rate from the previous iteration, and determining the read gate parameter based on the calculated change in error rate. Adjusting.

  In some cases, adjusting the read gate parameter based on the defined metric for minimization includes applying a numerical optimization algorithm.

  In some implementations, the step of optimizing the parameters of a single qubit qugate operating on the measurement qubit in parallel is an iterative process using closed-loop feedback, and each iteration is performed in parallel for each measurement qubit. Defining a corresponding metric for minimization as a determined error rate, measuring the measurement qubit to determine an error rate, and storing the determined current error rate Calculating a change in error rate between the current error rate and the stored error rate from the previous iteration, and based on the calculated change in error rate, the single qubit gate Adjusting the parameters.

  In some cases, adjusting the parameters of the single qubit gate based on the defined metric for minimization includes applying a numerical optimization algorithm.

  In some implementations, the step of optimizing the parameters of a single qubit qugate operating on the data qubit in parallel is an iterative process using closed-loop feedback, and each iteration is performed in parallel for each data qubit. Defining a corresponding metric for minimization as a determined error rate, measuring the corresponding measurement qubit to determine an error rate, and storing the determined current error rate Calculating a change in error rate between the current error rate and the stored error rate from the previous iteration, and the single qubit based on the calculated change in error rate. Adjusting the parameters of the gate.

  In some cases, adjusting the single qubit gate parameters based on a defined metric for minimization includes applying a numerical optimization algorithm.

  In other implementations, selecting a set of CNOT gates that define the same direction and optimizing the parameters for the selected CNOT gates in parallel may be performed in parallel for each selected set of CNOT gates. For each data qubit in the selected set, defining a corresponding metric for minimization as a determined error rate, and measuring the corresponding measurement qubit to determine an error rate Storing the determined current error rate, calculating a change in error rate between the current error rate and the stored error rate from the previous iteration, and an error rate Adjusting the CNOT gate parameter based on the calculated change in.

  In some cases, adjusting the single qubit gate parameters based on a defined metric for minimization includes applying a numerical optimization algorithm.

  The subject matter described herein can be implemented to realize one or more of the following advantages. By optimizing the physical gate parameters, and thus qubit performance, on the fly while performing error correction, parallel optimization of continuous error correction execution is achieved. The performance of the quantum computer to be implemented provides improved performance and reliability compared to a quantum computer using other characterization methods that may require the required error detection operations and other computational interruptions Can do. For example, a quantum computer that implements parallel optimization of performing continuous error correction performs system drift, i.e., for each gate parameter per qubit, while the system is running without interrupting the computation. Optimal parameter drift as a result of system hardware changes due to temperature can be countered.

  In many situations, a detection event is the only information available that reflects system performance while error detection is being performed. Quantum computers that implement parallel optimization of performing continuous error correction require detection events, which is an important technique that can be applied to many different forms of error correction.

  In addition, the main challenge of error correction operation is to know how the gates characterized by other methods perform in error detection circuits in multi-qubit systems, so that continuous error correction is performed. Quantum computers that implement parallel optimization of the above achieve improved performance in error correction circuits compared to other characterization methods. The qubits that store the data are generally not measured between computations, but still require optimization, which can be achieved by parallel optimization of successive error correction runs.

  A quantum computer that implements parallel optimization of performing continuous error correction may be model-free, for example, the initial description may be model-free, and the need to build an error model. To avoid. Quantum computers that implement parallel optimization of performing continuous error correction can therefore avoid the need to collect statistics on various error types for use in training such error models. Often, the error model requires the physical system to be well below a threshold so that individual first order errors are sparse in order to collect sufficient statistics, and thus compared to other characterization methods. Save time and computational resources required.

  In addition, any size quantum computer that implements parallel optimization of performing continuous error correction performs a high level of scalability, eg, O (1), to optimize each gate within the quantum computer. Can be realized.

  The details of one or more implementations of the subject matter are described in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the detailed description, the accompanying drawings, and the appended claims.

1 is a one-dimensional schematic perspective view of an exemplary error correction system. FIG. 2 is a two-dimensional schematic perspective view of a qubit in an exemplary error correction system. FIG. 1 is a one-dimensional schematic perspective view of an exemplary hardware pattern in an error correction system including a one-dimensional array of qubits. FIG. 1 is a one-dimensional schematic perspective view of an exemplary hardware pattern in an error correction system including a one-dimensional array of qubits. FIG. 2 is a circuit representation of a one-dimensional schematic perspective view of a qubit in an exemplary error correction system. 2 is a two-dimensional schematic perspective view of an exemplary hardware pattern in an error correction system. FIG. 2 is a flowchart of an exemplary process for error correction. 4 is a flow diagram of an example process for optimizing a single qubit qugate parameter on a measurement qubit. 4 is a flow diagram of an example process for optimizing a single qubit qugate parameter on a data qubit. 2 is a flow diagram of an exemplary process for optimizing CNOT gate parameters.

  Like reference numbers and designations in the various drawings indicate like elements.

  This document describes quantum systems and methods for continuously and effectively optimizing qubit performance in situ while performing error correction operations on the quantum system. The method directly monitors the output from error detection and provides this information as feedback to calibrate the quantum gate associated with the quantum system. In some implementations, the physical qubits are spatially divided into one or more independent hardware patterns, ie, configurations in which errors that can be attributed to each hardware pattern are non-overlapping . The one or more different sets of hardware patterns are then temporarily interleaved so that all physical qubits and operations are optimized. With this method, optimization of each section of the hardware pattern can be performed individually and in parallel, resulting in O (1) scaling.

Exemplary Operating Environment FIG. 1A is a one-dimensional schematic perspective view of an exemplary error correction system 100 for iterative code. System 100 is a one-dimensional division of a two-dimensional surface code. The system includes a one-dimensional array of qubits 102. For clarity, nine qubits are shown in FIG. 1A, but the system may include a fairly large number of qubits, eg, millions of qubits. The array of qubits includes data qubits, eg, 104, 108, 112, 116, and 120, interleaved with measurement qubits, eg, measurement qubits labeled 106, 110, 114, and 118. Data qubits labeled as. In the case of bit flip error detection, the qubit may be a measured Z-type qubit.

  The system may include a set of readout quantum gates, eg, readout quantum gate 122. The read gate may be configured to operate with measurement qubits, eg, measurement qubits 106, 110, 114 and 118. Each read gate may provide a corresponding measured qubit state and may be associated with a corresponding set of physical read gate parameters.

  The system may include a set of single qubit quantum gates, for example, single qubit gates 132 and 134. The single qubit quantum gate may be configured to operate with either a single data qubit or a single measurement qubit. The single qubit gate shown in FIG. 1A includes a PauliX gate, eg, PauliX gate 134, and a Hadamard gate, eg, Hadamard gate 132, although in some implementations the system may include other single qubit gates. Good. For example, the single qubit gate may include any phase shift gate or rotation gate. Each single qubit quantum gate may be associated with a corresponding set of physical single qubit quantum gate parameters.

  The system may include a set of controlled NOT (CNOT) gates, such as CNOT gate 124. A controlled gate may act on more than one qubit, and one or more of the qubits may act as a control for several operations. A CNOT gate may operate with two qubits, a control qubit and a target qubit, and performs a NOT operation on the target qubit only when the control qubit is 1>. The CNOT gate in FIG. 1A is configured to operate with a pair of nearby measurement and data qubits, where one qubit operates as the control qubit and the other target qubit, for example, the CNOT gate 124 It operates with a pair of qubits 104 and 106. If error detection is designed to detect bit-flip errors, each data qubit manipulated by the CNOT gate may be a control qubit, and each neighboring measurement qubit has a corresponding target qubit It may be. Each CNOT gate may be associated with a corresponding set of physical CNOT gate parameters.

  A CNOT gate operating at a target qubit, eg, 106, eg, 124 in one or more directions relative to the target qubit, eg, left and right of the target qubit as shown in FIG. It may be defined. In the example repeat code, as shown in FIG. 1A, the CNOT quantum gate may copy a bit flip error from the associated data qubit to the associated measurement qubit for detection. In another example, if the error detection is designed to detect a phase flip error, the measurement qubit may be the control qubit and the neighboring data qubit is the target qubit. Also good. The CNOT quantum gate may then copy the phase flip error from the associated measurement qubit to the associated data qubit.

  The system may include an error correction subsystem 130 that is in data communication with the qubits 102. The error correction subsystem may be configured to monitor the output from error detection and feed back this information to the system to calibrate the quantum gate. Error correction subsystem 130 may spatially divide qubits 102 into one or more hardware patterns and perform quantum measurements on the measured qubits in each hardware pattern. The one or more hardware patterns may be independent such that optimization of each hardware pattern relative to each other may be inherently independent. The step of dividing the qubit into one or more hardware patterns is described in more detail below with reference to FIG. A measurement output, or detection event, may indicate a change in the measured pattern of the state relative to the measurement qubit, which indicates the presence of an error in the vicinity, i.e. the associated data qubit or measurement qubit. Indicates whether or not the error occurred. Thus, the measured outputs in them and their measured outputs may not directly correlate to data qubits or errors on measured qubits. The step of correlating the error and gate parameters is described in more detail below with reference to FIGS. 2A and 2B.

  The error correction subsystem 130 may use the results of the performed quantum measurements to calculate relevant quantities or metrics of interest, such as the current error rate for each measured qubit. The error correction subsystem 130 is also implemented such as calculating an average value of the determined error rate for one or more measured measurement qubits, or determining a change in error rate over time. Additional calculations may be performed using the results of the quantum measurements. The error correction subsystem 130 may include a data store and may store the results of performed quantum measurements or additional calculations.

  The error correction subsystem may optimize the parameters of the quantum gate acting on the qubit 102 using the results of the measurements made. For example, the error correction subsystem 130 implements a numerical optimization algorithm, such as the Nerder-Mead algorithm, to determine the appropriate adjustment of the quantum gate parameters, eg, the minimization of a set of quantum gate parameters. Also good. Once an appropriate adjustment is determined, the error correction subsystem may provide the adjustment as feedback to the qubit 102 and adjust the parameters of the quantum gate accordingly.

  FIG. 1B is a two-dimensional schematic perspective view of qubit 150 in an exemplary error correction system. The system may include a two-dimensional array of qubits 150. Again, for clarity, 81 qubits are shown in FIG. 1B, but the system may include a fairly large number of qubits, eg, millions of qubits. A measurement qubit, eg, 154, 156, 158, and so on, that the array of qubits has four neighboring measurement qubits for the data qubit above, below, right, and left It may include data qubits, eg, data qubits labeled 152, interleaved with measurement qubits labeled 160. FIG. 1B shows the scalability of the system 100A of FIG. 1 to a higher dimension.

  FIGS. 2A and 2B below illustrate exemplary hardware patterns used to implement quantum gate optimization.

  FIG. 2A is a one-dimensional schematic perspective view of an exemplary hardware pattern 200 in an error correction system that includes a one-dimensional array of qubits. For example, the error correction system may be an error correction system that includes a one-dimensional array of qubits 102, as described above with reference to FIG. 1A, and gate cross-hatching means that any measured qubit has an error from its gate. It corresponds to whether to detect.

  The hardware pattern 200 may include four hardware groupings 206, each including a measurement qubit and a corresponding single qubit operation for that qubit, for example, the hardware grouping 202 includes a measurement qubit 204 and a corresponding Single qubit operations 208 are included. The grouping within the hardware pattern may be operated independently. Errors from a single qubit operation 208 may not propagate to nearby data qubits, using relative detection fractions from the measured qubits, as described below with reference to FIG. Changes in gate parameters may be inferred.

  Furthermore, when error detection is designed to detect bit-flip errors, each data qubit manipulated by the CNOT gate is a control qubit, and each nearby measurement qubit is the corresponding target qubit The bit flip error may not propagate to the data qubit due to the direction of the CNOT gate applied to the data qubit and measurement qubit pair. Rather, the bit flip error may be localized to a specific measurement qubit and thus a specific hardware grouping.

  For gate error localization, the measurement qubit may have a single qubit qugate parameter that is individually optimized in full parallel as one hardware pattern 200. Depending on the configuration, the hardware pattern into which the data qubit and the measurement qubit are divided may include one pattern including a hardware grouping that includes only the measurement qubit.

  FIG. 2B is a one-dimensional schematic perspective view of exemplary hardware patterns 210 and 220 in an error correction system including a one-dimensional array of qubits. For example, the error correction system may be an error correction system that includes a one-dimensional array of qubits 102 as described above with reference to FIG. 1A, and gate cross-hatching means that any measured qubit has an error from its gate. It corresponds to whether to detect.

  The hardware pattern 210 may include multiple hardware groupings, eg, hardware groupings 212, each of which corresponds to one data quanta along with corresponding single qubit operations for measurement and data qubits and CNOT gates. For example, as shown in FIG. 2B, the hardware grouping 212 includes a measurement qubit 214, a single qubit operation 216, and CNOT gates 218 and 219. The grouping in the hardware pattern may be operated independently. Errors from the single qubit operation 216 and CNOT gates 218 and 219 do not have to propagate outside the hardware grouping 212 and are measured within each hardware grouping as described below with reference to FIGS. The detection event fraction of qubits may be used to infer changes in gate parameters for the gates in each grouping.

  Furthermore, when error detection is designed to detect bit-flip errors, each data qubit manipulated by the CNOT gate is a control qubit, and each nearby measurement qubit is the corresponding target qubit Unlike the hardware pattern 200, a bit flip error may be copied from a data qubit to a nearby measurement qubit through a CNOT gate. Thus, a single error on a data qubit may generate two detection events on nearby measurement qubits, optimizing CNOT gate parameters in parallel on the same measurement qubit or data qubit It may not be possible to do. There may be natural limitations on the hardware pattern, eg, 210 and 220. In general, a CNOT gate that is completely contained in a hardware pattern may be optimized in that pattern.

  If the next nearest data qubits simultaneously optimize their single qubit parameters, they may both copy the error into the same measured qubit. Thus, errors can be confusing. To avoid this problem, all other data qubits may be optimized to avoid double mapping errors to measurement qubits. Two hardware patterns 210 and 220 that can simultaneously optimize their single qubit parameters without such confusion may be generated, for example, optimization of both patterns 210 and 220 relative to each other is essentially Independent. Depending on the configuration, the hardware pattern into which the data qubit and the measurement qubit are divided may include at least one pattern, and the corresponding hardware grouping includes both the data qubit and the measurement qubit.

  The hardware patterns 200, 210, and 220 shown in FIGS. 2A and 2B constitute the minimum number of hardware patterns that can be used to perform error correction in a one-dimensional error correction system as shown in FIG. 1A. To do. The table below counts the number of patterns that can be interleaved to optimize all gates in parallel. There are three interleaved patterns, and one gate in each pattern may be optimized in parallel. This number is ideal in any sense, i.e., assuming that the system is implemented with no parasitic interactions with qubits that should not interact. May be a constant for repetitive codes of the size The pattern shown is a minimal set of patterns, and some implementations may add more as needed. By selecting such a hardware pattern for the system, the gate parameters in each hardware grouping in each hardware pattern will change the gate parameter to yield a measured error rate for each hardware grouping. It may be optimized by optimizing. Further, by selecting a finite number of hardware patterns, each operation necessary to optimize the quantum computer performing error detection can be accessed. Once the hardware pattern is selected, all hardware groupings can be optimized independently in parallel, which is O (1) scaling to optimize all single gates in any size quantum computer It is a strategy.

  Although there are three separate patterns that require optimization, there are multiple operations that can be independently optimized within a pattern. The steps of optimizing the gate parameters are described in more detail below with reference to FIGS.

  The hardware patterns shown in the table above and described above with reference to FIGS. 2A and 2B are exemplary and not comprehensive. By tracking error propagation within a particular circuit, the exact pattern and each grouping can be customized and determined for the system. For example, the hardware pattern need not be calculated in advance by the system software. In some implementations, the hardware pattern may be determined by changing the parameters on a particular gate and observing where the detected event change was found. By changing each of the parameters at each of the particular gates in this manner, the generated information may be processed and used to determine the hardware pattern. Such a method for determining hardware patterns is sensitive to hardware non-idealities and may increase system performance and efficiency.

  FIG. 3 is a circuit representation of a one-dimensional schematic perspective view of a qubit in an exemplary error correction system. In this simplified circuit representation, the output of the measurement qubit 304 has three inputs: one for the associated measurement qubit 304 and one for each neighboring data qubit 302 and 306. May operate as a multiplexer 308 having two. Only one of the inputs to the multiplexer may be selected at a time to directly search for the output of the data or measurement box, eg, one of data boxes 302, 306 and measurement box 304. This results in the three hardware patterns 200, 210 and 220 described above with reference to FIGS. 2A and 2B.

  FIG. 4 is a two-dimensional schematic perspective view 400 of an exemplary hardware pattern in an error correction system. The same analysis described above with reference to FIGS. 2A and 2B may be applied to the surface code to generate the indicated hardware pattern. The hardware pattern may include one hardware pattern 404 that includes measurement qubits. The remaining hardware patterns 406-412 may include both data qubits and measurement qubits.

  The hardware patterns 404-412 shown in FIG. 4 constitute the minimum number of hardware patterns that can be used to implement error correction for a system that includes a two-dimensional array of qubits. The table below counts the number of patterns that are interleaved to optimize all gates in parallel. There are five interleaved patterns, and one gate may be optimized in each pattern. The pattern shown is representative and not a minimal set. Other patterns exist and may be more complex. The number and complexity of the patterns depends on the exact details of how the quantum gates are executed across the array. As described above, by selecting such a hardware pattern for the system, the gate parameters within each hardware grouping in each hardware pattern will change the gate parameter and measure for each hardware grouping. It may be optimized by optimizing the error rate made. Furthermore, by selecting a finite number of hardware patterns, each operation required to optimize the quantum computer performing error detection can be accessed. Once a hardware pattern is selected, all hardware groupings can be optimized independently and in parallel, which is an O (to optimize all single gates in a quantum computer of any size. 1) A scaling strategy.

  There are five separate patterns that require optimization, but there are multiple operations that can be independently optimized within a pattern. The steps of optimizing the gate parameters are described in more detail below with reference to FIGS.

  The hardware patterns shown in the table above and described above with reference to FIG. 4 are exemplary and not comprehensive. By tracking error propagation within a particular circuit, the exact pattern and each grouping can be customized and determined for the system. For example, the hardware pattern need not be pre-calculated by the system software. In some implementations, the hardware pattern may be determined by changing the parameters on a particular gate and observing where the detected event change was found. By changing each of the parameters at each of the particular gates in this manner, the generated information may be processed and used to determine the hardware pattern. Such a method for determining hardware patterns is sensitive to hardware non-idealities and may increase system performance and efficiency.

  Although the hardware patterns described herein are specific to a one-dimensional chain of qubits that execute repetitive code, this technique can be generalized to most error correction frameworks. Any framework that detects errors using a fixed group of maximum size qubits and the number of groups to which any qubit belongs does not correspond to the system size uses the hardware and method described herein. can do. For example, the technology may be compatible with all topology codes, including subsystem code, and all concatenated codes by focusing on the lowest level concatenation. This includes surface and color codes, and Steane and Shor codes. The hardware and methods described herein may not be compatible with finite rate block codes if it is desired to preserve O (1) scaling at system size. Hardware patterns and groupings can be found algorithmically by simulating an error detection circuit or by physically changing the control parameters to determine where the detected fraction changes.

  In particular, FIGS. 2A and 2B, 3 and 4 have been described with respect to iteration code and surface code, but the method of tracking the error signature from the gate to the physical measurement is applied outside of the iteration and surface code, and any Applicable to quantum circuits and may be used as a method for providing feedback for optimization.

Performing In Situ Quantum Error Correction FIG. 5 is a flow diagram of an exemplary process 500 for performing continuous optimization of quantum gate parameters while performing error correction. For example, process 500 may be performed during an error correction procedure by system 100 or 300 described above with reference to FIGS. 1A-1B and FIG. Process 500 uses error detection to self-diagnose and allows continuous optimization of control parameters while the system is running, thus countering system drift without interrupting computation.

  The system spatially divides the set of data qubits and measurement qubits into separate hardware patterns (step 502). The system splits the set of data and measurement qubits so that errors that can be attributed to each separate hardware pattern do not overlap with errors that can be attributed to other separate hardware patterns To do. Depending on the configuration, the hardware pattern may include one pattern having a grouping that includes measurement qubits and two or more patterns having a grouping that includes both data qubits and measurement qubits. An arrangement for dividing the set of data qubits and measurement qubits into separate hardware patterns is described in more detail above with reference to FIGS. 2A and 2B and FIG.

  The system enters a stage for optimizing the parameters of quantum gates operating on qubits in each hardware pattern having a grouping that includes measurement qubits (step 504). Depending on the configuration, each of the measurement qubits in the set of data qubits and measurement qubits may form one of the hardware patterns constructed in step 502. For example, in one dimension, the system may optimize the parameters of the quantum gate operating on the measured qubits in the hardware pattern 200 described above with reference to FIG. 2A. In another example, in two dimensions, the system may optimize the parameters of quantum gates operating with measured qubits in hardware pattern 404 described above with reference to FIG.

  The step of optimizing the parameters of the quantum gate operating with the measurement qubit may be considered as the simplest optimization stage. For example, when considering the step of performing error correction on the iterative code, the measurement qubit may detect a bit flip error. Due to the direction of the CNOT gate applied to the measurement and data qubit pair, the bit flip error does not propagate from the measurement qubit to the data qubit, so the error is localized to a specific measurement qubit. The The measurement qubits are therefore single qubit qugates operating on them that are individually optimized in full parallel as one hardware pattern, as described below with reference to steps 506 and 508 May have the following parameters.

  The system performs optimization of the parameters of the read gate operating with the measurement qubit (step 506). Optimization of the parameters of the read gate operating with the measurement qubit may be performed in parallel for each measurement qubit in the hardware pattern. An exemplary process for optimizing the parameters of the read gate operating with the measurement qubit is described in detail below with reference to FIG.

  The system optimizes the parameters of a single qubit quantum gate operating with the measurement qubit (step 508). Optimization of the parameters of the single qubit quantum gate operating with the measurement qubit may be performed in parallel for each measurement qubit in the hardware pattern. An exemplary process for optimizing the parameters of a single qubit quantum gate operating with the measurement qubit is described in detail below with reference to FIG.

  The system enters a stage for optimizing parameters of quantum gates operating on qubits in each hardware pattern having a grouping that includes both data qubits and measurement qubits (step 510). Depending on the configuration, in each hardware pattern having a grouping that includes both data and measurement qubits, the data qubits may be accompanied by measurement qubits in their respective hardware groupings constructed in step 502. . For example, in one dimension, the system may optimize the parameters of a single qubit quantum gate operating with data qubits in hardware patterns 210 and 220 described above with reference to FIG. 2B. In another example, in two dimensions, the system optimizes the parameters of a single qubit quantum gate operating with data qubits in hardware patterns 406, 408, 410 and 412 described above with reference to FIG. May be.

  The step of optimizing the parameters of the single qubit quantum gate operating with the data qubit is more complex than the step of optimizing the parameters of the single qubit quantum gate operating with the measurement qubit. Also good. For example, when considering the step of performing error correction on a repetitive code, a bit flip error is transferred from a data qubit to a nearby measurement qubit through a CNOT gate operating on both the data qubit and the measurement qubit. You may copy. Thus, a single error on a data qubit may generate an output or detection event at each of its neighboring measurement qubits, as described above with reference to FIGS. 2A and 2B. Data qubits therefore both copy the error to the same measured qubit and generate error confusion if the next nearest data qubit simultaneously optimizes the parameters of their single qubit gate As such, it is not necessary to have the parameters of single qubit quantum gates operating on them that are individually optimized in full parallel as one hardware pattern. Instead, all other data qubits are optimized in parallel as one hardware pattern, as described below with reference to step 512 and FIG. Mapping may be avoided.

  The system performs parameter optimization of a single qubit gate operating on the data qubit in each hardware pattern having a grouping that includes both data qubits and measurement qubits (step 512). Optimization of the parameters of a single qubit quantum gate operating with data qubits in each hardware pattern may be performed separately for each hardware pattern. However, the optimization of the parameters of a single qubit quantum gate that operates with data qubits within each grouping within each hardware pattern may be performed in parallel for each data qubit within the hardware pattern. An exemplary process for optimizing the parameters of a single qubit quantum gate operating with the data qubit is described in detail below with reference to FIG.

  The step of performing parameter optimization of a CNOT gate operating on a data qubit and measurement qubit pair can also be complicated due to error confusion. Errors on the data qubit may propagate to the measurement qubit on each side of the data qubit involved. Thus, an error on a data qubit may generate an output or detection event at each of its nearby measurement qubits, as described above with reference to FIG. 2B. The parameters of a CNOT gate operating with a pair of data and measurement qubits may therefore not be optimized in parallel on the same data or measurement qubit. This naturally limits the hardware pattern to the same as described above with reference to step 510, for example. To avoid error confusion, there may be a simple rule, i.e. only CNOT gates that are completely contained in the hardware pattern may be optimized with this pattern.

  The system performs optimization of parameters of CNOT gates operating on data and measurement qubit pairs in each hardware grouping that includes both data and measurement qubits in the hardware pattern (steps). 514). Optimization of the parameters of the CNOT gate operating on the data qubit and measurement qubit pairs in the hardware pattern may be performed separately for each hardware pattern. Further, the system selects a CNOT gate that defines the same direction in the hardware pattern, and sets the parameter of the CNOT gate that defines the same direction in parallel for each data qubit in the hardware pattern. Optimize. For example, in one dimension, for each hardware pattern that includes data qubits and measurement qubits, the system first optimizes the selected CNOT gate parameter in parallel to the left of the data qubits. A set of CNOT gates may be selected and a set of CNOT gates to the right of the data qubit that optimizes the selected CNOT gate parameters in parallel may be selected. An exemplary process for optimizing the parameters of a CNOT gate operating with the data and measurement qubits is described in detail below with reference to FIG.

  For clarity, an exemplary process 500 flow diagram for performing continuous optimization of quantum gate parameters while performing error correction is described with reference to steps 504-514. However, the operations of steps 504 through 514 need not be performed sequentially in the order presented. The steps may be performed in different sequences or multiple times. That is, if necessary, before the next step in the sequence is performed, for example, in some implementations, the system operates with qubits operating on qubits in each hardware pattern that includes measurement qubits. Before entering the stage for optimizing the parameters of the gates, first, to optimize the parameters of the quantum gates operating on the qubits in each hardware pattern, including both data qubits and measurement qubits You may enter the stage. Similarly, once the system has entered a stage for optimizing the parameters of a quantum gate that operates with qubits within each hardware pattern including, for example, measurement qubits, the system may perform the optimization step 506 before performing it. First, an optimization step 508 may be performed. By cycling between steps 506, 508, 512 and 514, i.e., cycling between hardware patterns, all of all gates for all qubits while the system is running The system drift may be countered by the parameters.

  FIG. 6 is a flow diagram of an example process 600 for optimizing parameters of a read gate or a single qubit qugate operating with measured qubits. Process 600 is for optimizing read quantum gate parameters as described above in step 506 of FIG. 5 or for optimizing single qubit quantum gate parameters as described above in step 508 of FIG. The system 100 or 300 described above with reference to FIGS. 1A-1B and FIG. Depending on the configuration, each of the measurement qubits in the set of data qubits and measurement qubits described in FIGS. 1A-1B and FIG. 3 is represented in the hardware pattern constructed in step 502 above with reference to FIG. One of them is formed. For example, in one dimension, the system may optimize the parameters of a read quantum gate or a single qubit quantum gate that operates on the measured qubits in the hardware pattern 202 described above with reference to FIG. 2A. In another example, in two dimensions, the system may optimize the parameters of quantum gates operating with measured qubits in hardware pattern 404 described above with reference to FIG.

  Process 600 may be performed in parallel for each measured qubit in the corresponding hardware pattern. Process 600 may continuously repeat the process of optimizing the parameters of a read gate or single qubit qugate operating with measured qubits using closed loop feedback.

  In parallel, for each measured qubit, the system defines the corresponding metric for error minimization as the determined error rate (step 602). The quantum gate error may be minimized by minimizing the error rate of each qubit, also called a detection event fraction. In the case of a hardware pattern that includes a single measurement qubit, the metric for error minimization may be a fraction of detection events for that qubit. In the case of hardware patterns that include multiple measured qubits, such as those shown in FIGS. 2A and 4, the metric for error minimization is the average fraction of detection events taken for all measured qubits. .

  In parallel, for each measured qubit, the system measures the measured qubit to determine the current error rate (step 604).

  The system stores the determined error rate (step 606). The system stores the determined error rate for each iteration of process 600 so that changes in error rate are monitored over time and correlated with changes made to the quantum gate parameters.

  The system calculates the change in error rate between the determined current error rate and the stored error rate from the previous iteration (step 608). A measured output, or detection event, and a change in the measured pattern of states relative to the measurement qubit may indicate the presence of a nearby error, regardless of the data qubit or measurement qubit. However, the detection event itself may not directly correlate to errors on the measurement qubits or data qubits. Thus, in order to correlate the change in error with the change in gate parameter, the change in localized detection event fraction, ie the error rate, may be compared with the change in gate parameter.

  In parallel, for each measured qubit, the system adjusts the read gate parameter, or single qubit qugate parameter, based on the calculated change in error rate (step 610). The system applies a numerical optimization algorithm, such as the Nelder-Mead method, to the read gate parameter or single qubit quantum gate parameter, based on the change in error rate calculated in step 608. The adjustment may be determined.

  The system may continuously repeat steps 602 through 610 described above. In principle, in order to obtain more information about the physical process associated with the gate error, it may be possible to distinguish between the measured value X and the measured value Y qubit, and this information May be fed back to the system to optimize it more efficiently.

  FIG. 7 is a flow diagram of an example process 700 for optimizing the parameters of a single qubit qugate operating with data qubits. Process 700 is performed by system 100 or 300 described above with reference to FIGS. 1A-1B and FIG. 3 for optimizing the parameters of the single qubit quantum gate as described above in step 512 of FIG. Also good. The process may be performed for each hardware pattern having a grouping that includes both data qubits and measurement qubits constructed in step 502 with reference to FIG. 5 above. For example, in one dimension, the system may optimize the parameters of a single qubit quantum gate operating with data qubits in hardware patterns 210 and 220 described above with reference to FIG. 2B. In another example, in two dimensions, the system may optimize the parameters of quantum gates operating with measured qubits in hardware patterns 406, 408, 410 and 412 described above with reference to FIG.

  Process 700 may be performed in parallel for each data qubit in the corresponding hardware pattern. Process 700 may be a continuously repeated process that uses closed loop feedback to optimize the parameters of a single qubit qugate operating on the data qubit.

  In parallel, for each data qubit, the system defines the corresponding metric for error minimization as the determined error rate (step 702). The quantum gate error may be minimized by minimizing the error rate of each qubit, also referred to as a detection event fraction. In this case of a hardware pattern having a grouping that includes multiple measured qubits, such as those shown in FIGS. 2B and 4, the metric for error minimization is the average of the detection events taken for all measured qubits It may be a fraction.

  In parallel, for each data qubit, the system measures the corresponding neighboring measurement qubit to determine the current error rate (step 704). For example, in a one-dimensional system, the system may measure at least two corresponding measurement qubits. For example, in a two-dimensional system, the system may measure at least four corresponding measurement qubits.

  The system stores the determined error rate (step 706). The system monitors error rate changes over time and stores the determined error rate for each iteration of the process 700 so that it can be correlated with changes made to the quantum gate parameters.

  The system calculates a change in error rate between the determined current error rate and the stored error rate from the previous iteration (step 708). A measured output, or detection event, and a change in the measured pattern of states relative to the measurement qubit may indicate the presence of a nearby error, regardless of the data qubit or measurement qubit. However, the detection event itself may not directly correlate to errors on the measurement qubits or data qubits. Thus, in order to correlate the change in error with the change in gate parameter, the change in localized detection event fraction, ie the error rate, may be compared with the change in gate parameter.

  In parallel, for each data qubit, the system adjusts the parameters of the single qubit gate based on the calculated change in error rate (step 710). Based on the error rate change calculated in step 708, the system applies a numerical optimization algorithm such as the Nelder-Mead method to determine the adjustment to be made to the single qubit quantum gate parameter. May be.

  The system may repeat steps 702 to 710 described above continuously. In principle, in order to obtain more information about the physical process associated with the gate error, it may be possible to distinguish between the measurement X and the measurement Y qubit, Feedback may be provided to the system to optimize the quantum gate more efficiently.

  FIG. 8 is a flow diagram of an example process 800 for optimizing the parameters of a CNOT gate operating with a data qubit and measurement qubit pair. Process 800 may be implemented by system 100 or 300 described above with reference to FIGS. 1A-1B and FIG. 3 for optimizing CNOT gate parameters as described above in step 514 of FIG. The process may be performed for each hardware pattern having a grouping that includes both data qubits and measurement qubits constructed in step 502 with reference to FIG. 5 above. For example, in one dimension, the system may optimize the parameters of the CNOT gate operating on the data and measurement qubit pairs in the hardware patterns 210 and 220 described above with reference to FIG. 2B. In another example, in two dimensions, the system may optimize the parameters of quantum gates operating with measured qubits in hardware patterns 406-412 described above with reference to FIG.

  The process 800 may be performed in parallel for each CNOT gate that is completely contained in the corresponding hardware pattern that defines the same direction with respect to the data qubit on which the CNOT gate operates. Process 800 may be a continuously repeated process that uses closed loop feedback to optimize the parameters of the CNOT gate.

  In parallel, for each data qubit, the system defines the corresponding metric for error minimization as the determined error rate (step 802). The quantum gate error may be minimized by minimizing the error rate of each qubit, also referred to as a detection event fraction. In this case of a hardware pattern with a grouping that includes multiple measurement qubits, such as those shown in FIGS. 2B and 4, the metric for error minimization is taken for all measurement qubits. It may be an average fraction of detection events.

  In parallel, for each data qubit, the system measures the corresponding neighboring measurement qubit to determine the current error rate (step 804). For example, in a one-dimensional system, the system may measure at least two corresponding measurement qubits. For example, in a two-dimensional system, the system may measure at least four corresponding measurement qubits.

  The system stores the determined error rate (step 806). The system monitors the change in error rate over time and stores the determined error rate for each iteration of process 800 so that it can be correlated with changes made to the quantum gate parameters.

  The system calculates the change in error rate between the determined current error rate and the stored error rate from the previous iteration (step 808). A measured output, or detection event, and a change in the measured pattern of states relative to the measurement qubit may indicate the presence of a nearby error, regardless of the data qubit or measurement qubit. However, the detection event itself may not directly correlate to errors on the measurement qubits or data qubits. Thus, in order to correlate the change in error with the change in gate parameter, the change in localized detection event fraction, ie the error rate, may be compared with the change in gate parameter.

  In parallel, for each data qubit, the system adjusts the CNOT gate parameter based on the calculated change in error rate (step 810). The system may apply a numerical optimization algorithm such as the Nelder-Mead method based on the error rate change calculated in step 808 to determine the adjustment to be made to the CNOT quantum gate parameter. .

  The system may continuously repeat steps 802 through 810 described above. In principle, in order to obtain more information about the physical process associated with the gate error, it may be possible to distinguish between the measurement X and the measurement Y qubit, May be fed back to the system to optimize it more efficiently.

  Implementation of digital and / or quantum subject and digital function operations and quantum operations described herein tangibly in digital electronic circuits, suitable quantum circuits, or more generally quantum computing systems Digital and / or quantum computer software or firmware, digital and / or quantum computer hardware including the structures disclosed herein, and their structural equivalents, or one of them Multiple combinations can be implemented. The term “quantum computing system” may include, but is not limited to, a quantum computer, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

  An implementation of the digital and / or quantum subject matter described herein for execution by one or more digital and / or quantum computer programs, ie, data processing devices, or for controlling its operation It can be implemented as one or more modules of digital and / or quantum computer program instructions encoded in a temporary storage medium. The digital and / or quantum computer storage medium is a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits, or one or more combinations thereof Can do. Alternatively or additionally, the program instructions are transmitted to an artificially generated propagated signal capable of encoding digital and / or quantum information, eg, a suitable receiver device for execution by a digital and / or quantum data processing device It can be encoded with a machine-generated electrical, optical, or electromagnetic signal generated to encode the information to do.

  The terms quantum information and quantum data refer to information or data carried by and held in or stored in a quantum system, where the least non-obvious system is a system that defines qubits, ie units of quantum information. It is understood that the term “quantum bit” encompasses all quantum systems that can be adequately approximated as a two-level system in the corresponding context. Such quantum systems may include, for example, multilevel systems having more than one level. By way of example, such a system can include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the calculated fundamental state is identified by the ground state and the first excited state, but other configurations are possible where the calculated state is identified by a higher level excited state. Is understood. The term “data processing apparatus” refers to digital and / or quantum data processing hardware such as programmable digital processors, programmable quantum processors, digital computers, quantum computers, multiple digital and quantum processors or computers, and their Includes all types of apparatus, devices, and machines for processing digital and / or quantum data for processing, including combinations. The apparatus further includes a special purpose logic circuit, such as an FPGA (Field Programmable Gate Array), ASIC (Special Purpose Integrated Circuit), or quantum, designed to simulate or generate information about a particular quantum system. It can be or include a simulator, ie a quantum data processing device. In particular, the quantum simulator is a special purpose quantum computer that does not have the ability to perform universal quantum computation. In some cases, the device constitutes, in addition to hardware, a digital and / or quantum computer program, eg, processor firmware, protocol stack, database management system, operating system, or one or more combinations thereof It can contain code that generates an execution environment for the code.

  A digital computer program may also be referred to or described as a program, software, software application, module, software module, script, or code, and includes a compiled or interpreted language, or a declarative or procedural language It can be written in any form of programming language and can be deployed in any form including a stand-alone program or module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program may also be referred to or described as a program, software, software application, module, software module, script, or code, including a compiled or interpreted language, or a declarative or procedural language It can be written in any form of programming language, can be converted to a suitable quantum programming language, or can be written in a quantum programming language such as QCL or Quiper.

  A digital and / or quantum computer program may correspond to a file in the file system, but need not. One or more programs stored in another program or part of a file holding data, eg, a markup language document, in a single file dedicated to the program in question, or in multiple collaborative files Multiple scripts can be stored in a file, subprogram, or code portion that stores one or more modules, for example. On one digital or one quantum computer where the digital and / or quantum computer program is located at one site or distributed across multiple sites interconnected by a digital and / or quantum data communications network or It can be deployed to run on multiple digital and / or quantum computers. A quantum data communication network is understood to be a quantum system, eg, a network that can transmit quantum data using qubits. In general, a digital data communication network cannot transmit quantum data, but a quantum data communication network can transmit both quantum data and digital data.

  The processes and logic flows described herein operate on one or more digital and / or quantum processors and optionally execute one or more digital and / or quantum computer programs to input digital And can be implemented by one or more programmable digital and / or quantum computers that perform functions by operating on quantum data and generating output. The process and logic flow can also be performed by special purpose logic circuits, such as FPGA or ASIC, or quantum simulators, or by a combination special purpose logic circuit or quantum simulator and one or more programmed digital and / or quantum computers. It can be implemented and the device can be implemented as them.

  That one or more digital and / or quantum computer systems are “configured to” perform a particular operation or action means that the system is software that, in operation, causes the system to perform the operation or action; It means installing firmware, hardware, or a combination of both. Configuring one or more digital and / or quantum computer programs to perform a particular operation or action means that the one or more programs are executed by a digital and / or quantum data processing device. Sometimes means including instructions that cause the device to perform the action or action. When executed by the quantum computing device, the quantum computer may receive instructions from the digital computer that cause the device to perform the operation or action.

  A digital and / or quantum computer suitable for executing a digital and / or quantum computer program may be a general purpose or special purpose digital and / or quantum processor or both, or any other kind of central digital and / or quantum processing unit. Can be based. In general, the central digital and / or quantum processing unit may receive instructions and digital and / or digital read-only memory, random access memory, or quantum systems suitable for transmitting quantum data, eg, photons, or combinations thereof. Alternatively, quantum data is received.

  The essential elements of a digital and / or quantum computer are a central processing unit for executing or executing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and the memory can be supplemented by a special purpose logic circuit or incorporated into the circuit or quantum simulator. In general, a digital and / or quantum computer also includes one or more mass storage devices, eg, a magnetic suitable for storing quantum information, to transmit and receive quantum system digital and / or quantum data. It may include or be operably connected to a magneto-optical disk, an optical disk. However, digital and / or quantum computers need not have such devices.

  Digital and / or quantum computer readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include, by way of example, semiconductor memory devices, eg, EPROM, EEPROM, and flash memory devices, Magnetic disks, such as internal hard disks or removable disks, magneto-optical disks, CD-ROM and DVD-ROM disks, and quantum systems, such as all forms of non-volatile digital and including trapped atoms or electrons And / or quantum memory, media and memory devices. Quantum memory is a device that can store quantum data for long periods of time with high fidelity and efficiency, for example, optical materials that store and store quantum features of quantum data such as light being used for transmission and superposition or quantum coherence It is understood that this is a light-matter interface.

  Control of the various systems described herein, or portions thereof, can be stored in one or more non-transitory machine-readable storage media and performed on one or more digital and / or quantum processing devices. It can be implemented in a digital and / or quantum computer program product that includes instructions. One or more digital and / or quantum processing devices and memory that store executable instructions for implementing the operations described herein, respectively, for the systems described herein, or portions thereof. It can be implemented as an apparatus, method or system that can be included.

  This specification includes a number of specific implementation details, which should not be construed as limitations on the scope of what can be claimed, but as descriptions of features that may be specific to a particular implementation. is there. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above and initially so claimed to operate in a particular combination, one or more features from the claimed combination may be implemented from that combination in some cases. The claimed combinations may be related to partial combinations or variations of partial combinations.

  Similarly, although operations have been described in a particular order in the drawings, this may be done in a particular order or in a sequential order that indicates such operations, or all indications, in order to achieve the desired result. It should not be understood as requiring that the performed operation be performed. In certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system modules and components in the above implementations should not be understood as requiring such separation in all implementations, and the described program components and systems are generally integrated into a single software product. It should be understood that it can be packaged into multiple software products.

  A specific implementation of the subject has been described. Other implementations are within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. By way of example, the processes shown in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

130 Error correction subsystem

Claims (28)

Communicate data with the measurement qubit,
Dividing the data qubit and the measurement qubit into a plurality of patterns, wherein at least one pattern receives a non-overlapping error for the pattern, and the non-overlapping error for the pattern is an error that can be attributed to the pattern When,
For each pattern that includes a measurement qubit,
Optimizing in parallel the parameters of the readout quantum gate operating with the measurement qubits,
Optimizing the parameters of a single qubit quantum gate operating with the measurement qubits in parallel;
For each pattern containing data qubits and measurement qubits operated by a CNOT gate,
Optimize the parameters of the single qubit quantum gate operating with the data qubits in parallel,
Selecting a set of CNOT gates that define the same direction and optimizing the parameters for the selected CNOT gates in parallel;
An apparatus comprising an error correction subsystem configured to: Multiple data qubits;
A plurality of measurement qubits interleaved with the data qubits such that each data qubit has one or more neighboring measurement qubits;
A plurality of readout quantum gates, each readout quantum gate configured to operate with a measurement qubit;
A plurality of single qubit qugates, each single qubit qugate configured to operate with data qubits or measurement qubits;
A plurality of CNOT quantum gates configured to operate with data qubits and neighboring measurement qubits, each CNOT gate defining one of a plurality of directions;
The apparatus of claim 1, further comprising:   The plurality of data qubits and measurement qubits define a one-dimensional chain of qubits, wherein the plurality of data qubits and measurement qubits are opposite to the first direction and the first direction. The apparatus of claim 2, wherein the apparatus is interleaved to include a second direction.   The apparatus of claim 2, wherein the plurality of single qubit gates are phase shift gates or rotation gates.   The apparatus of claim 2, wherein the data qubit is a control qubit and the neighboring measurement qubit is a target qubit for each CNOT gate.   The apparatus of claim 2, wherein the data qubit is a target qubit and the neighboring measurement qubit is a control qubit for each CNOT gate. In order to optimize in parallel the parameters of the readout quantum gate operating on the measurement qubit, the error correction subsystem is configured to perform an iterative process using closed-loop feedback, and at each iteration, the error correction The subsystem is
Define the corresponding metric for minimization as the determined error rate,
Measuring the measurement qubit to determine a current error rate;
Storing the determined current error rate;
Calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
Adjusting the read gate parameter based on the calculated change in error rate;
The apparatus of claim 1, configured as follows.   8. The apparatus of claim 7, wherein the error correction subsystem is configured to apply a numerical optimization algorithm to adjust the read gate parameter based on the calculated change in error rate. In order to optimize in parallel the parameters of a single qubit quantum gate operating on the measurement qubit, the error correction subsystem is configured to perform an iterative process using closed-loop feedback, and at each iteration, the The error correction subsystem in parallel, for each measurement qubit,
Define the corresponding metric for minimization as the determined error rate,
Measuring the measurement qubit to determine the error rate;
Storing the determined current error rate;
Calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
The apparatus of claim 1, configured to adjust a parameter of the single qubit gate based on the calculated change in error rate.   The error correction subsystem is configured to apply a numerical optimization algorithm to adjust the parameters of the single qubit gate based on the calculated change in error rate. apparatus. In order to optimize in parallel the parameters of a single qubit quantum gate operating on the data qubits, the error correction subsystem is configured to perform an iterative process using closed-loop feedback, and at each iteration, the The error correction subsystem in parallel, for each data qubit,
Define the corresponding metric for minimization as the determined error rate,
Measuring the corresponding measurement qubit to determine the error rate;
Storing the determined current error rate;
Calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
The apparatus of claim 1, configured to adjust a parameter of the single qubit gate based on the calculated change in error rate.   12. The error correction subsystem is configured to apply a numerical optimization algorithm to adjust parameters of the single qubit gate based on the calculated change in error rate. apparatus. In order to select a set of CNOT gates that define the same direction and optimize the parameters for the selected CNOT gates in parallel, the error correction subsystem includes:
In parallel, for each data qubit in the selected set,
Define the corresponding metric for minimization as the determined error rate,
Measuring the corresponding measurement qubit to determine the error rate;
Storing the determined current error rate;
Calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
The apparatus of claim 1, configured to adjust the CNOT gate parameter based on the calculated change in error rate.   14. The apparatus of claim 13, wherein the error correction subsystem is configured to apply a numerical optimization algorithm to adjust the CNOT gate parameter based on the calculated change in error rate. Dividing the data qubit and the measurement qubit into a plurality of patterns, wherein at least one pattern receives a non-overlapping error for the pattern, and the non-overlapping error for the pattern is an error that can be attributed to the pattern When,
For each pattern that includes a measurement qubit,
Optimizing in parallel the parameters of the readout quantum gate operating with the measurement qubits;
Optimizing the parameters of a single qubit quantum gate operating with the measurement qubits in parallel;
For each pattern that includes data qubits and measurement qubits operated by a CNOT gate,
Optimizing the parameters of a single qubit quantum gate operating on the data qubits in parallel;
Selecting a set of CNOT gates that define the same direction and optimizing the parameters for the selected CNOT gates in parallel;
Including a method. Multiple data qubits;
A plurality of measurement qubits that interleave with the data qubits such that each data qubit has neighboring measurement qubits;
A plurality of readout quantum gates, each readout quantum gate configured to operate with a measurement qubit;
A plurality of single qubit qugates, each single qubit qugate configured to operate with data qubits or measurement qubits;
A plurality of CNOT quantum gates configured to operate with data qubits and neighboring measurement qubits, each CNOT gate defining one of a plurality of directions;
16. The method of claim 15, further comprising accessing a quantum information storage system comprising:   The plurality of data qubits and measurement qubits define a one-dimensional chain of qubits, wherein the plurality of data qubits and measurement qubits are opposite to the first direction and the first direction. The method of claim 16, wherein the method is interleaved to include a second direction.   The method of claim 16, wherein the plurality of single qubit gates are phase shift gates or rotation gates.   The method of claim 16, wherein the data qubit is a control qubit and the neighboring measurement qubit is a target qubit for each CNOT gate.   The method of claim 16, wherein the data qubit is a target qubit and the neighboring measurement qubit is a control qubit for each CNOT gate. The step of optimizing the parameters of the readout quantum gate operating on the measurement qubits in parallel is an iterative process using closed loop feedback, each iteration in parallel, for each measurement qubit,
Defining a corresponding metric for minimization as a determined error rate;
Measuring the measurement qubit to determine a current error rate;
Storing the determined current error rate;
Calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
Adjusting the read gate parameter based on the calculated change in error rate;
The method of claim 15 comprising:   The method of claim 21, wherein adjusting the parameters of the single qubit gate based on the calculated change in error rate comprises applying a numerical optimization algorithm. The step of optimizing the parameters of the single qubit qugate operating with the measurement qubits in parallel is an iterative process using closed loop feedback, each iteration in parallel, for each measurement qubit,
Defining a corresponding metric for minimization as a determined error rate;
Measuring the measurement qubit to determine an error rate;
Storing the determined current error rate;
Calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
Adjusting parameters of the single qubit gate based on the calculated change in error rate;
The method of claim 15 comprising:   24. The method of claim 23, wherein adjusting the single qubit gate parameters based on the calculated change in error rate comprises applying a numerical optimization algorithm. The step of optimizing the parameters of the single qubit quantum gate operating on the data qubits in parallel is an iterative process using closed loop feedback, each iteration in parallel, for each data qubit,
Defining a corresponding metric for minimization as a determined error rate;
Measuring the corresponding measurement qubit to determine an error rate;
Storing the determined current error rate;
Calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
Adjusting parameters of the single qubit gate based on the calculated change in error rate;
The method of claim 15 comprising:   26. The method of claim 25, wherein adjusting the single qubit gate parameter based on the calculated change in error rate comprises applying a numerical optimization algorithm. Selecting a set of CNOT gates that define the same direction, and optimizing the parameters for the selected CNOT gates in parallel includes, for each set of CNOT gates selected:
In parallel, for each data qubit in the selected set,
Defining a corresponding metric for minimization as a determined error rate;
Measuring the corresponding measurement qubit to determine an error rate;
Storing the determined current error rate;
Calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
Adjusting the CNOT gate parameter based on the calculated change in error rate;
The method of claim 15 comprising:   27. The method of claim 26, wherein adjusting the parameters of the single qubit gate based on the calculated change in error rate comprises applying a numerical optimization algorithm.