JP2024026294A - In-situ quantum error correction - Google Patents

Abstract

To provide a method, a system and an apparatus for continuous and parallel optimization of quantum bit performance in-situ while an error correction operation on a quantum system is running.SOLUTION: A method for parallel optimization of continuously running quantum error correction by closed-loop feedback includes the steps of: continuously and effectively optimizing quantum bit performance in-situ while an error correction operation on a quantum system is running; directly monitoring output from error detection; providing the information as feedback to calibrate quantum gates associated with the quantum system; and spatially partitioning the physical quantum bit into one or more independent hardware patterns, the errors attributable to each hardware pattern being non-overlapping. The one or more different sets of hardware patterns are then temporarily interleaved such that all physical quantum bits and operations are optimized.SELECTED DRAWING: Figure 1A

Description

Optimization of physical gate parameters is required to build fault-tolerant quantum computers. Characterization methods such as randomized benchmarking or tomography require interruption of necessary error detection operations and do not guarantee optimal performance in error correction circuits. Optimizing physical gate parameters using error model optimization methods requires that an error model be trained such that measured physical errors can be linked to physical gates, and determined errors can be controlled • Requires changes in parameters to be linked back, increasing the complexity of the optimization process.

This specification relates to qubit performance in quantum computing.

This specification describes techniques for optimizing qubit performance in situ, sequentially and in parallel while error correction operations on a quantum system are performed.

In general, one inventive aspect of the subject matter described herein provides a plurality of data qubits and a plurality of measurements interleaving the data qubits such that each data qubit has a neighboring measurement qubit. a plurality of readout quantum gates, each single-qubit quantum gate configured to operate with either a data qubit or a measurement qubit; , a plurality of single-qubit quantum gates, each CNOT quantum gate configured to operate on a data qubit and a nearby measurement qubit, each CNOT gate defining one of a plurality of directions. accessing a quantum information storage system including a CNOT quantum gate; and dividing the data qubits and the measurement qubits into a plurality of patterns, wherein at least one pattern is subject to a non-overlapping error for the pattern; A non-overlapping error for is an error that can be attributed to the pattern, a step of optimizing parameters of a readout quantum gate operating on the measurement qubit in parallel for each pattern including the measurement qubit; optimizing in parallel the parameters of a single-qubit quantum gate operating on a qubit, and for each pattern including a data qubit operated by a CNOT gate and a measurement qubit, a single qubit operating on the data qubit; The method may include the following steps: optimizing parameters of the quantum gates in parallel; and selecting a set of CNOT gates defining the same direction and optimizing parameters for the selected CNOT gates in parallel. can.

Other implementations of the aspects include corresponding computer systems, apparatus, and computer programs stored on one or more computer storage devices, each configured to perform the actions of the methods. Configuring a system of one or more computers to perform a particular operation or action through software, firmware, hardware, or a combination thereof installed on the system that causes the system to perform the action. I can do it. One or more computer programs may be configured to perform particular operations or actions when executed by a data processing device by including instructions that cause the device to perform the actions.

Each of these and other implementations may optionally include one or more of the following features alone or in combination.

In some implementations, the plurality of data qubits and measurement qubits define a one-dimensional chain of qubits, and the plurality of directions define a first direction and a first direction. Interleaved to include a second direction opposite the first direction.

In other implementations, the plurality of single qubit gates are phase shift gates or rotation gates.

In some cases, the data qubit is the control qubit and the nearby measurement qubit is the target qubit for each CNOT gate.

In other cases, the data qubit is the target qubit and the nearby measurement qubit is the control qubit for each CNOT gate.

In some implementations, optimizing the parameters of readout quantum gates operating on the measurement qubit in parallel is an iterative process with closed-loop feedback, where each iteration defining a corresponding metric for the determined error rate as the determined error rate; measuring the measured qubit to determine the current error rate; and storing the determined current error rate. , calculating a change in error rate between the current error rate and the stored error rate from the previous iteration; and determining the read gate parameter based on the calculated change in error rate. and adjusting.

In some cases, adjusting the read gate parameters based on the defined metric for minimization includes applying a numerical optimization algorithm.

In some implementations, optimizing in parallel the parameters of a single-qubit quantum gate operating on the measurement qubit is an iterative process with closed-loop feedback, where each iteration is performed for each measurement qubit in parallel. , defining a corresponding metric for minimization as the determined error rate, measuring the measured qubit to determine the error rate, and storing the determined current error rate. , calculating a change in error rate between the current error rate and the stored error rate from the previous iteration; and calculating the change in error rate of the single-qubit gate based on the calculated change in error rate. and adjusting the parameters.

In some cases, adjusting the parameters of the single-qubit gate based on the defined metric for minimization includes applying a numerical optimization algorithm.

In some implementations, optimizing in parallel the parameters of a single-qubit quantum gate operating on the data qubit is an iterative process with closed-loop feedback, where each iteration is performed for each data qubit in parallel. , defining a corresponding metric for minimization as the determined error rate; measuring the corresponding measured qubit to determine the error rate; and storing the determined current error rate. calculating a change in error rate between the current error rate and the stored error rate from the previous iteration; and based on the calculated change in error rate, the single qubit. and adjusting parameters of the gate.

In some cases, adjusting the parameters of the single-qubit gate based on the defined metric for minimization includes applying a numerical optimization algorithm.

In other implementations, selecting a set of CNOT gates that define the same direction and optimizing parameters for the selected CNOT gates in parallel includes For each data qubit in the selected set, defining a corresponding metric for minimization as the determined error rate and measuring the corresponding measurement qubit to determine the error rate. and storing the determined current error rate; calculating a change in error rate between the current error rate and the stored error rate from the previous iteration; adjusting the CNOT gate parameter based on the calculated change in .

In some cases, adjusting the parameters of the single-qubit gate based on the defined metric for minimization includes applying a numerical optimization algorithm.

The subject matter described herein can be implemented to realize one or more of the following advantages. Parallel optimization of successive error correction runs by continuously and effectively optimizing physical gate parameters, and thus qubit performance, on the fly while error correction is running. The performance of the quantum computer implemented provides improved performance and reliability compared to quantum computers using other characterization methods that may require necessary error detection operations and interruption of other computations. I can do it. For example, a quantum computer that implements parallel optimization of continuous error correction runs can detect system drift, i.e., for each gate parameter per qubit, while the system is running without interrupting the computation. , drifts in the optimal parameters as a result of temperature-induced system hardware changes can be countered.

In many situations, detection events are the only information available that reflects system performance while error detection is running. Quantum computers implementing parallel optimization of continuous error correction execution require detection events, an important technique applicable to many different forms of error correction.

Furthermore, since the main challenge for error correction operations is knowing how otherwise characterized gates perform with error detection circuitry in multi-qubit systems, continuous error correction implementation Quantum computers implementing parallel optimization of quantization achieve improved performance in error correction circuits compared to other characterization methods. Although the qubits that store data are generally not measured during computation, they still require optimization, which can be achieved by parallel optimization of successive error correction runs.

A quantum computer that implements parallel optimization of continuous error correction runs may be model-free, e.g., the initial description may be model-free, eliminating the need for constructing an error model. To avoid. Quantum computers implementing parallel optimization of successive error correction runs can therefore avoid the need to collect statistics on various error types for use in training such error models. Often, the error model requires the physical system to be well below a threshold so that the individual first-order errors are sparse in order to collect sufficient statistics, and thus compared to other characterization methods. save time and required computational resources.

Furthermore, quantum computers of arbitrary size that implement parallel optimization of successive error correction runs require high levels of scalability, e.g., O(1), to optimize each gate within the quantum computer. can be realized.

The details of one or more implementations of the subject matter herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will be apparent from the detailed description, the accompanying drawings, and the appended claims.

1 is a one-dimensional schematic perspective view of an exemplary error correction system; FIG. FIG. 2 is a two-dimensional schematic perspective view of a qubit in an exemplary error correction system. 1 is a one-dimensional schematic perspective view of an exemplary hardware pattern in an error correction system including a one-dimensional array of qubits; FIG. 1 is a one-dimensional schematic perspective view of an exemplary hardware pattern in an error correction system including a one-dimensional array of qubits; FIG. 1 is a one-dimensional schematic perspective circuit representation of a qubit in an example error correction system. 1 is a two-dimensional schematic perspective view of an exemplary hardware pattern in an error correction system; FIG. 1 is a flowchart of an example process for error correction. 2 is a flowchart of an example process for optimizing single-qubit quantum gate parameters on a measurement qubit. 1 is a flowchart of an example process for optimizing single-qubit quantum gate parameters on data qubits. 2 is a flowchart of an example process for optimizing CNOT gate parameters.

Like reference numbers and designations in the various drawings indicate like elements.

This specification describes quantum systems and methods for continuously and effectively optimizing qubit performance in situ while error correction operations are performed on the quantum system. The method directly monitors the output from the error detection and provides this information as feedback for calibrating quantum gates associated with the quantum system. In some implementations, the physical qubit is spatially partitioned into one or more independent hardware patterns, i.e., configurations in which the errors attributable to each hardware pattern are non-overlapping. . The one or more different sets of hardware patterns are then temporally interleaved so that all physical qubits and operations are optimized. The method allows optimization of each section of the hardware pattern to be performed individually and in parallel, resulting in O(1) scaling.

Exemplary Operating Environment FIG. 1A is a one-dimensional schematic perspective view of an exemplary error correction system 100 for repeating codes. System 100 is a one-dimensional division of a two-dimensional surface code. The system includes a one-dimensional array of qubits 102. Although nine qubits are shown in FIG. 1A for clarity, the system may include a significantly larger number of qubits, eg, millions of qubits. The array of qubits includes data qubits, e.g., 104, 108, 112, 116, and 120, interleaved with measurement qubits, e.g., labeled measurement qubits, 106, 110, 114, and 118. Contains a data qubit labeled . In the case of bit flip error detection, the qubit may be a measurement Z-type qubit.

The system may include a set of readout quantum gates, eg, readout quantum gate 122. The readout gate may be configured to operate on measurement qubits, eg, measurement qubits 106, 110, 114 and 118. Each read gate may provide the state of a corresponding measured qubit and may be associated with a corresponding set of physical read gate parameters.

The system may include a set of single-qubit quantum gates, eg, single-qubit gates 132 and 134. The single-qubit quantum gate may be configured to operate with either a single data qubit or a single measurement qubit. Although the single qubit gates shown in FIG. 1A include a PauliX gate, e.g., PauliX gate 134, and a Hadamard gate, e.g., Hadamard gate 132, in some implementations the system may include other single qubit gates. good. For example, the single qubit gate may include any phase shift gate or rotation gate. Each single-qubit quantum gate may be associated with a corresponding set of physical single-qubit quantum gate parameters.

The system may include a set of controlled NOT (CNOT) gates, such as CNOT gate 124. A controlled gate may act on more than one qubit, and one or more of the qubits may act as a control for some operation. A CNOT gate may operate on two qubits, a control qubit and a target qubit, and performs a NOT operation on the target qubit only when the control qubit is 1>. The CNOT gate in FIG. 1A is configured to operate on neighboring measurement and data qubit pairs, with one qubit acting as the control qubit and the other target qubit, e.g. It operates on a pair of qubits 104 and 106. If error detection is designed to detect bit flip errors, each data qubit operated by the CNOT gate may be a control qubit, and each neighboring measurement qubit may be a corresponding target qubit. It may be. Each CNOT gate may be associated with a corresponding set of physical CNOT gate parameters.

A CNOT gate, e.g. 124, operating on a target qubit, e.g. May be defined. In the example repetition code, a CNOT quantum gate may copy a bit flip error from the associated data qubit to the associated measurement qubit for detection, as shown in FIG. 1A. In another example, if the error detection is designed to detect phase flip errors, the measurement qubit may be the control qubit and the neighboring data qubit may be the target qubit. Good too. The CNOT quantum gate may then copy the phase flip error from the associated measurement qubit to the associated data qubit.

The system may include an error correction subsystem 130 in data communication with the qubit 102. The error correction subsystem may be configured to monitor output from error detection and feed this information back to the system to calibrate the quantum gate. Error correction subsystem 130 may spatially partition qubit 102 into one or more hardware patterns and perform quantum measurements on the measured qubits in each hardware pattern. The one or more hardware patterns may be independent such that optimization of each hardware pattern relative to each other may be essentially independent. The step of dividing a qubit into one or more hardware patterns is explained in more detail below with reference to FIG. 2. A measurement output, or detection event, may indicate a change in the measured pattern of states for the measurement qubit, which indicates the presence of a nearby error, i.e., the error is caused by the associated data or measurement qubit. Indicates whether the occurrence occurred in Therefore, the measurement outputs therein and their measurement outputs may not be directly correlated to errors on the data or measurement qubits. The step of correlating errors and gating parameters is described in more detail below with reference to FIGS. 2A and 2B.

Error correction subsystem 130 may use the results of the performed quantum measurements to calculate a related quantity, or metric, of interest, such as a current error rate for each measured qubit. Error correction subsystem 130 also performs steps such as calculating an average value of the determined error rate for one or more measured measurement qubits, or determining a change in the error rate over time. Additional calculations may be performed using the results of the quantum measurements obtained. Error correction subsystem 130 may include a data store and may store the results of quantum measurements or additional calculations performed.

The error correction subsystem may use the results of the measurements performed to optimize the parameters of the quantum gate acting on the qubit 102. For example, error correction subsystem 130 may implement a numerical optimization algorithm, such as the Nelder-Mead algorithm, to determine appropriate adjustments to quantum gate parameters, e.g., minimizing a set of quantum gate parameters. Good too. Once the appropriate adjustment is determined, the error correction subsystem may provide the adjustment as feedback to the qubit 102 and adjust the parameters of the quantum gate accordingly.

FIG. 1B is a two-dimensional schematic perspective view of a qubit 150 in an exemplary error correction system. The system may include a two-dimensional array of qubits 150. Again, for clarity, 81 qubits are shown in FIG. 1B, but the system may include a significantly larger number of qubits, eg, millions of qubits. The array of qubits includes measurement qubits, e.g., 154, 156, 158, and It may include a data qubit, eg, a data qubit labeled 152, interleaved with a measurement qubit labeled 160. FIG. 1B illustrates the scalability of the system 100A of FIG. 1 to higher dimensions.

2A and 2B below illustrate example hardware patterns used to perform quantum gate optimization.

FIG. 2A is a one-dimensional schematic perspective view of an exemplary hardware pattern 200 in an error correction system that includes a one-dimensional array of qubits. For example, the error correction system may be an error correction system that includes a one-dimensional array of qubits 102, as described above with reference to FIG. corresponds to whether it is detected or not.

The hardware pattern 200 may include four hardware groupings 206, each of which includes a measurement qubit and a corresponding single-qubit operation for that qubit, e.g., the hardware grouping 202 includes a measurement qubit 204 and a corresponding single-qubit operation. includes a single qubit operation 208. Groupings within a hardware pattern may operate independently. Errors from a single qubit operation 208 do not have to propagate to neighboring data qubits, and the relative detection fraction from that measurement qubit can be used to calculate the error as described below with reference to FIG. Changes in gate parameters may be inferred.

Furthermore, if the error detection is designed to detect bit flip errors and each data qubit operated by the CNOT gate is a control qubit and each neighboring measurement qubit is the corresponding target qubit. , the bit flip error may not propagate to the data qubit due to the orientation of the CNOT gate applied to the data qubit and measurement qubit pair. Rather, bit flip errors may be localized to specific measurement qubits and thus specific hardware groupings.

For localization of gate errors, the measurement qubits may have single qubit quantum gate parameters that are individually optimized fully in parallel as one hardware pattern 200. Depending on the configuration, the hardware pattern into which the data and measurement qubits are divided may include one pattern that includes a hardware grouping that includes only measurement qubits.

FIG. 2B is a one-dimensional schematic perspective view of exemplary hardware patterns 210 and 220 in an error correction system that includes a one-dimensional array of qubits. For example, the error correction system may be an error correction system that includes a one-dimensional array of qubits 102, as described above with reference to FIG. corresponds to whether it is detected or not.

Hardware pattern 210 may include multiple hardware groupings, e.g., hardware grouping 212, each of which supports one data qubit along with corresponding single qubit operations for measurement and data qubits and CNOT gates. For example, as shown in FIG. 2B, hardware grouping 212 includes measurement qubit 214, single qubit operation 216, and CNOT gates 218 and 219. The groupings within the hardware pattern may operate independently. Errors from single qubit operations 216 and CNOT gates 218 and 219 do not have to propagate outside of hardware grouping 212, and measurements within each hardware grouping, as described below with reference to FIGS. The detected event fraction of qubits may be used to infer changes in gate parameters for gates within each grouping.

Furthermore, if the error detection is designed to detect bit flip errors and each data qubit operated by the CNOT gate is a control qubit and each neighboring measurement qubit is the corresponding target qubit. , unlike hardware pattern 200, the bit flip error may be copied from a data qubit to a nearby measurement qubit through a CNOT gate. Therefore, a single error on a data qubit may generate two detection events on nearby measurement qubits, optimizing CNOT gate parameters in parallel on the same measurement or data qubit. It may not be possible to do so. There may be natural limitations to the hardware pattern, eg, 210 and 220. In general, CNOT gates that are completely included in a hardware pattern may be optimized in that pattern.

If the next nearest data qubits simultaneously optimize their single qubit parameters, they may both copy the error to the same measurement qubit. Therefore, errors can be confusing. To avoid this problem, all other data qubits may be optimized to avoid double mapping errors to measurement qubits. Two hardware patterns 210 and 220 may be generated that can simultaneously optimize their single qubit parameters without such confusion, e.g., optimization of both patterns 210 and 220 relative to each other essentially It is independent. Depending on the configuration, the hardware pattern by which the data and measurement qubits are divided may include at least one pattern, and the corresponding hardware grouping includes both data and measurement qubits.

The hardware patterns 200, 210, and 220 shown in FIGS. 2A and 2B constitute the minimum number of hardware patterns that can be used to implement error correction in a one-dimensional error correction system such as that shown in FIG. 1A. do. The table below counts the number of patterns that can be interleaved to optimize all gates in parallel. There are three interleaved patterns, and one gate in each pattern may be optimized in parallel. This number is arbitrary in the ideal sense, i.e. assuming that the system is implemented in a state where the qubits do not have any parasitic interactions with qubits with which they should not interact. may be constant for an iteration code of size. The illustrated patterns are a minimal set of patterns; some implementations may add more as needed. By selecting such a hardware pattern for the system, the gate parameters within each hardware grouping in each hardware pattern can be adjusted to change the gate parameters and the measured error rate for each hardware grouping. It may be optimized by optimizing. Furthermore, by selecting a finite number of hardware patterns, each operation necessary to optimize a quantum computer that performs error detection can be accessed. Once the hardware pattern is chosen, all hardware groupings can be optimized in parallel and independently, which is O(1) scaling for optimizing every single gate in a quantum computer of arbitrary size. It's a strategy.

Although there are three separate patterns that require optimization, there are multiple operations within a pattern that can be independently optimized. The steps for optimizing gate parameters are explained in more detail below with reference to FIGS. 5-8.

The hardware patterns shown in the table above and described above with reference to FIGS. 2A and 2B are representative patterns and are not exhaustive. By tracking error propagation within a particular circuit, the exact pattern and respective groupings can be customized and determined for the system. For example, the hardware pattern does not need to be pre-computed by the system software. In some implementations, the hardware pattern may be determined by changing parameters on particular gates and observing where changes in detected events are found. By changing each of the parameters in each of the particular gates in such a manner, the information generated may be processed and used to determine the hardware pattern. Such methods of determining hardware patterns are sensitive to hardware non-ideality and can enhance system performance and efficiency.

FIG. 3 is a one-dimensional schematic perspective circuit representation of a qubit in an exemplary error correction system. In this simplified circuit representation, the output of measurement qubit 304 has three inputs: one for the associated measurement qubit 304 and one for each neighboring data qubit 302 and 306. The multiplexer 308 may also operate as a multiplexer 308 having one. Only one of the inputs to the multiplexer may be selected at a time to directly probe the output of one of the data or measurement boxes, eg, data boxes 302, 306 and measurement box 304. From this arises the three hardware patterns 200, 210 and 220 described above with reference to FIGS. 2A and 2B.

FIG. 4 is a two-dimensional schematic perspective view 400 of an exemplary hardware pattern in an error correction system. The same analysis described above with reference to FIGS. 2A and 2B may be applied to the surface code to generate the illustrated hardware pattern. The hardware pattern may include one hardware pattern 404 that includes measurement qubits. The remaining hardware patterns 406-412 may include both data and measurement qubits.

The hardware patterns 404-412 shown in FIG. 4 constitute the minimum number of hardware patterns that can be used to implement error correction for a system that includes a two-dimensional array of qubits. The table below counts the number of patterns that are interleaved to optimize all gates in parallel. There may be five interleaved patterns, one gate being optimized in each pattern. The patterns shown are representative and not a minimum set. Other patterns exist and may be more complex. The number and complexity of the patterns depends on the exact details of in what order the quantum gates are executed across the array. As described above, by selecting such a hardware pattern for the system, the gate parameters within each hardware grouping in each hardware pattern can be changed to The error rate may be optimized by optimizing the error rate. Moreover, by selecting a finite number of hardware patterns, each operation required to optimize a quantum computer that performs error detection can be accessed. Once the hardware pattern is chosen, all hardware groupings can be optimized independently and in parallel, which is O( 1) It is a scaling strategy.

Although there are five separate patterns that require optimization, there are multiple operations within a pattern that can be independently optimized. The steps for optimizing gate parameters are explained in more detail below with reference to FIGS. 5-8.

The hardware patterns shown in the table above and described above with reference to FIG. 4 are representative patterns and are not comprehensive. By tracking error propagation within a particular circuit, the exact pattern and respective groupings can be customized and determined for the system. For example, the hardware pattern need not be pre-calculated in the system's software. In some implementations, the hardware pattern may be determined by changing parameters on particular gates and observing where changes in detected events are found. By changing each of the parameters in each of the particular gates in such a manner, the information generated may be processed and used to determine the hardware pattern. Such methods of determining hardware patterns are sensitive to hardware non-ideality and can enhance system performance and efficiency.

Although the hardware pattern described herein is specific to one-dimensional chains of qubits executing repetitive codes, the technique can be generalized to most error correction frameworks. Any framework that detects errors using groups of qubits of a fixed maximum size and in which the number of groups to which any qubit belongs does not correspond to the system size can utilize the hardware and methods described herein. can do. For example, the technique may be compatible with all topology code, including subsystem code, and all connected code by focusing on the lowest level of connections. This includes surface and color codes, and Steane and Shor codes. The hardware and methods described herein may not be compatible with finite rate block codes if one wishes to preserve O(1) scaling in system size. Hardware patterns and groupings can be discovered algorithmically by simulating error detection circuits or by physically changing control parameters and determining where the detection fraction changes.

In particular, although Figures 2A and 2B, 3 and 4 have been described with respect to iterative and surface codes, the method for tracking error signatures from gates to physical measurements can be applied outside of the iterative and surface codes and can be applied to arbitrary It can be applied to quantum circuits and may be used as a method to provide feedback for optimization.

Performing In-Situ Quantum Error Correction FIG. 5 is a flowchart of an example process 500 for performing continuous optimization of quantum gate parameters while performing error correction. For example, process 500 may be performed during an error correction procedure by system 100 or 300 described above with reference to FIGS. 1A-1B and FIG. 3. Process 500 uses error detection to self-diagnose and allow continuous optimization of control parameters while the system is running, thus combating system drift without interrupting calculations.

The system spatially partitions the data and measurement qubit sets into separate hardware patterns (step 502). The system partitions the data and measurement qubit sets such that errors attributable to each separate hardware pattern do not overlap with errors attributable to other separate hardware patterns. do. Depending on the configuration, the hardware pattern may include one pattern with a grouping that includes measurement qubits and two or more patterns that have groupings that include both data qubits and measurement qubits. The arrangement of dividing the data and measurement qubit sets into separate hardware patterns is described in more detail above with reference to FIGS. 2A and 2B and FIG. 4.

The system enters a step to optimize parameters of quantum gates operating on the qubits in each hardware pattern having a grouping that includes the measured qubits (step 504). By configuration, each of the measurement qubits in the set of data qubits and measurement qubits may form one of the hardware patterns constructed in step 502. For example, in one dimension, the system may optimize the parameters of a quantum gate operating on a measured qubit in the hardware pattern 200 described above with reference to FIG. 2A. In another example, in two dimensions, the system may optimize the parameters of quantum gates operating on measured qubits in hardware pattern 404, described above with reference to FIG.

The step of optimizing the parameters of the quantum gate operating on the measured qubit may be considered the simplest optimization step. For example, when considering implementing error correction on a repeating code, the measurement qubit may detect a bit flip error. Due to the orientation of the CNOT gate applied to the pair of measurement and data qubits, the bit flip error does not propagate from the measurement qubit to the data qubit, so the error is localized to the particular measurement qubit. Ru. The measurement qubits are therefore single-qubit quantum gates operating on them that are individually optimized fully in parallel as one hardware pattern, as described below with reference to steps 506 and 508. It may have the following parameters.

The system performs optimization of the parameters of the readout gate operating on the measured qubit (step 506). Optimization of the parameters of the readout gate operating on the measurement qubit may be performed in parallel for each measurement qubit in the hardware pattern. An exemplary process for optimizing the parameters of the read gate operating on the measurement qubit is described in detail below with reference to FIG. 6.

The system performs parameter optimization of a single-qubit quantum gate operating on the measured qubit (step 508). Optimization of the parameters of the single-qubit quantum gate operating on the measurement qubit may be performed in parallel for each measurement qubit in the hardware pattern. An exemplary process for optimizing the parameters of a single-qubit quantum gate operating with the measured qubit is described in detail below with reference to FIG. 6.

The system enters a step to optimize parameters of quantum gates operating on qubits in each hardware pattern having groupings that include both data qubits and measurement qubits (step 510). By configuration, in each hardware pattern that has groupings that include both data and measurement qubits, the data qubits may be accompanied by measurement qubits in their respective hardware groupings constructed in step 502. . For example, in one dimension, the system may optimize the parameters of a single-qubit quantum gate operating on data qubits in hardware patterns 210 and 220 described above with reference to FIG. 2B. In another example, in two dimensions, the system optimizes the parameters of single-qubit quantum gates operating on data qubits in hardware patterns 406, 408, 410, and 412, described above with reference to FIG. It's okay.

Performing parameter optimization for a single-qubit quantum gate operating on the data qubit is more complex than performing parameter optimization for the single-qubit quantum gate operating on the measurement qubit. Good too. For example, when considering implementing error correction on a repeating code, bit flip errors are transferred from a data qubit to a neighboring measurement qubit through a CNOT gate operating on both the data qubit and the measurement qubit. May be copied. Thus, a single error on a data qubit may generate an output, or detection event, on each of its neighboring measurement qubits, as described above with reference to FIGS. 2A and 2B. Data qubits are therefore Therefore, it is not necessary to have the parameters of single-qubit quantum gates operating on them individually fully parallel optimized as one hardware pattern. Instead, all other data qubits are optimized in parallel as one hardware pattern, as described below with reference to step 512 and FIG. Mapping may be avoided.

The system performs parameter optimization for a single qubit gate operating on a data qubit in each hardware pattern that has a grouping that includes both a data qubit and a measurement qubit (step 512). Optimization of the parameters of a single-qubit quantum gate operating on data qubits in each hardware pattern may be performed separately for each hardware pattern. However, optimization of the parameters of single-qubit quantum gates operating on data qubits in each grouping within each hardware pattern may be performed in parallel for each data qubit within that hardware pattern. An exemplary process for optimizing the parameters of a single-qubit quantum gate operating on data qubits is described in detail below with reference to FIG. 7.

Implementing parameter optimization for a CNOT gate operating on data and measurement qubit pairs can also be complex due to error confounds. Errors on the data qubits may propagate to the measurement qubits on each side of the data qubits involved. Thus, an error on a data qubit may generate an output, or detection event, in each of its neighboring measured qubits, as described above with reference to FIG. 2B. The parameters of a CNOT gate operating on data and measurement qubit pairs therefore do not have to be optimized in parallel on the same data or measurement qubit. This naturally limits the hardware pattern to, for example, the same as described above with reference to step 510. To avoid error confusion, there may be a simple rule: only CNOT gates that are completely included in a hardware pattern may be optimized in that pattern.

The system performs parameter optimization of CNOT gates operating on pairs of data and measurement qubits in each hardware grouping that includes both data and measurement qubits in the hardware pattern. 514). Optimization of the parameters of a CNOT gate operating on a pair of data and measurement qubits in that hardware pattern may be performed separately for each hardware pattern. Additionally, the system selects CNOT gates that define the same direction in the hardware pattern and sets the parameters of the CNOT gates that define the same direction in parallel for each data qubit in the hardware pattern. Optimize. For example, in one dimension, for each hardware pattern that includes a data qubit and a measurement qubit, the system first optimizes the selected CNOT gate parameters to the left of the data qubit in parallel. A set of CNOT gates to the right of the data qubit may be selected to optimize the selected CNOT gate parameters in parallel. An exemplary process for optimizing the parameters of a CNOT gate operating on data and measurement qubits is described in detail below with reference to FIG. 8.

For clarity, a flowchart of an exemplary process 500 for performing continuous optimization of quantum gate parameters while performing error correction is described with reference to steps 504-514. However, it may not be necessary for the acts of steps 504-514 to be performed sequentially in the order presented. The steps may be performed in different sequences or multiple times. That is, if necessary, before the next step in the sequence is performed, e.g., in some implementations, the system performs a Before proceeding to the step of optimizing the gate parameters, we first set out the steps for optimizing the parameters of the quantum gate operating on the qubits in each hardware pattern, including both data qubits and measurement qubits. You can go through stages. Similarly, once the system enters the stage for optimizing the parameters of the quantum gates operating on the qubits in each hardware pattern, including, for example, the measurement qubits, the system An optimization step 508 may be performed first. By cycling between steps 506, 508, 512 and 514, i.e. by cycling between hardware patterns, all gates for all qubits are The system drift in the parameters may be counteracted.

FIG. 6 is a flowchart of an example process 600 for optimizing parameters of a readout gate or single-qubit quantum gate operating on a measured qubit. The process 600 may be performed to optimize the parameters of a readout quantum gate as described above in step 506 of FIG. 5 or to optimize the parameters of a single-qubit quantum gate as described above in step 508 of FIG. , may be implemented by the system 100 or 300 described above with reference to FIGS. 1A-1B and FIG. By construction, each of the measurement qubits in the collection of data and measurement qubits described in FIGS. 1A-1B and FIG. form one of them. For example, in one dimension, the system may optimize the parameters of a readout quantum gate or a single-qubit quantum gate operating on a measured qubit in the hardware pattern 202 described above with reference to FIG. 2A. In another example, in two dimensions, the system may optimize the parameters of quantum gates operating on measured qubits in hardware pattern 404, described above with reference to FIG.

Process 600 may be performed in parallel for each measured qubit in the corresponding hardware pattern. Process 600 may continuously iterate the process of optimizing parameters of a readout gate or single-qubit quantum gate operating on a measured qubit using closed-loop feedback.

In parallel, for each measured qubit, the system defines a corresponding metric for error minimization as the determined error rate (step 602). The quantum gate error may be minimized by minimizing the error rate of each qubit, also called the fraction of detected events. In the case of a hardware pattern that includes a single measurement qubit, the metric for error minimization may be the fraction of detected events for that qubit. In the case of hardware patterns containing multiple measurement qubits, such as those shown in Figures 2A and 4, the metric for error minimization is the average fraction of detection events taken for all measurement qubits. .

In parallel, for each measured qubit, the system measures the measured qubit to determine the current error rate (step 604).

The system stores the determined error rate (step 606). The system stores the determined error rate for each iteration of process 600 so that changes in error rate can be monitored over time and correlated with changes made to the quantum gate parameters.

The system calculates the change in error rate between the determined current error rate and the stored error rate from previous iterations (step 608). Measurement outputs, or detection events, and changes in the measured pattern of states for the measurement qubits, whether on the data qubits or the measurement qubits, may indicate the presence of nearby errors. However, the detection event itself may not directly correlate to errors on the measurement or data qubits. Therefore, in order to correlate the change in error with the change in the gating parameter, the change in the localized detected event fraction, ie, the error rate, may be compared to the change in the gating parameter.

In parallel, for each measured qubit, the system adjusts readout gate parameters, or single-qubit quantum gate parameters, based on the calculated change in error rate (step 610). The system applies a numerical optimization algorithm, such as the Nelder-Mead method, to the readout gate parameters or single-qubit quantum gate parameters based on the change in error rate calculated in step 608. may decide to adjust.

The system may continuously repeat steps 602-610 described above. In principle, it may be possible to distinguish the qubits of measurement X and measurement Y in order to obtain more information about the physical process associated with the gate error, and to transfer this information may be fed back to the system to optimize it more efficiently.

FIG. 7 is a flowchart of an example process 700 for optimizing parameters of a single-qubit quantum gate operating on data qubits. Process 700 is performed by system 100 or 300 described above with reference to FIGS. 1A-1B and FIG. 3 for optimizing the parameters of the single-qubit quantum gate as described above in step 512 of FIG. Good too. The process may be performed for each hardware pattern that has groupings that include both data and measurement qubits as constructed in step 502 with reference to FIG. 5 above. For example, in one dimension, the system may optimize the parameters of a single-qubit quantum gate operating on data qubits in hardware patterns 210 and 220 described above with reference to FIG. 2B. In another example, in two dimensions, the system may optimize the parameters of quantum gates operating on the measured qubits in hardware patterns 406, 408, 410, and 412 described above with reference to FIG.

Process 700 may be performed in parallel for each data qubit in a corresponding hardware pattern. Process 700 may be a continuously iterated process that uses closed-loop feedback to optimize the parameters of a single-qubit quantum gate operating on the data qubit.

In parallel, for each data qubit, the system defines a corresponding metric for error minimization as the determined error rate (step 702). Quantum gate errors may be minimized by minimizing the error rate of each qubit, also called the fraction of detected events. In this case of hardware patterns with groupings containing multiple measured qubits, such as those shown in Figures 2B and 4, the metric for error minimization is the average of the detection events taken over all measured qubits. It may also be a fraction.

In parallel, for each data qubit, the system measures its corresponding neighboring measurement qubits to determine the current error rate (step 704). For example, in a one-dimensional system, the system may measure at least two corresponding measurement qubits. For example, in a two-dimensional system, the system may measure at least four corresponding measurement qubits.

The system stores the determined error rate (step 706). The system monitors changes in the error rate over time and stores the determined error rate for each iteration of the process 700 so that it can be correlated with changes made to the quantum gate parameters.

The system calculates the change in error rate between the determined current error rate and the stored error rate from previous iterations (step 708). Measurement outputs, or detection events, and changes in the measured pattern of states for the measurement qubits, whether on the data qubits or the measurement qubits, may indicate the presence of nearby errors. However, the detection event itself may not directly correlate to errors on the measurement or data qubits. Therefore, in order to correlate the change in error with the change in the gating parameter, the change in the localized detected event fraction, ie, the error rate, may be compared to the change in the gating parameter.

In parallel, for each data qubit, the system adjusts the parameters of the single qubit gate based on the calculated change in error rate (step 710). The system applies a numerical optimization algorithm, such as the Nelder-Mead method, to determine adjustments to be made to the single-qubit quantum gate parameters based on the change in error rate calculated in step 708. It's okay.

The system may continuously repeat steps 702-710 described above. In principle, it may be possible to distinguish between the qubits of measurement X and measurement Y in order to obtain more information about the physical process associated with the gate error in question, and this information Feedback may be provided to the system to optimize quantum gates more efficiently.

FIG. 8 is a flowchart of an example process 800 for optimizing the parameters of a CNOT gate operating on data and measurement qubit pairs. Process 800 may be performed by system 100 or 300 described above with reference to FIGS. 1A-1B and FIG. 3 for optimizing parameters of a CNOT gate as described above in step 514 of FIG. The process may be performed for each hardware pattern that has groupings that include both data and measurement qubits constructed in step 502 with reference to FIG. 5 above. For example, in one dimension, the system may optimize the parameters of a CNOT gate operating on data and measurement qubit pairs in hardware patterns 210 and 220 described above with reference to FIG. 2B. In another example, in two dimensions, the system may optimize the parameters of quantum gates operating on measured qubits in hardware patterns 406-412 described above with reference to FIG.

Process 800 may be performed in parallel for each CNOT gate that is completely included in a corresponding hardware pattern that defines the same direction with respect to the data qubits on which that CNOT gate operates. Process 800 may be a continuously iterated process that uses closed-loop feedback to optimize the parameters of the CNOT gate.

In parallel, for each data qubit, the system defines a corresponding metric for error minimization as the determined error rate (step 802). Quantum gate errors may be minimized by minimizing the error rate of each qubit, also called the fraction of detected events. In this case of hardware patterns with groupings containing multiple measurement qubits, such as those shown in these Figures 2B and 4, the metric for error minimization is taken for all measurement qubits. It may also be an average fraction of detected events.

In parallel, for each data qubit, the system measures the corresponding neighboring measurement qubits to determine the current error rate (step 804). For example, in a one-dimensional system, the system may measure at least two corresponding measurement qubits. For example, in a two-dimensional system, the system may measure at least four corresponding measurement qubits.

The system stores the determined error rate (step 806). The system stores the determined error rate for each iteration of process 800 so that changes in the error rate can be monitored over time and correlated with changes made to the quantum gate parameters.

The system calculates the change in error rate between the determined current error rate and the stored error rate from previous iterations (step 808). Measurement outputs, or detection events, and changes in the measured pattern of states for the measurement qubits, whether on the data qubits or the measurement qubits, may indicate the presence of nearby errors. However, the detection event itself may not directly correlate to errors on the measurement or data qubits. Therefore, in order to correlate the change in error with the change in the gating parameter, the change in the localized detected event fraction, ie, the error rate, may be compared to the change in the gating parameter.

In parallel, for each data qubit, the system adjusts the CNOT gate parameters based on the calculated change in error rate (step 810). The system may apply a numerical optimization algorithm, such as the Nelder-Mead method, to determine adjustments to be made to the CNOT quantum gate parameters based on the change in error rate calculated in step 808. .

The system may continuously repeat steps 802-810 described above. In principle, it may be possible to distinguish between the qubits of measurements may be fed back to the system to optimize it more efficiently.

The digital and/or quantum subject matter and operations of digital functions and implementations of quantum operations described herein are tangibly embodied in a digital electronic circuit, a suitable quantum circuit or, more generally, a quantum computing system. digital and/or quantum computer software or firmware that includes the structures disclosed herein, and structural equivalents thereof, or one or more of the following: Can be implemented in multiple combinations. The term "quantum computing system" may include, but is not limited to, a quantum computer, quantum information processing system, quantum cryptography system, or quantum simulator.

Implementations of the digital and/or quantum subject matter described herein may be implemented by one or more digital and/or quantum computer programs; It may be implemented as one or more modules of digital and/or quantum computer program instructions encoded on a temporary storage medium. The digital and/or quantum computer storage medium is a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits, or a combination of one or more thereof. I can do it. Alternatively or additionally, transmitting the program instructions to a suitable receiver device for execution by an artificially generated propagation signal capable of encoding digital and/or quantum information, e.g. a digital and/or quantum data processing device. can be encoded with machine-generated electrical, optical, or electromagnetic signals generated to encode information for.

The terms quantum information and quantum data refer to information or data carried by, carried by, or stored in a quantum system, the least non-trivial system of which is a qubit, a system that defines a unit of quantum information. It is understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as two-level systems in the corresponding context. Such quantum systems may include, for example, multi-level systems having two or more levels. By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits. In many implementations, the computational elementary state is identified as a ground state and a first excited state, although other configurations are possible in which the computational state is identified as a higher level excited state. is understood. The term "data processing equipment" refers to digital and/or quantum data processing hardware, including, for example, a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, multiple digital and quantum processors or computers, and It encompasses all types of apparatus, devices and machines for processing digital and/or quantum data for processing, including combinations. The apparatus may further include special purpose logic circuits, such as FPGAs (Field Programmable Gate Arrays), ASICs (Special Application Integrated Circuits), or quantum The simulator may be or include a quantum data processing device. In particular, a quantum simulator is a special purpose quantum computer that does not have the capability to perform universal quantum computations. The device optionally constitutes, in addition to hardware, digital and/or quantum computer programs, such as processor firmware, protocol stacks, database management systems, operating systems, or one or more combinations thereof. Can contain code that generates an execution environment for the code.

A digital computer program may also be referred to or described as a program, software, software application, module, software module, script, or code, including compiled or interpreted languages, or declarative or procedural languages. It may be written in any form of programming language and may be deployed in any form, including stand-alone programs or modules, components, subroutines, or other units suitable for use in a digital computing environment. A quantum computer program may also be referred to or described as a program, software, software application, module, software module, script, or code, including a compiled or interpreted language, or a declarative or procedural language. It can be written in any form of programming language, can be translated into a suitable quantum programming language, or can be written in a quantum programming language, for example QCL or Quipper.

Digital and/or quantum computer programs may, but need not, correspond to files within a file system. A program can be a part of another program or a file that holds data, for example a markup language document, in a single file dedicated to the program in question, or in one or more cooperating files. Multiple scripts may be stored in a file, subprogram, or portion of code that stores one or more modules, for example. a digital and/or quantum computer program on one digital or one quantum computer located at one site or distributed across multiple sites interconnected by a digital and/or quantum data communication network; It can be deployed to run on multiple digital and/or quantum computers. A quantum data communication network is understood to be a network in which quantum systems, for example quantum bits, can be used to transmit quantum data. Although digital data communication networks generally cannot transmit quantum data, quantum data communication networks can transmit both quantum and digital data.

The processes and logic flows described herein may be implemented by operating on one or more digital and/or quantum processors and optionally executing one or more digital and/or quantum computer programs to implement the processes and logic flows described herein. and one or more programmable digital and/or quantum computers that perform the functions by operating on quantum data and generating output. The processes and logic flows may also be implemented by special purpose logic circuits, such as FPGAs or ASICs, or by quantum simulators, or by a combination of special purpose logic circuits or quantum simulators and one or more programmed digital and/or quantum computers. can be implemented and the device can be implemented as such.

One or more digital and/or quantum computer systems being "configured to" perform a particular operation or action means that the system, in operation, is configured to include software that causes the system to perform the operation or action; Refers to installing firmware, hardware, or a combination thereof. Configuring one or more digital and/or quantum computer programs to perform a particular operation or action means that the one or more programs are executed by a digital and/or quantum data processing device. In this case, it means to include an instruction for causing the device to perform the operation or action. A quantum computer may receive instructions from a digital computer that, when executed by the quantum computing device, cause the device to perform the operations or actions.

A digital and/or quantum computer suitable for the execution of a digital and/or quantum computer program can be a general purpose or special purpose digital and/or quantum processor, or any other kind of central digital and/or quantum processing unit. can be based on. Typically, a central digital and/or quantum processing unit receives instructions and digital and/or or receive quantum data.

The essential elements of a digital and/or quantum computer are a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and digital and/or quantum data. The central processing unit and the memory may be supplemented by special purpose logic circuitry or incorporated into the circuitry or quantum simulator. Generally, a digital and/or quantum computer also includes one or more mass storage devices, e.g. It may include or be operably connected to magneto-optical disks, optical disks. However, digital and/or quantum computers do not need to have such devices.

Digital and/or quantum computer readable media suitable for storing digital and/or quantum computer program instructions and digital and/or quantum data include, by way of example, semiconductor memory devices, such as EPROMs, EEPROMs, and flash memory devices; All forms of non-volatile digital and and/or quantum memories, media and memory devices. Quantum memory is a device in which quantum data can be stored for long periods of time with high fidelity and efficiency, e.g. optical materials (where light is used for transmission and matter memorizes and preserves quantum features of quantum data, such as superposition or quantum coherence). light-matter) interface.

Control of the various systems or portions thereof described herein is stored in one or more non-transitory machine-readable storage media and executable by one or more digital and/or quantum processing devices. It can be implemented in a digital and/or quantum computer program product containing instructions. The systems described herein, or portions thereof, each include one or more digital and/or quantum processing devices and memory storing executable instructions for implementing the operations described herein. It can be implemented as an apparatus, method, or system that can include.

Although this specification contains numerous specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. be. Certain features that are described herein in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Furthermore, although features may be described above and originally claimed as operating in a particular combination, one or more features from the claimed combination may in some cases be implemented from that combination. The claimed combinations may relate to subcombinations or variations of subcombinations.

Similarly, although acts are illustrated in a particular order in the drawings, this does not imply that such acts may be performed in the particular order shown or in a sequential order to achieve a desired result. shall not be understood as requiring that the actions indicated be performed. Multitasking and parallel processing may be advantageous in certain environments. Furthermore, the separation of various system modules and components in the implementations described above is not to be understood as requiring such separation in all implementations, but rather the integration of the program components and systems described into a single software product in general. It should be understood that the software may be packaged into multiple software products.

Described a specific implementation of the subject. Other implementations are within the scope of the following claims. For example, the acts recited in the claims can be performed in a different order and still achieve the desired results. By way of example, the processes illustrated in the accompanying drawings do not necessarily require the particular order shown, or sequential order, to achieve desired results. In some cases, multitasking and parallel processing may be advantageous.

130 Error Correction Subsystem

Claims (12)

A quantum computing system,
A quantum computing system comprising an error correction subsystem in data communication with a measurement qubit, the error correction subsystem configured to receive error detection information and perform corresponding error correction on the qubit. and based on the error detection information, in parallel with the error correction,
dividing the data qubits and the measurement qubits into a plurality of patterns, at least one pattern being subject to errors with respect to said pattern, and each error with respect to said at least one pattern being an error localized to said pattern; , the pattern includes a pattern including measurement qubits or a pattern including data qubits and measurement qubits operated by a CNOT gate;
For each pattern containing the measurement qubit,
optimizing in parallel parameters of a readout quantum gate operating on the measurement qubit;
optimizing in parallel parameters of a plurality of single-qubit quantum gates operating on the measured qubit. multiple data qubits,
a plurality of measurement qubits interleaving the data qubits such that each data qubit has one or more neighboring measurement qubits;
a plurality of readout quantum gates, each readout quantum gate configured to operate on a measurement qubit;
a plurality of single-qubit quantum gates, each single-qubit quantum gate configured to operate on a data qubit or a measurement qubit;
a plurality of CNOT quantum gates, each CNOT quantum gate configured to operate with a data qubit and a neighboring measurement qubit, each CNOT gate defining one of a plurality of directions;
The system of claim 1, further comprising: The plurality of data qubits and measurement qubits define a one-dimensional chain of qubits, the plurality of directions being a first direction and opposite to the first direction. 3. The system of claim 2, wherein the system is interleaved to include a second direction of . 3. The system of claim 2, wherein the plurality of single qubit gates are phase shift gates or rotation gates. In order to optimize in parallel the parameters of readout quantum gates operating on the measurement qubits, the error correction subsystem is configured to perform an iterative process with closed-loop feedback, in each iteration the error correction The subsystem is
defining a corresponding metric for minimization as the determined error rate;
measuring the measured qubit to determine a current error rate;
storing the determined current error rate;
calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
The system of claim 1, configured to: adjust the read gate parameter based on the calculated change in error rate. 6. The system of claim 5, wherein the error correction subsystem is configured to apply a numerical optimization algorithm to adjust the read gate parameters based on the calculated change in error rate. In order to optimize in parallel the parameters of a single-qubit quantum gate operating on the measurement qubit, the error correction subsystem is configured to perform an iterative process with closed-loop feedback, in each iteration the The error correction subsystem, in parallel, for each measured qubit,
defining a corresponding metric for minimization as the determined error rate;
measuring the measured qubit to determine an error rate;
storing the determined current error rate;
calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
and adjusting parameters of the single qubit gate based on the calculated change in error rate;
1 . The error correction subsystem is preferably configured to apply a numerical optimization algorithm to adjust parameters of the single qubit gate based on the calculated change in error rate. system described in. A method for quantum computing, the method being implemented by a quantum information storage system, the quantum information storage system comprising:
multiple data qubits,
a plurality of measurement qubits interleaving the data qubits such that each data qubit has a neighboring measurement qubit;
a plurality of readout quantum gates, each readout quantum gate configured to operate on a measurement qubit;
a plurality of single-qubit quantum gates, each single-qubit quantum gate configured to operate with a data qubit or a measurement qubit;
The method includes:
(i) dividing the data qubits and the measurement qubits into a plurality of patterns, at least one pattern being subject to non-overlapping errors to said pattern, and the non-overlapping errors to said patterns being attributable errors to said pattern; There are steps and
(ii) receiving error detection information;
(iii) performing error correction on the quantum bit, corresponding to the error detection information;
(iv) based on the error detection information, in parallel with the error correction, for each pattern containing the measured qubits;
optimizing in parallel parameters of a readout quantum gate operating on the measurement qubit;
optimizing in parallel parameters of the plurality of single-qubit quantum gates operating on the measured qubit. The plurality of data qubits and measurement qubits define a one-dimensional chain of qubits, the plurality of directions being a first direction and opposite to the first direction. 9. The method of claim 8, wherein the method is interleaved to include a second direction of . 9. The method of claim 8, wherein the plurality of single qubit gates are phase shift gates or rotation gates. The step of optimizing in parallel the parameters of the readout quantum gate operating on the measurement qubit is an iterative process with closed-loop feedback, where each iteration consists of, in parallel, for each measurement qubit:
defining a corresponding metric for minimization as the determined error rate;
measuring the measured qubits to determine a current error rate;
storing the determined current error rate;
calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
adjusting the read gate parameters based on the calculated change in error rate;
including;
9. The method of claim 8, wherein adjusting the parameters of the single qubit gate based on the calculated change in error rate preferably comprises applying a numerical optimization algorithm. Optimizing in parallel a single-qubit quantum gate operating on the measurement qubit is an iterative process with closed-loop feedback, where each iteration consists of, in parallel, for each measurement qubit:
defining a corresponding metric for minimization as the determined error rate;
measuring the measured qubit to determine an error rate;
storing the determined current error rate;
calculating a change in the error rate between the current error rate and the stored error rate from a previous iteration;
adjusting parameters of the single qubit gate based on the calculated change in error rate;
including;
9. The method of claim 8, wherein adjusting the parameters of the single qubit gate based on the calculated change in error rate preferably comprises applying a numerical optimization algorithm.