JP2019216507A - Control device for multistage converter - Google Patents

Abstract

To achieve single-pulse drive capable of suppressing generation of a high harmonic wave and reducing voltage distortion.SOLUTION: A control device for a multistage converter according to an embodiment comprises: a modulation rate calculation unit 21 that calculates a modulation rate of a multistage converter 1; a phase shift amount generation unit 22 that generates a phase shift amount of a gate signal that drives an upper arm S1 of a positive leg LP and an upper arm S3 of a negative leg LN of each unit converter 11-14 for a number of stages of the unit converters 11-14, wherein the phase shift amount corresponds to the modulation rate; and gate signal generation unit 23 that generates first gate signals of the number of stages and a second gate signal in each of which an on-pulse width and an off-pulse width are the same as each other, wherein each first gate signal has a center of the on-pulse width that is progressed from a phase of an output voltage command by the phase shift amount, and the second gate signal has a center of the off-pulse width that is delayed from the phase of the output voltage command by the phase shift amount, and that assigns the first gate signals to the upper arms S1 of the positive legs LP of the unit converters 11-14, and assigns the second gate signal to the upper arms S3 of the negative legs LN of the unit converters 11-14.SELECTED DRAWING: Figure 1

Description

  Embodiments of the present invention relate to a control device for a multi-stage converter.

  As a large-capacity method of a semiconductor power converter represented by an inverter, there is a method of connecting a plurality of power converter outputs in series to obtain a high voltage. This is called a multi-stage converter or MMC (Modular Multilevel Converter), and is mainly applied to a large-capacity converter such as a grid connection converter or a motor driving converter.

  The multi-stage converter has a feature that a plurality of levels of voltage output can be obtained by a circuit configuration in which the outputs of unit converters each having a DC power supply such as a capacitor and a rectifier are connected in multiple series. From such characteristics, a voltage output in a plurality of steps can be obtained, and an output close to a sine wave can be directly obtained. Since the number of steps increases as the number of converter stages increases, when the number of converter stages is large, the output is low in distortion by one-pulse driving in which each switching element is driven at the output voltage fundamental frequency without high-speed switching such as PWM. Voltage is obtained. In the one-pulse driving, the switching frequency can be suppressed as compared with the PWM, so that the switching loss generated at every switching can be reduced, and the effect of reducing the converter loss and the cooling device can be expected.

  To operate the multi-stage converter, it is possible to operate the unit power converter by performing PWM modulation by triangular wave carrier comparison etc. in the same way as a single converter, but when performing one-pulse modulation, it operates by the conventional carrier comparison It is difficult to do. Therefore, Non-Patent Document 1 proposes a one-pulse modulation method of a multi-serial converter using an H bridge as a unit converter.

  In this method, the output voltage command of the multi-stage converter is compared with a threshold value having the same number of voltage steps as the number of converter stages in the positive and negative directions, and each converter is switched at the point where the command and the threshold value intersect. This is a method for achieving modulation. One pulse control can be easily implemented because of the simple configuration for comparing the command and the threshold.

Hiroshi Koyama, Ryuta Hasegawa, Takuro Arai "One-pulse control of delta-connection modular multi-level STATCOM", IEICE D, Vol. 137 No. 3 pp. 246-255 (2017)

  However, since the number of converter stages that output a voltage changes according to the magnitude of the output voltage command, when the output voltage is low, the number of converter stages that output the voltage decreases, and the converter utilization decreases. In addition, since a converter that does not output a voltage is in a bypass state without performing switching, in a region where the output voltage is small, low-order harmonics increase with a decrease in the number of output stages, and voltage distortion may increase.

  An embodiment of the present invention has been made in view of the above circumstances, and provides a control device for a multi-stage converter capable of implementing one-pulse drive that suppresses generation of harmonics and reduces voltage distortion.

  The control device for a multi-stage converter according to the embodiment controls a multi-stage converter in which a plurality of unit converters each including a DC power supply and a positive leg and a negative leg connected in parallel with the DC power supply are connected in series. A control device, an output voltage command of the multi-stage converter, a modulation rate calculating unit that calculates a modulation rate using the voltage of the DC power supply, based on the modulation rate, a plurality of the unit converter, A phase shift amount generation unit that generates a phase shift amount of a gate signal that drives the upper arm of the positive leg and the upper arm of the negative leg, and a signal that drives a plurality of the unit converters at an output voltage fundamental frequency. The on-pulse width and the off-pulse width are the same, the center of the on-pulse width is the first gate signal advanced by the phase shift amount with respect to the phase of the output voltage command, and the center of the off-pulse width is the output voltage command. Generating a second gate signal delayed by the phase shift amount with respect to a phase, wherein the first gate signal is the gate signal of the upper arm of the positive leg of the plurality of unit converters, and the second gate signal And a gate signal generation unit that sets the gate signal of the upper arm of the negative leg of the plurality of unit converters, wherein the phase shift amount is greater than zero and less than 180 °.

FIG. 1 is a diagram schematically showing a control device of the multistage converter according to the first embodiment. FIG. 2 is a diagram illustrating an example of a relationship between a modulation factor and a phase shift amount. FIG. 3 is a diagram illustrating an example of the gate signal of the upper arm and the output voltage of the multi-stage converter when the modulation factor is 1 and when the modulation factor is 0.2. FIG. 4 is a diagram showing another example of the gate signal of the upper arm and the output voltage of the multi-stage converter when the modulation factor is 1 and when the modulation factor is 0.2. FIG. 5 is a diagram schematically illustrating a control device of the multistage converter according to the second embodiment. FIG. 6 is a diagram illustrating an example of the gate signal output from the control device, the output voltage of each unit converter, and the output voltage and output current of the multi-stage converter. 7, the positive leg on the arm is driven by a gate signal obtained by shifting the alpha _P phase, an example of a unit converter output voltage when driven by a gate signal obtained by shifting the alpha _N phase negative leg on the arm FIG. FIG. 8 is a diagram illustrating an example of the unit converter output voltage and the estimated fundamental wave component. FIG. 9 is a diagram illustrating an example of the unit converter output voltage and the estimated fundamental wave component. FIG. 10 is a flowchart illustrating an example of the operation of the voltage adjustment unit of the control device illustrated in FIG. FIG. 11 is a diagram for explaining an example of the operation of the control device of the multistage converter according to the third embodiment. FIG. 12 is a diagram for explaining an example of the operation of the control device for a multi-stage converter according to the third embodiment. FIG. 13 is a diagram for explaining an example of the operation of the control device of the multistage converter according to the fourth embodiment.

Hereinafter, a control device of a multistage converter according to an embodiment will be described with reference to the drawings.
FIG. 1 is a diagram schematically showing a control device of the multistage converter according to the first embodiment.
The control device of the present embodiment is a control device that controls the operation of the multi-stage converter 1 using an H-bridge composed of, for example, four arms as a unit converter.

  The multi-stage converter 1 has two output terminals. In the following description, one output terminal of the multi-stage converter 1 is a positive output terminal TP, and the other output terminal is a negative output terminal TN.

The multi-stage converter 1 includes a plurality of unit converters 11 to 14. Each of the unit converters 11 to 14 is an H bridge circuit in which a positive leg LP having an upper arm S1 and a lower arm S2 and a negative leg LN having an upper arm S3 and a lower arm S4 are connected in parallel. It is.
The multi-stage converter 1 is provided between an output terminal located between the upper arm S1 and the lower arm S2 of the positive leg LP of the unit converters 11 to 14 and a position located between the upper arm S3 and the lower arm S4 of the negative leg LN. Output terminals to be connected in series between the unit converters 11 to 14. The multi-stage converter 1 may have a configuration in which at least two-stage unit converters are connected in series, and there is no particular need to provide an upper limit for the number of stages.

  In the following description, in a multi-stage converter in which N unit converters are connected in series, a unit converter connected to a positive output terminal is used as a first-stage unit converter, and a unit converter connected to a negative output terminal is used. The unit is the unit converter of the Nth stage, and is referred to as the first stage, the second stage,..., The Nth unit in the order in which the N unit converters connected in series are arranged. In the example shown in FIG. 1, the multi-stage converter includes four unit converters 11 to 14, and the unit converter 11 connected to the positive output terminal TP is the first stage, and the unit converter connected to the negative output terminal TN. The converter 14 is the fourth stage, the unit converter 12 is the second stage, and the unit converter 13 is the third stage in the order in which the four unit converters 11 to 14 connected in series are arranged.

The unit converters 11 to 14 have the same configuration. Each of the unit converters 11 to 14 includes a positive leg LP, a negative leg LN, a DC power supply PS, and a voltage sensor SV.
Voltage sensor SV detects the voltage of DC power supply PS and outputs a detected value to control device 2.

  In each of the plurality of unit converters 11 to 14, the leg connected to the positive side output terminal TP of the multi-stage converter 1 or the unit converter on the positive side of itself is defined as a positive leg LP, and the leg connected to the negative side output terminal TN or itself. The leg connected to the unit converter on the negative side is referred to as a negative leg LN. The positive leg LP and the negative leg LN are connected in parallel with a capacitor that is a DC power supply PS.

  In each of the plurality of unit converters 11 to 14, each of the four arms (two upper arms S1, S3 and two lower arms S2, S4) includes an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Semiconductor). A semiconductor switching element in which a diode is connected in antiparallel to a semiconductor element such as a field-effect transistor (metal-oxide semiconductor field-effect transistor) or a MOSFET (semiconductor field-effect transistor: metal-oxide semiconductor field-effect transistor) is provided.

  In each of the positive leg LP and the negative leg LN of each of the unit converters 11 to 14, the semiconductor switching elements of the upper arms S1, S3 and the lower arms S2, S4 perform inversion operations, respectively, and the semiconductor switching of the upper arms S1, S3. When the elements are on, the semiconductor switching elements of the lower arms S2 and S4 are turned off. However, in order to prevent a short circuit between the upper arms S1, S3 and the lower arms S2, S4, when providing a dead time period for turning off both semiconductor switching elements of the upper arms S1, S3 and the lower arms S2, S4, A dead time period is provided so that the semiconductor switching elements of the upper arms S1, S3 and the lower arms S2, S4 are simultaneously turned off.

  The configuration of the multi-stage converter 1 is not limited to that shown in FIG. For example, an energy storage element such as a storage battery may be connected to the DC section of the unit converter instead of the capacitor. Further, the DC units of unit converters 11 to 14 may be connected to an AC power supply and a transformer via a rectifier. Further, three-phase outputs can be obtained by connecting three sets of multistage converter outputs in a star connection, a delta connection, or a V connection.

The control device 2 includes a modulation factor calculation unit 21, a phase shift amount generation unit 22, and a gate signal generation unit 23.
In the present embodiment, the control device 2 operates the multi-stage converter 1 by one-pulse driving. In the one-pulse drive, the semiconductor switching elements of the unit converters 11 to 14 are driven at the output voltage fundamental frequency. In the one-pulse drive, the switching frequency can be suppressed as compared with the PWM drive, so that the loss generated at the time of switching can be reduced, and the effect of reducing the converter loss and the cooler can be expected.

  The control device 2 drives the legs LP and LN of the unit converters 11 to 14 with a switching pulse (gate signal) having the same (duty 50%) time width between ON and OFF, and changes the phase of the gate signal to each. Adjust the output voltage by adjusting the leg. At this time, the phase adjustment amount (phase shift amount) is defined by the center of the on-pulse width of the gate signal of the upper arm S1 of the positive leg LP and the center of the off-pulse width of the gate signal of the upper arm S3 of the negative leg LN. , The phase operation is performed so that the amount of phase is advanced and delayed with respect to the output voltage.

The modulation factor calculator 21 calculates the modulation factor M using the voltage _VDC of the DC power supply PS of the unit converters 11 to 14 and the voltage command value V ^* . The modulation factor M calculated by the modulation factor calculator 21 is input to the phase shift amount generator 22. The modulation rate calculation unit 21 calculates the modulation rate M using, for example, the following equation (4).

The phase shift amount generator 22 outputs the phase shift amount of each of the legs LP and LN of the unit converters 11 to 14 corresponding to the input modulation factor M. Since the positive leg LP and the negative leg LN exist for the number of stages of the unit converters 11 to 14, the lead / lag phase operation amount (phase shift amount) is required for the number of converter stages. In the example shown in FIG. 1, since the number of stages of the unit converter is four, the phase shift amount generation unit 22 outputs _four phase shift amounts α _{1 to} α ₄ .

The relationship between the phase shift amount α _n when the lead-lag equal shift is performed and the fundamental wave amplitude of the output voltage of the multi-stage converter is shown in the following equation. Here, _VDC is the voltage value of the DC power supply PS of each of the unit converters 11 to 14, and it is assumed that the DC power supply voltage of each stage is constant and equal in all stages. In addition, N is the number of stages of the unit converter constituting the multi-stage converter.

The fundamental wave v ₁ is defined by the following equation. In the following equation (2), ω is an output voltage angular frequency.
v ₁ = V ₁ cosωt (2)
From the above equation (1), the fundamental wave amplitude in the case of the four-stage configuration shown in FIG. 1 is expressed by the following equation (3).

We define as follows (4) the ratio of the sum of the DC power supply voltage V _DC of each stage and the output fundamental wave amplitude V ₁ as the modulation factor M.

FIG. 2 is a diagram illustrating an example of a relationship between a modulation factor and a phase shift amount. Here, it is assumed that the phase shift amounts α _{1 to} α ₄ satisfy α ₁ <α ₂ <α ₃ <α ₄ .
From the above equations (3) and (4), it can be seen that there are countless combinations of the phase shift amounts α _{1 to} α ₄ for obtaining the desired modulation rate M (or output voltage). For example, the relationship between the modulation rate M and the phase shift amounts α _{1 to} α ₄ in FIG. 2 is obtained by selecting the harmonics from a plurality of combinations of the phase shift amounts α _{1 to} α ₄ satisfying the modulation rate M with the constraint condition. This is a value obtained by extracting the phase shift amounts α _{1 to} α ₄ that minimize the amount by the optimization algorithm. It is also possible to calculate the phase shift amounts α _{1 to} α ₄ from the solution of the nonlinear simultaneous equations. In the present embodiment, the phase shift amounts α _{1 to} α ₄ are set to be in a range larger than zero and smaller than 180 °.

The phase shift amount generation unit 22 uses, for example, the phase shift amounts α _{1 to} α ₄ calculated in advance using the above equations (3) and (4), and for example, the phase shift amount α corresponding to the modulation factor M. it may comprise of ₁ to? ₄ table.

The gate signal generation unit 23 receives the phase shift amounts α _{1 to} α ₄ from the phase shift amount generation unit 22 and supplies the gate signals of the upper arm S1 of the positive leg LP to be supplied to the four unit converters 11 to 14 ( First gate signals) _{Spα1 to Spα4} and gate signals (second gate signals) _{Snα1 to Snα4} of the upper arm S3 of the negative leg LN are generated. In the present embodiment, the on-time and the off-time of the gate signal are equal (duty is 50%), and each phase is 180 °.

FIG. 3 is a diagram illustrating an example of the gate signal of the upper arm and the output voltage of the multi-stage converter when the modulation factor is 1 and when the modulation factor is 0.2.
The gate signal generation unit 23 determines, for example, the center of the off-pulse width in the time axis direction of the gate signals (second gate signals) _{Snα1 to Snα4} of the upper arm S3 of the negative leg LN from the phase of the voltage command (the position at 0 °). Also delays the phase of the phase shift amounts α _{1 to} α ₄ , and _sets the center of the on-pulse width in the time axis direction of the gate signals (first gate signals) _{Sp α1 to Spα4} of the upper arm S1 of the positive leg LP to the phase of the voltage command. The phase of the phase shift amounts α _{1 to} α ₄ is advanced by more than (0 ° position).

As described above, the gate signal generation unit 23 adjusts the phases of the phase shift amounts α _{1 to} α _{4 based on} the phase of the voltage command, and outputs four gate signals of the upper arm S1 of the positive leg LP and the negative leg. Four gate signals of the upper arm S3 of LN are generated. The gate signal generation unit 23 inverts the gate signal of the upper arm S1 of the positive leg LP to generate a gate signal of the lower arm S2, and inverts the gate signal of the upper arm S3 of the negative leg LN to gate the lower arm S4. Generate a signal.

In the present embodiment, the gate signal S _Piarufa1 is the center of the pulse width of the gate signal supplied to the upper arm S1 of the positive leg LP (is advanced) by shifting the phase shift amount alpha ₁ phase is a signal, gate signal S _Piarufa2 is a positive leg and the center of the pulse width on the gate signal supplied to the arm S1 of LP shifts the phase shift alpha ₂ phase (is advanced) signal, the gate signal S _Piarufa3 is positive is the center of the phase-shifted by shift amount alpha ₃ phases (is advanced) signal pulse width of the supplied gate signals to the arm S1 on the leg LP, the gate signal S _Piarufa4 is on an arm S1 of the positive leg LP supplying center of pulse width of the gate signals by shifting the phase shift amount alpha ₄ phases (is advanced) is a signal.

Further, the gate signal S _Enuarufa1 is a gate signal center (delayed) signal obtained by shifting the phase shift amount alpha ₁ phase the off pulse width supplied to the arm S3 on the negative leg LN, gate signal S _Enuarufa2 is negative leg on the arm S3 of the LN center off pulse width of the supplied gate signals phase-shifted by shift amount alpha ₂ phase (delayed) a signal, the gate signal S _{N [alpha] 3} is the upper arm S3 of the negative leg LN is the center of the phase-shifted by shift amount alpha ₃ of the phase (delay) signal off pulse width of the supplied gate signal, the gate signal S _{N [alpha] 4,} the off pulse width of the gate signal supplied to the upper arm S3 of the negative leg LN centered (delayed) phase-shifted by shift amount alpha ₄ phases is the signal.

  The gate signal generation unit 23 performs a plurality of unit conversions so that the upper arm S1 and the lower arm S2 and the lower arm S2 and the lower arm S2 and the lower arm S2 and the lower arm S2 and the lower arm S2 and the lower arm S2 are supplied with gate signals in an inverted relation to each other. The generated gate signal is output to the devices 11 to 14.

In the present embodiment, the gate signal generation unit 23 may _assign the gate signals S _{pα1 to} S _pα4 to any of the positive legs LP of the unit converters 11 to 14, and the gate signal of the upper arm S3 of the negative leg LN. The signals _{Snα1 to Snα4} may be assigned to any of the negative legs LN of the unit converters 11 to 14.

  As shown in FIG. 3, it can be seen that when both the modulation rate is 1 and the modulation rate is 0.2, the legs LP and LN of all the unit converters 11 to 14 are switching. Further, even when the unit converters 11 to 14 in each stage are operated by one-pulse driving, the sum of the output voltages of the multi-stage converter 1 has a pseudo-PWM-like waveform, and the generation of low-order harmonics can be suppressed. .

  Also, by defining the phase shift amount of the gate signal as described above, as shown in FIG. 3, the leg LPs of all the unit converters 11 to 14 are generated at the timing of the output voltage zero and the time domain before and after the timing. , LN are turned on, or all the upper arms S1, S3 are turned off.

  For example, when performing one-pulse driving, if the center of the off-pulse width and the center of the on-pulse width of the gate signal having a duty ratio of 50% do not lag or advance from the voltage command (when the phase shift amount is zero), the gate signal becomes the voltage. The phase of the command is switched at timings of 90 ° and −90 °.

  On the other hand, in the present embodiment, the center of the off pulse width of the gate signal of the upper arm S3 of the negative leg LN is delayed from the voltage command, and the center of the on pulse width of the gate signal of the upper arm S1 of the positive leg LP is advanced from the voltage command. Not. Thereby, the arc extinguishing timing of the gate signal of the upper arm S3 of the negative leg LN is at a point of -90 ° from the center of the OFF width, and before the phase of the voltage command reaches -90 °, the upper arm of all the negative legs LN. S3 turns off. The ignition timing of the gate signal of the upper arm S3 of the negative leg LN is at a point + 90 ° from the center of the off pulse width, and all the upper arms S3 of the negative leg LN are turned on before the phase of the voltage command reaches 90 °. I do.

  On the other hand, when the phase shift amount is zero, the ignition timing of the gate signal of the upper arm S1 of the positive leg LP is at a point of −90 ° from the center of the on-pulse width. On the other hand, in the present embodiment, since the center of the on-pulse width of the gate signal of the upper arm S1 of the positive leg LP is advanced beyond the position of 0 ° of the voltage command, the gate signal of the upper arm S1 of the positive leg LP is the voltage command. The upper arms S1 of all the positive legs LP are turned on at a point where the phase of -90 ° or later. In addition, the arc extinguishing timing of the gate signal of the upper arm S1 of the positive leg LP is a point at + 90 ° from the center of the on-pulse width, and all upper arms S1 of the positive leg LP are turned off at a point where the phase of the voltage command is 90 ° or later. I do.

  From the above, all the upper arms S1 and S3 are turned off at the timing when the phase of the voltage command is −90 °, and all the upper arms S and S3 are turned on at the timing when the phase of the voltage command is + 90 °. At the timing when the output voltage of the multi-stage converter 1 becomes zero, the output voltages of all the unit converters 11 to 14 also become zero.

  There are two timings at which the output voltage becomes zero: -90 ° and + 90 ° in each cycle of the output voltage. At this timing, since the switching states of all the legs LP and LN of all the unit converters 11 to 14 become the same, for example, the gate signal is switched according to a change in the modulation rate, or the unit converters 11 to 14 are switched. It is possible to exchange the gate signals in the positive leg LP or the negative leg LN between. That is, at the timing when the output voltage becomes zero, the switching state is the same in all the legs, so even if the gate signal is switched, the switching state does not change before and after, and the gate signal can be replaced without affecting the output voltage. It becomes possible. Further, replacement can be performed twice in each cycle.

FIG. 4 is a diagram showing another example of the gate signal of the upper arm and the output voltage of the multi-stage converter when the modulation factor is 1 and when the modulation factor is 0.2.
In this example, the gate signal generation unit 23 sets, for example, the center of the off-pulse width in the time axis direction of the gate signal (fourth gate signal) of the upper arm S3 of the negative leg LN with respect to the phase (0 ° position) of the voltage command. The phase of the phase shift amounts α _{1 to} α ₄ is advanced, and the center of the on-pulse width in the time axis direction of the gate signal (third gate signal) of the upper arm S1 of the positive leg LP is set to the phase of the voltage command (position of 0 °). ), The phases of the phase shift amounts α _{1 to} α ₄ are delayed.

Also in this case, the gate signal generation unit 23 adjusts the phases of the phase shift amounts α _{1 to} α _{4 based on} the phase of the voltage command as described above, and controls the gates of the upper arms S1 of the four positive legs LP. Signals (third gate signals) _{Spα1 to Spα4} and gate signals (fourth gate signals) _Snα1 to _Snα4 of the upper arm S3 of the four negative legs LN are generated. The gate signal generation unit 23 inverts the gate signal of the upper arm S1 of the positive leg LP to generate a gate signal of the lower arm S2, and inverts the gate signal of the upper arm S3 of the negative leg LN to gate the lower arm S4. Generate a signal.

The gate signal generation unit 23 performs a plurality of unit conversions so that the upper arm S1 and the lower arm S2 and the lower arm S2 and the lower arm S2 and the lower arm S2 and the lower arm S2 and the lower arm S2 and the lower arm S2 are supplied with gate signals in an inverted relation to each other. The generated gate signal is output to the devices 11 to 14. When the phase shift amounts α _{1 to} α ₄ are common, the outputs of the multi-stage converter 1 in the case shown in FIG. 3 and the case shown in FIG. 4 are the same.

  As in the example shown in FIG. 3, similarly to the example shown in FIG. 3, even when the modulation rate is 1 and the modulation rate is 0.2, the legs LP and LN of all the unit converters 11 to 14 are switched. You can see that there is. Further, even when the unit converters 11 to 14 in each stage are operated by one-pulse driving, the sum of the output voltages of the multi-stage converter 1 has a pseudo-PWM-like waveform, and the generation of low-order harmonics can be suppressed. .

  Also, by defining the phase shift amount of the gate signal as described above, as shown in FIG. 4, the leg LP of all the unit converters 11 to 14 is obtained at the timing of the output voltage zero and the time domain before and after the timing. , LN are turned on, or all the upper arms S1, S3 are turned off.

  At the timing when the phase of the voltage command is −90 °, all upper arms S1 and S3 are turned on, and when the phase of the voltage command is + 90 °, all upper arms S and S3 are turned off. At the timing when the output voltage of the multi-stage converter 1 becomes zero, the output voltages of all the unit converters 11 to 14 also become zero.

  There are two timings at which the output voltage becomes zero: -90 ° and + 90 ° in each cycle of the output voltage. At this timing, since the switching states of all the legs LP and LN of all the unit converters 11 to 14 become the same, for example, the gate signal is switched according to a change in the modulation rate, or the unit converters 11 to 14 are switched. It is possible to exchange the gate signals in the positive leg LP or the negative leg LN between. That is, at the timing when the output voltage becomes zero, since the switching state is the same in all the legs, even if the gate signal is switched, the switching state does not change before and after, so that loss is avoided and the output voltage is reduced. The gate signals can be exchanged without any influence. Further, replacement can be performed twice in each cycle.

  As described above, according to the control device for a multi-stage converter of the present embodiment, all the unit converters can be used for voltage output regardless of the magnitude of the output voltage, suppressing generation of harmonics, One-pulse drive for reducing distortion can be realized.

Next, a control device for a multistage converter according to a second embodiment will be described in detail with reference to the drawings.
In the following description of a plurality of embodiments, the same components as those of the above-described first embodiment will be denoted by the same reference numerals, and description thereof will be omitted.

FIG. 5 is a diagram schematically illustrating a control device of the multistage converter according to the second embodiment.
The control device 2 of the present embodiment differs from the above-described first embodiment in that the gate signal generation unit 23 includes a voltage adjustment unit 24.

The voltage adjustment unit 24 uses the phase shift amounts α _{1 to} α ₄ , the DC power supply voltage values of the plurality of unit converters 11 to 14, and the output current value of the multi-stage converter _{1 to} generate a plurality of unit converters. A gate signal is assigned to each of the unit converters 11 to 14 so that variations in the DC power supply voltages of 11 to 14 are suppressed.

The voltage adjusting unit 24 sequentially supplies each of the gate signals based on the phase shift amounts α _{1 to} α ₄ (α ₁ <α ₂ <α ₃ <α ₄ ) to the plurality of unit converters 11 to 14, for example. As described above, the gate signal may be switched periodically.

  Since the output current value of the multi-stage converter 1 is equal to the output current value of each of the plurality of unit converters 11 to 14, the current sensor (not shown) includes the output path of the multi-stage converter 1 and the unit converters 11 to 11. 14 may be provided in at least one of the output paths. An output value of at least one current sensor is supplied to the voltage adjusting unit 24.

Hereinafter, an example of the operation of the voltage adjustment unit 24 will be described.
FIG. 6 is a diagram illustrating an example of the gate signal output from the control device, the output voltage of each unit converter, and the output voltage and output current of the multi-stage converter.

Here, the phase shift amounts α _{1 to} α ₄ are α ₁ <α ₂ <α ₃ <α ₄ (−α ₄ <−α ₃ <−α ₂ <−α ₁ ), and the first stage unit positive leg gate signal arm S1 on the LP _{S Piarufa4} transducer 11, arm S3 is driven by the gate signals _{S Enuarufa1} on the negative leg LN, of the second-stage unit converter 12 of the upper arm S1 of the positive leg LP The gate signal S _pα3 , the upper arm S3 of the negative leg LN is driven by the gate signal _Snα2 , and the upper arm S1 of the positive leg LP of the third unit converter 13 is driven by the gate signal S _pα2 , the upper arm S3 of the negative leg LN. _Is driven by the gate signal _Snα3 , and the upper arm S1 of the positive leg LP of the unit converter 14 at the fourth stage is driven by the gate signal _Spα1 and the upper arm S3 of the negative leg LN is driven by the gate signal _Snα4. Is shown.

  When the output voltages of the unit converters 11 to 14 are compared, the output converters 11 to 14 have different output voltage phases. In addition, when comparing the time widths during which each of the plurality of unit converters 11 to 14 outputs a voltage, a difference occurs in the voltage output time among the unit converters 11 to 14.

  Since the multi-stage converter 1 is configured by connecting the output terminals of the plurality of unit converters 11 to 14 in series, the output current of the multi-stage converter 1 passes through all the unit converters 11 to 14, A common current flows through the unit converters 11 to 14.

  The output active power of each of the unit converters 11 to 14 is an inner product of the output voltage of each of the unit converters 11 to 14 and the output current of the multi-stage converter 1. Therefore, when the output voltage phase and the voltage output time width of each of the unit converters 11 to 14 are different, a difference occurs in the output active power among the unit converters 11 to 14. As a result, if the voltage of the DC power supply PS between the unit converters 11 to 14 varies, the output voltage of the multi-stage converter 1 may be distorted.

  Therefore, in the present embodiment, the voltage adjustment unit 24 of the control device 2 calculates an estimated value of the output active power of each of the unit converters 11 to 14, and outputs the unit converters 11 to 14 every cycle or every predetermined cycle. The variation in the voltage of the DC power supply PS is suppressed by exchanging the gate signals to be applied to the DC power supply.

The voltage adjustment unit 24 calculates an estimated value of the output active power of any unit converter according to the combination of the gate signals S _{pα1 to} S _pα4 and S _{nα1 to} S _nα4 , and calculates the estimated value of the unit converter having a large DC power supply voltage. output active power is increased, so that the output effective power of the DC power source voltage is smaller unit converters decreases, the gate signal _{S pα1} ~S _pα4, may be assigned _{S nα1} ~S _nα4.

  The estimated value of the output voltage of the unit converter when the upper arm S1 of the positive leg LP and the upper arm S3 of the negative leg LN are driven by an arbitrary gate signal will be described below.

7, the arm is driven by a gate signal obtained by shifting the phase of alpha _P on the positive leg LP, the output of the unit converter when driven by a gate signal obtained by shifting the phase of the negative leg on the arm alpha _N FIG. 4 is a diagram illustrating an example of a voltage.

  The unit converter outputs a positive voltage when only the upper arm S1 of the positive leg LP is on, and outputs a negative voltage when only the upper arm S3 of the negative leg LN is on. When the switching states of the positive leg LP and the negative leg LN are the same, the output voltage of the unit converter becomes zero.

Here, with respect to the phase (position of 0 °) of the output voltage command V ^* of the multi-stage converter 1, the center position of the time when the gate signal of the upper arm S1 of the positive leg LP is ON is α _P , and the negative leg LN is when the gate signal of the upper arm S3 is defined off to -α center position of that time _N, it is possible to represent the output voltage v _oh in the unit converter by the following equation when a Fourier series expansion. Here, _VDC is the DC power supply voltage of the unit converter. In the following expression (5), θ is the angle (instantaneous angle value) of the output voltage command V ^* and is a value that changes with time. That is, the output voltage v _oh is a function of θ.

When the fundamental wave v _oh1 is _obtained from the above equation (5), the following equation is obtained.

Further, from the above equation (6), the fundamental wave execution value V _oh1 and the phase difference Φ _oh between the output voltage of the multi-stage converter 1 and the output voltage of the unit converter can be expressed as follows.

8 and 9 are diagrams illustrating an example of the unit converter output voltage and the estimated fundamental wave component.
8 and 9, the output voltage of the unit converter is indicated by a solid line, and the equivalent of the fundamental wave component of the unit converter output voltage is indicated by a broken line. It can be confirmed that the amplitude and phase of the fundamental wave component can be estimated using the phase shift amount of the gate signal supplied to the positive leg LP and the negative leg LN.

That is, when the example shown in FIG. 8 is applied to the above equation (6), the fundamental wave v _oh1 of the output voltage of the unit converter is expressed as _follows .

When the example shown in FIG. 9 is applied to the above equation (6), the fundamental wave v _oh1 of the output voltage of the unit converter is expressed as _follows .

Here, the output current i _O of the multi-stage converter 1 is defined by the following equation (9). Here, in the equation (9), Φ _i is a phase difference between the output voltage command V ^* and the output current i _O, and I _O is an output current execution value of the multi-stage converter 1.
Since the output current i _O of the multistage converter 1 flows in common to each of the plurality of unit converters 11 to 14, the unit current is calculated from the inner product of the output voltage fundamental wave value and the output current value of the unit converters 11 to 14. output active power _{P oh} transducers 11-14 can be expressed by the following equation.
P _oh = V _{oh1 IO} cos (Φ _oh −Φ _i ) (10)

As described above, the voltage adjustment unit 24 uses the output current i _O , the phase shift amount of the gate signal of the positive leg LP, and the phase shift amount of the gate signal of the negative leg LN to convert the unit converters 11 to 11. It is possible to calculate an estimated value of each of the 14 output active powers _Poh .

Next, a method of suppressing unbalanced DC voltage between the unit converters using the estimated value of the output active power of the unit converters 11 to 14 will be described.
FIG. 10 is a flowchart illustrating an example of the operation of the voltage adjustment unit of the control device illustrated in FIG.

Each of the DC power supply voltage _{V DC} unit converter 11 to 14 is likely to become unbalanced by variation of the output effective power _{P oh} each unit converter 11-14. Therefore, in the present embodiment, the voltage adjustment unit 24 detects the DC power supply voltage _VDC of each of the unit converters 11 to 14 configuring the multi-stage converter 1 (step S1).
Subsequently, the voltage adjustment unit 24 calculates an average value of the detected DC power supply voltage _VDC (Step S2).

Then, the difference between the n = 1 (step S3), and the voltage adjusting unit 24, for example, the average value of the DC power supply voltage _{V DC} of the unit converters 11 to 14, a DC power source voltage _{V DC} of unit converters 1n Is greater than or equal to a predetermined threshold (step S4).

Voltage adjusting unit 24, to the DC power supply voltage _V average value and the DC power supply voltage _{V DC} and the difference is greater unit converters 1n than a predetermined threshold value of the _DC unit converters 11-14, the output effective power _{P oh} Is assigned to the upper arm S1 gate signal of the positive leg LP and the upper arm S3 gate signal of the negative leg LN (step S5).

The voltage adjusting section 24, the DC power supply voltage V average value and the DC power supply voltage V _DC and the difference is less unit converters 1n than a predetermined threshold value of the _DC unit converters 11-14, the output effective power P A combination of the upper arm S1 gate signal of the positive leg LP having a small _oh and the upper arm S3 gate signal of the negative leg LN is assigned (step S6).

  The voltage adjusting unit 24 determines whether n is the number of stages (= N) of the multi-stage converter 1 (step S7). If n is smaller than N, 1 is added to n (step S8), and n = N The above steps S4 to S6 are repeated until the above is reached.

As described above, in the present embodiment, the assignment of the gate signal to be supplied to the unit converters 11 to 14 is performed based on the estimated value of the output active power P _oh and the DC power supply voltage _{VDC of} each of the unit converters 11 to 14. Do.

The timing at which the voltage adjuster 24 switches the gate signal between the unit converters 11 to 14 will be described below.
The voltage adjustment unit 24 sets the timing when the states of the gate signals of the upper arms S1 and S3 match in all the unit converters 11 to 14, for example, when the phases of the output voltages shown in FIG. Thus, the gate signals are exchanged between the unit converters 11 to 14. By exchanging the gate signals of the unit converters 11 to 14 at this timing, the unbalance of the DC power supply voltage V _DC can be suppressed without affecting the output voltage of the multi-stage converter 1 and the switching states of all the arms. Becomes possible.

  As described above, according to the control device for a multi-stage converter of the present embodiment, all unit converters can be used for voltage output regardless of the magnitude of the output voltage, as in the first embodiment. In addition, it is possible to realize one-pulse driving that suppresses generation of harmonics and reduces voltage distortion.

Next, a control device for a multi-stage converter according to a third embodiment will be described in detail with reference to the drawings.
In the above-described first embodiment, the control device 2 advances the center of the on-time of the positive leg upper arm switching signal with respect to the voltage command, and moves the center of the off time of the negative leg upper arm switching signal with respect to the voltage command. Modulation to be delayed has been described. Further, the description has been given of the modulation in which the control device 2 delays the center of the on-time of the positive leg upper arm switching signal with respect to the voltage command, and advances the center of the off time of the negative leg upper arm switching signal with respect to the voltage command.

  FIG. 11 and FIG. 12 are diagrams for explaining an example of the operation of the control device of the multi-stage converter according to the third embodiment. Note that FIG. 11 shows the output voltage of the multi-stage converter when the modulation factor is 1, and FIG. 12 shows the output voltage and the like when the modulation factor is 0.2.

In the example illustrated in FIG. 11, the multi-stage converter 1 includes four unit converters 11 to 14, and the control device 2 drives the positive leg LP with the gate signals S _{pα1 to} S _pα4 of the four upper arms S 1, The negative leg LN can be driven by the gate signals S _{nα1 to Snα4} of the four upper arms S3. Therefore, as the combination of the upper arm gate signals to be given to the unit converters 11 to 14, there are two squares of the number of stages.

In the present embodiment, the controller 2 sets the phase shift amounts α _{1 to} α ₄ (α ₁ <α ₂ <α ₃ <α ₄ ) for the positive leg LP and the negative leg LN in the same unit converters 11 to 14. Assigns gate signals having the same delay and advance amounts.

In FIG. 11, the same gate signal is assigned to each of the unit converters 11 to 14 with the phase shift amounts α _{1 to} α ₄ (α ₁ <α ₂ <α ₃ <α ₄ ) delayed and advanced in the positive leg and the negative leg. 4 shows an example of output voltages of the unit converters 11 to 14 at the time.

Here, the control unit 2 assigns the gate signal _{S Enuarufa1} positive leg gate signal _{S Piarufa1} the arm S1 on the LP, the upper arm S3 of the negative leg LN of the unit converter 11, a positive leg of unit converters 12 gate signal _{S Piarufa2} the arm S1 on the LP, assign the gate signal _{S Enuarufa2} on arm S3 of the negative leg LN, the gate signal _{S Piarufa3} on arm S1 of the positive leg LP of unit converters 13, the upper arm of the negative leg LN S3 assign the gate signal _{S N [alpha] 3,} a unit converter 14 of the positive leg gate signal on arm S1 of _{LP S} pα4, assigns a gate signal _{S N [alpha] 4} to the upper arm S3 of the negative leg LN.

  In this case, the phase difference between the center of the gate signal ON time width of the upper arm S1 of the positive leg LP and the output voltage command, and the phase difference between the center of the gate signal OFF time width of the upper arm S3 of the negative leg LN and the output voltage command are: It has positive and negative symmetry. Therefore, when the same lead signal and the same delay signal are applied to the upper arms S1 and S3 of each of the plurality of unit converters 11 to 14, the output voltage width changes according to the phase shift amount and the output voltage phase changes. do not do. That is, the output voltage phases of unit converters 11 to 14 are the same as the output voltage phases of multi-stage converter 1. Thus, since there is no difference in the output voltage phase between the unit converters 11 to 14, the calculation of the estimated value of the output active power of the unit converter can be simplified.

As described above, when the positive leg LP and the negative leg LN of the same unit converters 11 to 14 are driven by the target gate signal having a positive or negative phase shift amount, the output voltage phases of the unit converters 11 to 14 are equal. The output voltage width, that is, the output voltage fundamental wave amplitude is different. Therefore, if this control method is adopted, a difference occurs between the output active powers of the unit converters 11 to 14, and the DC power supply voltages of the unit converters 11 to 14 become unbalanced.
Therefore, a method of controlling the imbalance of the DC power supply voltage between the unit converters 11 to 14 by the control device 2 of the present embodiment will be described below.

The center position (α _P ) of the on-pulse width of the gate signal for driving the upper arm S1 of the positive leg LP with respect to the output voltage command phase of the multi-stage converter 1, and the off-pulse width of the gate signal for driving the upper arm S3 of the negative leg LN As described above, the relational expression between the center position (−α _N ) and the output voltages of the unit converters 11 to 14 (fundamental wave v _oh1 ) is expressed by the expression (6).

In the present embodiment, the center position of the on-pulse width of the gate signal for driving the upper arm S1 of the positive leg LP and the center position of the off-pulse width of the gate signal for driving the upper arm S3 of the negative leg LN correspond to the phase (0 In order to assign a gate signal to each of the unit converters 11 to 14 so as to be applicable to (°), if the phase shift amount is α _n , the expression (6) can be converted into the following expression (11). it can.

According to the above equation (11), regardless of the magnitude of the phase shift amount, the output voltage of the multi-stage converter 1 and the output voltage of the unit converters 11 to 14 have the same phase, and the unit converters 11 to 14 The output voltage phase difference is also eliminated.

Here, the output active power of the unit converters 11 to 14 will be considered.
The output active power of the unit converters 11 to 14 is obtained by the above equation (10). However, since the output voltage phase of the unit converters 11 to 14 is the same as the output voltage of the multi-stage converter 1, the active power is It is determined only by the current amplitude, phase, unit converter output fundamental voltage, and unit converter DC voltage. Here, since the output current flows in common to the plurality of unit converters 11 to 14, the magnitude of the output active power of the unit converters 11 to 14 depends on the magnitude of the output voltage fundamental wave amplitude (= V _oh1 ). Proportional.

Here, when the output current phase difference Φ _i with respect to the output voltage of the multi-stage converter 1 is −90 <Φ _i <90, the power factor of the multi-stage converter 1 is always positive. Since the output voltage phases of the unit converters 11 to 14 are the same between the stages, the output voltage power factor becomes equal. Therefore, the output active power of the unit converters 11 to 14 increases in proportion to the output fundamental wave amplitude of the unit converters 11 to 14.

Therefore, a DC voltage imbalance suppression method will be described by taking a four-stage multistage converter 1 as an example. Since there are four stages, the phase shift amounts are four, and are assumed _to be α _{1 to} α ₄ respectively. Here, the relationship between the cosine values of the respective phase shift amounts is as follows.
cosα ₁ > cosα ₂ > cosα ₃ > cosα ₄ (12)

At this time, the output active powers of the unit converters 11 to 14 given the respective phase shift amounts are as follows.

As in the expressions (13) to (16), the relative magnitudes of the output active powers P _{oh1 to} P _oh4 are determined by the phase shift amounts α _{1 to} α ₄ . _Assuming that the relationship between the magnitudes of the cosine values of the phase shift amounts α _{1 to} α ₄ is, for example, Expression (12), the relationship between the magnitudes of the output active powers P _{oh1 to} P _oh4 is as follows.
_Poh1 > _Poh2 > _Poh3 > _Poh4 (17)

Here, it is assumed that the individual DC power supply voltages of the unit converters 11 to 14 constituting the multi-stage converter 1 are in an unbalanced state as in the following equation (18).
V _DCa > V _DCb > V _DCc > V _DCd (18)
When balancing this DC power supply voltage, the voltage adjusting unit 24 of the control device 2 assigns a phase shift amount at which the output active power becomes relatively large to the unit converters 11 to 14 whose DC power supply voltage is relatively large periodically, A unit converter having a relatively small DC power supply voltage is assigned a phase shift amount having a relatively small output active power.

That is, in the above example, the voltage adjusting unit 24 of the control device 2, the phase shift amount alpha ₁ to the unit converter of the DC power supply voltage V _DCa, the phase shift amount alpha ₂ DC power supply voltage is a unit conversion V _DCb to vessels, the amount of phase shift alpha ₃ to unit converters of the DC power supply voltage V _DCc the phase shift alpha ₄ DC power supply voltage is allocated to the unit converter V _DCd.

  As described above, by switching the gate signal applied to the plurality of unit converters 11 to 14 based on the relative magnitude of the DC power supply voltage and the cosine value of the phase shift amount, the output current detection value is not used. Therefore, it is possible to suppress the unbalance of the DC power supply voltage.

Further, when the output current phase Φ _i is −180 <Φ _i <−90 and 90 <Φ _i <180, the polarity of the output active power is negative, so that the unit conversion in which the DC power supply voltage is relatively large is considered. The phase shift amount in which the absolute value of the output active power becomes smaller is assigned to the converters 11 to 14, and the phase shift in which the absolute value of the output active power becomes larger for the unit converters 11 to 14 in which the DC power supply voltage is relatively small. By allocating the amount, the unbalance of the DC power supply voltage can be similarly suppressed without using the output current detection value.

  As described above, according to the control device for a multi-stage converter of the present embodiment, all unit converters can be used for voltage output regardless of the magnitude of the output voltage, as in the first embodiment. In addition, it is possible to realize one-pulse driving that suppresses generation of harmonics and reduces voltage distortion.

Next, a control device for a multistage converter according to a fourth embodiment will be described in detail with reference to the drawings.
In the above-described third embodiment, the absolute value of the phase advance amount of the gate signal of the positive leg LP and the phase delay amount of the gate signal of the negative leg LN for the gate signals of the upper arms S1 and S3 to be provided to the unit converters 11 to 14. It has been described that the gate signals are assigned so that the values are equal. According to this method, the output voltage phases of the unit converters 11 to 14 become the same, and the estimation of the output active power of the unit converters 11 to 14 can be simplified. On the other hand, the difference between the output voltage fundamental wave amplitudes of the unit converters 11 to 14 may be large.

  Therefore, in the present embodiment, the control device 2 assigns a gate signal to the unit converters 11 to 14 so as to reduce variation in the output voltage fundamental wave amplitude among the unit converters 11 to 14.

  In this embodiment, the shift amounts of the on-pulse width center of the gate signal of the upper arm S1 of the positive leg LP are arranged in ascending order with respect to the multi-stage converter output voltage commands corresponding to the number of stages of the multi-stage converter. When the shift amounts at the center of the off pulse width of the gate signal of the upper arm S3 are arranged in ascending order, the shift amounts in the same order are distributed to the same unit converter.

For example, when the phase shift amounts are α _{1 to} α ₄ in the four-stage multi-stage converter 1, α ₁ <α ₂ <when the shift amounts of the on-pulse width center of the gate signal of the upper arm S 1 of the positive leg LP are arranged in ascending order. When α ₃ <α ₄ and the shift amount of the center of the off-pulse width of the gate signal of the upper arm S3 of the negative leg LN is arranged in ascending order, when −α ₄ <−α ₃ <−α ₂ <−α ₁ , _{Four combinations of} the _first α ₁ and -α ₄ , the second α ₂ and -α ₃ , the third α ₃ and -α ₂ , and the fourth α ₄ and -α ₁ in the same unit Assign to converter.

For example, FIG. 6 shows an example of output voltages of the unit converters 11 to 14 when the above assignment is performed. That is, the upper arm S1 of the positive leg LP of the unit converter 11 of the first stage is _driven by the gate signal _Spα4 , and the upper arm S3 of the negative leg LN is driven by the gate signal _Snα1. The upper arm S1 of the leg LP is _driven by the gate signal S _pα3 , the upper arm S3 of the negative leg LN is driven by the gate signal _Snα2 , and the upper arm S1 of the positive leg LP of the unit converter 13 at the third stage is _shifted by the gate signal S _pα2 , the arm S3 is driven by the gate signals _{S N [alpha] 3} on the negative leg LN, gate signal arm S1 on the positive leg LP of unit converters 14 of the four-stage _{S pα1,} gate signals over arm S3 of the negative leg LN _{S N [alpha] 4} 5 shows an example when driving is performed.

FIG. 13 is a diagram illustrating the unit converter output voltage when the magnitude of the output voltage of the multi-stage converter is changed.
In each of the examples shown in FIGS. 6 and 13, it can be confirmed that the variation in the output voltage width of the unit converters 11 to 14 is suppressed. By allocating the phase shift amount as described above, the pulse having the smallest shift amount in the positive leg LP, the pulse having the largest shift amount in the negative leg LN, the pulse having the second smallest shift amount in the positive leg LP, and the negative leg Thus, the shift amount between the positive side and the negative side can be made uniform among the unit converters 11 to 14, such as a pulse having the second largest shift amount.

  As described above, according to the control device for a multi-stage converter of the present embodiment, all unit converters can be used for voltage output regardless of the magnitude of the output voltage, as in the first embodiment. In addition, it is possible to realize one-pulse driving that suppresses generation of harmonics and reduces voltage distortion.

The assignment of the gate signal to the unit converters 11 to 14 is not limited to the method of the second to fourth embodiments.
For example, in the above-described second embodiment, the voltage adjusting unit 24 calculates an estimated value of the output active power of any unit converter when driven by an arbitrary gate signal, and calculates the DC value of the plurality of unit converters 11 to 14. The method of appropriately distributing the power supply voltage so as to suppress the imbalance has been described.

  For example, the voltage adjusting unit 24 calculates, for each of the unit converters 11 to 14, a change in the DC power supply voltage due to an arbitrary gate signal supplied one cycle before, for example, the unit converter having a large amount of change in the DC power supply voltage. The gate signal may be exchanged between the unit converter and the unit converter in which the amount of change in the DC power supply voltage is small. By allocating the gate signals in this manner, the voltage adjusting unit 24 can suppress the variation of the DC power supply voltage without estimating the output active power of the unit converters 11 to 14.

  Further, the above embodiments may be combined. For example, the assignment of the gate signal described in the above-described second embodiment may be applied to the third embodiment and the fourth embodiment. For example, the voltage adjustment unit 24 arranges the respective phase shift amounts of the positive leg LP and the negative leg LN in descending order of the calculated estimated value of the output active power, and sequentially gates the unit converters in descending order of the DC power supply voltage. Signals may be assigned. Thus, it is possible to suppress the variation of the DC power supply voltage, and it is possible to obtain the same effect as the above-described embodiments.

  Further, for example, in the above-described third and fourth embodiments, there are several types of combinations of gate signals applied to the positive leg LP and the negative leg LN. Are four patterns. Therefore, the assignment may be performed so that the gate signals are exchanged every period so that all the unit converters 11 to 14 experience combinations of gate signals corresponding to the number of stages.

For example, the voltage adjusting unit 24, the upper arm S1 of the positive leg LP of unit converters 11, the gate signal _{S Piarufa1,} gate signal _{S Piarufa2,} gate signal _{S Piarufa3,} gate signal _{S Piarufa4,} gate signal _{S pα1} ... order gates of supplying a signal, supplied to the upper arm S1 of the positive leg LP of unit converters 12, the gate signal _{S Piarufa2,} gate signal _{S Piarufa3,} gate signal _{S Piarufa4,} gate signal _{S Piarufa1,} the gate signal _{S pα2} ... order gate signal _Then , a _forward gate signal of the gate signal S _pα3 , the gate signal S _pα4 , the gate signal S _pα1 , the gate signal S _pα2 , the gate signal S _pα3 ... _Is supplied to the upper arm S1 of the positive leg LP of the unit converter 13. A gate signal S _pα4 , a gate signal S _pα1 , a gate signal S _pα2 , a gate signal S _pα3 , A forward gate signal of the gate signals S _pα4 ... _{May be} supplied, and the gate signals may be periodically replaced.

The voltage adjusting section 24, the upper arm S3 of the negative leg LN of the unit converter 11, the gate signal _{S N [alpha] 4,} the gate signal _{S N [alpha] 3,} the gate signals _{S Enuarufa2,} gate signal _{S Enuarufa1,} gate signal _{S N [alpha] 4} ... order gates of , _And a _forward gate signal of the gate signal S _nα3 , the gate signal S _nα2 , the gate signal S _nα1 , the gate signal S _nα4 , the gate signal S _nα3 ... To the upper arm S3 of the negative leg LN of the unit converter 12. _Then , a _forward gate signal of the gate signal S _nα2 , the gate signal S _nα1 , the gate signal S _nα4 , the gate signal S _nα3 , the gate signal S _nα2 ... _Is supplied to the upper arm S3 of the negative leg LN of the unit converter 13, The gate signal S _nα1 , the gate signal S _nα4 , the gate signal S _nα3 , the gate signal S _nα2 , the gate signal S _nα1 , the gate signal S _nα4 , The gate signals may be periodically replaced by supplying forward gate signals of the gate signals S _nα1 .

By driving the N-stage multi-stage converter 1 by sequentially replacing the gate signal in a predetermined order at a predetermined period as described above, in the N-period, the gate signals supplied to the unit converters 11 to 1N in N periods The combinations are equal (the order of supply is different). Therefore, the variation of the DC power supply voltage of the unit converters 11 to 1N is suppressed after the number of cycles of the number of stages has elapsed. In this method, since the unit converters 11 to 1N only need to experience a combination of common gate signals, information on the DC power supply voltage and output current is not required, and variations in the DC power supply voltage can be suppressed. it can.
In any case, the gate signal generation unit 23 switches the gate signals of the plurality of unit converters 11 to 14 at the timing when the output voltage of the multi-stage converter 1 becomes zero, so that the output voltage is not affected. The gate signals can be exchanged.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Multi-stage converter, 2 ... Control device, 11-14 ... Unit converter, 21 ... Modulation rate calculation part, 22 ... Phase shift amount generation part, 23 ... Gate signal generation part, 24 ... Voltage adjustment part, 100 ... Transformation , Rectifier, LP: positive leg, LN: negative leg, S1, S3: upper arm, S2, S4: lower arm, _{Snα1 to Snα4} , _{Spα1 to Spα4} : gate signal, α1 to α4: phase Shift amount, PS: DC power supply, SV: Voltage sensor, TP: Positive output terminal, TN: Negative output terminal.

Claims (9)

A DC power supply, a control device that controls a multi-stage converter in which a plurality of unit converters each including a positive leg and a negative leg connected in parallel with the DC power supply are connected in series,
An output voltage command of the multi-stage converter, a modulation rate calculation unit that calculates a modulation rate using the voltage of the DC power supply,
A phase shift amount generation unit that generates a phase shift amount of a gate signal that drives the upper arm and the upper arm of the negative leg of the plurality of unit converters based on the modulation factor;
A signal for driving a plurality of the unit converters at an output voltage fundamental wave frequency, wherein an ON pulse width and an OFF pulse width are the same, and a center of an ON pulse width is advanced by the phase shift amount with respect to a phase of the output voltage command. A first gate signal and a second gate signal in which the center of the off pulse width is delayed by the phase shift amount with respect to the phase of the output voltage command, and the first gate signal is generated by the plurality of unit converters. A gate signal generating unit that sets the gate signal of the upper arm of the positive leg, and sets the second gate signal as the gate signal of the upper arm of the negative leg of the plurality of unit converters;
The controller for a multi-stage converter, wherein the phase shift amount is greater than zero and less than 180 °. A DC power supply, a control device that controls a multi-stage converter in which a plurality of unit converters each including a positive leg and a negative leg connected in parallel with the DC power supply are connected in series,
An output voltage command of the multi-stage converter, a modulation rate calculation unit that calculates a modulation rate using the voltage of the DC power supply,
A phase shift amount generation unit that generates a phase shift amount of a gate signal that drives the upper arm and the upper arm of the negative leg of the plurality of unit converters based on the modulation factor;
A signal for driving a plurality of the unit converters at an output voltage fundamental wave frequency, wherein an ON pulse width and an OFF pulse width are the same, and a center of an ON pulse width is delayed by the phase shift amount with respect to the phase of the output voltage command. A third gate signal, and a fourth gate signal in which the center of an off pulse width is advanced by the phase shift amount with respect to the phase of the output voltage command, and the third gate signal is output to a plurality of the unit converters. A gate signal generating unit that sets the gate signal of the upper arm of the positive leg, and sets the fourth gate signal as the gate signal of the negative leg of the plurality of unit converters;
The controller for a multi-stage converter, wherein the phase shift amount is greater than zero and less than 180 °.   The gate signal generation unit is configured to fire the gate signal that drives the upper arm of the positive leg when the predetermined amount of phase shift is applied, and the gate signal that drives the upper arm of the negative leg. Using the angle, calculate the estimated value of the fundamental voltage output from the unit converter, and calculate the output active power of the unit converter from the output current phase of the multi-stage converter and the estimated value of the fundamental voltage amplitude. And a voltage adjuster that replaces gate signals supplied to the plurality of unit converters based on the DC power supply voltages of the plurality of unit converters and the estimated value of the output active power. A control device for a multi-stage converter according to claim 1 or 2.   The absolute value of the phase shift amount between the gate signal for driving the upper arm of the positive leg and the gate signal for driving the upper arm of the negative leg is equal in each of the plurality of unit converters. The control device for a multi-stage converter according to claim 2.   In each of the plurality of unit converters, the phase soft amount between the gate signal for driving the upper arm of the positive leg and the gate signal for driving the upper arm of the negative leg is the phase shift amount for the number of stages. The control device for a multi-stage converter according to claim 1 or 2, wherein the devices have the same order when arranged in ascending order.   The multi-stage converter control device according to claim 4, wherein the gate signal generation unit switches gate signals of the plurality of unit converters at a timing when an output voltage of the multi-stage converter becomes zero.   The multi-stage converter according to claim 6, wherein the gate signal generation unit includes a voltage adjustment unit that switches a gate signal to be assigned to the plurality of unit converters according to a change amount of the DC power supply voltage one cycle before. Control device.   The gate signal generating unit calculates a firing angle between a gate signal for driving the upper arm of the positive leg and a gate signal for driving the upper arm of the negative leg when the predetermined phase shift amount is applied. And calculating the estimated value of the fundamental voltage amplitude output from the unit converter, and estimating the output active power of the unit converter from the output current phase of the multi-stage converter and the estimated value of the fundamental voltage amplitude. A voltage adjuster that calculates a value and switches a gate signal to be supplied to the plurality of unit converters based on the DC power supply voltages of the plurality of unit converters and an estimated value of the output active power. The control device for a multi-stage converter according to claim 4 or 5.   The gate signal generation unit sequentially replaces the gate signals to be assigned to the plurality of unit converters in a predetermined order at predetermined intervals, and combines gate signals assigned to the plurality of unit converters in a cycle corresponding to the number of stages. The control device for a multi-stage converter according to claim 4, further comprising a voltage adjustment unit configured to make a voltage adjustment equal to: