JP2019213122A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device including an output circuit suitable for high-speed operation.SOLUTION: A semiconductor device is connected to a first power supply voltage and a second power supply voltage lower than the first power supply voltage. The semiconductor device includes a driver circuit which receives input of an output signal of a circuit operating when receiving the second power supply voltage and outputs a signal which shifted a voltage level, and an output circuit which receives input of the output signal of the driver circuit. The output circuit includes a first transistor provided between the first power supply voltage and an output node, and a second transistor provided between the output node and a ground voltage. The driver circuit includes an intermediate voltage generation circuit which receives input of the output signal and converts the signal into a voltage level of an intermediate voltage, and a signal generation circuit which outputs a driving signal for driving the first transistor according to the intermediate voltage generated in the intermediate voltage generation circuit.SELECTED DRAWING: Figure 4

Description

  The present disclosure relates to a semiconductor device including an output circuit.

  In general, a semiconductor device capable of generating output voltages of a plurality of voltage levels is composed of a MOS transistor having a thick gate oxide film thickness so as to withstand high voltage conditions.

  However, when the semiconductor device is composed of a MOS transistor having a thick gate oxide film thickness, there is a problem that the operation speed is lowered or the circuit scale is increased. Therefore, it is necessary to improve the operation speed and suppress an increase in circuit scale by configuring the semiconductor device with a MOS transistor having a gate oxide film thickness as thin as possible.

  In this regard, Patent Document 1 discloses an output circuit composed of a MOS transistor having a thin gate oxide film thickness by adjusting a withstand voltage so as to withstand a high voltage condition.

JP 2013-21118A

  However, the output circuit has a problem that it is difficult to secure an operating current of a circuit that generates an intermediate voltage when the withstand voltage is adjusted, and may not be suitable for high-speed operation.

  The present disclosure has been made to solve the above-described problem, and provides a semiconductor device including an output circuit suitable for high-speed operation.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an aspect of the present disclosure is a semiconductor device connected to a first power supply voltage and a second power supply voltage lower than the first power supply voltage, and operates by receiving the supply of the second power supply voltage. A driver circuit that receives an output signal of the circuit and outputs a signal whose voltage level is shifted, and an output circuit that receives an input of the output signal of the driver circuit. The output circuit includes a first transistor provided between the first power supply voltage and the output node, and a second transistor provided between the output node and the ground voltage. The driver circuit receives an output signal and converts it to a voltage level of an intermediate voltage, and a signal generation that outputs a drive signal for driving the first transistor according to the intermediate voltage generated by the intermediate voltage generation circuit Circuit.

  According to an embodiment, the semiconductor device of the present disclosure can operate the output circuit at high speed.

It is a figure which illustrates notionally the structure of the liquid crystal panel system 100 according to Embodiment 1. FIG. It is a figure explaining a part of microcomputer 20 based on Embodiment 1. FIG. It is a figure explaining an example of the output circuit 40 of the microcomputer 20 based on Embodiment 1. FIG. FIG. 3 is a diagram illustrating a circuit configuration of a driver 61 based on the first embodiment. 3 is a circuit configuration diagram of a clamp voltage generation circuit 63 based on Embodiment 1. FIG. 6 is a diagram illustrating a potential of a driver 61 based on Embodiment 1. FIG. It is a figure explaining the structure of driver 61 # based on the modification of Embodiment 1. FIG. It is a figure explaining the structure of the driver 61A based on Embodiment 2. FIG.

  Embodiments will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a diagram conceptually illustrating the configuration of a liquid crystal panel system 100 according to the first embodiment.

  Referring to FIG. 1, a liquid crystal panel system 100 includes a liquid crystal panel 10 and a microcomputer 20 that transmits data to the liquid crystal panel 10.

  The microcomputer 20 transmits data to the liquid crystal panel 10 based on the LVDS (Low voltage differential signaling) method. LVDS is a relatively high-speed differential interface with small amplitude and low power consumption.

  On the liquid crystal panel 10 side, the transmitted data is received by the timing controller. The timing controller outputs the data to the column driver. The column driver drives a liquid crystal display (LCD). Thus, desired data is displayed on the LCD.

FIG. 2 is a diagram for explaining a part of the microcomputer 20 based on the first embodiment.
Referring to FIG. 2, the microcomputer 20 operates by receiving various power supplies.

  For example, the microcomputer 20 includes a core region 30 and an output circuit 40. The core region operates by being connected to the power supply voltage VDD2 and receiving the voltage supply.

The output circuit 40 is connected to the power supply voltage VDD1 and operates by receiving the voltage supply.
In this example, the power supply voltage VDD1 is higher than the power supply voltage VDD2.

For example, the power supply voltage VDD1 is 1.8V, and the power supply voltage VDD2 is 1.0V.
In this example, a case where a differential output signal is output from the output circuit 40 to the liquid crystal panel 10 is shown.

  FIG. 3 is a diagram illustrating an example of the output circuit 40 of the microcomputer 20 based on the first embodiment.

  Referring to FIG. 3, output circuit 40 includes a final stage circuit 62, a driver 61 that drives final stage circuit 62, and a clamp voltage generation circuit 63 that generates a clamp voltage.

The output circuit 40 receives a signal input from the core region 30.
The core region 30 is connected to the power supply voltage VDD2 and operates by receiving the voltage supply.

  In this example, the case where the input of the signal from an inverter (INV) is received is shown. Specifically, the case where signals S0, / S0 and signals S1, / S1 are input to the output circuit 40 from the core region 30 via an inverter (INV) is shown.

  The driver 61 outputs a drive signal for driving the transistor of the final stage circuit 62 according to the input of the signals S0 and / S0.

The clamp voltage generation circuit 63 generates a clamp voltage used for ensuring the withstand voltage.
Final stage circuit 62 includes P-channel MOS transistors MP2P, MP2N, MP3P, and MP3N, and N-channel MOS transistors MN2P, MN2N, MN3P, and MN3N.

  P-channel MOS transistors MP2P, MP2N, MP3P, MP3N and N-channel MOS transistors MN2P, MN2N, MN3P, MN3N are low breakdown voltage MOS transistors. Specifically, it is a MOS transistor provided corresponding to the power supply voltage VDD2. The MOS transistor provided corresponding to the power supply voltage VDD2 is a MOS transistor having a thin gate oxide film thickness as compared with the MOS transistor provided corresponding to the power supply voltage VDD1.

  P-channel MOS transistors MP2P and MP3P and N-channel MOS transistors MN2P and MN3P are connected in series between power supply voltage VDD1 and ground voltage GND.

  In parallel with the P-channel MOS transistors MP2P and MP3P and the N-channel MOS transistors MN2P and MN3P, the P-channel MOS transistors MP2N and MP3N and the N-channel MOS transistors MN2N and MN3N are connected in series between the power supply voltage VDD1 and the ground voltage GND. Connected.

  Data signal PAD0 is output from a connection node between P channel MOS transistor MP3P and N channel MOS transistor MN3P.

  Data signal PAD1 is output from a connection node between P channel MOS transistor MP3N and N channel MOS transistor MN3N.

The data signals PAD0 and PAD1 are output to the liquid crystal panel 10 as differential output signals.
P-channel MOS transistors MP2P and MP2N receive signals PSW_P and PSW_N from driver 61.

The signals PSW_P and PSW_N are complementary to each other.
P-channel MOS transistors MP3P and MP3N both receive clamp voltage ClampP from clamp voltage generation circuit 63 at their gates.

  N channel MOS transistors MN3P and MN3N both receive clamp voltage ClampN from clamp voltage generation circuit 63 at their gates.

  N-channel MOS transistors MN2P and MN2N receive signals S1 and / S1 from core region 30.

  With the input of the clamp voltages ClampP and ClampN, the breakdown voltage of the MOS transistor is ensured, and the final stage circuit 62 can be configured using the low breakdown voltage MOS transistor. As an example, the clamp voltage ClampP is set to 0.45 × power supply voltage VDD1 (1.8V). The clamp voltage ClampN is set to 0.55 × power supply voltage VDD1 (1.8 V). In addition, the said clamp voltage is an example and is not limited to the said value.

FIG. 4 is a diagram illustrating the circuit configuration of the driver 61 based on the first embodiment.
Referring to FIG. 4, driver 61 includes an intermediate voltage generation circuit 2 that converts signals S0 and / S0 into a voltage level of an intermediate voltage, and a signal generation that receives a signal from intermediate voltage generation circuit 2 and outputs a drive signal. Circuit 1.

  Intermediate voltage generation circuit 2 includes resistance elements R1 and R2, P channel MOS transistors MP1P and MP1N, and an N channel MOS transistor MN2.

Resistance element R1 is provided between power supply voltage VDD1 and internal node N0.
Resistance element R2 is provided between power supply voltage VDD1 and internal node N1 in parallel with resistance element R1.

  P-channel MOS transistor MP1P is connected between internal node N0 and internal node N2, and has its gate receiving signal S0.

  P channel MOS transistor MP1N is connected between internal node N1 and internal node N2, and has its gate receiving signal / S0.

  N-channel MOS transistor MN2 is connected between internal node N2 and ground voltage GND, and receives a mirror voltage from reference current generation circuit 50 at its gate.

  The reference current generation circuit 50 generates a reference current Iref2, and a mirror voltage for supplying the reference current is generated.

  The reference current generation circuit 50 may be provided in the output circuit 40 or may be provided in another circuit.

  N-channel MOS transistor MN2 receives the mirror voltage at its gate to realize the function of a constant current source. In this example, a case where a constant constant current Iref2 is supplied to the ground voltage GND side is shown. The mirror voltage may be changed according to manufacturing variations of MOS transistors and temperature conditions so as to supply a constant constant current Iref2.

  Intermediate voltage signals NP and NN obtained by shifting the voltage levels of the signals S0 and / S0 are output from the internal nodes N0 and N1 of the intermediate voltage generation circuit 2 to the signal generation circuit 1.

  Signal generation circuit 1 includes resistance elements R3 and R4, N-channel MOS transistors MN1P and MN1N, and MN1.

Resistance element R3 is provided between power supply voltage VDD1 and internal node N3.
Resistance element R4 is provided between power supply voltage VDD1 and internal node N4 in parallel with resistance element R3.

  N channel MOS transistor MN1P is connected between internal node N3 and internal node N5, and has its gate receiving signal NP.

  N channel MOS transistor MN1N is connected between internal node N4 and internal node N5, and has its gate receiving signal NN.

  N-channel MOS transistor MN1 is connected between internal node N5 and ground voltage GND, and receives a mirror voltage input from reference current generation circuit 50 at its gate.

  The reference current generation circuit 50 generates a reference current Iref1, and a mirror voltage for supplying the reference current is generated.

  N-channel MOS transistor MN1 receives the mirror voltage at its gate to realize the function of a constant current source. In this example, a case where a constant constant current Iref1 is supplied to the ground voltage GND side is shown. The mirror voltage may be changed according to manufacturing variations of MOS transistors and temperature conditions so as to supply a constant constant current Iref1.

  Signals PSW_P and PSW_N are output from the internal nodes N 3 and N 4 of the signal generation circuit 1 to the final stage circuit 62.

  The signals PSW_P and PSW_N are complementary signals and drive signals for driving the P-channel MOS transistors MP2P and MP2N of the final stage circuit 62.

FIG. 5 is a circuit configuration diagram of the clamp voltage generation circuit 63 based on the first embodiment.
Referring to FIG. 5, clamp voltage generation circuit 63 includes resistance elements R5 to R8 as an example.

  Resistance elements R5 to R8 are connected in series between power supply voltage VDD1 and ground voltage GND.

The clamp voltage is generated by resistance division of the resistance elements R5 to R8.
A clamp voltage ClampN is output from a connection node between the resistance element R5 and the resistance element R6.

  A clamp voltage ClampP50 is output from a connection node between the resistance element R6 and the resistance element R7.

  A clamp voltage ClampP is output from a connection node between the resistance element R7 and the resistance element R8.

  The clamp voltages ClampP and ClampN are input to the gate of the MOS transistor of the final stage circuit 62.

  The clamp voltage generation circuit 63 has been described as a configuration including the resistance elements R5 to R8 as an example, but is not particularly limited to this configuration, and other configurations may be employed.

FIG. 6 is a diagram illustrating the potential of the driver 61 based on the first embodiment.
As shown in FIG. 6, an example of the potential of the driver 61 is shown.

A case where the voltages of the signals S0 and / S0 are 1.0V and 0V will be described.
Specifically, the power supply voltage VDD1 is 1.8V, and the power supply voltage VDD2 is 1.0V.

  The resistance elements R1 and R2 are 1.5 kΩ. The resistance elements R3 and R4 are 250Ω.

  The constant current Iref1 flowing through the constant current source is set to 5 mA. The constant current Iref2 is set to 1 mA.

The intermediate voltage generation circuit 2 will be described.
In this case, the potentials of nodes N1 and N0 are as follows when signals NN and NP are at "L" level and "H" level.

The potential on the “L” level side of the node N1 is 1.8V− (Iref2 / 2 + ΔIds) × 1.5 kΩ.
The potential on the "H" level side of the node N0 is 1.8V- (Iref2 / 2-ΔIds) × 1.5 kΩ
ΔIds is a change in the drain current of the P-channel MOS transistor, and indicates a change determined by GM (= ΔIds / ΔVgs) of the P-channel MOS transistor.

  ΔVgs is given by a signal driven at the voltage level of the power supply voltage Vdd2 of the low potential system (for example, 1V system).

In this example, a case where ΔIds is set to 0.3 mA will be described as an example.
In this case, the potential of the node N1 is set to 0.6V. Further, the potential of the node N0 is set to 1.5V.

Next, the signal generation circuit 1 will be described.
The N-channel MOS transistor of the signal generation circuit 1 operates based on the “H” level and “L” level signals set at the nodes N0 and N1.

  Specifically, when the signal is at “L” level, the N-channel MOS transistor of signal generation circuit 1 is off, and when it is at “H” level, the N-channel MOS transistor is turned on.

  Based on the operation of the N-channel MOS transistor, the potentials of the nodes N3 and N4 are set as follows.

The potential on the “H” level side of the node N4 is 1.8V.
The potential on the “L” level side of the node N3 is 1.8V-Iref1 × 250Ω.
The potential of the node N3 is set to 0.55V.

  It is assumed that the breakdown voltage of each MOS transistor of the driver 61 is set to 1.27V.

  In this example, as an example, the sizes of P-channel MOS transistors MP1P and MP1N, N-channel MOS transistors MN1P and MN1N, and N-channel MOS transistors MN1 and MN2 are adjusted. The source voltage (node N2) of the constant current source is set to 0.6V. The source voltage (node N5) of the constant current source is set to 0.55V.

  Based on the above, the gate-source voltage Vgs, the gate back bias voltage Vgb, and the gate drain voltage Vdg of the N-channel MOS transistor MN1P of the signal generation circuit 1 are expressed by the following equations.

Vgs = potential on the “H” level side of the node N0−source voltage of the constant current source = 0.95V
Vgb = Vgs
Vdg = “H” level side potential of the node N0− “L” level side potential of the node N3 = 0.95V
Further, the gate-source voltage Vsg, the gate-drain voltage Vgd, and the gate back bias voltage Vbg of the P-channel MOS transistor MP1P are expressed by the following equations.

Vsg = potential on the “H” level side of the node N0−potential of the signal S0 = 0.5V
Vgd = potential of signal S0−source voltage of constant current source = 0.4V
Vbg = Vsg
Further, the gate-source voltage Vgs, the gate back bias voltage Vgb, and the gate drain voltage Vdg of the N-channel MOS transistor MN1N are expressed by the following equations.

Vgs = potential on the “L” level side of the node N1−source voltage of the constant current source = 0.05V
Vgb = Vgs
Vdg = potential on the “H” level side of the node N4−potential on the “L” level side of the node N1 = 1.2V
Further, the gate-source voltage Vgs, the gate back bias voltage Vgb, and the gate drain voltage Vds of the N-channel MOS transistor MP1N are expressed by the following equations.

Vgs = potential of signal / S0−potential on the “L” level side of node N1 = −0.6V
Vsd = signal / S0 potential−constant current source voltage = −0.6V
Vgb = Vgs
Therefore, since the breakdown voltage of each MOS transistor is 1.27 V or less, it is possible to ensure the breakdown voltage of the N-channel MOS transistor and the P-channel MOS transistor.

  Note that the case where the voltages of the signals S0 and / S0 are 1.0 V and 0 V has been described, but the case where the voltages of the signals S0 and / S0 are inverted is basically the same as only the potential relationship is switched.

  According to the driver 61 according to the first embodiment, the signal generation circuit 1 and the intermediate voltage generation circuit 2 operate as independent circuits.

The signal generation circuit 1 and the intermediate voltage generation circuit 2 have independent constant current sources.
Specifically, the signal generation circuit 1 operates with a constant current Iref1. The intermediate voltage generation circuit 2 operates with a constant current Iref2.

  The conventional circuit has difficulty in securing the operating current and may not be suitable for high-speed operation. However, the configuration based on Embodiment 1 can operate at high speed because the operating current is stably supplied.

  In this example, a differential interface that outputs a differential output signal has been described. However, the present invention is not limited to this configuration, and a single-ended output circuit may be used.

  For example, the configuration is such that the MOS transistors on the other side of the final stage circuit 62 provided in parallel with each other are excluded. Specifically, the P channel MOS transistors MP2N and MP3N and the N channel MOS transistors MN2N and MN3N may be excluded. Alternatively, the P channel MOS transistors MP2P and MP3P and the N channel MOS transistors MN2P and MN3P may be omitted.

(Modification of Embodiment 1)
FIG. 7 is a diagram illustrating the configuration of the driver 61 # based on the modification of the first embodiment.

  Referring to FIG. 7, driver 61 # is different in that the constant current source of intermediate voltage generation circuit 2 is changed to resistance element R10. Since other configurations are the same, detailed description thereof will not be repeated.

  With this structure, the circuit can be simplified and the area can be reduced.

(Embodiment 2)
FIG. 8 is a diagram illustrating the configuration of the driver 61A based on the second embodiment.

  Referring to FIG. 8, the driver 61A according to the second embodiment has a protection function when the operation is stopped.

  Specifically, P channel MOS transistors PT1, PT2, PT3 are further provided.

  Specifically, P-channel MOS transistor PT3 is provided between power supply voltage VDD1 and resistance elements R1 and R2, and its gate receives a control signal that is turned off when driver 61A stops operating. On the other hand, the control signal makes P channel MOS transistor PT3 conductive during operation.

  P channel MOS transistor PT1 receives clamp voltage ClampP50 as a source side. The drain side is connected to node N0.

  The gate receives a control signal for making P channel MOS transistor PT1 conductive when driver 61A stops operating.

  P-channel MOS transistor PT2 receives clamp voltage ClampP50 as a source side. The drain side is connected to node N1.

  The gate receives a control signal for making P channel MOS transistor PT2 conductive when driver 61A stops operating.

  When the P channel MOS transistors PT1 and PT2 are turned on, the clamp voltage ClampP50 is supplied to the nodes N0 and N1. As an example, the clamp voltage ClampPP50 is set to 0.5 × power supply voltage VDD1 (1.8V) = 0.9V.

Further, the P channel MOS transistor PT3 is turned off.
As a result, the voltage at the internal node of driver 61A can be maintained at an intermediate voltage, and a voltage exceeding the breakdown voltage of the MOS transistor can be prevented from being applied to each MOS transistor.

  P-channel MOS transistors PT1 and PT2 can be formed of MOS transistors having a thick gate oxide film instead of MOS transistors having a thin gate oxide film in terms of withstand voltage.

  As mentioned above, although this indication was concretely demonstrated based on embodiment, it cannot be overemphasized that this indication is not limited to embodiment, and can be variously changed in the range which does not deviate from the summary.

  1 signal generation circuit, 2 intermediate voltage generation circuit, 10 liquid crystal panel, 20 microcomputer, 30 core region, 40 output circuit, 50 reference current generation circuit, 61, 61A driver, 62 final stage circuit, 63 clamp voltage generation circuit, 100 liquid crystal Panel system.

Claims (13)

A semiconductor device connected to a first power supply voltage and a second power supply voltage lower than the first power supply voltage,
A driver circuit which receives an input of an output signal of a circuit which operates by receiving the supply of the second power supply voltage, and outputs a signal whose voltage level is shifted;
An output circuit that receives an input of an output signal of the driver circuit,
The output circuit is
A first transistor provided between the first power supply voltage and an output node;
A second transistor provided between the output node and a ground voltage;
The driver circuit is
An intermediate voltage generating circuit that receives an input of the output signal and converts the voltage to a voltage level of an intermediate voltage;
And a signal generation circuit that outputs a drive signal for driving the first transistor according to the intermediate voltage generated by the intermediate voltage generation circuit.   The semiconductor device according to claim 1, wherein the intermediate voltage generation circuit includes a first constant current source that supplies a predetermined constant current.   The semiconductor device according to claim 2, wherein the signal generation circuit includes a second constant current source that supplies a predetermined constant current. The output circuit is
A third transistor for securing a breakdown voltage between the first transistor and the output node;
The semiconductor device according to claim 1, further comprising a fourth transistor for securing a breakdown voltage between the output node and the second transistor.     The semiconductor device according to claim 4, wherein the first to fourth transistors are low breakdown voltage transistors corresponding to the first power supply voltage.   The semiconductor device according to claim 4, wherein a clamp voltage is input to gates of the third and fourth transistors. The intermediate voltage generation circuit includes:
A first resistance element connected to the second power supply voltage;
A fifth transistor connected in series with the first resistive element;
A second resistive element connected to the second power supply voltage in parallel with the first resistive element;
A sixth transistor connected in series with the second resistive element;
The fifth and sixth transistors are connected to the first constant current source,
The gates of the fifth and sixth transistors receive the output signal and its inverted output signal, respectively.
The signal generation circuit includes:
A third resistance element connected to the second power supply voltage;
A seventh transistor connected in series with the third resistive element;
A fourth resistance element connected to the second power supply voltage in parallel with the third resistance element;
An eighth transistor connected in series with the fourth resistive element;
The seventh and eighth transistors are connected to the second constant current source,
The gates of the seventh and eighth transistors receive signals from the connection node of the first resistance element and the fifth transistor and the connection node of the second resistance element and the sixth transistor, respectively. received,
The first transistor receives the intermediate voltage input from a connection node between the third resistance element and the seventh transistor or a connection node between the fourth resistance element and the eighth transistor. The semiconductor device according to claim 3.   The semiconductor device according to claim 7, wherein the fifth to eighth transistors are low breakdown voltage transistors. The first, third, fifth and sixth transistors are first conductivity type transistors,
The semiconductor device according to claim 7, wherein the second, fourth, seventh, and eighth transistors are transistors of a second conductivity type. A reference current generation circuit for generating a reference current;
4. The semiconductor device according to claim 3, wherein each of the first and second constant current sources includes a transistor having a gate receiving a mirror voltage generated by the reference current generation circuit.   The semiconductor device according to claim 1, wherein the intermediate voltage generation circuit includes a resistance element for setting a predetermined current amount.   The intermediate voltage generation circuit further includes a ninth transistor for stopping supply of current between the second power supply voltage and the first and second resistance elements when operation is stopped. Semiconductor device.   13. The semiconductor device according to claim 12, wherein the intermediate voltage generation circuit further includes a protection circuit for setting the connection node to an intermediate potential when the operation is stopped.

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