JP2019211658A - Display device and electronic apparatus - Google Patents

Abstract

To provide a display device capable of performing image processing.SOLUTION: Each pixel included in a display device is provided with a storage node, and the storage node holds a desired correction signal. The correction signal is calculated by an external device and written into each pixel. The correction signal is added by capacitive coupling to an image signal, and supplied to a display element. The display element can display a corrected image. The correction allows the image to be up-converted, etc.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a display device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, A driving method or a manufacturing method thereof can be given as an example.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.

A technique for forming a transistor using a metal oxide formed over a substrate has attracted attention. For example, Patent Documents 1 and 2 disclose a technique in which a transistor using zinc oxide or an In—Ga—Zn-based oxide is used as a switching element of a pixel of a display device.

Further, Patent Document 3 discloses a memory device in which a transistor having an extremely low off-state current is used for a memory cell.

JP 2007-123861 A JP 2007-96055 A JP 2011-119694 A

In display devices, higher resolution has been developed, and hardware capable of displaying at 8K4K (pixel number: 7680 × 4320) resolution or higher has been developed. On the other hand, since the number of high-resolution image sources is enormous, it is necessary to arrange peripheral technologies such as an imaging device, a storage device, and a communication device in order to disseminate them in general.

Another technique for generating a high-resolution image source is image correction such as up-conversion. By performing image correction, a low-resolution image can be pseudo-converted into a high-resolution image. Since the image correction is performed by a peripheral device of the display device, a conventional technique can be used for a device that handles an image source before image correction.

However, a device that performs image correction analyzes large amounts of image data and generates new image data, which causes a problem of increased circuit scale and power consumption. In addition, real-time processing cannot catch up, and display delay may occur.

Image correction has such problems, but for example, there is a possibility that problems such as power consumption and delay may be alleviated by distributing functions related to image correction to a plurality of devices. In addition, peripheral devices can be reduced by providing the display device with a function related to image correction.

Therefore, an object of one embodiment of the present invention is to provide a display device capable of performing image processing. Another object is to provide a display device that can perform an up-conversion operation.

Another object is to provide a display device with low power consumption. Another object is to provide a highly reliable display device. Another object is to provide a novel display device or the like. Another object is to provide a method for driving the display device. Another object is to provide a novel semiconductor device or the like.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention relates to a display device capable of performing image processing. Alternatively, the present invention relates to a display device capable of correcting image data.

One embodiment of the present invention is a display device including a first pixel, a second pixel, a third pixel, and a light source. The first pixel includes the first pixel circuit and the first pixel circuit. The second pixel has a second pixel circuit and a second light conversion layer, the third pixel has a third pixel circuit, and the light source is the first light source. Thru | or the function which injects blue light into the 3rd pixel, a 1st pixel has a function which converts the said blue light into red light, and inject | emits outside, and a 2nd pixel has said blue light The third pixel has a function of transmitting the blue light and emitting the light to the outside, and the first to third pixel circuits include display elements. And the first to third pixel circuits have a function of storing a first signal and a function of generating a third signal by adding a second signal to the first signal. Is a display device having a function of performing an operation based on the third signal.

Blue light has a peak wavelength in the range of 460 nm to 500 nm, the red light has a peak wavelength in the range of 610 nm to 780 nm, and the green light has a peak wavelength in the range of 500 nm to 570 nm.

The first to third pixel circuits each include a first transistor, a second transistor, a third transistor, a first capacitor element, a second capacitor element, and a display element. One of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor, and the other electrode of the first capacitor is connected to one of the source and the drain of the second transistor. One of the source and the drain of the second transistor is electrically connected to the gate of the third transistor, and one of the source and the drain of the third transistor is one of the second capacitors. The one electrode of the second capacitor element is electrically connected to the one electrode of the display element.

At least the second transistor and the third transistor include a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr). , La, Ce, Nd or Hf).

A liquid crystal element can be used as the display element.

By using one embodiment of the present invention, a display device capable of performing image processing can be provided. Alternatively, a display device that can perform an up-conversion operation can be provided.

Alternatively, a display device with low power consumption can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device or the like can be provided. Alternatively, a method for driving the display device can be provided. Alternatively, a novel semiconductor device or the like can be provided.

FIG. 6 illustrates a pixel circuit. 6 is a timing chart illustrating the operation of a pixel circuit. 4A and 4B illustrate a pixel circuit and a timing chart. FIG. 6 illustrates a pixel circuit. FIG. 11 is a block diagram illustrating a display device. The figure explaining a pixel array. The figure explaining the simulation result of a pixel. The figure explaining the simulation result of a pixel. The figure explaining the simulation result of a pixel. The figure explaining the simulation result of a pixel. FIG. 10 illustrates a display device. The figure explaining a touch panel. FIG. 10 illustrates a display device. FIG. 10 illustrates a display device. 6A and 6B illustrate a transistor. 6A and 6B illustrate a transistor. 10A and 10B each illustrate an electronic device.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. Note that hatching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings.

(Embodiment 1)
In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

One embodiment of the present invention is a display device having a function for adding correction data to image data. Each pixel is provided with a storage node, and desired correction data is held in the storage node. The correction data is generated by an external device and written to each pixel.

The correction data is added to the image data by capacitive coupling and supplied to the display element. Therefore, the corrected image can be displayed on the display element. With this correction, image up-conversion can be performed. Alternatively, image brightness correction and the like can be performed.

In one embodiment of the present invention, the data potential that can be supplied to the display element is higher than the potential of the correction data or the potential of the image data. That is, a potential higher than the output of the row driver that outputs the data potential can be supplied to the display element.

Therefore, a high voltage can be generated even if a general-purpose driver IC is used as the low driver. For example, a liquid crystal element that requires a high voltage for gradation control can be driven. Alternatively, since the voltage supplied from the row driver to drive a general liquid crystal element can be reduced to about ½, the power consumption of the display device can be reduced.

FIG. 1 illustrates a pixel 11a that can be used in the display device of one embodiment of the present invention. The pixel 11 a includes a transistor 101, a transistor 102, a transistor 103, a capacitor 104, a capacitor 105, and a liquid crystal element 106.

One of a source and a drain of the transistor 101 is electrically connected to one electrode of the capacitor 104. The other electrode of the capacitor 104 is electrically connected to one of a source and a drain of the transistor 102. One of the source and the drain of the transistor 102 is electrically connected to one of the source and the drain of the transistor 103. The other of the source and the drain of the transistor 103 is electrically connected to one electrode of the capacitor 105. One electrode of the capacitor 105 is electrically connected to one electrode of the liquid crystal element 106.

Here, a wiring to which the other electrode of the capacitor 104, one of the source and the drain of the transistor 102, and one of the source and the drain of the transistor 103 are connected is a node NM. A wiring connected to one of the source and the drain of the transistor 103, one electrode of the capacitor 105, and one electrode of the liquid crystal element 106 is a node NA.

A gate of the transistor 101 is electrically connected to the wiring 122. A gate of the transistor 102 is electrically connected to the wiring 121. A gate of the transistor 103 is electrically connected to the wiring 126. The other of the source and the drain of the transistor 101 is electrically connected to the wiring 125. The other of the source and the drain of the transistor 102 is electrically connected to the wiring 124.

The other electrode of the capacitor 105 is electrically connected to the common wiring 132. The other electrode of the liquid crystal element 106 is electrically connected to the common wiring 133. Note that an arbitrary potential can be supplied to the common wirings 132 and 133, and they may be electrically connected.

The wirings 121, 122, and 126 can function as signal lines for controlling the operation of the transistors. The wiring 125 can function as a signal line for supplying image data. The wiring 124 can function as a signal line for writing data to the node NM.

The node NM is a storage node, and the data supplied to the wiring 124 can be written to the node NM by turning on the transistor 102 and turning off the transistor 103. By using transistors with extremely low off-state current as the transistors 102 and 103, the potential of the node NM can be held for a long time. As the transistor, for example, a transistor using a metal oxide for a channel formation region (hereinafter referred to as an OS transistor) can be used.

Note that an OS transistor may be applied to another transistor included in the pixel. Alternatively, a transistor including Si in a channel formation region (hereinafter, Si transistor) may be used as a transistor included in a pixel. Alternatively, both an OS transistor and a Si transistor may be used. Note that examples of the Si transistor include a transistor including amorphous silicon, a transistor including crystalline silicon (typically, low-temperature polysilicon), and a transistor including single crystal silicon.

In the case where a reflective liquid crystal element is used for the display element, a silicon substrate can be used, and the display element can be formed to have a region where the Si transistor and the OS transistor overlap. Accordingly, the pixel density can be improved even when the number of transistors is relatively large.

As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium. For example, a CAAC-OS or a CAC-OS described later can be used. A CAAC-OS is suitable for a transistor or the like in which atoms constituting a crystal are stable and reliability is important. In addition, since the CAC-OS exhibits high mobility characteristics, it is suitable for a transistor that performs high-speed driving.

Since the OS transistor has a large energy gap, it exhibits extremely low off-state current characteristics. In addition, the OS transistor has characteristics different from those of the Si transistor such that impact ionization, avalanche breakdown, a short channel effect, and the like do not occur, and a circuit with high breakdown voltage and high reliability can be formed. In addition, variations in electrical characteristics due to non-uniformity of crystallinity, which is a problem in Si transistors, are less likely to occur in OS transistors.

The semiconductor layer included in the OS transistor includes, for example, an In-M-Zn-based oxide containing indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It can be set as the film | membrane described by.

In the case where the oxide semiconductor included in the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is In ≧ M, Zn It is preferable to satisfy ≧ M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 3, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8 etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.

As the semiconductor layer, an oxide semiconductor with low carrier density is used. For example, the semiconductor layer has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, more preferably 1 × 10 ¹³ / cm ³ or less, more preferably 1 × 10 ¹¹ / cm 3. ³ or less, more preferably less than 1 × 10 ¹⁰ / cm ³ , and an oxide semiconductor having a carrier density of 1 × 10 ⁻⁹ / cm ³ or more can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Accordingly, it can be said that the oxide semiconductor has stable characteristics because the impurity concentration is low and the density of defect states is low.

Note that the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (such as field-effect mobility and threshold voltage) of the transistor. In addition, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the semiconductor layer have appropriate carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like. .

In the oxide semiconductor constituting the semiconductor layer, when silicon or carbon, which is one of Group 14 elements, is included, oxygen deficiency increases and the n-type semiconductor is formed. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when alkali metal and alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, which may increase off-state current of the transistor. For this reason, the concentration of alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. To.

In addition, when nitrogen is contained in the oxide semiconductor included in the semiconductor layer, electrons as carriers are generated, the carrier density is increased, and the oxide semiconductor is easily n-type. As a result, a transistor including an oxide semiconductor containing nitrogen is likely to be normally on. Therefore, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

The semiconductor layer may have a non-single crystal structure, for example. The non-single-crystal structure includes, for example, a CAAC-OS (C-Axis Crystalline Oxide Semiconductor Semiconductor or C-Axis Aligned and A-B-Plane Annealed Crystal Oxide Crystal Structure, c-axis oriented crystal, Includes a microcrystalline structure or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

An oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystal component. Alternatively, an amorphous oxide film has, for example, a completely amorphous structure and does not have a crystal part.

Note that the semiconductor layer may be a mixed film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Good. For example, the mixed film may have a single-layer structure or a stacked structure including any two or more of the above-described regions.

Hereinafter, a structure of a CAC (Cloud-Aligned Composite) -OS which is one embodiment of a non-single-crystal semiconductor layer is described.

The CAC-OS is one structure of a material in which an element included in an oxide semiconductor is unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as a mosaic or patch.

Note that the oxide semiconductor preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. One kind selected from the above or a plurality of kinds may be included.

For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). _X1 (X1 is greater real than 0) and.), or indium zinc oxide _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic _{InO X1} or _in X2 _Zn Y2 _{O Z2,} is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.

That, CAC-OS includes a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is the main component region is a composite oxide semiconductor having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

On the other hand, CAC-OS relates to a material structure of an oxide semiconductor. CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn and O, and nanoparticles mainly composed of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.

Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.

Incidentally, a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component region, in some cases clear boundary can not be observed.

Instead of gallium, selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. In the case where one or a plurality of types are included, the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.

The CAC-OS can be formed by a sputtering method under a condition where the substrate is not intentionally heated, for example. In the case where a CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. For example, the flow rate ratio of the oxygen gas is 0% or more and less than 30%, preferably 0% or more and 10% or less. .

The CAC-OS is characterized in that no clear peak is observed when it is measured using a θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.

In addition, in the CAC-OS, in an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-shaped high luminance region and a plurality of regions in the ring region are provided. A bright spot is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

In addition, for example, in a CAC-OS in an In—Ga—Zn oxide, GaO _X3 is a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region and the region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 are unevenly distributed and mixed.

The CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO _X3 or the like is a main component and a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is a region having higher conductivity than a region containing GaO _X3 or the like as a main component. _That, In _{X2 Zn} Y2 _{O Z2} or _{InO X1,} is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Therefore, a region where In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility (μ) can be realized.

On the other hand, areas such as _{GaO X3} is the main _component, as compared to the In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component area, it is highly regions insulating. That is, a region containing GaO _X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _{X3 and the} like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act complementarily, thereby increasing the An on-current (I _on ) and high field effect mobility (μ) can be realized.

In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is suitable as a constituent material for various semiconductor devices.

In the pixel 11a, data written to the node NM is capacitively coupled with image data supplied from the wiring 125 and can be output to the node NA. Note that the transistor 101 can have a function of selecting pixels and supplying image data. The transistor 103 can function as a switch that controls operation of the liquid crystal element 106.

When the data written from the wiring 124 to the node NM is larger than the threshold value for operating the liquid crystal element 106, the liquid crystal element 106 may operate before the image data is written. Therefore, it is preferable to provide the transistor 103 and turn on the transistor 103 and operate the liquid crystal element 106 after the potential of the node NM is determined.

That is, if desired correction data is stored in the node NM, the correction data can be added to the supplied image data. Since the correction data may be attenuated due to elements on the transmission path, it is preferable to generate the correction data in consideration of the attenuation.

Details of the operation of the pixel 11a will be described with reference to timing charts shown in FIGS. Note that positive and negative arbitrary data can be used as the correction data (Vp) supplied to the wiring 124. Here, a case where positive data is supplied will be described. In the following description, the high potential is represented by “H” and the low potential is represented by “L”.

Note that detailed changes due to circuit configuration, operation timing, and the like are not taken into account in potential distribution, coupling, or loss. In addition, although the potential change due to capacitive coupling depends on the capacitance ratio between the supply side and the supply side, the capacitance values of the nodes NM and NA are assumed to be sufficiently small for the sake of clarity.

First, an operation for writing the correction data (Vp) to the node NM will be described with reference to FIG. In addition, when aiming at correction of image data such as up-conversion, it is preferable to perform the operation for each frame.

At time T1, when the potential of the wiring 121 is “H”, the potential of the wiring 122 is “L”, the potential of the wiring 125 is “L”, and the potential of the wiring 126 is “H”, the transistor 102 and the transistor 103 are turned on, The potential of the node NA is the potential of the wiring 124. At this time, the operation of the liquid crystal element 106 can be reset by setting the potential of the wiring 124 to a reset potential (for example, a reference potential such as 0 V).

Prior to time T1, the display operation of the liquid crystal element 106 in the previous frame is being performed.

At time T2, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “H”, the potential of the wiring 125 is “L”, and the potential of the wiring 126 is “L”, the transistor 101 is turned on and the capacitor 104 The potential of the other electrode is “L”. This operation is a reset operation for performing a subsequent capacitive coupling operation.

At time T3, when the potential of the wiring 121 is “H”, the potential of the wiring 122 is “H”, the potential of the wiring 125 is “L”, and the potential of the wiring 126 is “L”, the transistor 102 is turned on and the wiring 124 The potential (correction data (Vp)) is written to the node NM. Note that the potential of the wiring 124 is preferably set to a desired value (correction data (Vp)) after time T2 and before T3.

At time T4, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “H”, the potential of the wiring 125 is “L”, and the potential of the wiring 126 is “L”, the transistor 102 is turned off and the node NM Correction data (Vp) is held.

At time T5, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “L”, the potential of the wiring 125 is “L”, and the potential of the wiring 126 is “L”, the transistor 101 is turned off, and the correction data The (Vp) write operation ends.

Next, the image data (Vs) correction operation and the display operation of the liquid crystal element 106 will be described with reference to FIG.

At time T11, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “L”, the potential of the wiring 124 is “L”, and the potential of the wiring 126 is “H”, the transistor 103 is turned on and the node NA is connected. The potential of the node NM is distributed. The correction data (Vp) held in the node NM is preferably set in consideration of distribution to the node NA.

At time T12, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “H”, the potential of the wiring 124 is “L”, and the potential of the wiring 126 is “H”, the transistor 101 is turned on and the capacitor 104 Due to the capacitive coupling, the potential of the wiring 125 is added to the potential of the node NA. That is, the node NA becomes a potential (Vs + Vp) ′ obtained by adding the potential obtained by distributing the correction data (Vp) to the image data (Vs). It should be noted that the potential (Vs + Vp) 'includes potential fluctuations due to capacitive coupling of inter-wiring capacitance.

At time T13, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “L”, the potential of the wiring 124 is “L”, and the potential of the wiring 126 is “L”, the transistor 101 is turned off and the node NA Is held at the potential (Vs + Vp) ′. Then, display operation is performed in the liquid crystal element 106 in accordance with the potential.

The above is the description of the image data (Vs) correction operation and the display operation of the liquid crystal element 106. Although the correction data (Vp) writing operation and the image data (Vs) input operation described above may be performed continuously, the image data is written after the correction data (Vp) is written to all pixels. An input operation of (Vs) may be performed. Although details will be described later, in one embodiment of the present invention, the same image data can be supplied to a plurality of pixels at the same time, so that the operation speed can be improved by writing correction data (Vp) to all the pixels first. it can.

Note that when an operation such as image correction is not performed, the display operation by the liquid crystal element 106 may be performed by supplying image data to the wiring 124 and controlling conduction and non-conduction of the transistors 102 and 111. At this time, the transistor 101 may be always non-conductive.

The pixel of one embodiment of the present invention can have a structure of the pixel 11b illustrated in FIG. The pixel 11b has a configuration in which the transistor 103 and the wiring 126 are omitted from the pixel 11a.

The transistor 103 in the pixel 11a is a switch for preventing the liquid crystal element 106 from being inadvertently operated by supplying correction data (Vp). However, if the visual recognition can be prevented even when the liquid crystal element 106 is operated, the transistor 103 is changed. It can be omitted. For example, an operation such as turning off the backlight when the correction data (Vp) is supplied may be used in combination. It is also effective when using a liquid crystal element with a low operating speed.

Alternatively, a structure in which the capacitor 105 is omitted may be employed as in a pixel 11b ′ illustrated in FIG. As described above, an OS transistor can be used as a transistor connected to the node NM. Since the OS transistor has an extremely small leakage current, image data can be held for a relatively long time even when the capacitor 105 functioning as a holding capacitor is omitted.

This configuration is also effective when the frame frequency is high and the image data holding period is relatively short, such as field sequential driving. By omitting the capacitor 105, the aperture ratio can be improved. Alternatively, the transmittance of the pixel can be improved. Note that a structure in which the capacitor 105 is omitted may be applied to other pixel circuit structures described in this specification.

The correction operation of the image data (Vs) of the pixel circuit shown in FIGS. 3A and 3B and the display operation of the liquid crystal element 106 will be described with reference to FIGS.

At time T1, when the potential of the wiring 121 is “H”, the potential of the wiring 122 is “L”, the potential of the wiring 124 is “L”, and the potential of the wiring 125 is “L”, the transistor 102 is turned on and the node NA The potential is the potential of the wiring 124. At this time, the operation of the liquid crystal element 106 can be reset by setting the potential of the wiring 124 to a reset potential (eg, “L”).

Prior to time T1, the display operation of the liquid crystal element 106 in the previous frame is being performed.

At time T2, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “H”, the potential of the wiring 124 is “Vp”, and the potential of the wiring 125 is “L”, the transistor 101 is turned on and the capacitor 104 The potential of the other electrode is “L”. This operation is a reset operation for performing a subsequent capacitive coupling operation.

At time T3, when the potential of the wiring 121 is “H”, the potential of the wiring 122 is “H”, the potential of the wiring 124 is “Vp”, and the potential of the wiring 125 is “L”, the potential of the wiring 124 at the node NA (correction) Data (Vp)) is written.

At time T4, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “H”, the potential of the wiring 124 is “Vp”, and the potential of the wiring 125 is “L”, the transistor 102 is turned off and the node NA Correction data (Vp) is held.

At time T5, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “L”, the potential of the wiring 125 is “L”, and the potential of the wiring 126 is “L”, the transistor 101 is turned off, and the correction data The (Vp) write operation ends.

Next, the image data (Vs) correction operation and the display operation of the liquid crystal element 106 will be described. Note that a desired potential is supplied to the wiring 125 at an appropriate timing.

At time T11, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “H”, and the potential of the wiring 124 is “L”, the transistor 101 is turned on, and the potential of the node NA is increased by capacitive coupling of the capacitor 104. The potential of the wiring 125 is added. That is, the node NA becomes a potential (Vs + Vp) ′ obtained by adding the correction data (Vp) to the image data (Vs). It should be noted that the potential (Vs + Vp) 'includes potential fluctuations due to capacitive coupling of inter-wiring capacitance.

At time T12, when the potential of the wiring 121 is “L”, the potential of the wiring 122 is “L”, and the potential of the wiring 124 is “L”, the transistor 101 is turned off and the potential (Vs + Vp) ′ is held at the node NM. The Then, display operation is performed in the liquid crystal element 106 in accordance with the potential.

The pixel of one embodiment of the present invention can have a structure of the pixel 11c illustrated in FIG. The pixel 11c has a configuration in which a transistor 107 and a wiring 130 are added to the pixel 11a.

In the pixel 11 c, the reset potential of the liquid crystal element 106 can be reset by supplying a reset potential to the wiring 130 and turning on the transistor 107. With this structure, the potential rewriting operation of the node NM and the node NA can be controlled independently, and the display operation period of the liquid crystal element 106 can be extended.

In the case where an operation such as image correction is not performed, the display operation by the liquid crystal element 106 may be performed by supplying image data from the wiring 130 and controlling conduction and non-conduction of the transistor 107. At this time, the transistor 103 may be kept off at all times.

The pixel of one embodiment of the present invention can have a structure of the pixel 11d illustrated in FIG. The pixel 11d has a configuration in which a back gate is provided for each transistor. The back gate is electrically connected to the front gate and has an effect of increasing the on-current. Alternatively, the back gate may be supplied with a constant potential different from that of the front gate. With this structure, the threshold voltage of the transistor can be controlled. Note that although FIG. 4B illustrates a structure in which all transistors have a back gate, a transistor without a back gate may be included. In addition, the structure in which the transistor includes a back gate is also effective for other pixel circuits in this embodiment.

In addition, the liquid crystal element 106 used in the display device of one embodiment of the present invention preferably performs AC driving in which the polarity is reversed for each frame in order to prevent burn-in. For example, when the same image is displayed in successive frames, the operation shown in Table 1 or Table 2 may be performed. Note that a and b shown in the table represent specific potentials, and potential loss at the node NA is omitted.

Table 1 shows an example in which an operation using positive polarity data is performed in the Nth frame. In the (N + 1) th frame, an operation using negative polarity data shown in modes A, B, or C is performed, and correction data (Vp) and / or an image are set so that the absolute values of the potentials of the Nth frame and the node NA are equal. Data (Vs) may be adjusted and supplied. Table 2 shows an example of an operation using negative polarity data in the Nth frame. In the (N + 1) th frame, if the operation is performed so that the absolute values of the potentials of the Nth frame and the node NA are equal. Good. In this operation, the common potential is not changed and is constant.

In the case of operating in the mode B, the image data (Vs) is adjusted, so that a still image or the like can be displayed while rewriting the correction data (Vp) between frames.

5A to 5C are block diagrams of a display device to which the pixel 11a, the pixel 11b, or the pixel 11c can be applied. Each display device will be described below. In addition, description of the element which overlaps between drawings is abbreviate | omitted.

FIG. 5A illustrates an example of a display device including a pixel array in which the pixels 11 are provided in a matrix, a row driver 12, a column driver 13, a circuit 14, and a circuit 15. Wirings 121, 122, 126 and the like are electrically connected to the row driver 12. Wirings 124 and 125 are electrically connected to the column driver 13. As the pixel 11, the pixel 11a or the pixel 11b can be applied.

For example, a shift register circuit can be used for the row driver 12 and the column driver 13. The circuit 14 has a function of generating correction data. The circuit 14 can also be referred to as an external device for generating correction data. Further, the circuit 15 can supply a reset potential Sr for resetting the operation of the liquid crystal element 106 to the column driver 13.

Image data S 1 is input to the circuit 14, and the image data S 1 and the generated correction data W are output to the column driver 13. The image data S1 may be input to the column driver 13 without going through the circuit 14.

The circuit 14 may have a neural network. For example, it is possible to generate highly accurate correction data W by using a deep neural network that has learned a huge amount of images as teacher data.

FIG. 5B illustrates an example of a display device including a pixel array in which the pixels 11c are provided in a matrix, a row driver 12, a column driver 13, a circuit 14, and a circuit 15. The circuit 15 can supply the reset potential Sr to the wiring 130.

FIG. 5C illustrates an example of a display device including a pixel array in which pixels 11c are provided in a matrix, a row driver 12, a column driver 13, a column driver 17, a circuit 14, and a circuit 15. is there. A wiring 130 is electrically connected to the column driver 17.

As the column driver 17, for example, a shift register circuit can be used. The circuit 15 can supply the reset potential Sr to the column driver 17. Further, when an operation such as image correction is not performed, the display operation of the liquid crystal element 106 can be performed by supplying the image data Sx to the column driver 17.

5A to 5C illustrate the configuration including the circuit 14 and the circuit 15, but a configuration having both functions in one circuit may be used.

The display device of one embodiment of the present invention has a structure in which image correction can be performed in pixels. Therefore, the image data supplied to the pixels is low-resolution image data, and the same image data is supplied to a plurality of pixels. When supplying the same image data to four pixels in the horizontal and vertical directions, the same image data may be supplied to each of the signal lines connected to each pixel, but the signal lines supplying the same image data are electrically connected to each other. By connecting, image data writing operation can be speeded up.

FIG. 6 is a diagram showing a part of a pixel array of a display device capable of color display, and shows a configuration in which signal lines supplying the same image data can be electrically connected via a switch. In general, a pixel of a display device that can perform color display has a combination of sub-pixels that emit colors of R (red), G (green), and B (blue). In FIG. 6, three sub-pixels R, G, and B arranged in the horizontal direction constitute one pixel, and represent four pixels in the horizontal and vertical directions.

Here, the same image data is input to the four pixels in the horizontal and vertical directions. In FIG. 6, the same image data is input to the subpixels R1 to R4. For example, the same image data is supplied to the wirings 125 [1] and 125 [4] that are connected to the subpixels R1 to R4 and function as signal lines, and the wirings 122 [1] and 122 [2] that function as scanning lines. ], The same image data can be input to the four sub-pixels. However, this method is not efficient.

In one embodiment of the present invention, two signal lines are turned on by a switch provided between signal lines, and two scanning lines are turned on by a switch provided between scanning lines, thereby simultaneously writing four sub-pixels. Enable.

As shown in FIG. 6, the switch 141 provided between the wirings 125 [1] and 125 [4] is turned on, whereby the image data supplied to one of the wirings 125 [1] or 125 [4]. Can be simultaneously written in the sub-pixel R1 and the sub-pixel R2. At this time, when the switch 144 provided between the wiring 122 [1] and the wiring 122 [2] is turned on, the sub-pixel R3 and the sub-pixel R4 can be written simultaneously. That is, four subpixels can be written simultaneously.

Similarly, the switch 142 provided between the wirings 125 [2] and 125 [5] and the switch 143 provided between the wirings 125 [3] and 125 [6] are made conductive as necessary. Thus, simultaneous writing of four sub-pixels is possible in other pixels. As the switches 141 to 144, for example, transistors can be used.

By simultaneously writing four sub-pixels, writing time can be shortened and the frame frequency can be increased.

Next, simulation results of the pixel 11a shown in FIG. 1 and the pixel 11b shown in FIG. 3 will be described. The common parameters are as follows. The transistor sizes are all L / W = 4 μm / 4 μm, the capacitance value of the capacitor 104 is 100 fF, the capacitance of the capacitor 105 is 50 fF, the capacitance of the liquid crystal element 106 is 20 fF, the common wiring 132, The potential of 133 was both 0V. Note that SPICE was used as the circuit simulation software.

FIGS. 7A to 7C are diagrams illustrating operation parameters for simulation of the pixel 11a. The vertical axis represents the potential of each wiring, and the horizontal axis represents time according to the timing chart of FIG.

FIG. 7A illustrates the potential of the wiring connected to the gate of the transistor. Times T2 to T5 correspond to a correction data (Vp) writing operation. Times T11 to T13 correspond to an operation of adding the image data (Vs) to the correction data (Vp).

FIG. 7B is a diagram showing the potential of the wiring 124 that supplies the correction data (Vp). Here, Vp = 8V. Note that the correction data (Vp) supplied to the wiring 124 may be performed between T2 and T5.

FIG. 7C is a diagram illustrating the potential of the wiring 125 that supplies the image data (Vs). Here, the conditions changed from 1 V to 8 V every 1 V are used. Note that 1 V is supplied as the potential “L” to the wiring 125 when the correction data (Vp) is written.

FIG. 7D shows a simulation result showing a change in the potential of the node NA when the above operating parameters are applied. It can be seen that the potential shown after time 13 is the potential applied to the node NA, which is higher than the image data (Vs). However, as described above, the potential of the node NA is affected by the potential drop when the correction data (Vp) is distributed from the node NM to the node NA, the influence of the capacitance ratio at the time of capacitive coupling, the influence of the capacitance between wirings, and the like. May not reach the desired potential.

FIG. 8A is a diagram illustrating the relationship between the image data (Vs) and the potential of the node NA in the above-described parameters. A circle (◯) indicates a simulation result when 8V is input as correction data (Vp). Note that Vref (the potential of the wiring 125 at the time of writing) is 1V, and Vp−Vref = 7V. In the data indicated by white circles, the triangle mark (Δ) is the simulation result when the correction data (Vp) is directly written in the node NA. Thus, there is a slight difference between the two, and there may be a case where the correction cannot be sufficiently performed when there is a limitation in the design or operation conditions.

FIG. 8B is a simulation result in which it is verified whether or not the above divergence can be suppressed by adding the potential corresponding to the loss to the correction data (Vp) in advance, considering the result of FIG. 8A. . In the above-described parameters, the potential of the node NA can be set to a desired value by adding the potential of +5.6 V to the correction data (Vp).

FIG. 8C shows a simulation result when the capacitance value of the capacitor 104 is changed from 100 fF to 300 fF for the same purpose. Although there is a slight divergence when the potential of the image data (Vs) is low, the potential of the node NA can be almost set to a desired value.

That is, it can be seen that the potential of the node NA can be set to a desired value by setting the correction data (Vp) or the capacitance value of the capacitor 104 to an appropriate value.

FIGS. 9A to 9C are diagrams for explaining the operation parameters of the simulation of the pixel 11b. The vertical axis represents the potential of each wiring, and the horizontal axis represents time according to the timing chart of FIG. Since the transistor 103 is omitted in the pixel 11b, data of the wiring 126 is not illustrated in FIG. 9B and 9C are the same as FIGS. 8B and 8C.

FIG. 9D shows a simulation result showing a change in potential of the node NA when the above operating parameters are applied. FIG. 10 is a diagram showing the relationship between the image data (Vs) and the potential of the node NA in the parameters described above. Since the pixel 11b is not affected at least by the potential drop due to the distribution of the correction data (Vp), it is not necessary to add the correction data (Vp) described above. Further, since the capacitance value of the capacitor 104 can be reduced, the degree of freedom in design can be improved.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of a structure of a display device using a liquid crystal element is described. In the present embodiment, descriptions of operations and functions related to the correction described in the first embodiment are omitted.

11A to 11C illustrate a structure of a display device in which one embodiment of the present invention can be used.

In FIG. 11A, a sealant 4005 is provided so as to surround the display portion 215 provided over the first substrate 4001, and the display portion 215 is sealed with the sealant 4005 and the second substrate 4006. .

The display portion 215 is provided with a pixel array including the pixels described in Embodiment 1.

In FIG. 11A, the scan line driver circuit 221a, the signal line driver circuit 231a, the signal line driver circuit 232a, and the common line driver circuit 241a each include a plurality of integrated circuits 4042 provided over the printed board 4041. The integrated circuit 4042 is formed using a single crystal semiconductor or a polycrystalline semiconductor. The signal line driver circuit 231a and the signal line driver circuit 232a have the function of the column driver described in Embodiment 1. The scan line driver circuit 221a has the function of the row driver described in the embodiment. The common line driver circuit 241a has a function of supplying a predetermined potential to the common wirings 132 and 133 described in Embodiment 1 or the like.

Various signals and potentials supplied to the scan line driver circuit 221a, the common line driver circuit 241a, the signal line driver circuit 231a, and the signal line driver circuit 232a are supplied through an FPC (FPC: Flexible printed circuit) 4018.

An integrated circuit 4042 included in the scan line driver circuit 221 a and the common line driver circuit 241 a has a function of supplying a selection signal to the display portion 215. The integrated circuit 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a has a function of supplying image data to the display portion 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealant 4005 over the first substrate 4001.

Note that there is no particular limitation on the connection method of the integrated circuit 4042, and a wire bonding method, a COG (Chip On Glass) method, a TCP (Tape Carrier Package) method, a COF (Chip On Film) method, or the like can be used. it can.

FIG. 11B illustrates an example in which the integrated circuit 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a is mounted by a COG method. In addition, a part of or the entire driver circuit can be formed over the same substrate as the display portion 215 to form a system-on-panel.

FIG. 11B illustrates an example in which the scan line driver circuit 221a and the common line driver circuit 241a are formed over the same substrate as the display portion 215. By forming the driver circuit simultaneously with the pixel circuit in the display portion 215, the number of components can be reduced. Therefore, productivity can be improved.

In FIG. 11B, a sealant 4005 is provided so as to surround the display portion 215 provided over the first substrate 4001, the scan line driver circuit 221a, and the common line driver circuit 241a. In addition, a second substrate 4006 is provided over the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a. Therefore, the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a are sealed together with the display element by the first substrate 4001, the sealant 4005, and the second substrate 4006.

FIG. 11B illustrates an example in which the signal line driver circuit 231a and the signal line driver circuit 232a are separately formed and mounted on the first substrate 4001, but the present invention is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted. In addition, as illustrated in FIG. 11C, the signal line driver circuit 231a and the signal line driver circuit 232a may be formed over the same substrate as the display portion 215.

In some cases, the display device includes a panel in which the display element is sealed, and a module in which an IC including a controller or the like is mounted on the panel.

The display portion and the scan line driver circuit provided over the first substrate include a plurality of transistors.

The transistor included in the peripheral driver circuit and the transistor included in the pixel circuit in the display portion may have the same structure or different structures. The transistors included in the peripheral driver circuit may all have the same structure, or two or more structures may be used in combination. Similarly, the transistors included in the pixel circuit may all have the same structure, or two or more structures may be used in combination.

In addition, the input device 4200 can be provided over the second substrate 4006. A structure in which the input device 4200 is provided in the display device illustrated in FIGS. 11A and 11B can function as a touch panel.

There is no limitation on a detection element (also referred to as a sensor element) included in the touch panel of one embodiment of the present invention. Various sensors that can detect the proximity or contact of an object to be detected, such as a finger or a stylus, can be applied as the detection element.

As a sensor method, for example, various methods such as a capacitance method, a resistance film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be used.

In this embodiment, a touch panel having a capacitive detection element will be described as an example.

Examples of the electrostatic capacity method include a surface electrostatic capacity method and a projection electrostatic capacity method. In addition, examples of the projected capacitance method include a self-capacitance method and a mutual capacitance method. The mutual capacitance method is preferable because simultaneous multipoint detection is possible.

The touch panel of one embodiment of the present invention includes a structure in which a separately manufactured display device and a detection element are attached, a structure in which an electrode that forms the detection element is provided on one or both of a substrate that supports the display element and a counter substrate, and the like Various configurations can be applied.

FIGS. 12A and 12B show an example of a touch panel. FIG. 12A is a perspective view of the touch panel 4210. FIG. 12B is a schematic perspective view of the input device 4200. For the sake of clarity, only representative components are shown.

The touch panel 4210 has a structure in which a separately manufactured display device and a detection element are bonded to each other.

The touch panel 4210 includes an input device 4200 and a display device, which are provided to overlap each other.

The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239. The electrode 4228 can be electrically connected to the wiring 4239. The FPC 4272b is electrically connected to each of the plurality of wirings 4237 and the plurality of wirings 4238. The FPC 4272b can be provided with an IC 4273b.

Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case where a touch sensor is provided between the first substrate 4001 and the second substrate 4006, an optical touch sensor using a photoelectric conversion element may be used in addition to a capacitive touch sensor.

FIG. 13 is a cross-sectional view of the portion indicated by the chain line N1-N2 in FIG. The display device illustrated in FIG. 13 includes an electrode 4015, and the electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019. In FIG. 13, the electrode 4015 is electrically connected to the wiring 4014 in the opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

The electrode 4015 is formed using the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed using the same conductive layer as the source electrode and the drain electrode of the transistor 4010 and the transistor 4011.

In addition, the display portion 215 and the scan line driver circuit 221a provided over the first substrate 4001 include a plurality of transistors. In FIG. 13, the transistor 4010 and the scan line driver circuit 221a included in the display portion 215 are included. The transistor 4011 included in FIG. Note that in FIG. 13, bottom-gate transistors are illustrated as the transistors 4010 and 4011; however, top-gate transistors may be used.

In FIG. 13, the insulating layer 4112 is provided over the transistors 4010 and 4011.

In addition, the transistor 4010 and the transistor 4011 are provided over the insulating layer 4102. In addition, the transistor 4010 and the transistor 4011 include an electrode 4017 formed over the insulating layer 4111. The electrode 4017 can function as a back gate electrode.

The display device illustrated in FIG. 13 includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same step as the gate electrode of the transistor 4010 and an electrode formed in the same step as the source electrode and the drain electrode. Each electrode overlaps with the insulating layer 4103 interposed therebetween.

In general, the capacitance of a capacitor provided in the pixel portion of the display device is set so that charge can be held for a predetermined period in consideration of leakage current of a transistor arranged in the pixel portion. The capacity of the capacitor may be set in consideration of the off-state current of the transistor.

The transistor 4010 provided in the display portion 215 is electrically connected to the display element. FIG. 13 illustrates an example of a liquid crystal display device using a liquid crystal element as a display element. In FIG. 13, a liquid crystal element 4013 which is a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033 which function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other with the liquid crystal layer 4008 interposed therebetween.

As the liquid crystal element 4013, liquid crystal elements to which various modes are applied can be used. For example, VA (Vertical Alignment), TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, ASM (Axially Symmetrical Aligned Micro-cell) mode, OCB (Optical All Coil mode) ) Mode, AFLC (Antiferroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, VA-IPS mode, guest host mode, and the like can be used.

Alternatively, a normally black liquid crystal display device such as a transmissive liquid crystal display device using a vertical alignment (VA) mode may be used as the liquid crystal display device described in this embodiment. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

Note that the liquid crystal element is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal. The optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). As the liquid crystal used in the liquid crystal element, a thermotropic liquid crystal, a low-molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal (PDLC), a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. . These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

FIG. 13 illustrates an example of a liquid crystal display device including a vertical electric field liquid crystal element; however, a liquid crystal display device including a horizontal electric field liquid crystal element can be used in one embodiment of the present invention. When the horizontal electric field method is employed, a liquid crystal exhibiting a blue phase for which an alignment film is not used may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which 5% by weight or more of a chiral agent is mixed is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and exhibits optical isotropy. In addition, a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. .

The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Yes. A spherical spacer may be used.

If necessary, an optical member (optical substrate) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source. Further, a micro LED or the like may be used as the backlight and the sidelight.

In the display device illustrated in FIG. 13, a light-blocking layer 4132, a colored layer 4131, and an insulating layer 4133 are provided between the substrate 4006 and the second electrode layer 4031.

As a material that can be used for the light-blocking layer 4132, carbon black, titanium black, metal, metal oxide, a composite oxide containing a solid solution of a plurality of metal oxides, and the like can be given. The light shielding layer 4132 may be a film containing a resin material or a thin film of an inorganic material such as a metal. Alternatively, the light-blocking layer 4132 can be a stacked film including a material containing the material of the colored layer 4131. For example, a stacked structure of a film including a material used for the colored layer 4131 that transmits light of a certain color and a film including a material used for the colored layer 4131 that transmits light of another color can be used. It is preferable to use a common material for the coloring layer 4131 and the light shielding layer because the device can be shared and the process can be simplified.

As a material that can be used for the colored layer 4131, a metal material, a resin material, a resin material containing a pigment or a dye, or the like can be given. By appropriately selecting and using the material, light such as R (red), G (green), and B (blue) can be generated, and full color display can be performed.

Note that a color conversion layer containing a semiconductor material may be used as an alternative to the coloring layer 4131. For example, when light having a certain wavelength is incident on a layer having a nano-sized semiconductor, it can be converted into light having a different wavelength.

When a certain type of semiconductor is irradiated with light having high energy, it enters an excited state, and emits light when transitioning to a stable state. At this time, the wavelength of the light emitted from the semiconductor is determined by the energy gap of the semiconductor material. However, in the nano-sized semiconductor, electrons, holes, and excitons are confined in the inside, and the energy state becomes discrete and the energy shifts. . Therefore, the wavelength of light emitted from the semiconductor also changes.

Such a nano-sized semiconductor is called a quantum dot. Since the amount of energy shift depends on the size of the quantum dot, the emission wavelength can be easily adjusted by adjusting the size of the quantum dot. In addition, since the discreteness of the quantum dots limits phase relaxation, the peak width of the emission spectrum is narrow, and light emission with good color purity can be obtained. Therefore, a color conversion layer having quantum dots can be used as an alternative to the colored layer 4131.

FIG. 14 is a schematic cross-sectional view of a pixel when a color conversion layer having quantum dots is used. The pixel is composed of sub-pixels of a pixel 4350R (red), a pixel 4350G (green), and a pixel 4350B (blue), and light incident from the light source 4300 is converted into a peak wavelength by the color conversion layers 4301 and 4302 and then externally. It is injected. Here, the light source 4300 is preferably an element that emits blue light having a peak wavelength at a wavelength of 460 to 500 nm. For example, a blue LED can be used.

In addition, as a structure of the light source 4300, in addition to the backlight in which the LED is disposed directly below the display unit, a sidelight in which the LED disposed on the side and the light guide plate are combined may be used.

Blue light incident on the pixel 4350R (red) reaches the color conversion layer 4301 through the liquid crystal layer 4008 and the like. The color conversion layer 4301 can convert blue light into red light having a peak wavelength at a wavelength of 610 nm to 780 nm, and the red light is emitted to the outside.

Blue light incident on the pixel 4350G (green) reaches the color conversion layer 4302 through the liquid crystal layer 4008 and the like. The color conversion layer 4302 can convert blue light into green light having a peak wavelength at a wavelength of 500 nm to 570 nm, and the green light is emitted to the outside.

The pixel 4350B (blue) does not need to be wavelength-converted, and thus a color conversion layer is not provided and blue light emitted from the light source 4300 is transmitted.

This configuration also has an advantage that the light emitted from the light source can be used effectively. In a general white light source + colored layer structure, unnecessary wavelength components are absorbed by the colored layer, so that light use efficiency is poor. Moreover, since white LED often used as a light source is comprised by blue LED + fluorescent substance etc., there exists a subject in luminous efficiency. On the other hand, in this configuration, light from a light source such as a blue LED can be used as it is in the pixel 4350B (blue). Some quantum dots that can be used for the color conversion layers 4301 and 4302 have an internal quantum efficiency of nearly 100%. Therefore, in the said structure, the utilization efficiency of light is high and it can also suppress the power consumption of a light source.

The materials constituting the quantum dots include group 14 elements, group 15 elements, group 16 elements, compounds composed of a plurality of group 14 elements, elements belonging to groups 4 to 14 and group 16 elements. Compounds of Group 2, elements of Group 16 and Group 16, compounds of Group 13 elements and Group 15 elements, compounds of Group 13 elements and Group 17 elements, Group 14 elements and Group 15 Examples thereof include compounds with elements, compounds of Group 11 elements and Group 17 elements, iron oxides, titanium oxides, chalcogenide spinels, and semiconductor clusters.

Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide , Gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, indium telluride, sulfide Indium, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, Tellurium, Hou Carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, calcium selenide, calcium telluride, beryllium sulfide, beryllium selenide, Beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide , Copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tantalum oxide, titanium oxide, zirconium oxide, silicon nitride, germanium nitride, Aluminum oxide, chi Barium oxide, selenium, zinc and cadmium compound, indium, arsenic and phosphorus compound, cadmium, selenium and sulfur compound, cadmium, selenium and tellurium compound, zinc, cadmium and selenium compound, indium, gallium and arsenic compound Examples thereof include, but are not limited to, compounds of indium, gallium, and selenium, compounds of indium, selenium, and sulfur, compounds of copper, indium, and sulfur, and combinations thereof. Moreover, you may use what is called an alloy type quantum dot whose composition is represented by arbitrary ratios.

As a structure of the quantum dot, there are a core type, a core-shell type, a core-multishell type, and any of them may be used. In order to improve the quantum efficiency of light emission, it is effective to cover the core formed of nanocrystals with a shell made of a material having a wider energy gap. By covering the core with the shell, it is possible to reduce the influence of defects and dangling bonds existing on the nanocrystal surface. Therefore, it is preferable to use a core-shell type or core-multishell type quantum dot. Examples of the shell material include zinc sulfide and zinc oxide.

A quantum dot is a semiconductor nanocrystal having a size of several nanometers. Since the energy gap increases as the crystal size decreases, light emission shifts to a low wavelength side (high energy side). Therefore, by controlling the size of the quantum dots, the emission wavelength can be adjusted from ultraviolet to infrared. The size (diameter) of the quantum dots is, for example, in the range of 0.5 nm to 20 nm, preferably 1 nm to 10 nm.

A plurality of quantum dots are provided in the light conversion layer. As the size distribution width is narrower, the emission spectrum becomes narrower and light emission with good color purity can be obtained. The shape of the quantum dot is not particularly limited, and may be spherical, rod-shaped, disk-shaped, or other shapes. Note that a quantum rod that is a rod-shaped quantum dot has a function of exhibiting light having directivity, and thus a light-emitting element with better external quantum efficiency can be obtained by using the quantum rod as a light-emitting material.

The light conversion layer having quantum dots can be formed by an existing technique such as an ink jet method, but has a high degree of difficulty in miniaturization. Therefore, it is preferably applied to a large display such as a television or a digital signage. The pixel circuit of one embodiment of the present invention has a function of increasing the voltage output from the driver IC. Therefore, a driver IC with a low output voltage can be used, and power consumption can be reduced even with a large display.

In addition, the display device illustrated in FIG. 13 includes an insulating layer 4111 and an insulating layer 4104. As the insulating layer 4111 and the insulating layer 4104, insulating layers that hardly transmit an impurity element are used. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, entry of impurities from the outside can be prevented.

In addition, since the transistor is easily broken by static electricity or the like, it is preferable to provide a protective circuit for protecting the driving circuit. The protection circuit is preferably configured using a non-linear element.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, examples of transistors that can be used instead of the transistors described in the above embodiments will be described with reference to drawings.

The display device of one embodiment of the present invention can be manufactured using various types of transistors such as a bottom-gate transistor and a top-gate transistor. Therefore, the semiconductor layer material and the transistor structure to be used can be easily replaced in accordance with an existing production line.

[Bottom gate type transistor]
FIG. 15A1 is a cross-sectional view of a channel protection transistor 810 which is a kind of bottom-gate transistor. In FIG. 15A1, the transistor 810 is formed over a substrate 771. In addition, the transistor 810 includes an electrode 746 over the substrate 771 with an insulating layer 772 interposed therebetween. In addition, a semiconductor layer 742 is provided over the electrode 746 with an insulating layer 726 interposed therebetween. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer.

In addition, the insulating layer 741 is provided over the channel formation region of the semiconductor layer 742. Further, an electrode 744 a and an electrode 744 b are provided over the insulating layer 726 in contact with part of the semiconductor layer 742. The electrode 744a can function as one of a source electrode and a drain electrode. The electrode 744b can function as the other of the source electrode and the drain electrode. Part of the electrode 744 a and part of the electrode 744 b are formed over the insulating layer 741.

The insulating layer 741 can function as a channel protective layer. By providing the insulating layer 741 over the channel formation region, it is possible to prevent the semiconductor layer 742 from being exposed when the electrodes 744a and 744b are formed. Accordingly, the channel formation region of the semiconductor layer 742 can be prevented from being etched when the electrodes 744a and 744b are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.

The transistor 810 includes the insulating layer 728 over the electrode 744a, the electrode 744b, and the insulating layer 741, and the insulating layer 729 over the insulating layer 728.

In the case where an oxide semiconductor is used for the semiconductor layer 742, a material that can take oxygen from part of the semiconductor layer 742 and generate oxygen vacancies at least in a portion of the electrodes 724a and 724b in contact with the semiconductor layer 742 is used. It is preferable. In the region where oxygen vacancies occur in the semiconductor layer 742, the carrier concentration increases, and the region becomes n-type and becomes an n-type region (n ⁺ layer). Accordingly, the region can function as a source region or a drain region. In the case where an oxide semiconductor is used for the semiconductor layer 742, tungsten, titanium, or the like can be given as an example of a material that can take oxygen from the semiconductor layer 742 and generate oxygen vacancies.

When the source region and the drain region are formed in the semiconductor layer 742, the contact resistance between the electrode 724a and the electrode 724b and the semiconductor layer 742 can be reduced. Thus, favorable electric characteristics of the transistor, such as field effect mobility and threshold voltage, can be obtained.

In the case where a semiconductor such as silicon is used for the semiconductor layer 742, a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 724a and between the semiconductor layer 742 and the electrode 724b. A layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.

The insulating layer 729 is preferably formed using a material having a function of preventing or reducing the diffusion of impurities from the outside to the transistor. Note that the insulating layer 729 can be omitted as necessary.

A transistor 811 illustrated in FIG. 15A2 is different from the transistor 810 in that the transistor 811 includes an electrode 723 that can function as a back gate electrode over the insulating layer 729. The electrode 723 can be formed using a material and a method similar to those of the electrode 746.

In general, the back gate electrode is formed using a conductive layer, and the channel formation region of the semiconductor layer is sandwiched between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same manner as the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or may be a ground potential (GND potential) or an arbitrary potential. In addition, the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently of the gate electrode.

Both the electrode 746 and the electrode 723 can function as gate electrodes. Thus, each of the insulating layer 726, the insulating layer 729, the insulating layer 728, and the insulating layer 729 can function as a gate insulating layer. Note that the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.

Note that when one of the electrode 746 and the electrode 723 is referred to as a “gate electrode”, the other is referred to as a “back gate electrode”. For example, in the transistor 811, when the electrode 723 is referred to as a “gate electrode”, the electrode 746 is referred to as a “back gate electrode”. In the case where the electrode 723 is used as a “gate electrode”, the transistor 811 can be regarded as a kind of top-gate transistor. One of the electrode 746 and the electrode 723 may be referred to as a “first gate electrode”, and the other may be referred to as a “second gate electrode”.

By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, and further by setting the electrode 746 and the electrode 723 to have the same potential, a region where carriers flow in the semiconductor layer 742 becomes larger in the film thickness direction. The amount of carrier movement increases. As a result, the on-state current of the transistor 811 is increased and the field-effect mobility is increased.

Therefore, the transistor 811 is a transistor having a large on-state current with respect to the occupied area. In other words, the area occupied by the transistor 811 can be reduced with respect to the required on-state current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Thus, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

In addition, since the gate electrode and the back gate electrode are formed using conductive layers, they have a function of preventing an electric field generated outside the transistor from acting on a semiconductor layer in which a channel is formed (particularly, an electric field shielding function against static electricity). . Note that the electric field shielding function can be improved by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.

In addition, when the back gate electrode is formed using a light-blocking conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side. Therefore, light deterioration of the semiconductor layer can be prevented, and deterioration of electrical characteristics such as shift of the threshold voltage of the transistor can be prevented.

According to one embodiment of the present invention, a highly reliable transistor can be realized. In addition, a highly reliable semiconductor device can be realized.

FIG. 15B1 is a cross-sectional view of a channel protection transistor 820 which is one of bottom-gate transistors. The transistor 820 has substantially the same structure as the transistor 810, except that an insulating layer 741 covers an end portion of the semiconductor layer 742. In addition, the semiconductor layer 742 and the electrode 744a are electrically connected to each other in an opening formed by selectively removing part of the insulating layer 729 which overlaps with the semiconductor layer 742. In addition, the semiconductor layer 742 and the electrode 744b are electrically connected to each other in an opening formed by selectively removing part of the insulating layer 729 which overlaps with the semiconductor layer 742. A region of the insulating layer 729 overlapping with a channel formation region can function as a channel protective layer.

A transistor 821 illustrated in FIG. 15B2 is different from the transistor 820 in that the transistor 821 includes an electrode 723 that can function as a back gate electrode over the insulating layer 729.

By providing the insulating layer 729, exposure of the semiconductor layer 742 that occurs when the electrodes 744a and 744b are formed can be prevented. Therefore, the semiconductor layer 742 can be prevented from being thinned when the electrodes 744a and 744b are formed.

The distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are longer in the transistor 820 and the transistor 821 than in the transistor 810 and the transistor 811. Thus, parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. In addition, parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.

A transistor 825 illustrated in FIG. 15C1 is a channel-etched transistor which is one of bottom-gate transistors. In the transistor 825, the electrode 744a and the electrode 744b are formed without using the insulating layer 729. Therefore, part of the semiconductor layer 742 exposed when the electrodes 744a and 744b are formed may be etched. On the other hand, since the insulating layer 729 is not provided, the productivity of the transistor can be increased.

A transistor 825 illustrated in FIG. 15C2 is different from the transistor 820 in that the transistor 825 includes an electrode 723 that can function as a back gate electrode over the insulating layer 729.

[Top gate type transistor]
A transistor 842 illustrated in FIG. 16A1 is one of top-gate transistors. The transistor 842 is different from the transistors 830 and 840 in that the electrode 744a and the electrode 744b are formed after the insulating layer 729 is formed. The electrodes 744 a and 744 b are electrically connected to the semiconductor layer 742 in openings formed in the insulating layers 728 and 729.

Further, part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the impurity 755 is introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask, so that self-alignment ( Impurity regions can be formed in a self-aligning manner. The transistor 842 has a region where the insulating layer 726 extends beyond the end portion of the electrode 746. When the impurity 755 is introduced into the semiconductor layer 742, the impurity concentration of the region where the impurity 755 is introduced through the insulating layer 726 of the semiconductor layer 742 is higher than the region where the impurity 755 is introduced without passing through the insulating layer 726. Get smaller. Therefore, in the semiconductor layer 742, an LDD (Lightly Doped Drain) region is formed in a region that does not overlap with the electrode 746.

A transistor 843 illustrated in FIG. 16A2 is different from the transistor 842 in having an electrode 723. The transistor 843 includes an electrode 723 formed over the substrate 771 and overlaps with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. The electrode 723 can function as a back gate electrode.

Alternatively, the insulating layer 726 in a region which does not overlap with the electrode 746 may be removed as in the transistor 844 illustrated in FIG. 16B1 and the transistor 845 illustrated in FIG. Further, the insulating layer 726 may be left as in the transistor 846 illustrated in FIG. 16C1 and the transistor 847 illustrated in FIG.

The transistors 842 to 847 can also form impurity regions in the semiconductor layer 742 in a self-aligned manner by introducing the impurity 755 into the semiconductor layer 742 using the electrode 746 as a mask after the electrode 746 is formed. . According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. According to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 4)
Electronic devices that can use the display device according to one embodiment of the present invention include a display device, a personal computer, an image storage device or an image playback device including a recording medium, a mobile phone, a portable game machine, and a portable data terminal , Digital book terminals, video cameras, digital still cameras and other cameras, goggles-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices Automatic teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 17A illustrates an example of a mobile phone, which includes a housing 951, a display portion 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, and the like. The mobile phone includes a touch sensor in the display portion 952. All operations such as making a call or inputting characters can be performed by touching the display portion 952 with a finger or a stylus. Further, the housing 901 and the display portion 952 are flexible and can be used by being bent as illustrated. By using the display device of one embodiment of the present invention for the display portion 952, display with high display quality can be performed.

FIG. 17B illustrates a portable data terminal, which includes a housing 911, a display portion 912, a camera 919, and the like. Information can be input and output by a touch panel function of the display portion 912. By using the display device of one embodiment of the present invention for the display portion 912, display with high display quality can be performed.

FIG. 17C illustrates a television which includes a housing 971, a display portion 973, operation keys 974, speakers 975, a communication connection terminal 976, an optical sensor 977, and the like. The display portion 973 is provided with a touch sensor and can perform an input operation. By using the display device of one embodiment of the present invention for the display portion 973, display with high display quality can be performed.

FIG. 17D illustrates an information processing terminal which includes a housing 901, a display portion 902, a display portion 903, a sensor 904, and the like. The display portion 902 and the display portion 903 are formed of a single display panel and have flexibility. The housing 901 is also flexible and can be used by being bent as illustrated, or can be used in a flat plate shape like a tablet terminal. The sensor 904 can sense the shape of the housing 901. For example, the display of the display portion 902 and the display portion 903 can be switched when the housing is bent. By using the display device of one embodiment of the present invention for the display portion 902 and the display portion 903, display with high display quality can be performed.

FIG. 17E illustrates a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display portion 965, operation keys 966, a zoom lever 968, a lens 969, and the like. By using the display device of one embodiment of the present invention for the display portion 965, display with high display quality can be performed.

FIG. 17F illustrates digital signage having a structure in which a large display portion 922 is attached to a side surface of a pillar 921. By using the display device of one embodiment of the present invention for the display portion 922, display with high display quality can be performed.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

11 pixel 11a pixel 11b pixel 11c pixel 11d pixel 12 row driver 13 column driver 14 circuit 15 circuit 17 column driver 101 transistor 102 transistor 103 transistor 104 capacitor element 105 capacitor element 106 liquid crystal element 107 transistor 111 transistor 121 wiring 122 wiring 124 wiring 125 wiring 126 wiring 130 wiring 132 common wiring 133 common wiring 141 switch 142 switch 143 switch 144 switch 215 display unit 221a scanning line driving circuit 231a signal line driving circuit 232a signal line driving circuit 241a common line driving circuit 723 electrode 724a electrode 724b electrode 726 insulating layer 728 Insulating layer 729 Insulating layer 741 Insulating layer 742 Semiconductor layer 744a Electrode 744b Electrode 746 Electrode 755 Impurity 71 substrate 772 insulating layer 810 transistor 811 transistor 820 transistor 821 transistor 825 transistor 830 transistor 840 transistor 842 transistor 843 transistor 844 transistor 845 transistor 846 transistor 847 transistor 901 housing 902 display portion 903 display portion 904 sensor 911 housing 912 display portion 919 camera 921 Column 922 Display portion 951 Case 952 Display portion 953 Operation button 954 External connection port 955 Speaker 956 Microphone 957 Camera 961 Case 962 Shutter button 963 Microphone 965 Display portion 966 Operation key 967 Speaker 968 Zoom lever 969 Lens 971 Case 973 Display 974 Operation key 975 Speaker 976 Communication connection terminal 9 7 photosensor 4001 substrate 4005 sealant 4006 substrate 4008 liquid crystal layer 4010 4011 transistors 4013 liquid crystal element 4014 wiring 4015 electrodes 4017 electrodes 4018 FPC
4019 Anisotropic conductive layer 4020 Capacitor element 4021 Electrode 4030 Electrode layer 4031 Electrode layer 4032 Insulating layer 4033 Insulating layer 4035 Spacer 4041 Printed circuit board 4042 Integrated circuit 4102 Insulating layer 4103 Insulating layer 4104 Insulating layer 4110 Insulating layer 4111 Insulating layer 4112 Insulating layer 4131 Colored layer 4132 Light-shielding layer 4133 Insulating layer 4200 Input device 4210 Touch panel 4227 Electrode 4228 Electrode 4237 Wiring 4238 Wiring 4239 Wiring 4263 Substrate 4272b FPC
4273b IC
4300 Light source 4301 Color conversion layer 4302 Color conversion layer 4350B Pixel 4350G Pixel 4350R Pixel

Claims (6)

A display device having a first pixel, a second pixel, a third pixel, and a light source,
The first pixel has a first pixel circuit and a first light conversion layer,
The second pixel has a second pixel circuit and a second light conversion layer,
The third pixel includes a third pixel circuit;
The light source has a function of making blue light incident on the first to third pixels,
The first pixel has a function of converting the blue light into red light and emitting the light outside.
The second pixel has a function of converting the blue light into green light and emitting the light outside.
The third pixel has a function of transmitting the blue light and emitting the light to the outside.
The first to third pixel circuits have display elements,
The first to third pixel circuits have a function of storing a first signal and a function of generating a third signal by adding a second signal to the first signal,
The display device has a function of performing an operation based on the third signal. In claim 1,
The blue light has a peak wavelength in a range of 460 nm to 500 nm, the red light has a peak wavelength in a range of 610 nm to 780 nm, and the green light has a peak wavelength in a range of 500 nm to 570 nm. In claim 1 or 2,
The first to third pixel circuits each include a first transistor, a second transistor, a third transistor, a first capacitor element, a second capacitor element, and the display element. And
One of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor,
The other electrode of the first capacitor is electrically connected to one of a source and a drain of the second transistor;
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor;
One of a source and a drain of the third transistor is electrically connected to one electrode of the second capacitor;
The display device in which one electrode of the second capacitor is electrically connected to one electrode of the display element. In claim 3,
At least the second transistor and the third transistor include a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf). In any one of Claims 1 thru | or 4,
The display device, wherein the display element is a liquid crystal element. An electronic apparatus comprising the display device according to any one of claims 1 to 5 and a camera.